Ultralow Distortion
Differential ADC Driver
Data Sheet ADA4937-1/ADA4937-2
Rev. F Document Feedback
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FEATURES
Extremely low harmonic distortion (HD)
−112 dBc HD2 at 10 MHz
−84 dBc HD2 at 70 MHz
−77 dBc HD2 at 100 MHz
−102 dBc HD3 at 10 MHz
−91 dBc HD3 at 70 MHz
−84 dBc HD3 at 100 MHz
Low input voltage noise: 2.2 nV/√Hz
High speed
−3 dB bandwidth of 1.9 GHz, G = 1
Slew rate: 6000 V/μs, 25% to 75%
Fast overdrive recovery of 1 ns
0.5 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The ADA4937-1/ADA4937-2 are low noise, ultralow distortion,
high speed differential amplifiers. They are an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 100 MHz. The adjustable level of the output common
mode allows the ADA4937-1/ADA4937-2 to match the input
of the ADC. The internal common-mode feedback loop also
provides exceptional output balance as well as suppression of
even-order harmonic distortion products.
With the ADA4937-1/ADA4937-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors that determine the closed-loop gain of the amplifier.
The ADA4937-1/ADA4937-2 are fabricated using Analog Devices,
Inc., proprietary silicon-germanium (SiGe), complementary
bipolar process, enabling them to achieve very low levels of
distortion with an input voltage noise of only 2.2 nV/√Hz.
The low dc offset and excellent dynamic performance of the
ADA4937-1/ADA4937-2 make them well-suited for a wide
variety of data acquisition and signal processing applications.
FUNCTIONAL BLOCK DIAGRAMS
06591-001
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADA4937-1
–
FB
+IN
–IN
+FB
PD
–V
S
–V
S
–V
S
–V
S
–OUT
+OUT
V
OCM
+V
S
+V
S
+V
S
+V
S
Figure 1. ADA4937-1
0
6591-002
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–FB2
+V
S1
+V
S1
+FB1
–IN1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
ADA4937-2
Figure 2. ADA4937-2
–
55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115 1 10 100
DISTORTI ON (d Bc)
FREQUENCY (MHz)
HD2, V
S
=5.0V
HD3, V
S
=5.0V
HD2, V
S
=3.3V
HD3, V
S
=3.3V
06591-003
Figure 3. Harmonic Distortion vs. Frequency
The ADA4937-1/ADA4937-2 are available in a Pb-free, 3 mm ×
3 mm, 16-lead LFCSP (ADA4937-1, single) or a Pb-free, 4 mm ×
4 mm, 24-lead LFCSP (ADA4937-2, dual). The pinout has been
optimized to facilitate PCB layout and minimize distortion.
The ADA4937-1/ADA4937-2 are specified to operate over the
automotive (−40°C to +105°C) temperature range and between
3.3 V and 5 V supplies.
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 16
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Analyzing an Application Circuit ............................................ 18
Setting the Closed-Loop Gain .................................................. 18
Estimating the Output Noise Voltage ...................................... 18
Impact of Mismatches in the Feedback Networks ................. 19
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 20
Setting the Output Common-Mode Voltage .......................... 20
Power-Down Operation ............................................................ 20
Layout, Grounding, and Bypassing .............................................. 22
High Performance ADC Driving ................................................. 23
3.3 V Operation .......................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/2016—Rev. E to Rev. F
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/2015—Rev. D to Rev. E
Changes to Table 6 ............................................................................ 7
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
8/2013—Rev. C to Rev. D
Changes to Input Bias Current Parameter, Table 1 ...................... 3
Changes to Input Bias Current Parameter, Table 3 ...................... 5
Updated Outline Dimensions ....................................................... 26
3/2010—Rev. B to Rev. C
Changes to Table 2, Power Supply Parameter ............................... 4
Changes to Table 4, Power Supply Parameter ............................... 6
Changes to Figure 43 ...................................................................... 15
Added the Power-Down Operation Section ............................... 20
10/2009—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Operating Temperature Range Parameter, Table 2 .. 4
Changes to Table 3 ............................................................................ 5
Changes to Figure 4 .......................................................................... 7
Changes to Figure 5 and Figure 6 .................................................... 8
Added EP Row to Table 7 and EP Row to Table 8 ........................ 8
Added Figure 46, Figure 47, and Figure 48; Renumbered
Sequentially ..................................................................................... 15
Changes to Table 9 .......................................................................... 18
Changes to Input Common-Mode Voltage Range in Single-
Supply Applications Section .......................................................... 20
Changes to Ordering Guide .......................................................... 26
11/2007—Rev. 0 to Rev. A
Added the ADA4937-2 ...................................................... Universal
Changes to Features .......................................................................... 1
Changes to Specifications ................................................................. 3
Changes to Figure 4 ........................................................................... 7
Changes to Typical Performance Characteristics.......................... 9
Inserted Figure 44 ........................................................................... 15
Added the Terminating a Single-Ended Input Section ............. 19
Changes to Table 10 and Table 11 ................................................ 21
Changes to Layout, Grounding, and Bypassing Section ........... 22
Inserted Figure 59, Figure 60, and Figure 61 .............................. 22
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/2007—Revision 0: Initial Version
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 3 of 28
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, V OCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, Gain (G) = +1, RL, dm = 1 kΩ, unless otherwise noted. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
±DIN to ±OUT Performance
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 1900 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p 200 MHz
Large Signal Bandwidth VOUT, dm = 2 V p-p 1700 MHz
Slew Rate VOUT, dm = 2 V p-p; 25% to 75% 6000 V/µs
Settling Time VOUT, dm = 2 V p-p 7 ns
Overdrive Recovery Time VIN = 0 V to 1.5 V step; G = 3.16 <1 ns
NOISE/HARMONIC PERFORMANCE See Figure 51 for distortion test circuit
Second Harmonic
V
OUT, dm
= 2 V p-p; 10 MHz
−112
dBc
VOUT, dm = 2 V p-p; 70 MHz −84 dBc
VOUT, dm = 2 V p-p; 100 MHz −77 dBc
Third Harmonic VOUT, dm = 2 V p-p; 10 MHz −102 dBc
VOUT, dm = 2 V p-p; 70 MHz −91 dBc
VOUT, dm = 2 V p-p; 100 MHz −84 dBc
IMD f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p −91 dBc
Voltage Noise (RTI) f = 100 kHz 2.2 nV/√Hz
Input Current Noise f = 100 kHz 4 pA/√Hz
Noise Figure G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz 15 dB
Crosstalk (ADA4937-2) f = 100 MHz −72 dB
INPUT CHARACTERISTICS
Offset Voltage VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = 2.5 V −2.5 ±0.5 +2.5 mV
TMIN to TMAX variation ±1 µV/°C
Input Bias Current
−50
−30
−10
µA
TMIN to TMAX variation 0.01 µA/°C
Input Offset Current −2 +0.5 +2 µA
Input Resistance Differential 6 MΩ
Common mode 3 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage 0.3 to 3.0 V
CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V −69 −80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT; single-ended output; RF = RG = 10 kΩ 0.9 4.1 V
Linear Output Current Per amplifier; RL, dm = 20 Ω; f = 10 MHz ±70 mA
Output Balance Error ∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz;
see Figure 50 for test circuit
−61 dB
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 4 of 28
VOCM to ±OUT Performance
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth 440 MHz
Slew Rate VIN = 1.5 V to 3.5 V; 25% to 75% 1150 V/µs
Input Voltage Noise (RTI) f = 100 kHz 7.5 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range 1.2 3.8 V
Input Resistance 8 10 12 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = +VS/2 2 7.1 mV
Input Bias Current 0.5 µA
VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = ±1 V −70 −75 dB
Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = ±1 V 0.97 0.98 1.00 V/V
POWER SUPPLY
Operating Range 3.0 5.25 V
Quiescent Current per Amplifier Enabled 38.0 39.5 42.0 mA
TMIN to TMAX variation 17 µA/°C
Powered down 0.02 0.3 0.5 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = 1 V −70 −90 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤1 V
Enabled ≥2 V
Turn-Off Time 1 µs
Turn-On Time
200
ns
PD Bias Current per Amplifier
Enabled PD = 5 V 10 30 50 µA
Powered Down PD = 0 V −300 −200 −150 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 5 of 28
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, −VS = 0 V, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
±DIN to ±OUT Performance
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 1800 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p 200 MHz
Large Signal Bandwidth VOUT, dm = 2 V p-p 1300 MHz
Slew Rate VOUT, dm = 2 V p-p; 25% to 75% 4000 V/µs
Settling Time VOUT, dm = 2 V p-p 7 ns
Overdrive Recovery Time VIN = 0 V to 1.0 V step; G = 3.16 <1 ns
NOISE/HARMONIC PERFORMANCE See Figure 51 for distortion test circuit
Second Harmonic VOUT, dm = 2 V p-p; 10 MHz −113 dBc
VOUT, dm = 2 V p-p; 70 MHz −85 dBc
V
OUT, dm
= 2 V p-p; 100 MHz
−77
dBc
Third Harmonic VOUT, dm = 2 V p-p; 10 MHz −95 dBc
VOUT, dm = 2 V p-p; 70 MHz −77 dBc
VOUT, dm = 2 V p-p; 100 MHz −71 dBc
IMD f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p −87 dBc
Voltage Noise (RTI) f = 100 kHz 2.2 nV/√Hz
Input Current Noise f = 100 kHz 4 pA/√Hz
Noise Figure G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz 15 dB
Crosstalk (ADA4937-2) f = 100 MHz −72 dB
INPUT CHARACTERISTICS
Offset Voltage VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = +VS/2 −2.5 ±0.5 +2.5 mV
TMIN to TMAX variation ±1 µV/°C
Input Bias Current −50 −30 −10 µA
TMIN to TMAX variation 0.01 µA/°C
Input Resistance
Differential
6
MΩ
Common mode 3 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage 0.3 to 1.2 V
CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V −67 −80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT; single-ended output; RF = RG = 10 kΩ 0.8 2.5 V
Linear Output Current Per amplifier; RL, dm = 20 Ω; f = 10 MHz ±47 mA
Output Balance Error ∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz;
see Figure 50 for test circuit
−61 dB
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 6 of 28
VOCM to ±OUT Performance
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth 440 MHz
Slew Rate VIN = 0.9 V to 2.4 V; 25% to 75% 900 V/µs
Input Voltage Noise (RTI) f = 100 kHz 7.5 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range 1.2 2.1 V
Input Resistance 10 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = 1.67 V 2 7.1 mV
Input Bias Current 0.5 µA
VOCM CMRR ∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V −70 −75 dB
Gain ∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V 0.97 0.98 1.00 V/V
POWER SUPPLY
Operating Range 3.0 5.25 V
Quiescent Current per Amplifier Enabled 36 38 40 mA
TMIN to TMAX variation 17 µA/°C
Powered down 0.02 0.2 0.5 mA
Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = 1 V −70 −90 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤1 V
Enabled ≥2 V
Turn-Off Time 1 µs
Turn-On Time
200
ns
PD Bias Current per Amplifier
Enabled PD = 3.3 V 10 20 30 µA
Powered Down PD = 0 V −200 −120 −100 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage 5.5 V
See Figure 4
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD51-7.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
16-Lead LFCSP (Exposed Pad) 95 12.6 °C/W
24-Lead LFCSP (Exposed Pad) 67 8.78 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4937-1/
ADA4937-2 packages is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes the properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4937-1/
ADA4937-2. Exceeding a junction temperature of 150°C for
an extended period can result in changes in the silicon devices,
potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through holes, ground,
and power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the ADA4937-1 single
16-lead LFCSP (95°C/W), and the ADA4937-2 dual 24-lead
LFCSP (67°C/W) on a JEDEC standard 4-layer board.
3.5
0
–40 11090 100
MAXIMUM POWER DISSIPATIO N (W)
AMBI E NT TE M P E RATURE ( °C)
06591-004
0.5
1.0
1.5
2.0
2.5
3.0
–30 –20 –10 010 20 30 40 50 60 70 80
ADA4937-2
ADA4937-1
Figure 4. Maximum Power Dissipation vs. Temperature, 4-Layer Board
ESD CAUTION
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 8 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PLANE ON T HE P CB THAT I S THERM ALL Y CO NDUCTI V E .
06591-005
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
–FB
+IN
–IN
+FB
PD
–V
S
–V
S
–V
S
–V
S
–OUT
+OUT
V
OCM
+V
S
+V
S
+V
S
+V
S
ADA4937-1
TOP VIEW
(No t t o Scal e)
Figure 5. ADA4937-1 Pin Configuration
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PL ANE ON T HE P CB THAT IS T HE RM ALL Y CONDUCTIVE .
06591-006
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–FB2
+V
S1
+V
S1
+FB1
–IN1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
ADA4937-2
TOP VIEW
(No t t o Scal e)
Figure 6. ADA4937-2 Pin Configuration
Table 7. ADA4937-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 −FB Negative Output for Feedback
Component Connection.
2 +IN Positive Input Summing Node.
3 −IN Negative Input Summing Node.
4 +FB Positive Output for Feedback
Component Connection.
5 to 8 +VS Positive Supply Voltage.
9 VOCM Output Common-Mode Voltage.
10 +OUT Positive Output for Load Connection.
11
−OUT
Negative Output for Load Connection.
12 PD Power-Down Pin.
13 to 16 −VS Negative Supply Voltage.
EP Exposed Paddle. The exposed pad is not
electrically connected to the device. It is
typically soldered to ground or a power
plane on the PCB that is thermally
conductive.
Table 8. ADA4937-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1.
2 +FB1 Positive Output Feedback Pin 1.
3, 4 +VS1 Positive Supply Voltage 1.
5 −FB2 Negative Output Feedback Pin 2.
6 +IN2 Positive Input Summing Node 2.
7 −IN2 Negative Input Summing Node 2.
8 +FB2 Positive Output Feedback Pin 2.
9, 10 +VS2 Positive Supply Voltage 2.
11 VOCM2 Output Common-Mode Voltage 2.
12 +OUT2 Positive Output 2.
13 −OUT2 Negative Output 2.
14 PD2 Power-Down Pin 2.
15, 16 −VS2 Negative Supply Voltage 2.
17 VOCM1 Output Common-Mode Voltage 1.
18 +OUT1 Positive Output 1.
19 −OUT1 Negative Output 1.
20 PD1 Power-Down Pin 1.
21, 22 −VS1 Negative Supply Voltage 1.
23 −FB1 Negative Output Feedback Pin 1.
24 +IN1 Positive Input Summing Node 1.
EP Exposed Paddle. The exposed pad is
not electrically connected to the
device. It is typically soldered to
ground or a power plane on the PCB
that is thermally conductive.
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = 0 V, VOUT, dm = 2 V p-p, VOCM = +VS/2, RT = 61.9 , RG = RF = 200 , G = 1, RL, dm = 1 kΩ, unless otherwise
noted. Refer to Figure 49 for the test setup circuit.
–15
–12
–9
–6
–3
0
3
6
1 10 100 1000
0
6591-075
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +1, R
F
= 200Ω
G = +2, R
F
= 402Ω
G = +5, R
F
= 402Ω
Figure 7. Small Signal Frequency Response for Various Gains,
VOUT, dm = 100 mV p-p
6
–15
–12
–9
–6
–3
0
3
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
V
S
= 3.3V
V
S
= 5.0V
06591-008
Figure 8. Small Signal Frequency Response for Various Supplies,
VOUT, dm = 100 mV p-p
6
–12
–9
–6
–3
0
3
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
+25°C
+105°C
–40°C
06591-009
Figure 9. Small Signal Frequency Response for Various Temperatures,
VOUT, dm = 100 mV p-p
–15
–12
–9
–6
–3
0
3
6
1 10 100 1000
06591-076
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +1, R
F
= 200Ω
G = +2, R
F
= 402Ω
G = +5, R
F
= 402Ω
Figure 10. Large Signal Frequency Response for Various Gains
6
–15
–12
–9
–6
–3
0
3
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
V
S
= 3.3V
V
S
= 5.0V
06591-011
Figure 11. Large Signal Frequency Response for Various Supplies
6
–12
–9
–6
–3
0
3
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
+25°C
+105°C
–40°C
06591-012
Figure 12. Large Signal Frequency Response for Various Temperatures
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 10 of 28
6
–9
–6
–3
0
3
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 200Ω
06591-013
Figure 13. Small Signal Frequency Response for Various Loads,
VOUT, dm = 100 mV p-p
–15
–12
–9
–6
–3
0
3
6
1 10 100 1000
06591-077
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
VS = 3.3V, G = +1, RF = 200Ω
VS = 3.3V, G = +2, RF = 402Ω
VS = 3.3V, G = +5, RF = 402Ω
Figure 14. Small Signal Frequency Response for Various Gains,
VS = 3.3 V, VOUT, dm = 100 mV p-p
–15
–12
–9
–6
–3
0
3
6
1 10 100 1000
06591-078
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +1, R
F
= 348Ω
G = +2, R
F
= 348Ω
G = +5, R
F
= 348Ω
Figure 15. Small Signal Frequency Response for Various Gains,
VOUT, dm = 100 mV p-p, RF = 348 Ω
6
–9
–6
–3
0
3
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 200Ω
06591-016
Figure 16. Large Signal Frequency Response for Various Loads
–15
–12
–9
–6
–3
0
3
6
1 10 100 1000
06591-079
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
V
S
= 3.3V, G = +1, R
F
= 200Ω
V
S
= 3.3V, G = +2, R
F
= 402Ω
V
S
= 3.3V, G = +5, R
F
= 402Ω
Figure 17. Large Signal Frequency Response for Various Gains, VS = 3.3 V
–15
–12
–9
–6
–3
0
3
6
1 10 100 1000
0
6591-080
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +1, RF = 348Ω
G = +2, RF = 348Ω
G = +5, RF = 348Ω
Figure 18. Large Signal Frequency Response for Various Gains, RF = 348 Ω
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 11 of 28
3
–12
–9
–6
–3
0
1 10 100 1000
V
OCM
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
VOCM = 1.0V
VOCM = 2.5V
VOCM = 3.9V
06591-019
Figure 19. Small Signal Frequency Response for Various VOCM
GAIN (dB)
FREQUENCY (MHz)
06591-020
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1 10 100 1000
RL = 1kΩ, ADA4937-1
RL = 100Ω, ADA4937-1
RL = 1kΩ, ADA4937-2
RL = 100Ω, ADA4937-2
Figure 20. 0.1 dB Flatness Response for Various Loads
–
55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
1 10 100
DISTORTION (dBc)
FREQUENCY (MHz)
HD2, VS = 5.0V
HD3, VS = 5.0V
HD2, VS = 3.3V
HD3, VS = 3.3V
06591-021
Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage
–
50
–60
–70
–80
–90
–100
–110
–120
1 10 100
DISTORTION (dBc)
FREQUENCY (MHz)
HD2, G = +1, RF = 200Ω
HD3, G = +1, RF = 200Ω
HD2, G = +2, RF = 402Ω
HD3, G = +2, RF = 402Ω
06591-022
Figure 22. Harmonic Distortion vs. Frequency and Gain
–
50
–60
–70
–80
–90
–100
–110
–120
1 10 100
DISTORTION (dBc)
FREQUENCY (MHz)
HD2, RL = 1kΩ
HD3, RL = 1kΩ
HD2, RL = 200Ω
HD3, RL = 200Ω
06591-023
Figure 23. Harmonic Distortion vs. Frequency and Load
–
50
–60
–70
–80
–90
–100
–110
–130
–120
–1 76543210
DISTORTION (dBc)
V
OUT
(V)
HD2, V
S
= 3.3V
HD3, V
S
= 3.3V
HD2, V
S
= 5.0V
HD3, V
S
= 5.0V
06591-024
Figure 24. Harmonic Distortion vs. VOUT and Supply Voltage
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 12 of 28
–
30
–50
–40
–60
–70
–80
–90
–100
–110
–120
1.0 4.03.53.02.52.01.5
DISTORTION (dBc)
V
OCM
(V)
HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 75MHz
HD3, f = 75MHz
06591-025
Figure 25. Harmonic Distortion vs. VOCM and Frequency
–
40
–50
–60
–70
–80
–90
–100
1.1 2.01.91.81.71.61.51.41.31.2
DISTORTION (dBc)
VOCM (V)
HD2, f = 30MHz
HD3, f = 30MHz
HD2, f = 75MHz
HD3, f = 75MHz
06591-026
Figure 26. Harmonic Distortion vs. VOCM and Frequency, VS = 3.3 V
–
50
–60
–70
–80
–90
–100
–110
–120
–130
1 10 100
DISTORTION (dBc)
FREQUENCY (MHz)
HD2, 1V p-p
HD3, 1V p-p
HD2, 2V p-p
HD3, 2V p-p
06591-027
Figure 27. Harmonic Distortion vs. Frequency and VOUT, VS = 3.3 V
0
–120
–100
–80
–60
–40
–20
69.4 69.6 70.670.470.270.069.8
DISTORTION (dBc)
FREQUENCY (MHz)
06591-028
Figure 28. 70 MHz Intermodulation Distortion
–
30
–70
–60
–50
–40
1 100010010
CMRR (dB)
FREQUENCY (MHz)
R
L
= 200Ω
06591-029
Figure 29. CMRR vs. Frequency
–60
–50
–40
–30
–20
–
10
1 10 100 1000
0
6591-068
FREQUENCY (MHz)
OUTPUT BALANCE (dB)
R
L
= 200Ω
Figure 30. Output Balance vs. Frequency
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 13 of 28
–
30
–100
–90
–80
–70
–50
–40
–60
1 10 100 1000
PSRR (dB)
FREQUENCY (MHz)
V
OUT, dm
PSRR, V
S
= 3.3V
V
OUT, dm
PSRR, V
S
= 5.0V
06591-031
Figure 31. PSRR vs. Frequency, RL = 200 Ω
0
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
1 10 100 1000
S-PARAMETERS (dB)
FREQUENCY (MHz)
S22
S11
06591-032
Figure 32. Return Loss (S11, S22) vs. Frequency
–
55
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
1 10 100
DISTORTION (dBc)
FREQUENCY (MHz)
SFDR, R
L
= 200Ω
SFDR, R
L
= 1kΩ
06591-033
Figure 33. Spurious-Free Dynamic Range vs. Frequency and Load
28
10
12
14
16
18
20
22
24
26
10 100
NOISE FIGURE (dB)
FREQUENCY (MHz)
G = +2
G = +4
G = +1
06591-034
Figure 34. Noise Figure vs. Frequency
–5
–4
–3
–2
–1
0
1
2
3
4
5
06591-069
TIME (4ns/DIV)
VOLTAGE (V)
V
IN
× 3.16
V
OUT, dm
Figure 35. Overdrive Recovery Time (Pulse Input)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0 100 200 300 400 500 600
06591-070
TIME (ns)
SIGNAL LEVEL (V)
+V
S
= +2.5V
–V
S
= –2.5V
V
IN
× 3
V
OUT, dm
Figure 36. Overdrive Amplitude Characteristics (Triangle Wave Input)
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 14 of 28
60
0
5
10
15
20
25
30
35
40
45
50
55
1.0 2.01.91.81.71.61.51.3 1.41.21.1
SUPPLY CURRENT (mA)
POWER-DOWN VOLTAGE (V)
+105°C
+55°C
+25°C
0°C
–40°C
06591-037
Figure 37. Supply Current vs. PD for Various Temperatures
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0
6591-071
TIME (1ns/DIV)
VOLTAGE (V)
+V
S
= +2.5V
–V
S
= –2.5V
V
OCM
= 0V
Figure 38. Small Signal Pulse Response
2.40
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
06591-072
TIME (2ns/DIV)
OUTPUT VOLTAGE (V)
V
S
= +5V
G = 1
R
L, dm
= 1kΩ
Figure 39. Small Signal VOCM Pulse Response
60
0
5
10
15
20
25
30
35
40
45
50
55
1.0 2.01.91.81.71.61.51.3 1.41.21.1
SUPPLY CURRENT (mA)
POWER-DOWN VOLTAGE (V)
+105°C
+55°C
+25°C
0°C
–40°C
06591-040
Figure 40. Supply Current vs. PD for Various Temperatures, VS = 3.3 V
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OUT, dm
= 4V p-p
V
OUT, dm
= 2V p-p
06591-074
TIME (1ns/DIV)
VOLTAGE (V)
+V
S
= +2.5V
–V
S
= –2.5V
V
OCM
= 0V
Figure 41. Large Signal Pulse Response
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
06591-073
TIME (2ns/DIV)
OUTPUT VOLTAGE (V)
V
S
= +5V
G = 1
R
L, dm
= 1kΩ
Figure 42. Large Signal VOCM Pulse Response
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 15 of 28
0
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
1
2
3
4
5
6
7
8
9
10
AMPLITUDE (V)
TIME (ms)
06591-043
OUTPUT
POWER-DOWN PULSE
Figure 43. PD Response vs. Time
06591-044
FREQUENCY (MHz)
CROSSTALK (dB)
–140
–120
–130
–110
–100
–90
–80
–70
–
40
–50
–60
10.3 10 100 1000
INPUT2, OUTPUT1
INPUT1, OUTPUT2
Figure 44. Crosstalk vs. Frequency for ADA4937-2
100
1
10
10 10M1M100k10k1k100
INPUT VOLTAGE NOISE (nV/ Hz)
FREQUENCY (Hz)
06591-045
Figure 45. Voltage Spectral Noise Density, RTI
10
0.1
1
0.01 1k1001010.1
IMPEDANCE (Ω)
FREQUENCY (MHz)
06591-146
G = 1
Figure 46. Closed-Loop Output Impedance
2
1
–2
1.0
–1.0
–0.5
VIN
0
0.5
0.1
–0.1
–1
0
VIN (V)
SETTLING ERROR (%)
TIME (1ns/DIV)
06591-147
SETTLING ERROR
Figure 47. 0.1% Settling Time
70
–20
50
–300
–250
–200
–150
–100
–50
0
–10
0
10
20
30
40
50
60
1 10G1G100M10M1M100k10k1k10010
OPEN-LOOP GAIN (dB)
OPEN-LOOP PHASE (Degrees)
FREQUENCY (Hz)
06591-401
PHASE
GAIN
Figure 48. Open-Loop Gain and Phase vs. Frequency
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 16 of 28
TEST CIRCUITS
ADA4937 1kΩ
5V
200
Ω
200Ω50Ω
200Ω
27.5Ω
200Ω
VOCM
61.9Ω
VIN
06591-046
Figure 49. Equivalent Basic Test Circuit
ADA4937
5V
200Ω
200Ω50Ω
200Ω
50Ω
50Ω
27.5Ω
200Ω
V
OCM
61.9Ω
V
IN
06591-047
Figure 50. Test Circuit for Output Balance
ADA4937
5V
200
Ω
200Ω50Ω
200Ω
412Ω
412Ω
27.5Ω
200Ω
V
OCM
61.9Ω
V
IN
FILTER
0.1µF
0.1µF
FILTER
06591-048
Figure 51. Test Circuit for Distortion Measurements
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 17 of 28
TERMINOLOGY
+IN
–IN +OUT
–OUT
+D
IN
–
FB
+FB
–D
IN
V
OCM
R
G
R
F
R
G
V
OUT, dm
R
L, dm
R
F
ADA4937
06591-049
Figure 52. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Common-Mode Voltage
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
Output Balance
Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the midpoint of the
divider with the magnitude of the differential signal (see Figure 50).
By this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 18 of 28
THEORY OF OPERATION
The ADA4937-1/ADA4937-2 differ from conventional
operational amplifiers in that they have two outputs whose voltages
move in opposite directions. Like an operational amplifier, they
rely on open-loop gain and negative feedback to force these
outputs to the desired voltages. The ADA4937-1/ADA4937-2
behave much like standard voltage feedback operational amplifiers,
which makes it easier to perform single-ended-to-differential
conversions, common-mode level shifting, and amplifications
of differential signals. Also like an operational amplifier, the
ADA4937-1/ADA4937-2 have high input impedance and low
output impedance.
Two feedback loops control the differential and common-mode
output voltages. The differential feedback loop, set with external
resistors, controls only the differential output voltage. The
common-mode feedback loop controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value. It is forced, by internal
common-mode feedback, to be equal to the voltage applied to
the VOCM input without affecting the differential output voltage.
The ADA4937-1/ADA4937-2 architecture results in outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. The common-
mode feedback loop forces the signal component of the output
common-mode voltage to zero. This results in nearly perfectly
balanced differential outputs that are identical in amplitude and
are exactly 180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The ADA4937-1/ADA4937-2 use open-loop gain and negative
feedback to force their differential and common-mode output
voltages in such a way as to minimize the differential and
common-mode error voltages. The differential error voltage is
defined as the voltage between the differential inputs labeled
+IN and −IN (see Figure 52). For most purposes, this voltage
can be assumed to be zero. Similarly, the difference between the
actual output common-mode voltage and the voltage applied to
VOCM can also be assumed to be zero. Starting from these two
assumptions, any application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 52 can be
determined by
G
F
dmIN
dmOUT
R
R
V
V
,
,
This assumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
To estimate the differential output noise of the ADA4937-1/
ADA4937-2 use the noise model in Figure 53. The input-referred
noise voltage density, vnIN, is modeled as a differential input, and
the noise currents, inIN− and inIN+, appear between each input and
ground. The noise currents are assumed to be equal and produce
a voltage across the parallel combination of the gain and feedback
resistances. vn, cm is the noise voltage density at the VOCM pin. Each
of the four resistors contributes (4kTRx)1/2. Table 9 summarizes
the input noise sources, the multiplication factors, and the output-
referred noise density terms.
ADA4937
+
R
F2
V
nOD
V
nCM
V
OCM
V
nIN
R
F1
R
G2
R
G1
V
nRF1
V
nRF2
V
nRG1
V
nRG2
i
nIN+
i
nIN–
06591-050
Figure 53. ADA4937-1/ADA4937-2 Noise Model
Table 9. Output Noise Voltage Density Calculations
Input Noise Contribution Input Noise Term Input Noise Voltage Density Output Multiplication Factor
Output Noise Voltage
Density Term
Differential Input vnIN v
nIN G
N v
nO1 = GN(vnIN)
Inverting Input inIN− inIN− × (RG2||RF2) GN v
nO2 = GN[inIN− × (RG2||RF2)]
Noninverting Input inIN+ inIN+ × (RG1||RF1) GN v
nO3 = GN[inIN+ × (RG1||RF1)]
VOCM Input vn, cm v
n, cm G
N(β1 − β2) vnO4 = GN(β1 − β2)(vn, cm)
Gain Resistor RG1 v
nRG1 (4kTRG1)1/2 G
N(1 − β1) vnO5 = GN(1 − β1)(4kTRG1)1/2
Gain Resistor RG2 v
nRG2 (4kTRG2)1/2 G
N(1 − β2) vnO6 = GN(1 − β2)(4kTRG2)1/2
Feedback Resistor RF1 v
nRF1 (4kTRF1)1/2 1 vnO7 = (4kTRF1)1/2
Feedback Resistor RF2 v
nRF2 (4kTRF2)1/2 1 vnO8 = (4kTRF2)1/2
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 19 of 28
Similar to the case of a conventional operational amplifier, the
output noise voltage densities can be estimated by multiplying
the input-referred terms at +IN and −IN by the appropriate output
factor, where:

21
N
ββ
G
2 is the circuit noise gain.
G1
F1
G1
1RR
R
β
and
G2
F2
G2
2RR
R
β
are the feedback factors.
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
becomes
G
F
NR
R
β
G 1
1
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
8
1i
2
nOinOD vv
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned in the Setting the Closed-Loop Gain
section), even if the external feedback networks (RF/RG) are
mismatched, the internal common-mode feedback loop still
forces the outputs to remain balanced. The amplitudes of the
signals at each output remain equal and 180° out of phase. The
input-to-output differential mode gain varies proportionately to
the feedback mismatch, but the output balance is unaffected.
As well as causing a noise contribution from VOCM, ratio matching
errors in the external resistors result in a degradation of the
ability of the circuit to reject input common-mode signals, much
the same as for a four-resistor difference amplifier made from a
conventional operational amplifier.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = 1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of approximately 40 dB, a worst-case
differential-mode output offset of 25 mV due to 2.5 V level
shift, and no significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 54, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
+V
S
ADA4937
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
06591-051
Figure 54. ADA4937-1/ADA4937-2 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 55),
the input impedance is

F
G
F
G
cmIN
RR
R
R
R
2
1
,
R
T
R
S
ADA4937
+V
S
R
F
R
G
R
S
R
G
R
F
V
OCM
R
T
V
OUT, dm
06591-052
Figure 55. ADA4937-1/ADA4937-2 Configured for Unbalanced
(Single-Ended) Input
The input impedance of the circuit is effectively higher than it is
for a conventional operational amplifier connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the Input Gain Resistor RG.
Terminating a Single-Ended Input
This section explains how to properly terminate a single-ended
input to the ADA4937-1/ADA4937-2. Using a simple example
with an input source of 2 V and a source resistor of 50 Ω, four
simple steps must be followed.
1. The input impedance must be calculated using the formula
267
)200200(2
200
1
200
)(2
1
F
G
F
G
IN
RR
R
R
R
06591-081
ADA4937
R
L
V
O
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
200Ω
R
F
200Ω
V
OCM
V
S
2V
R
IN
267Ω
Figure 56. Single-Ended Input Impedance RIN
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 20 of 28
2. For the source termination to be 50 Ω, the termination
resistor (RT) is calculated using RT||RIN = 50 Ω, which
makes RT equal to 61.9 Ω.
06591-082
ADA4937
R
L
V
O
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
200Ω
R
F
200Ω
V
OCM
V
S
2V
50Ω
R
T
61.9Ω
Figure 57. Adding Termination Resistor RT
3. To compensate for the imbalance of the gain resistors,
a correction resistor (RTS) is added in series with the
inverting Input Gain Resistor RG. RTS is equal to the
Thevenin equivalent of the Source Resistance RS||RT.
06591-083
R
S
50Ω
V
S
2V
R
T
61.9Ω
R
TH
27.4Ω
V
TH
1.1V
Figure 58. Calculating Thevenin Equivalent
RTS = RTH = RS||RT = 27.4 Ω. Note that VTH is not equal to VS/2,
which is the case if the termination is not affected by the
amplifier circuit.
06591-084
ADA4937
R
L
V
O
0.97V
+V
S
–V
S
R
TH
27.4Ω
R
G
200Ω
R
G
200Ω
R
F
200Ω
R
F
200Ω
V
OCM
V
TH
1.1V
R
TS
27.4Ω
Figure 59. Balancing Gain Resistor RG
4. The feedback resistor is calculated to adjust the output
voltage.
a. To make the output voltage VOUT = 1 V, RF must be
calculated using the following formula:
207
1.1
)4.27200(1
)(
TH
TS
G
OUT
FV
RRV
R
To make VO = VS = 2 V to recover the loss due to the input
termination, RF must be
414
1.1
)4.27200(2
)(
TH
TS
G
OUT
FV
RRV
R
06591-085
ADA4937
R
L
V
O
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
R
F
V
OCM
V
S
2V
R
T
61.9Ω
R
TS
27.4Ω
Figure 60. Complete Single-Ended-to-Differential System
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The ADA4937-1/ADA4937-2 are optimized for level-shifting
ground-referenced input signals. As such, the center of the input
common-mode range is shifted approximately 1 V down from
midsupply. For 5 V single-supply operation, the input common-
mode range at the summing nodes of the amplifier is 0.3 V to
3.0 V, and 0.3 V to 1.2 V with a 3.3 V supply. To avoid clipping
at the outputs, the voltage swing at the +IN and −IN terminals
must be confined to these ranges.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4937-1/ADA4937-2 is internally biased
at a voltage approximately equal to the midsupply point, [(+VS) +
(−VS)]/2. Relying on this internal bias results in an output
common-mode voltage that is within about 100 mV of the
expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external source,
or resistor divider (10 kΩ or greater resistors), be used. The output
common-mode offset listed in Table 2 and Table 4 assumes that the
VOCM input is driven by a low impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4937-1/ADA4937-2 devices share one reference output, it is
recommended that a buffer be used.
Table 10 and Table 11 list several common gain settings, asso-
ciated resistor values, input impedances, and output noise density
values for both balanced and unbalanced input configurations.
POWER-DOWN OPERATION
The ADA4937-1/ADA4937-2 power-down pin features an
internal 25 k pull-up resistor to the positive supply (+VS).
This ensures that, with the power-down pin left unconnected
(floating), the ADA4937-1/ADA4937-2 turn on. Applying a
voltage of ≤1 V turns the ADA4937-1/ADA4937-2 off.
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 21 of 28
Table 10. Differential Ground-Referenced Input, DC-Coupled, 1 kΩ Load; See Figure 54
Nominal Gain (dB) RF (Ω) RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
0 200 200 400 5.8
6 402 200 400 9.6
10 402 127 254 12.1
14 402 80.6 161 16.2
Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, RL = 1 kΩ; See Figure 55
Nominal Gain (dB) RF (Ω) RG1 (Ω) RT (Ω) RIN, cm (Ω) RG2 (Ω)1 Differential Output Noise Density (nV/√Hz)
0 200 200 61.9 267 226 5.5
6 402 200 60.4 301 228 8.6
10 402 127 66.5 205 155 10.1
14 402 80.6 76.8 138 111 12.2
1 RG2 = RG1 + (RS||RT)
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 22 of 28
LAYOUT, GROUNDING, AND BYPASSING
As high speed devices, the ADA4937-1/ADA4937-2 are sensitive
to the PCB environment in which they operate. Realizing their
superior performance requires attention to the details of high
speed PCB design. This section shows a detailed example of
how the design issues of the ADA4937-1 is addressed.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4937-1 as possible.
However, the area near the feedback resistors (RF), input gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3)
must be cleared of all ground and power planes (see Figure 61).
Clearing the ground and power planes minimizes any stray capa-
citance at these nodes and prevents peaking of the response of
the amplifier at high frequencies.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
06591-086
Figure 61. Ground and Power Plane Voiding in Vicinity of RF and RG
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended that two parallel bypass capaci-
tors (1000 pF and 0.1 µF) be used for each supply with the 1000 pF
capacitor placed closer to the device; further away, provide low
frequency bypassing using 10 µF tantalum capacitors from each
supply to ground.
Signal routing must be short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a sym-
metrical layout to maximize balanced performance. When
routing differential signals over a long distance, keep PCB
traces close together and twist any differential wiring to mini-
mize loop area. Doing this reduces radiated energy and makes
the circuit less susceptible to interference.
06591-087
1.30
0.80
0.80
1.30
Figure 62. Recommended PCB Thermal Attach Pad Dimensions (mm)
06591-088
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
Figure 63. Cross-Section of 4-layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 23 of 28
HIGH PERFORMANCE ADC DRIVING
The ADA4937-1/ADA4937-2 are ideally suited for broadband IF
applications. The circuit in Figure 64 shows a front-end connection
for an ADA4937-1 driving an AD9445, 14-bit, 105 MSPS ADC.
The AD9445 achieves optimum performance when driven
differentially. The ADA4937-1/ADA4937-2 eliminate the need for
a transformer to drive the ADC and performs a single-ended-
to-differential conversion and buffering of the driving signal.
The ADA4937-1/ADA4937-2 are configured with a single 5 V
supply and unity gain for a single-ended input to differential
output. The 61.9 Ω termination resistor, in parallel with the single-
ended input impedance of 267 Ω, provides a 50 Ω termination
for the source. The additional 26 Ω (226 Ω total) at the inverting
input balances the parallel impedance of the 50 Ω source and the
termination resistor driving the noninverting input.
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4937-1/ADA4937-2
remains unconnected allowing the internal divider to set the
output common-mode voltage at midsupply; one half of the
common-mode voltage is fed back to the summing nodes, biasing
−IN and +IN at 1.25 V. For a common-mode voltage of 2.5 V,
each ADA4937-1/ADA4937-2 output swings between 2.0 V and
3.0 V, providing a 2 V p-p differential output.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 64.
VIN–
VIN+
47pF
30nH
30nH
24.3Ω
24.3Ω
50Ω
SIGNAL
GENERATOR 226Ω
200Ω
V
OCM
5V
ADA4937-1
+
61.9Ω
200Ω
200
Ω
14
BUFFER T/H
ADC
CLOCK/
TIMING REF
SENSEAGND
0.1µF
0.1µF
AD9445
3.3V (A)
AVDD1
5V (A)
AVDD2
3.3V (D)
DRVDD
06591-054
Figure 64. Driving an AD9445, 14-Bit, 105 MSPS ADC
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 24 of 28
The circuit in Figure 66 shows a simplified front-end connection
for an ADA4937-1 driving an AD9246, 14-bit, 125 MSPS ADC.
The AD9246 achieves optimum performance when driven
differentially. The ADA4937-1/ADA4937-2 perform the single-
ended-to-differential conversion, eliminating the need for a
transformer to drive the ADC.
The ADA4937-1/ADA4937-2 are configured with a single 5 V
supply and a gain of ~2 V/V for a single-ended input to
differential output. The 76.8 Ω termination resistor, in parallel
with the single-ended input impedance of 137 Ω, provides a 50 Ω
ac termination for the source. The additional 30 Ω (120 Ω total) at
the inverting input balances the parallel ac impedance of the
50 Ω source and the termination resistor driving the
noninverting input.
The signal generator has a symmetric, ground-referenced bipolar
output. The VOCM pin of the ADA4937-1/ADA4937-2 remains
unconnected; therefore, the internal pull-ups set the output
common-mode voltage to midsupply. A portion of this is fed back
to the summing nodes, biasing −IN and +IN at 0.55 V. For a
common-mode voltage of 2.5 V, each ADA4937-1/ADA4937-2
output swings between 2.0 V and 3.0 V, providing a 2 V p-p
differential output.
The output is ac-coupled to a single-pole, low-pass filter. This
reduces the noise bandwidth of the amplifier and provides some
level of isolation from the switched capacitor inputs of the ADC.
The AD9246 is set for a 2 V p-p full-scale input by connecting
the SENSE pin to AGND. The inputs of the AD9246 are biased
at 1 V by connecting the CML output, as shown in Figure 66.
The circuit was tested with a −1 dBFS signal at various frequencies.
Figure 65 shows a plot of the second- and third-order harmonic
distortion (HD2/HD3) vs. frequency.
–
75
–80
–85
–90
–95
–100
0 1208040 1006020
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD2
HD3
G = +2
06591-055
Figure 65. HD2/HD3 for Combination of ADA4937-1/ADA4937-2 and
AD9246 ADC
1.8V
DRVDDAVDD
VIN–
VIN+
AD9246
AGND CMLSENSE
D13 TO
D0
10pF
10µF
10µF
10µF
33Ω
33Ω
200Ω
200Ω
50Ω
V
IN
90Ω
90Ω
76.8Ω5V
ADA4937-1
+
200Ω
200Ω
50Ω76.8Ω
10µF
06591-056
Figure 66. Driving an AD9246, 14-Bit, 125 MSPS ADC
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 25 of 28
3.3 V OPERATION
The ADA4937-1/ADA4937-2 provide excellent performance in
3.3 V single-supply applications. Significant power savings can
be realized when the ADA4937-1/ADA4937-2 are used in
combination with a low voltage ADC.
The circuit in Figure 67 is an example of the ADA4937-1 driving
an AD9230, 12-bit, 250 MSPS ADC that is specified to operate with
a single 1.8 V supply. The performance of the ADC is optimized
when it is driven differentially, making the best use of the signal
swing available within the 1.8 V supply. The ADA4937-1/
ADA4937-2 perform the single-ended-to-differential conversion,
common-mode level-shifting, and buffering of the driving signal.
The ADA4937-1/ADA4937-2 are configured with a single 3.3 V
supply and a gain of 2 V/V for a single-ended input to differential
output. The 59 Ω termination resistor, in parallel with the single-
ended input impedance of 306 Ω, provides a 50 Ω termination for
the source. The additional 26 Ω (226 Ω total) at the inverting input
balances the parallel impedance of the 50 Ω source and the
termination resistor that drives the noninverting input. The signal
generator has a symmetric, ground-referenced bipolar output. The
VOCM pin is connected to the CML output of the AD9230, and sets
the output common mode of the ADA4937-1/ADA4937-2 at 1.4 V.
One third of the output common-mode voltage of the amplifier is
fed back to the summing nodes, biasing −IN and +IN at ~0.5 V.
For a common-mode voltage of 1.4 V, each ADA4937-1/
ADA4937-2 output swings between 1.09 V and 1.71 V,
providing a 1.25 V p-p differential output.
A third-order, 125 MHz, low-pass filter between the ADA4937-1/
ADA4937-2 and the AD9230 reduces the noise bandwidth of
the amplifier and isolates the driver outputs from the ADC inputs.
1.8V
DRVDDAVDD
VIN–
VIN+
AD9230
AGND CML
D11 TO
D0
30pF10pF
56nH
56nH
33Ω
33Ω
50Ω
VIN
226Ω
200Ω
VOCM
3.3V
ADA4937-1
+
59Ω
453Ω
453
Ω
06591-057
Figure 67. Driving an AD9230, 12-Bit, 250 MSPS ADC
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 26 of 28
OUTLINE DIMENSIONS
1.45
1.30 SQ
1.15
111808-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12 13
4
EXPOSED
PAD
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.50
0.40
0.30
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS M O-220- WEED.
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGD-8.
06-11-2012-A
BOTTOM VIEWTOP VI EW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
2.20
2.10 SQ
2.00
1
24
7
12
13
1819
6
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.05 M AX
0.02 NO M
Figure 69. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity Branding
ADA4937-1YCPZ-R2 −40°C to +105°C 16-Lead LFCSP CP-16-21 250 H1S
ADA4937-1YCPZ-RL −40°C to +105°C 16-Lead LFCSP CP-16-21 5,000 H1S
ADA4937-1YCPZ-R7 −40°C to +105°C 16-Lead LFCSP CP-16-21 1,500 H1S
ADA4937-2YCPZ-R2 −40°C to +105°C 24-Lead LFCSP CP-24-10 250
ADA4937-2YCPZ-RL −40°C to +105°C 24-Lead LFCSP CP-24-10 5,000
ADA4937-2YCPZ-R7 −40°C to +105°C 24-Lead LFCSP CP-24-10 1,500
1 Z = RoHS Compliant Part.
Data Sheet ADA4937-1/ADA4937-2
Rev. F | Page 27 of 28
NOTES
ADA4937-1/ADA4937-2 Data Sheet
Rev. F | Page 28 of 28
NOTES
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