CS8151CGN8 - ON Semiconductor

October, 2008 − Rev. 18

1Publication Order Number:

CS8151/D

CS8151

5.0 V, 100 mA Low Dropout

Linear Regulator with

Watchdog, RESET,

and Wake Up

The CS8151 is a precision 5.0 V, 100 mA micro−power voltage

regulator with very low quiescent current (400 mA typical at 200 mA

load). The 5.0 V output is accurate within ±2% and supplies 100 mA

of load current with a typical dropout voltage of 400 mV.

Microprocessor control logic includes Watchdog, Wake Up and

RESET. This unique combination of low quiescent current and full

microprocessor control makes the CS8151 ideal for use in battery

operated, microprocessor controlled equipment.

The CS8151 Wake Up function brings the microprocessor out of

Sleep mode. The microprocessor in turn, signals its Wake Up status

back to the CS8151 by issuing a Watchdog signal.

The Watchdog logic function monitors an input signal (WDI) from

the microprocessor. The CS8151 responds to the falling edge of the

Watchdog signal which it expects at least once during each wake−up

period. When the correct Watchdog signal is received, a falling edge is

issued on the wake−up signal line.

RESET is independent of VIN and operates correctly to an output

voltage as low as 1.0 V. A RESET signal is issued in any of three

situations. During power up the RESET is held low until the output

voltage is in regulation. During operation if the output voltage shifts

below the regulation limits, the RESET toggles low and remains low

until proper output voltage regulation is restored. And finally, a

RESET signal is issued if the regulator does not receive a Watchdog

signal within the Wake Up period.

The RESET pulse width, Wake Up signal frequency, and Wake Up

delay time are all set by one external capacitor CDelay.

The regulator is protected against short circuit, over voltage, and

thermal runaway conditions. The device can withstand 74 V peak

transients, making it suitable for use in automotive environments.

Features

•5.0 V ± 2%/100 mA Output Voltage

•Micropower Compatible Control Functions

♦Wake Up

♦Watchdog

♦RESET

•Low Dropout Voltage: 400 mV @ 100 mA

•Low Sleep Mode Quiescent Current (400 mA Typ)

•Protection Features

♦Thermal Shutdown

♦Short Circuit

♦74 V Peak Transient Capability

♦Reverse Transient (−50 V)

•Internally Fused Leads in SO−14L and SO−16L Packages

•These are Pb−Free Devices

SO−16L

DWF SUFFIX

CASE 751G

D2PAK−7

DPS SUFFIX

CASE 936AB 1

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 11 of this data sheet.

ORDERING INFORMATION

SOIC−14

D SUFFIX

CASE 751A

See general marking information in the device marking

section on page 2 of this data sheet.

DEVICE MARKING INFORMATION

CS8151

http://onsemi.com

PIN CONNECTIONS AND MARKING DIAGRAMS

VIN

VOUT

Sense

WDI

GND

GND GND

GND

Wake Up

NC RESET

NC Delay

CS8151G

AWLYWW

SO−16L

CASE 751G

CS8151

AWLYYWWG

161

114

GND

Sense

VOUT

Delay RESET

Wake Up

GND

WDI

VIN

SO−14L

CASE 751A

A = Assembly Location

WL = Wafer Lot

Y, YY = Year

WW = Work Week

G = Pb−Free Package

D2PAK−7

CASE 936AB

8151

AWLYWWG

Tab = GND

Pin 1. VOUT

2. VIN

3. WDI

4. GND

5. Wake Up

6. RESET

7. Delay

Figure 1. Block Diagram

VIN

Delay

WDI

RESET

VOUT

Wake Up

Sense

GND

Overvoltage

Shutdown

Current Source

(Circuit Bias) Current

Limit

Sense

Wake Up

Circuit

+−

Timing

Circuit

Watchdog

Circuit

Thermal

Shutdown

Falling Edge

Detector

Bandgap

Reference

RESET

Circuit

Error

Amplifier

VOUT

Internally

connected

on D2PAK

CS8151

http://onsemi.com

MAXIMUM RATINGS*

Rating Value Unit

Power Dissipation Internally Limited −

Output Current (VOUT

, RESET, Wake Up) Internally Limited −

Reverse Battery −15 V

Peak Transient Voltage (60 V Load Dump @ VIN = 14 V) +74 V

Maximum Negative Transient (t < 2.0 ms) −50 V

ESD Susceptibility (Human Body Model) 2.0 kV

ESD Susceptibility (Machine Model) 200 V

Logic Inputs/Outputs −0.3 to +6.0 V

Storage Temperature Range −55 to +150 °C

Lead Temperature Soldering Wave Solder (through hole styles only) (Note 1)

Reflow (SMD styles only) (Notes 2 & 3)

260 peak

240 peak

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. 10 seconds max

2. 60 seconds max above 183°C

3. −5°C / +0°C allowable conditions

*The maximum package power dissipation must be observed

ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 125°C, −40°C ≤ TJ ≤ 150°C, 6.0 V ≤ VIN ≤ 26 V, 100 mA ≤ IOUT ≤ 100 mA,

C2 = 47 mF (ESR < 8.0 W), CDelay = 0.1 mF; unless otherwise specified.)

Characteristic Test Conditions Min Typ Max Unit

Output Section

Output Voltage, VOUT 9.0 V < VIN < 16 V

6.0 V < VIN < 26 V, 0 < IOUT < 100 mA

4.90

4.85

5.0

5.10

5.15

Dropout Voltage (VIN − VOUT) IOUT = 100 mA

IOUT = 100 mA

−

400

100

600

150

Load Regulation VIN = 14 V, 100 mA < IOUT < 100 mA −10 50 mV

Line Regulation IOUT = 1.0 mA, 6.0 V < VIN < 26 V −10 50 mV

Ripple Rejection 7.0 V < VIN < 17 V @ f = 120 Hz, IOUT = 100 mA 60 75 −dB

Current Limit VOUT = 4.5 V 100 250 −mA

Thermal Shutdown −150 180 210 °C

Overvoltage Shutdown VOUT < 1.0 V 50 56 62 V

Quiescent Current IOUT = 200 mA (Sleep)

IOUT = 50 mA

IOUT = 100 mA (Wake Up)

−

0.4

4.0

0.75

−

Reverse Current VOUT = 5.0 V, VIN = 0 V −1.0 1.5 mA

RESET

Threshold High (RTH) RTH VOUT Increasing VOUT − 0.3 −VOUT − 0.04 V

Threshold Low (RTL) RTL VOUT Decreasing 4.5 4.7 4.91 V

Hysteresis RTH − RTL 150 200 250 mV

Output Low 1.0 V < VOUT RTL, IOUT = 25 mA−0.2 0.8 V

Output High IOUT = 25 mA, VOUT > RTH 3.8 4.2 5.1 V

CS8151

http://onsemi.com

ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 125°C, −40°C ≤ TJ ≤ 150°C, 6.0 V ≤ VIN ≤ 26 V, 100 mA ≤ IOUT ≤ 100 mA,

C2 = 47 mF (ESR < 8.0 W), CDelay = 0.1 mF; unless otherwise specified.)

Characteristic UnitMaxTypMinTest Conditions

RESET

Current Limit RESET = 0 V, VOUT > VRTH (Sourcing)

RESET = 5.0 V, VOUT > 1.0 V (Sinking)

0.025

0.1

0.5

1.30

Delay Time POR Mode 3.0 5.0 7.0 ms

Watchdog Input

Threshold High − − 1.4 2.0 V

Threshold Low −0.8 1.3 −V

Hysteresis −25 100 −mV

Input Current 0 < WDI < 6.0 V −10 0 +10 mA

Pulse Width 50% WDI Falling Edge to

50% WDI Rising Edge and

50% WDI Rising Edge to

50% WDI Falling Edge

(see Figures 2, 3, and 4)

5.0 − − ms

Wake Up Output

Wake Up Period See Figure 2 30 40 50 ms

Wake Up Duty Cycle Nominal See Figure 4 40 50 60 %

RESET High to

Wake Up Rising Delay Time

50% RESET Rising Edge to

50% Wake Up Edge

(see Figures 2, 3, and 4)

15 20 25 ms

Wake Up Response to

Watchdog Input

50% WDI Falling Edge to

50% Wake Up Falling Edge

−2.0 10 ms

Wake Up Response to

RESET

50% RESET Falling Edge to

50% Wake Up Falling Edge,

VOUT = 5.0 V → 4.5 V

−2.0 10 ms

Output Low IOUT = 25 mA (Sinking) −0.2 0.8 V

Output High IOUT = 25 mA (Sourcing) 3.8 4.2 5.1 V

Current Limit Wake Up = 5.0 V

Wake Up = 0 V

0.025

0.05

1.0

−

7.0

3.5

CS8151

http://onsemi.com

PACKAGE PIN DESCRIPTION

Package Pin #

Symbol Function

SO−14L D2PAK SO−16L

7 1 8 VOUT Regulated output voltage 5.0 V ± 2%.

8 2 9 VIN Supply voltage to the IC.

9 3 11 WDI CMOS/TTL compatible input lead. The Watchdog function monitors the falling

edge of the incoming signal.

3−5,

10−12

44, 5, 6, 12, 13* GND Ground connection.

13 5 14 Wake Up CMOS/TTL compatible output consisting of a continuously generated signal used

to Wake Up the microprocessor from sleep mode.

14 6 15 RESET CMOS/TTL compatible output lead RESET goes low whenever VOUT drops by

more than 6.0% from nominal, or during the absence of a correct watchdog

signal.

1 7 16 Delay Input lead from timing capacitor for RESET and Wake Up signal.

6−7 Sense Kelvin connection which allows remote sensing of the output voltage for im-

proved regulation. If remote sensing is not required, connect to VOUT

*Pin 6 GND is not directly shorted to the fused paddle GND. The fused paddle GND (pins 4, 5, 12, 13) is connected through the substrate.

Pin 6 must be electrically connected to at least one of the fused paddle GND’s on the PC board.

CS8151

http://onsemi.com

TIMING DIAGRAMS

Watchdog

Pulse Width

VIN

RESET

Wake Up

WDI

VOUT

Wake Up

Duty Cycle = 50%

Power Up Sleep Mode Normal Operation with Varying Watchdog Signal

RESET High

to Wake Up

Delay Time

POR

Figure 2. Power Up, Sleep Mode and Normal Operation

Figure 3. Error Condition: Watchdog Remains Low and a RESET Is Issued

VIN

RESET

Wake Up

WDI

VOUT

POR

RESET High

to Wake Up

Delay Time

RESET Delay Time

RESET High

to Wake Up

Delay Time

Wake Up

Period

POR

RESET

Wake Up

WDI

VOUT

Watchdog Pulse Width

RTL

POR

Power Down

Wake Up Period

Figure 4. Power Down and Restart Sequence

CS8151

http://onsemi.com

DEFINITION OF TERMS

Dropout Voltage: The input−output voltage differential

at which the circuit ceases to regulate against further

reduction in input voltage. Measured when the output

voltage has dropped 100mV from the nominal value

obtained at 14V input, dropout voltage is dependent upon

load current and junction temperature.

Input Voltage: The DC voltage applied to the input

terminals with respect to ground.

Line Regulation: The change in output voltage for a

change in the input voltage. The measurement is made

under conditions of low dissipation or by using pulse

techniques such that the average chip temperature is not

significantly affected.

Load Regulation: The change in output voltage for a

change in load current at constant chip temperature.

Quiescent Current: The part of the positive input current

that does not contribute to the positive load current. The

regulator ground lead current.

Ripple Rejection: The ratio of the peak−to−peak input

ripple voltage to the peak−to−peak output ripple voltage.

Current Limit: Peak current that can be delivered to the

output.

CIRCUIT DESCRIPTION

Functional Description

To reduce the drain on the battery a system can go into a

low current consumption mode when ever its not performing

a main routine. The Wake Up signal is generated

continuously and is used to interrupt a microcontroller that

is in sleep mode. The nominal output is a 5.0 V square wave

with a duty cycle of 50% at a frequency that is determined

by a timing capacitor, CDelay.

When the microprocessor receives a rising edge from the

Wake Up output, it must issue a watchdog pulse and check

its inputs to decide if it should resume normal operations or

remain in the sleep mode.

Figure 5. Wake Up Response to WDI

Wake Up

Response

to WDI

Wake Up

WDI

Figure 6. Wake Up Response to RESET (Low Voltage)

Wake Up

Response

to RESET

RESET

Wake Up

The first falling edge of the watchdog signal causes the

Wake Up to go low within 2.0 ms (Typ) and remain low until

the next Wake Up cycle (see Figure 5). Other watchdog

pulses received within the same cycle are ignored (Figures

2, 3, and 4).

During power up, RESET is held low until the output

voltage is in regulation. During operation, if the output

voltage shifts below the regulation limits, the RESET

toggles low and remains low until proper output voltage

regulation is restored. After the RESET delay, RESET

returns high.

The Watchdog circuitry continuously monitors the input

watchdog signal (WDI) from the microprocessor. The

absence of a falling edge on the Watchdog input during one

Wake Up cycle will cause a RESET pulse to occur at the end

of the Wake Up cycle (see Figure 3).

The Wake Up output is pulled low during a RESET

regardless of the cause of the RESET. After the RESET

returns high, the Wake Up cycle begins again (see Figure 3).

The RESET pulse width, Wake Up signal frequency and

RESET high to Wake Up delay time are all set by one

external capacitor CDelay.

Wake Up Period = (4 × 105)CDelay

RESET Delay Time = (5 × 104)CDelay

RESET High to Wake Up Delay Time = (2 × 105)CDelay

Capacitor temperature coefficient and tolerance as well as

the tolerance of the CS8151 must be taken into account in

order to get the correct system tolerance for each parameter.

CS8151

http://onsemi.com

APPLICATION NOTES

Operation Without Watchdog

The CS8151 can be operated without the watchdog

functionality by connecting the WDI and Wake Up Pins.

This will eliminate false resets from occurring. Without the

connection, a reset would occur because a watchdog signal

on WDI would not occur in the required time frame. The

Wake Up Pin provides the watchdog signal into the

WDI Pin.

Figure 7. Device Operation Without Watchdog Function

VIN

CDelay

VOUT

WDI

RESET

GND

CS8151 Microprocessor

Wake Up

CDelay

C1 C2

VCC

RESET

Battery

Output Stage Protection

The output stage is protected against overvoltage, short

circuit and thermal runaway conditions (see Figure 8).

If the input voltage rises above the overvoltage shutdown

threshold (e.g. load dump), the output shuts down. This

response protects the internal circuitry and enables the IC to

survive unexpected voltage transients.

Should the junction temperature of the power device

exceed 180°C (Typ) the power transistor is turned off.

Thermal shutdown is an effective means to prevent die

overheating since the power transistor is the principle heat

source in the IC.

Figure 8. Typical Circuit Waveforms for Output

Stage Protection

VIN

VOUT

IOUT

> 50 V

Load

Dump

Short

Circuit

Thermal

Shutdown

Stability Considerations

The output or compensation capacitor C2 (see Figure 9)

helps determine three main characteristics of a linear

regulator: startup delay, load transient response and loop

stability.

Figure 9. Test and Application Circuit Showing

Output Compensation

CS8151

VIN

C1*

0.1 mF

VOUT

RESET

C2**

10 mF

*C1 required if regulator is located far from the power

supply filter.

**C2 required for stability.

RRST

The capacitor value and type should be based on cost,

availability, size and temperature constraints. A tantalum or

aluminum electrolytic capacitor is best, since a film or

ceramic capacitor with almost zero ESR can cause

instability. The aluminum electrolytic capacitor is the least

expensive solution, but, if the circuit operates at low

temperatures (−25°C to −40°C), both the value and ESR of

CS8151

http://onsemi.com

the capacitor will vary considerably. The capacitor

manufacturers data sheet usually provide this information.

The value for the output capacitor C2 shown in the test and

applications circuit should work for most applications,

however it is not necessarily the optimized solution.

To determine an acceptable value for C2 for a particular

application, start with a tantalum capacitor of the

recommended value and work towards a less expensive

alternative part.

Step 1: Place the completed circuit with a tantalum

capacitor of the recommended value in an environmental

chamber at the lowest specified operating temperature and

monitor the outputs with an oscilloscope. A decade box

connected in series with the capacitor will simulate the

higher ESR of an aluminum capacitor. Leave the decade box

outside the chamber, the small resistance added by the

longer leads is negligible.

Step 2: With the input voltage at its maximum value,

increase the load current slowly from zero to full load while

observing the output for any oscillations. If no oscillations

are observed, the capacitor is large enough to ensure a stable

design under steady state conditions.

Step 3: Increase the ESR of the capacitor from zero using

the decade box and vary the load current until oscillations

appear. Record the values of load current and ESR that cause

the greatest oscillation. This represents the worst case load

conditions for the regulator at low temperature.

Step 4: Maintain the worst case load conditions set in step

3 and vary the input voltage until the oscillations increase.

This point represents the worst case input voltage

conditions.

Step 5: If the capacitor is adequate, repeat steps 3 and 4

with the next smaller valued capacitor. A smaller capacitor

will usually cost less and occupy less board space. If the

output oscillates within the range of expected operating

conditions, repeat steps 3 and 4 with the next larger standard

capacitor value.

Step 6: Test the load transient response by switching in

various loads at several frequencies to simulate its real

working environment. Vary the ESR to reduce ringing.

Step 7: Raise the temperature to the highest specified

operating temperature. Vary the load current as instructed in

step 5 to test for any oscillations.

Once the minimum capacitor value with the maximum

ESR is found, a safety factor should be added to allow for the

tolerance of the capacitor and any variations in regulator

performance. Most good quality aluminum electrolytic

capacitors have a tolerance of ±20% so the minimum value

found should be increased by at least 50% to allow for this

tolerance plus the variation which will occur at low

temperatures. The ESR of the capacitor should be less than

50% of the maximum allowable ESR found in step 3 above.

Calculating Power Dissipation

In a Single Output Linear Regulator

The maximum power dissipation for a single output

regulator (Figure 10) is:

PD(max) +(VIN(max) *VOUT(min))IOUT(max)

)VIN(max)IQ

(1)

where:

VIN(max) is the maximum input voltage,

VOUT(min) is the minimum output voltage,

IOUT(max) is the maximum output current for the

application, and

IQ is the quiescent current the regulator consumes at

IOUT(max).

Once the value of PD(max) is known, the maximum

permissible value of RqJA can be calculated:

RqJA +150C*TA

(2)

The value of RqJA can then be compared with those in the

package section of the data sheet. Those packages with

RqJA

’s less than the calculated value in equation 2 will keep

the die temperature below 150°C.

SMART

REGULATOR®

Control

Features

IOUT

IIN

Figure 10. Single Output Regulator with Key

Performance Parameters Labeled

VIN VOUT

}

In some cases, none of the packages will be sufficient to

dissipate the heat generated by the IC, and an external

heatsink will be required.

A heat sink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

Heat Sinks

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed to

determine the value of RqJA:

RqJA +RqJC )RqCS )RqSA (3)

where:

RqJC = the junction−to−case thermal resistance,

RqCS = the case−to−heatsink thermal resistance, and

RqSA = the heatsink−to−ambient thermal resistance.

RqJC appears in the package section of the data sheet. Like

RqJA, it too is a function of package type. RqCS and RqSA are

functions of the package type, heatsink and the interface

between them. These values appear in heatsink data sheets

of heatsink manufacturers.

CS8151

http://onsemi.com

PACKAGE THERMAL DATA

Parameter D2PAK−7 SOIC−14 SOIC−16 Unit

RqJC Typical 1.8 23** 18 °C/W

RqJA Typical 10−50* 116 75 °C/W

*Depending on thermal properties of substrate. RqJA = RqJC + RqCA.

**Junction−Lead (#5)

Figure 11. Application Diagram

VIN

CDelay

VOUT

WDI

RESET

GND

CS8151 Microprocessor

Wake Up

CDelay

C1 C2

VCC

I/O

RESET

I/O

Battery

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 12. CS8151 Output Stability

with Output Capacitor Change

1000

100

0.1

0.010 10 20304050 100

ESR (W)

IOUT OUTPUT CURRENT (mA)

CVOUT = 47 mF

60 70 80 90

Unstable Region

Stable Region

CVOUT = 1 mF

CVOUT = 10 mF

CVOUT = 47 mF

CVOUT = 1 mF

Unstable Region

CS8151

http://onsemi.com

ORDERING INFORMATION

Device Package Shipping†

CS8151YDPS7G D2PAK−7

(Pb−Free)

50 Units / Rail

CS8151YDPSR7G D2PAK−7

(Pb−Free)

750 / Tape & Reel

CS8151YDWF16G SO−16L

(Pb−Free)

47 Units / Rail

CS8151YDWFR16G SO−16L

(Pb−Free)

1000 / Tape & Reel

CS8151D2G SO−14L

(Pb−Free)

55 Units / Rail

CS8151D2R2G SO−14L

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

CS8151

http://onsemi.com

PACKAGE DIMENSIONS

D2PAK−7 (SHORT LEAD)

DPS SUFFIX

CASE 936AB−01

ISSUE A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.396 0.406 10.05 10.31

B0.326 0.336 8.28 8.53

C0.170 0.180 4.31 4.57

D0.026 0.036 0.66 0.91

E0.045 0.055 1.14 1.40

G0.050 REF 1.27 REF

H0.539 0.579 13.69 14.71

L0.000 0.010 0.00 0.25

M0.100 0.110 2.54 2.79

N0.017 0.023 0.43 0.58

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

0.055 0.066 1.40 1.68

P0.058 0.078 1.47 1.98

S0.095 0.105 2.41 2.67

U0.256 REF 6.50 REF

V0.305 REF 7.75 REF

0 8 °°0 8 °°

TERMINAL 8

8.26

0.325

10.54

0.415

0.96

0.038

SCALE 3:1 ǒmm

inchesǓ

9.5

0.374

3.25

0.128

2.16

0.085

3.8

0.150

1.27

0.050

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

CS8151

http://onsemi.com

PACKAGE DIMENSIONS

SO−16L

DWF SUFFIX

CASE 751G−03

ISSUE C

14X

B16X

SEATING

PLANE

0.25 B S

16 9

hX 45_

0.25

H8X

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D10.15 10.45

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

CS8151

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE J NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

CS8151/D

SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative