1
®
FN6037.3
ISL43143, ISL43144, ISL43145
Low-Voltage, Single and Dual Supply,
Quad SPST, High Performance Analog
Switches
The Intersil ISL43143–ISL43145 devices are CMOS ,
precision, quad SPST analog switches designed to oper ate
from a single +2V to +12 V supply or from a ±2V to ±6V supply.
Targeted applications include battery powered equipment that
benefit from the de vices’ low pow er consumption (<1µW), lo w
leakage currents (5nA max), and fast switching speeds
(tON = 52ns, tOFF = 40ns). A 5Ω maxim um RON flatness
ensures signal fidelity, while channel-to-channel mismatch is
guaranteed to be less than 2Ω.
The ISL43143/ISL43144/ISL43145 are qu ad single -pole/
single-thro w (SPST) devices. The ISL43143 has fo ur normally
closed (NC) s witches; the ISL43144 has four normally open
(NO) s witches; the ISL43145 ha s tw o NO and tw o NC
s witch es and ca n be used as a dual SPDT, or a dual 2:1
multiplexer.
Table 1 summarizes the per formance of this family.
Features
• Fully Specified for 10% Tolerances at VS = ±5V and
V+ = 12V, 5V and 3.3V
• Four Separately Controlled SPST Switches
• Pin Compatible with DG411/DG412/DG413
• ON Resistance (RON Max.) . . . . . . . . . . . . . . . . . . . . 25Ω
•R
ON Matching Betw een Channels. . . . . . . . . . . . . . . . . . <1Ω
• Low P o w er Consumption (PD). . . . . . . . . . . . . . . . . . . .<1µW
• Low Off Leakage Current (Max at 85°C) . . . . . . . . . 2.5nA
• Fast Switching Action
-t
ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52ns
-t
OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
• Minimum 2000V ESD Protection per Method 3015.7
• TTL, CMOS Compatible
•Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Battery Powered, Handheld, and Portable Equipment
- Barcode Scanners
- Lapto ps, Notebooks, Palmtops
• Communications Systems
-Radios
- XDSL and PBX / PABX
- RF “Tee” Switches
- Base Stations
• Test Equipment
- Medi cal Ultrasound
- Electrocardiograph
-ATE
• A udio and Video Switching
• General Purpose Circuits
- +3V/+5V DACs and ADCs
- Digital Filters
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• AN557 “Recommended Test Procedures for Analog
Switches”
TABLE 1. FEATURES AT A GLANCE
ISL43143 ISL43144 ISL43145
Number of Switches 4 4 4
Configuration All NC All NO 2 NC/2 NO
±4.5V RON 18Ω18Ω18Ω
±4.5V tON/tOFF 52ns/40ns 52ns/40ns 52ns/40ns
10.8V RON 14Ω14Ω14Ω
10.8V tON/tOFF 40ns/27ns 40ns/27ns 40ns/27ns
4.5V RON 30Ω30Ω30Ω
4.5V tON/tOFF 64ns/29ns 64ns/29ns 64ns/29ns
3V RON 51Ω51Ω51Ω
3V tON/tOFF 120ns/50ns 120ns/50ns 120ns/50ns
Packages 16 Ld TSSOP, 16Ld QFN 4x4
Data Sheet December 1, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN6037.3
December 1, 2005
Pinouts (Note 1)
ISL43143 (TSSOP)
TOP VIEW ISL43143 (QFN)
TOP VIEW
ISL43144 (TSSOP)
TOP VIEW ISL43144 (QFN)
TOP VIEW
ISL43145 (TSSOP)
TOP VIEW ISL43145 (QFN)
TOP VIEW
NOTE:
1. Switches Shown for Logic “0” Input.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
COM1
NC1
V-
GND
NC4
IN4
COM4
IN2
NC2
V+
N.C.
NC3
COM3
IN3
COM2 1
3
4
15
NC1
V-
GND
NC4
COM1
IN1
IN2
COM2
16 14 13
2
12
10
9
11
6578
NC2
V+
N.C.
NC3
COM4
IN4
IN3
COM3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
NO1
COM1
V-
GND
COM4
IN4
NO4
IN2
COM2
V+
N.C.
COM3
NO3
IN3
NO2
1
3
4
15
COM1
V-
GND
COM4
NO1
IN1
IN2
NO2
16 14 13
2
12
10
9
11
6578
COM2
V+
N.C.
COM3
NO4
IN4
IN3
NO3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
NO1
COM1
V-
GND
COM4
IN4
NO4
IN2
NC2
V+
N.C.
NC3
COM3
IN3
COM2 1
3
4
15
COM1
V-
GND
COM4
NO1
IN1
IN2
COM2
16 14 13
2
12
10
9
11
6578
NC2
V+
N.C.
NC3
NO4
IN4
IN3
COM3
ISL43143, ISL43144, ISL43145
3FN6037.3
December 1, 2005
Truth Table
LOGIC
ISL43143 ISL43144 ISL43145
SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3
0ON OFFOFFON
1 OFF ON ON OFF
NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V.
Pin Descriptions
PIN FUNCTION
V+ Positive Power Supply Input
V- Negative Power Supply Input. Connect to GND
for Single Supply Configurations.
GND Ground Connection
IN Digital Control Input
COM Analog Switch Common Pin
NO Analog Switch Normally Open Pin
NC Analog Switch Normally Closed Pin
N.C. No Internal Connection
Ordering Information
PART NO.*PART
MARKING TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
ISL43143IV 43143IV -40 to 85 16 Ld TSSOP M16.173
ISL43143IVZ
(Note 2) 43143IVZ -40 to 85 16 Ld TSSOP
(Pb-free)
M16.173
ISL43143IR 43143IR -40 to 85 16 Ld QFN L16.4x4
ISL43143IRZ
(Note 2) 43143IRZ -40 to 85 16 Ld QFN
(Pb-free)
L16.4x4
ISL43144IV 43144IV -40 to 85 16 Ld TSSOP M16.173
ISL43144IVZ
(Note 2) 43144IVZ -40 to 85 16 Ld TSSOP
(Pb-free)
M16.173
ISL43144IR 43144IR -40 to 85 16 Ld QFN L16.4x4
ISL43144IRZ
(Note 2) 43144IRZ -40 to 85 16 Ld QFN
(Pb-free)
L16.4x4
ISL43145IV 43145IV -40 to 85 16 Ld TSSOP M16.173
ISL43145IVZ
(Note 2) 43145IVZ -40 to 85 16 Ld TSSOP
(Pb-free)
M16.173
ISL43145IR 43145IR -40 to 85 16 Ld QFN L16.4x4
ISL43145IRZ
(Note 2) 43145IRZ -40 to 85 16 Ld QFN
(Pb-free)
L16.4x4
*Most surface mount devices are available on tape and reel; add “-T”
to suffix.
NOTE:
2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
ISL43143, ISL43144, ISL43145
4FN6037.3
December 1, 2005
Absolute Maximum Ratings Thermal Info rmation
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V
All Other Pins (Note 3). . . . . . . . . . . . . .((V-) - 0.3V) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, IN, NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 100mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
Operating Conditions
Temperature Range
ISL4314XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Thermal Resistance (Typical) θJA (°C/W)
16 Ld TSSOP Package (Note 4) . . . . . . . . . . . . . . . 150
16 Ld QFN Package (Note 5). . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Moisture Sensitivity (See Technical Brief TB363)
All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(TSSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 and Tech Brief TB389.
Electrical Specifications: ±5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) (NO TE 6)
MIN TYP (NOTE 6)
MAX UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full V- - V+ V
ON Resistance, RON VS = ±4.5V, ICOM = 10mA, VNO or VNC = ±3.5V,
See Figure 5 25 - 18 25 Ω
Full - - 30 Ω
RON Matching Between Channels,
∆RON VS = ±4.5V, ICOM = 10mA, VNO or VNC = ±3V 25 - 0.5 2 Ω
Full - - 4 Ω
RON Flatness, RFLAT(ON) VS = ±4.5V, ICOM = 10mA, VNO or VNC = 0V, ±3V,
Note 8 25 - - 5 Ω
Full - - 5 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM OFF Leakage Current,
ICOM(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM ON Leakage Current,
ICOM(ON) VS = ±5.5V, VCOM = VNO or VNC = ±4. 5V, Note 7 25 -0.2 - 0.2 nA
Full -5 - 5 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 2.4 1.6 - V
Input Voltage Low, VINL Full - 1.5 0.8 V
Input Current, IINH, IINL VS = ±5.5V, VIN = 0V or V+ Full -1 - 1 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 52 65 ns
Full - - 75 ns
Turn-OFF Time, tOFF VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 40 50 ns
Full - - 55 ns
Break-Before-Make Time De la y
(ISL43145 only), tDVS = ±5.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 3 Full 5 19 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - - 5 pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF
ISL43143, ISL43144, ISL43145
5FN6037.3
December 1, 2005
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 26 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 34 - pF
OFF Isolation RL = 50Ω, CL = 15pF, f = 1MHz,
VNO or VNC = 1VRMS, See Figures 4 and 6 25 - 71 - dB
Crosstalk, Note 9 25 - -89 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 58 - dB
POWER SUPPLY CHARACTERISTICS
Power Supply Range Full ±2-±6V
Positive Supply Current, I+ VS = ±5.5V, VIN = 0V or V+, Switch On or Off 25 -1 0.01 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.01 1 µA
Full -1 - 1 µA
NOTES:
6. VIN = Input voltage to perform proper function.
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25°C.
9. Flatness is defined as the delta between the maximum and minimum RON values over the specified voltage range.
10. Between any two switches.
Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NO TE 6) TYP MAX
(NOTE 6)UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V,
See Figure 5 25 - 30 40 Ω
Full - - 50 Ω
RON Matching Between Channels,
∆RON V+ = 4. 5V, ICOM = 1.0mA, VNO or VNC = 3V 25 - 0.5 3 Ω
Full - - 4 Ω
RON Flatness, RFLAT(ON) V+ = 5.5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V,
Note 8 25 - 4.4 6 Ω
Full - - 8 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4. 5V, 1V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM OFF Leakage Current,
ICOM(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM ON Leakage Current,
ICOM(ON) V+ = 5.5V, VCOM = VNO or VNC = 1V, 4.5V, Note 7 25 -0.2 - 0.2 nA
Full -5 - 5 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 2.4 1.5 - V
Input Voltage Low, VINL Full - 1.4 0.8 V
Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full -1 - 1 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 64 80 ns
Full - - 90 ns
Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 29 40 ns
Full - - 45 ns
Break-Before-Make Time De la y
(ISL43145 only), tDV+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 3 Full 15 39 - ns
Electrical Specifications: ±5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) (NO TE 6)
MIN TYP (NOTE 6)
MAX UNITS
ISL43143, ISL43144, ISL43145
6FN6037.3
December 1, 2005
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1.2 2 pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 26 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 34 - pF
OFF Isolation RL = 50Ω, CL = 15pF, f = 1MHz,
VNO or VNC = 1VRMS, See Figures 4 and 6 25 - 71 - dB
Crosstalk, Note 9 25 - -89 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 58 - dB
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, Switch On or Off 25 -1 0.01 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.01 1 µA
Full -1 - 1 µA
Electrical Specifications: 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NO TE 6) TYP MAX
(NOTE 6)UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V
See Figure 5 25 - 51 60 Ω
Full - - 70 Ω
RON Matching Between Channels,
∆RON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V 25 - 0.5 3 Ω
Full - - 4 Ω
RON Flatness, RFLAT(ON) V+ = 3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1.5V,
Note 8 25 - 12 17 Ω
Full - - 17 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM OFF Leakage Current,
ICOM(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM ON Leakage Current,
ICOM(ON) V+ = 3.6V, VCOM = VNO or VNC = 1V, 3V, Note 7 25 -0.2 - 0.2 nA
Full -5 - 5 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 2.4 1.0 - V
Input Voltage Low, VINL Full - 0.9 0.8 V
Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full -1 - 1 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 120 138 ns
Full - - 160 ns
Turn-OFF Time, tOFF V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 50 60 ns
Full - - 65 ns
Break-Before-Make Time De la y
(ISL43145 only), tDV+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 3 Full 30 60 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 2 pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 26 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 34 - pF
Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NO TE 6) TYP MAX
(NOTE 6)UNITS
ISL43143, ISL43144, ISL43145
7FN6037.3
December 1, 2005
OFF Isolation RL = 50Ω, CL = 15pF, f = 1MHz,
VNO or VNC = 1VRMS, See Figures 4 and 6 25 - 71 - dB
Crosstalk, Note 9 25 - -89 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 58 - dB
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, Switch On or Off 25 -1 0.01 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.01 1 µA
Full -1 - 1 µA
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 3.0V, VINL = 0.8V
(Note 5), Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NO TE 6) TYP MAX
(NOTE 6)UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V
See Figure 5 25 - 14 20 Ω
Full - - 30 Ω
RON Matching Between Channels,
∆RON V+ = 10 .8V, ICOM = 1.0mA, VNO or VNC = 9V 25 - 0.3 2 Ω
Full - - 4 Ω
RON Flatness, RFLAT(ON) V+ = 13.2V, ICOM = 1.0mA, V NO or VNC = 3V, 6V, 9V,
Note 8 25 - 1.7 2 Ω
Full - - 3 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM OFF Leakage Current,
ICOM(OFF) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V,
Note 7 25 -0.1 - 0.1 nA
Full -2.5 - 2.5 nA
COM ON Leakage Current,
ICOM(ON) V+ = 13V, VCOM = VNO or VNC = 1V, 12V, Note 7 25 -0.2 - 0.2 nA
Full -5 - 5 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 3.2 2.8 - V
Input Voltage Low, VINL Full - 2.2 0.8 V
Input Current, IINH, IINL V+ = 13V, VIN = 0V or V+ Full -1 - 1 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 40 50 ns
Full - - 83 ns
Turn-OFF Time, tOFF V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 27 35 ns
Full - - 40 ns
Break-Before-Make Time De la y
(ISL43145 only), tDV+ = 13.2V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 3 Full 5 20 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 12 14 pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 26 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 34 - pF
OFF Isolation RL = 50Ω, CL = 15pF, f = 1MHz,
VNO or VNC = 1VRMS, See Figures 4 and 6 25 - 71 - dB
Crosstalk, Note 9 25 - -89 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 58 - dB
Electrical Specifications: 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NO TE 6) TYP MAX
(NOTE 6)UNITS
ISL43143, ISL43144, ISL43145
8FN6037.3
December 1, 2005
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 13V, VIN = 0V or V+, Switch On or Off 25 -1 0.01 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.01 1 µA
Full -1 - 1 µA
Test Cir cuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance. FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 3.0V, VINL = 0.8V
(Note 5), Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NOTE 6) TYP MAX
(NOTE 6) UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
3V
0V
VNX
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
VOUT V(NO or NC) RL
RLRON()
+
------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
VOUT
RL CL
COM
NO or NC
IN
300Ω35pF
GND
V+ C
V- C
VNX
C
VOUT
∆VOUT
ON OFF ON
Q = ∆VOUT x CL
SWITCH
OUTPUT
LOGIC
INPUT
3V
0V CL
VOUT
RG
VGGND
NO or NC
COM
V+ C
LOGIC
INPUT
IN
CV-
ISL43143, ISL43144, ISL43145
9FN6037.3
December 1, 2005
FIGURE 3A. MEASUREMENT POINTS
CL includes fixture and stray capacitance.
Reconfigure accordingly to test SW3 and SW4.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL43145 ONLY)
Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
Repeat test for all switches.
FIGURE 5. RON TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
90%
3V
0V
tD
0V
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
90%
tD
0V
VOUT1
VOUT2
90%
90% LOGIC
INPUT
IN1
COM1 RL1 CL1
VOUT1
300Ω
35pF
COM2
RL2 CL2
VOUT2 300Ω
35pF
NO1
NC2
GND
IN2
VNX
V+ C
C
V-
C
ANALYZER
RL
SIGNAL
GENERATOR
V+ C
0V or 2.4V
NO or NC
COM
IN
GND
C
V-
V+
C
0.8V or 2.4V
NO or NC
COM
IN
GND
VNX
V1
RON = V1/1mA
1mA
C
V-
0V or 2.4V
ANALYZER
V+
C
NO1 or NC1
SIGNAL
GENERATOR
RLGND
IN2
COM1
IN2
50Ω
0V or 2.4V
NO
COM2 NO2 or NC2
C
V-
CONNECTION
V+
GND
NO or NC
COM
IN
IMPEDANCE
ANALYZER
0V or 2.4V
V-
ISL43143, ISL43144, ISL43145
10 FN6037.3
December 1, 2005
Detailed Description
The ISL43143–ISL43145 quad analog switches off er precise
switching capability from a bipolar ±2V to ±6V or a single 2V
to 12V supply with low on-resistance (18Ω) and high speed
switching (tON =52ns, t
OFF = 40ns). The devices are
especially well suited for portable battery powered
equipment thanks to the low operating supply voltage (2V),
low po wer consumption (1µW), lo w leakage currents (5nA
max). High frequency applications also benefit from the wide
bandwidth, and the very high OFF isolation and crosstalk
rejection.
Supply Sequencing And Overvolta ge Protection
As with any CMOS device, proper power supply sequencing
is required to pro te ct the device from excessive input
currents which might permanently damage the IC. All I/O
pins contain ESD protection diodes from the pin to V+ and to
V- (see Figure 8). To prevent forward biasing these diodes,
V+ and V- must be applied before any input signals, and
input signal voltages must remain between V+ and V-. If
these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
Power-Supply Considerations
The ISL4314X construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL4314X 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supp l y),
as well as room for overshoot and noise spikes.
This family of switches performs equally well when operated
with bipolar or single voltage supplies, and bipolar supplies
need not be symmetrica l. The minimum recommended
supply voltage is 2V or ±2V. It is important to note that the
input signal range, switching times, and ON-resistance
degrade at lower supply voltages. Refer to the electrical
specification tables and Typical Performance Curves for
details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals, so switch parameters -
especially RON - are strong functions of both supplies.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.5V
to 10V (see Figure 17). At 12V the VIH le vel is about 2.8V, so
f or best results use a logic f amily the pro vides a V OH greater
than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails (see
Figure 18). Dr iving the digital input signals from GND to V+
with a fast transition time minimizes power dissipation. The
ISL43143-ISL43145 switches have been designed to
minimize the supply current whenever the digital input
voltage is not driven to the supply rails (0V to V+). For
example driving the device with 3V logic while operating with
dual or single 5V supplies the device dra ws only 10µA of
current (see Figure 18 for VIN = 3V). Similiar devices of
competitors can draw 8 times this amount of current.
High-Frequency Performance
In 50Ω systems , signal response is reasonably flat e v en past
200MHz (see Figure 19). Figure 19 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
f eedthrough from a switch’s input to its output. OFF Isolation
is the resistance to this f eedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 20 details the high OFF Isolation and
FIGURE 8. OVERVOLTAGE PROTECTION
V-
VCOM
VNO or NC
OPTIONAL PROTECTION
V+
INX
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
ISL43143, ISL43144, ISL43145
11 FN6037.3
December 1, 2005
Crosstalk rejection provided by this family. At 10MHz, OFF
isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease OFF Isolation an d
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Alth ough the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal v aries. The diff erence in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
s witch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
FIGURE 9. ON RESISTANCE vs POSITIVE SUPPLY VOLTAGE FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
RON (Ω)
V+ (V)
2468101235791113
0
50
100
150
200
25
75
125 V- = 0V
-40°C
85°C 25°C
10
15
20
25
30
35 V- = -3V
-40°C
85°C
25°C
15
20
25 V- = -5V VCOM = (V+) - 1V
ICOM = 1mA
-40°C
85°C
25°C
10
15
20
25
30
35
20
30
40
50
60
70
RON (Ω)
VCOM (V)
0246810121357911
V+ = 3V
V+ = 5V
25°C
-40°C
85°C
25°C
-40°C
85°C
V- = 0V
V- = 0V ICOM = 1mA
8
10
12
14
16
18
20
-40°C
85°C V+ = 12V
V- = 0V
25°C
20
25
30
35
40
45
10
15
20
25
RON (Ω)
VCOM (V)
-4-2024-5 -3 -1 1 3 5
VS = ±5V
VS = ±3V
ICOM = 1mA VS = ±2V
25°C 85°C
25°C
-40°C
85°C
-40°C
5
10
15
20
25
30
35
25°C
-40°C
85°C
Q (pC)
VCOM (V)
-5 0 5 10-2.5 2.5 7.5 12.5
-10
-5
0
5
10
15
VS = ±5V
V+ = 5V
V+ = 3V
V+ = 12V
ISL43143, ISL43144, ISL43145
12 FN6037.3
December 1, 2005
FIGURE 13. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 14. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE
FIGURE 15. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 16. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE
FIGURE 17. DIGIT AL SWITCHING POINT vs POSITIVE
SUPPLY VOLTAGE FIGURE 18. POSITIVE SUPPLY CURRENT vs DIGITAL INPUT
VOLTAGE
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
tON (ns)
V+ (V)
24681012
0
50
100
150
200
250
300
357911
V- = 0V
VCOM = (V+) - 1V
-40°C
85°C
25°C
tOFF (ns)
V+ (V)
24681012
10
20
30
40
50
357911
VCOM = (V+) - 1V
V- = 0V
-40°C
85°C
25°C
0
50
100
150
200
250
tON (ns)
V+ (V)
VCOM = (V+) - 1V
24681012357911
-40°C
85°C
V- = -3V
V- = -5V
-40°C
0
50
100
150
200
250
300
-40°C 85°C
-40°C
25°C
25°C
25°C
0
50
100
150
200
250
300
tOFF (ns)
V+ (V)
-40°C
85°C
VCOM = (V+) - 1V
V- = -3V
V- = -5V
24681012357911
0
50
100
150
-40°C 85°C
-40°C
25°C
25°C
25°C
V+ (V)
25
3.0
2.5
2.0
1.5
1.0
0.5 34 678910111213
V
INH
AND
V
INL
(V)
3.0
2.5
2.0
1.5
1.0
0.5
-40°C
VINL
85°C
-40°C
85°C
VINH
25°C
25°C
V- = 0V to -5V
V- = 0V to -5V
01.50.51 22.533.544.55
70
60
50
40
30
20
10
0
VIN (V)
I+CC (µA)
V- = -5V to 0V
V+ = +5V
ISL43143, ISL43144, ISL43145
13 FN6037.3
December 1, 2005
FIGURE 19. FREQUENCY RESPONSE FIGURE 20. CROSSTALK AND OFF ISOLATION
FIGURE 21. ±PSRR vs FREQUENCY
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSIST OR COUNT:
ISL43143: 209
ISL43144: 209
ISL43145: 209
PROCESS:
Si Gate CMOS
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
FREQUENCY (MHz)
3
0
-3
NORMALIZED GAIN (dB)
GAIN
PHASE 0
45
90
135
180
PHASE (DEGREES)
1 10 100 600
RL = 50Ω
VS = ±2V (VIN = 4VP-P)
V+ = 5V (VIN = 4VP-P)
VS = ±5V (VIN = 5VP-P)
VS = ±5V (VIN = 5VP-P)
V+ = 2.7V (VIN = 2VP-P)
VS = ±2V or V+ = 5V (VIN = 4VP-P)
V+ = 2.7V (VIN = 2VP-P)
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
CROSSTALK
RL = 50Ω
VS = ±2V to ±5V
V+ = 3V to 12V or
ALL HOSTILE CROSSTALK
PSRR (dB)
FREQUENCY (MHz)
0
10
20
30
40
50
60
70
0.3 1 10 100 1000
RL = 50Ω
VIN = 1VP-P
V+ = 3V to 12V or
VS = ±2V to ±5V
-PSRR, SWITCH ON
+PSRR, SWITCH ON
+PSRR, SWITCH OFF
-PSRR, SWITCH OFF
ISL43143, ISL43144, ISL43145
14 FN6037.3
December 1, 2005
ISL43143, ISL43144, ISL43145
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP) L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.23 0.28 0.35 5, 8
D 4.00 BSC -
D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8
E 4.00 BSC -
E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8
e 0.65 BSC -
k0.25 - - -
L 0.50 0.60 0.75 8
L1 - - 0.15 10
N162
Nd 4 3
Ne 4 3
P- -0.609
θ--129
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6037.3
December 1, 2005
ISL43143, ISL43144, ISL43145
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowab le dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N16 167
α0o8o0o8o-
Rev. 1 2/02
