Februar y 2000
PRELIMINARY
2000 Fairc hild S emi c onduc tor Corporation FDS7764A Rev B(W )
FDS7764A
30V N-Channel PowerTrench MOSFET
General Description
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
“low side” synchronous rectifier operation, providing an
extremely low RDS(ON) in a small package.
Applications
• Synchronous Rectifier
• DC/DC converter
Features
• 15 A, 30 V. RDS(ON) = 7.5 mΩ @ VGS = 4.5 V
RDS(ON) = 6.5 mΩ @ VGS = 1 0 V
• High performanc e trenc h technology for extremely
low RDS(ON) High power and current handl i ng
capability
S
D
S
S
SO-8
D
D
D
G
4
3
2
1
5
6
7
8
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain-Sourc e V oltage 30 V
VGSS Gate-Source Voltage ±12 V
IDDrain Current – Continuous (Note 1a) 15 A
– Pulsed 50
Power Dissipation for Single Operation (Note 1a) 2.5
(Note 1b) 1.2
PD
(Note 1c) 1.0
W
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1c) 50 (10 sec) °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS7764A FDS7764A 13’’ 12mm 2500 units
FDS7764A
FDS7764A Rev B(W )
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA30 V
∆BVDSS
∆TJ
Breakdown Voltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C20 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 µA
IGSSF Gate–Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
IGSSR Gate–Body Leak age, Reverse VGS = –12 V , VDS = 0 V –100 nA
On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA0.8 1.2 2.0 V
∆VGS(th)
∆TJ
Gate Threshold Voltage
Temperature Coeffic i ent ID = 250 µA, Referenced to 25°C-4 mV/°C
RDS(on) Static Drain–S ource
On–Resistance VGS = 10 V, ID = 15.5 A
VGS = 4.5 V, ID = 15 A
VGS = 4.5 V, ID = 15 A, TJ = 125°C
5.3
6.0
9.0
6.5
7.5
13.0
mΩ
ID(on) On–State Drain Current VGS = 4.5 V, VDS = 5 V 50 A
gFS Forward Transconductance VDS = 10 V, ID = 15 A 75 S
Dynamic Characteristics
Ciss Input Capacitance 5070 pF
Coss Output Capacitance 550 pF
Crss Reverse Transfer Capacitance
VDS = 15 V, V GS = 0 V,
f = 1.0 MHz 230 pF
Switching Characteristics (Note 2)
td(on) Turn–On Delay Time 17 25 ns
trTurn–On Rise Time 18 25 ns
td(off) Turn–Of f Delay Time 69 100 ns
tfTurn–Off Fall Ti me
VDD = 10 V, ID = 1 A,
VGS = 4.5 V, RGEN = 6 Ω
29 42 ns
QgTotal Gate Charge 33 46 nC
Qgs Gate–Source Charge 7.5 nC
Qgd Gate–Drain Charge
VDS = 15 V, ID = 15 A,
VGS = 4.5 V
6.8 nC
Drain–Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drai n–S ource Diode Forward Current 2.1 A
VSD Drain–Source Di ode Forward
Voltage VGS = 0 V, IS = 2.1 A (Note 2) 0.7 1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 50°/W when
mounted on a 1in2
pad of 2 oz copper
b) 105°/W when
mounted on a .04 in2
pad of 2 oz copper
c) 125°/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDS7764A
FDS7764A Rev B(W )
Typical Characteristics
0
10
20
30
40
50
00.511.5
VDS, DRAIN - S O URCE VOLTAG E ( V )
ID, DRAIN CURRENT (A)
3.5V
2.0V
VGS = 4.5V
2.5V
3.0V
0.75
1
1.25
1.5
1.75
0 102030405060
ID, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
VGS = 2.5V
3.0V
3.5V
4.0V
4.5V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = 15A
VGS = 10V
0
0.005
0.01
0.015
0.02
0.025
0246810
VGS, GATE TO SOURCE VOLTAGE (V)
RDS(ON), ON-RESISTANCE (OHM)
ID = 6 A
TA = 125oC
TA = 25oC
Figure 3. On-Resistance Variation with
Temperature. Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
15
30
45
60
0.511.522.53
VGS, GATE TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TA = 125oC
-55oC
VDS = 5V
25oC
0.001
0.01
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VSD, BODY DIODE FORWARD VOLTAGE (V)
IS, REVERSE DRAIN CURRENT (A)
TA = 125oC
25oC
-55oC
VGS = 0V
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS7764A
FDS7764A Rev B(W )
Typical Characteristics
0
1
2
3
4
5
010203040
Qg, GATE CHARGE (nC)
VGS, GATE-SOURCE VOLTAGE (V)
ID = 12.5A VDS = 5V
15V
10V
0
2000
4000
6000
8000
0 5 10 15 20 25 30
VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
CISS
CRSS
COSS
f = 1MHz
VGS = 0 V
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.01 0.1 1 10 100
VDS, DRAIN - S O URCE VOLTAG E ( V )
ID, DRAIN CURRENT (A)
DC
10s1s 100ms
100
µ
s
RDS(ON) LIMIT
VGS = 10V
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
10ms1ms
0
10
20
30
40
50
0.01 0.1 1 10 100
t1, TIME (s e c )
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJA = 125°C/W
TA = 25°C
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
RθJA(t) = r(t) + RθJA
RθJA = 125°C/W
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
P
(
pk
)
t1t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS7764A
SOIC(8ld s) Packaging
Configuration: Figure 1.0
Components Leader Tape
1680mm minimum or
210 empty poc kets
Tr aile r Tape
640mm min imum or
80 empty poc kets
SOIC(8lds ) Tape Leader and Trailer
Configuration: Figure 2.0
Cover Tape
Carrier Tape
Note/Comments
Packa ging Option
SOIC (8lds) Packaging Information
Standard
(no flow code) L86Z F011
Packa ging type
Reel Size
TNR
13" Dia
Rail/Tube
-
TNR
13" Dia
Qty per Reel/Tube/Bag 2,500 95 4,000
Box Dimension (mm) 343x64x343 530x130x83 343x64x343
Max qty per Box 5,000 30,000 8,000
D84Z
TNR
7" Dia
500
184x187x47
1,000
Weight per unit (gm) 0.0774 0.0774 0.0774 0.0774
Weight per Reel (kg) 0.6060 - 0.9696 0.1182
F63TN Label
ESD Label
343mm x 342mm x 64mm
St a nd ard Inte r m ed ia te bo x
ESD Label
F63TNR Label sampl e F63TNLabel
LOT: CBVK741B019
FSID: FDS9 9 53A
D/C1: D9842 QTY1: SPEC REV:
SPEC:
QTY: 2500
D/C2: Q TY2: CPN: N/F: F (F63TNR)3
F
852
NDS
9959
SOIC-8 Unit Orientation
F
852
NDS
9959
Pi n 1
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Antistatic Cover Tape
ESD Label
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STO RE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR R ADIOACTI VE FIELDS
TN R DA T E
PT NUM B ER
PEEL STRENGTH MIN _________ __ ___gms
MAX ______ _______ gms
Customized
Label
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,5 00 uni t s pe r 13" or 33 0c m d ia met er re el . The re el s are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
co me s in di ffe re nt s iz es depe nd ing on th e nu mbe r of pa rts
shipped.
F
852
NDS
9959
F
852
NDS
9959
F
852
NDS
9959
SO-8 Tape and Reel Data and Package Dimensions
July 1999, Rev. B
1998 Fairchild Semiconductor Corporation
Dimensions are in millimeter
Pkg type
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
SOIC(8lds)
(12mm)
6.50
+/-0.10 5.30
+/-0.10 12.0
+/-0.3 1.55
+/-0.05 1.60
+/-0.10 1.75
+/-0.10 10.25
min 5.50
+/-0.05 8.0
+/-0.1 4.0
+/-0.1 2.1
+/-0.10
0.450
+/-
0.150
9.2
+/-0.3 0.06
+/-0.02
P1
A0 D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size Reel
Option Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
12m m 7" Dia 7.00
177.8 0.059
1.5 512 +0.020/-0.008
13 +0.5/-0.2 0.795
20.2 2.165
55 0.488 +0.078/-0.000
12.4 +2/0 0.724
18.4 0.469 – 0.606
11.9 – 15.4
12m m 13" Dia 13.00
330 0.059
1.5 512 +0.020/-0.008
13 +0.5/-0.2 0.795
20.2 7.00
178 0.488 +0.078/-0.000
12.4 +2/0 0.724
18.4 0.469 – 0.606
11.9 – 15.4
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Opti on
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg m axim um
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or F ront Sectional View)
Component Rotation
User Direction of Feed
SOIC(8lds ) Embos sed Carrier Tape
Configuration: Figure 3.0
SOIC(8ld s) Reel Confi gu ratio n: Figure 4.0
SO-8 Tape and Reel Data and Package Dimensions, continued
July 1999, Rev. B
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [m ill imet ers ]
Part Weight per unit (gram): 0.0774
SO-8 Tape and Reel Data and Package Dimensions, continued
September 1998, Rev. A
9
TRADEMARKS
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
SyncFET™
TinyLogic™
UHC™
VCX™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
www.fairchildsemi.com
Rev. D
