Low Cost 16-Bit Sampling ADC AD1380 FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS Medical and analytical instrumentation Signal processing Data acquisition systems Professional audio Automatic test equipment (ATE) Telecommunications S/H +10V +20V OUT SPAN SPAN 32 6 BIPOLAR 7 4 COMPARATOR GAIN IN ADJ 5 3 24 MSB AD1380 S/H IN 31 SAMPLE AND HOLD 23 BIT 2 REF ADC 10 BIT 15 +5V 29 DIGITAL 30 COMMON 9 +15V 2 ANALOG 8 COMMON LSB 25 NC TIMING CIRCUITRY 27 BUSY -15V 1 28 26 START CONVERT CLOCK OUT NC = NO CONNECT 00764-001 Complete sampling 16-bit ADC with reference and clock 50 kHz throughput 1/2 LSB nonlinearity Low noise SHA: 300 V p-p 32-lead hermetic DIP Parallel output Low power: 900 W Figure 1. GENERAL DESCRIPTION The AD1380 is a complete, low cost 16-bit analog-to-digital converter, including internal reference, clock and sample/hold amplifier. Internal thin-film-on-silicon scaling resistors allow analog input ranges of 2.5 V, 5 V, 10 V, 0 V to +5 V and 0 V to +10 V. Important performance characteristics of the AD1380 include maximum linearity error of 0.003% of FSR (AD1380KD) and maximum 16-bit conversion time of 14 s. Transfer characteristics of the AD1380 (gain, offset and linearity) are specified for the combined ADC/sample-and-hold amplifier (SHA), so total performance is guaranteed as a system. The AD1380 provides data in parallel with corresponding clock and status outputs. All digital inputs and outputs are TTL or 5 V CMOS-compatible. The serial output function is no longer available after date code 0120. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. AD1380 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Output Data ......................................................................8 Absolute Maximum Ratings............................................................ 5 Input Scaling ..................................................................................8 ESD Caution.................................................................................. 5 Calibration (14-Bit Resolution Examples) .................................9 Theory of Operation ........................................................................ 6 Grounding, Decoupling and Layout Considerations ...............9 Description of Operation ................................................................ 7 Applications..................................................................................... 11 Gain Adjustment .......................................................................... 7 Outline Dimensions ....................................................................... 12 Zero Offset Adjustment............................................................... 7 Ordering Guide .......................................................................... 12 Timing............................................................................................ 7 REVISION HISTORY 6/05--Rev. C to Rev. D Updated Format................................................................. Universal Updated Outline Dimensions ....................................................... 12 5/03--Rev. B to Rev. C Removed serial output function and updated format.................................................................................. Universal Change to Product Description...................................................... 1 Change to Functional Block Diagram ........................................... 1 Change to Figure 5 .......................................................................... 4 Deleted Text from Digital Output Data section ........................... 5 Deleted Figure 7 and Renumbered Remainder of Figures.......... 5 Updated Outline Dimensions ......................................................... 8 Rev. D | Page 2 of 12 AD1380 SPECIFICATIONS Typical at TA = 25C, VS = 15 V, 5 V, combined sample-and-hold ADC, unless otherwise noted. Table 1. Model RESOLUTION ANALOG INPUTS Bipolar Min Digital Supply +15 V Supply Current -15 V Supply Current +5 V Supply Current Power Dissipation Max Min 2.5 5 10 0 to 5 0 to 10 Unipolar DIGITAL INPUTS 1 Convert Command Logic Loading TRANSFER CHARACTERISTICS 2 (COMBINED ADC/SHA) Gain Error Unipolar Offset Error Bipolar Zero Error Linearity Error Differential Linearity Error Noise 10 V Unipolar 20 V Bipolar THROUGHPUT Conversion Time Acquisition Time (20 V Step) SAMPLE AND HOLD Input Resistance Small Signal Bandwidth Aperture Time Aperture Jitter Droop Rate TMIN to TMAX Feedthrough DRIFT (ADC AND SHA) 5 Gain Unipolar Offset Bipolar Zero No Missing Codes (Guaranteed) DIGITAL OUTPUTS (TTL-COMPATIBLE) All Codes Complementary Clock Frequency POWER SUPPLY REQUIREMENTS Analog Supplies AD1380JD Typ 16 AD1380KD Typ 16 Max 2.5 5 10 0 to 5 0 to 10 V V V V V TTL-compatible, trailing edge of positive 50 ns (min) pulse 1 1 0.05 3 0.023 0.023 0.006 0.003 0.053 0.023 0.023 0.003 0.003 0.1 0.05 0.05 85 115 20 5 5 2 2 0 to +70 (14 Bits) 5 1.1 Rev. D | Page 3 of 12 +14.5 -14.5 +4.75 +15 -15 +5 25 30 15 900 s s k kHz ns ps rms V/ms mV/ms dB 20 5 5 5 1.1 +15.5 -15.5 +5.25 % FSR 4 % FSR % FSR % FSR % FSR V rms V rms 4 900 50 100 50 1 -80 2 2 0 to +70 (13 Bits) +15 -15 +5 25 30 15 900 0.1 0.05 0.05 14 6 4 900 50 100 50 1 -80 +14.5 -14.5 +4.75 LSTTL Loads 85 115 14 6 Unit Bits ppm/C ppm/C ppm/C C LSTTL Loads MHz +15.5 -15.5 +5.25 V V V mA mA mA mW AD1380 Model TEMPERATURE RANGE Specified Operating Min AD1380JD Typ Max Min 0 to 70 -25 to +85 AD1380KD Typ 0 to 70 -25 to +85 1 Logic 0 = 0.8 V max; Logic 1 = 2.0 V min for inputs. Logic 0 = 0.4 V max; Logic 1 = 2.4 V min for digital outputs. Tested on 10 V and 0 V to +10 V ranges. Adjustable to zero. 4 Full-scale range. 5 Guaranteed but not 100% production tested. 2 3 Rev. D | Page 4 of 12 Max Unit C C AD1380 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Logic Supply Voltage Analog Ground to Digital Ground Analog Inputs (Pin 6, Pin 7, Pin 31) Digital Input Output Short-Circuit Duration to Ground Sample/Hold Data Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating 18 V +7 V 0.3 V VS -0.3 V to VDD + 0.3 V Indefinite 1 sec for any one output 175C -65C to +150C 300C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 5 of 12 AD1380 THEORY OF OPERATION A 16-bit ADC partitions the range of analog inputs into 216 discrete ranges or quanta. All analog values within a given quantum are represented by the same digital code, usually assigned to the nominal midrange value. There is an inherent quantization uncertainty of 1/2 LSB associated with the resolution, in addition to the actual conversion errors. The actual conversion errors associated with ADCs are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, reference error, and power supply rejection. The matching and tracking errors in the converter have been minimized by the use of monolithic DACs that include the scaling network. characteristic left or right on the diagram over the operating temperature range. Gain drift causes a rotation of the transfer characteristic about the zero for unipolar ranges or the minus full-scale point for bipolar ranges. The worst-case accuracy drift is the summation of all three drift errors over temperature. Statistically, however, the drift error behaves as the root-sumsquared (RSS) and can be shown as RSS = G 2 + O 2 + L 2 where: G = gain drift error ( ppm / C). O = offset drift error ( ppm of FSR / C ). L = linearity error ( ppm of FSR / C). ALL BITS ON 000 ... 000 Monotonic behavior requires that the differential linearity error be less than 1 LSB. However, a monotonic converter can have missing codes. The AD1380 is specified as having no missing codes over temperature ranges noted in the Specifications section. There are three types of drift error over temperature: offset, gain and linearity. Offset drift causes a shift of the transfer Rev. D | Page 6 of 12 GAIN ERROR -1/2LSB 011 ... 111 OFFSET ERROR +1/2LSB ALL BITS OFF 111 ... 111 -FSR 2 0 ANALOG INPUT +FSR -1LSB 2 Figure 2. Transfer Characteristics for an Ideal Bipolar ADC 00764-002 DITIGAL OUTPUT (COB CODE) The initial gain and offset errors are specified at 0.1% FSR for gain and 0.05% FSR for offset. These errors may be trimmed to zero by the use of external trim circuits as shown in Figure 3 and Figure 4. Linearity error is defined for unipolar ranges as the deviation from a true straight line transfer characteristic from a zero voltage analog input, which calls for a zero digital output, to a point that is defined as full scale. The linearity error is based on the DAC resistor ratios. It is unadjustable and is the most meaningful indication of ADC accuracy. Differential nonlinearity is a measure of the deviation in the staircase step width between codes from the ideal least significant bit step size (Figure 2). AD1380 DESCRIPTION OF OPERATION +15V On receipt of a CONVERT START command, the AD1380 converts the voltage at its analog input into an equivalent 16-bit binary number. This conversion is accomplished as follows: the 16-bit successive-approximation register (SAR) has its 16-bit outputs connected to both the device bit output pins and the corresponding bit inputs of the feedback DAC. The analog input is successively compared to the feedback DAC output, one bit at a time (MSB first, LSB last). The decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state of the comparator at that time. In either adjustment circuit, the fixed resistor connected to Pin 5 should be located close to this pin to keep the pin connection runs short. Pin 5 is quite sensitive to external noise pickup and should be guarded by ANALOG COMMON. GAIN ADJUSTMENT TIMING The gain adjustment circuit consists of a 100 ppm/C potentiometer connected across VS with its slider connected through a 300 k resistor to Pin 3 (GAIN ADJ) as shown in Figure 3. The timing diagram is shown in Figure 6. Receipt of a CONVERT START signal sets the STATUS flag, indicating conversion in progress. This, in turn, removes the inhibit applied to the gated clock, permitting it to run through 17 cycles. All the SAR parallel bits, STATUS flip-flops and the gated clock inhibit signal are initialized on the trailing edge of the CONVERT START signal. At time t0, B1 is reset and B2 to B16 are set unconditionally. At t1, the Bit 1 decision is made (keep) and Bit 2 is reset unconditionally. This sequence continues until the Bit 16 (LSB) decision (keep) is made at t16. The STATUS flag is reset, indicating that the conversion is complete and the parallel output data is valid. Resetting the STATUS flag restores the gated clock inhibit signal, forcing the clock output to the low Logic 0 state. Note that the clock remains low until the next conversion. +15V 10k TO 100k 300k 3 AD1380 00764-003 100ppm/C 0.01F -15V Figure 3. Gain Adjustment Circuit (0.2% FSR) ZERO OFFSET ADJUSTMENT The zero offset adjustment circuit consists of a 100 ppm/C potentiometer connected across VS with its slider connected through a 1.8 M resistor to Pin 5 for all ranges. As shown in Figure 4, the tolerance of this fixed resistor is not critical; a carbon composition type is generally adequate. Using a carbon composition resistor having a -1200 ppm/C temperature coefficient contributes a worst-case offset temperature coefficient of 32 LSB14 x 61 ppm/LSB14 x 1200 ppm/C = 2.3 ppm/C of FSR, if the offset adjustment potentiometer is set at either end of its adjustment range. Since the maximum offset adjustment required is typically no more than 16 LSB14, use of a carbon composition offset summing resistor typically contributes no more than 1 ppm/C of FSR offset temperature coefficient. B B B 00764-005 Figure 5. Low Temperature Coefficient Zero Adjustment Circuit Corresponding parallel data bits become valid on the same positive-going clock edge. tACQUISITION (1) MAXIMUM THROUGHPUT TIME CONVERT START CONVERSION TIME (2) INTERNAL CLOCK STATUS MSB t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 (3) 0 5 AD1380 1 BIT 2 BIT 3 1 0 BIT 4 0 BIT 5 BIT 6 1 BIT 7 1 BIT 8 1 0 BIT 9 1 1 1 1 BIT 13 0 BIT 14 1 BIT 15 LSB An alternate offset adjustment circuit, which contributes a negligible offset temperature coefficient if metal film resistors (temperature coefficient <100 ppm/C) are used, is shown in Figure 5. Rev. D | Page 7 of 12 0 MSB 0 Figure 4. Zero Offset Adjustment Circuit (0.3% FSR) t16 (4) t17 BIT 12 1.8M AD1380 -15V BIT 11 00764-004 -15V 5 22k M.F. BIT 10 +15V 10k TO 100k 180k M.F. 180k M.F. 1 1 0 0 1 1 1 0 1 1 1 1 0 1 LSB 0 NOTES: 1. THE CONVERT START PULSEWIDTH IS 50ns MIN AND MUST REMAIN LOW DURING A CONVERSION. THE CONVERSION IS INITIATED BY THE TRAILING EDGE OF THE CONVERT COMMAND. 2. tCONV = 14s (MAX), tACQ = 6s (MAX). 3. MSB DECISION. 4. CLOCK REMAINS LOW AFTER LAST BIT DECISION. Figure 6. Timing Diagram (Binary Code 0110011101 111010) 00764-006 If no external trim adjustment is desired, Pin 5 (COMPARATOR IN) and Pin 3 may be left open. 10k TO 100k OFFSET ADJ AD1380 DIGITAL OUTPUT DATA INPUT SCALING Parallel data from TTL storage registers is in negative true form (Logic 1 = 0 V and Logic 0 = 2.4 V). Parallel data output coding is complementary binary for unipolar ranges and complementary offset binary for bipolar ranges. Parallel data becomes valid at least 20 ns before the STATUS flag returns to Logic 0, permitting parallel data transfer to be clocked on the 1 to 0 transition of the STATUS flag (see Figure 7). Parallel data output changes state on positive going clock edges. The AD1380 inputs should be scaled as close to the maximum input signal range as possible to use the maximum signal resolution of the ADC. Connect the input signal as shown in Table 3. See Figure 8 for circuit details. 6 10V SPAN R2 3.75k 7 20V SPAN COMPARATOR IN BIT 16 VALID R1 3.75k 5 TO SAR FROM DAC 20ns MIN TO 90ns 7.5k BIPOLAR OFFSET 4 ANALOG COMMON 8 Figure 7. LSB Valid to Status Low VREF COMPARATOR 00764-008 00764-007 BUSY (STATUS) Figure 8. Input Scaling Circuit Table 3. Input Scaling Connections Input Signal Line 10 V 5 V 2.5 V 0 V to +5 V 0 V to +10 V 1 Output Code COB COB COB CSB CSB Connect Pin 4 to Pin 51 Pin 51 Pin 51 Open Open Connect Pin 7 to Pin 32 Open Pin 51 Pin 51 Open Connect Input Signal to Pin 31 Pin 31 Pin 31 Pin 31 Pin 31 Connect Pin 32 to Pin 7 Pin 6 Pin 6 Pin 6 Pin 6 Pin 5 is extremely sensitive to noise and should be guarded by ANALOG COMMON. Table 4. Transition Values vs. Calibration Codes Output Code MSB LSB1 000. . . .0002 Range +Full Scale 011 . . . 111 Midscale 111 . . . 110 -Full Scale 1 2 10 V +10 V -3/2 LSB 0V -1/2 LSB -10 V +1/2 LSB 5 V +5 V -3/2 LSB 0V -1/2 LSB -5 V +1/2 LSB 2.5 V +2.5 V -3/2 LSB 0V -1/2 LSB -2.5 V +1/2 LSB 0 V to +10 V +10 V -3/2 LSB +5 V -1/2 LSB 0V +1/2 LSB 0 V to +5 V +5 V -3/2 LSB +2.5 V -1/2 LSB 0V +1/2 LSB For LSB value for range and resolution used, see Table 5. Voltages given are the nominal value for transition to the code specified. Table 5. Input Voltage Range and LSB Values Analog Input Voltage Range Code Designation One Least Significant Bit (LSB) FSR 2n n=8 n = 10 n = 12 n = 13 n = 14 n = 15 10 V COB 1 or CTC 2 20 V 5 V COB1or CTC2 10 V 2.5 V COB1 or CTC2 5V 0 V to +10 V CSB 3 10 V 0 V to +5 V CSB3 5V 2n 78.13 mV 19.53 mV 4.88 mV 2.44 mV 1.22 mV 0.61 mV 2n 39.06 mV 9.77 mV 2.44 mV 1.22 mV 0.61 mV 0.31 mV 2n 19.53 mV 4.88 mV 1.22 mV 0.61 mV 0.31 mV 0.15 mV 2n 39.06 mV 9.77 mV 2.44 mV 1.22 mV 0.61 mV 0.31 mV 2n 19.53 mV 4.88 mV 1.22 mV 0.61 mV 0.31 mV 0.15 mV 1 COB = complementary offset binary. CTC = complementary twos complement--achieved by using an inverter to complement the most significant bit to produce MSB. 3 CSB = complementary straight binary. 2 Rev. D | Page 8 of 12 AD1380 CALIBRATION (14-BIT RESOLUTION EXAMPLES) External zero adjustment and gain adjustment potentiometers, connected as shown in Figure 3 and Figure 4, are used for device calibration. To prevent interaction of these two adjustments, zero is always adjusted first and then gain. Zero is adjusted with the analog input near the most negative end of the analog range (0 for unipolar and minus full scale for bipolar input ranges). Gain is adjusted with the analog input near the most positive end of the analog range. 0 V to +10 V Range Set analog input to +1 LSB14 = 0.00061 V; adjust zero for digital output = 11111111111110. Zero is now calibrated. Set analog input to +FSR - 2 LSB = +9.99878 V; adjust gain for 00000000000001 digital output code; full scale (gain) is now calibrated. Half-scale calibration check: set analog input to 5.00000 V; digital output code should be 01111111111111. B -10 V to +10 V Range Set analog input to -9.99878 V; adjust zero for 1111111111110 digital output (complementary offset binary) code. Set analog input to 9.99756 V; adjust gain for 00000000000001 digital output (complementary offset binary) code. Half-scale calibration check: set analog input to 0.00000 V; digital output (complementary offset binary) code should be 01111111111111. Other Ranges Representative digital coding for 0 V to +10 V and -10 V to +10 V ranges is given in the 0 V to +10 V Range section and -10 V to +10 V Range section. Coding relationships and calibration points for 0 V to +5 V, -2.5 V to +2.5 V and -5 V to +5 V ranges can be found by halving proportionally the corresponding code equivalents listed for the 0 V to +10 V and -10 V to +10 V ranges, respectively, as indicated in Table 4. Zero and full-scale calibration can be accomplished to a precision of approximately 1/2 LSB using the static adjustment procedure described above. By summing a small sine or triangular wave voltage with the signal applied to the analog input, the output can be cycled through each of the calibration codes of interest to more accurately determine the center (or end points) of each discrete quantization level. A detailed description of this dynamic calibration technique is presented in Analog-Digital Conversion Handbook, edited by D. H. Sheingold, Prentice-Hall, Inc., 1986. GROUNDING, DECOUPLING AND LAYOUT CONSIDERATIONS Many data acquisition components have two or more ground pins that are not connected together within the device. These grounds are usually referred to as the DIGITAL COMMON (logic power return), ANALOG COMMON (analog power return), or analog signal ground. These grounds (Pin 8 and Pin 30) must be tied together at one point as close as possible to the converter. Ideally, a single solid analog ground plane under the converter would be desirable. Current flows through the wires and etch stripes on the circuit cards and, since these paths have resistance and inductance, hundreds of millivolts can be generated between the system analog ground point and the ground pins of the AD1380. Separate wide conductor stripe ground returns should be provided for high resolution converters to minimize noise and IR losses from the current flow in the path from the converter to the system ground point. In this way, AD1380 supply currents and other digital logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. Each of the AD1380 supply terminals should be capacitively decoupled as close to the AD1380 as possible. A large value (such as 1 F) capacitor in parallel with a 0.1 F capacitor is usually sufficient. Analog supplies are to be bypassed to the ANALOG COMMON (analog power return) Pin 30 and the logic supply is bypassed to DIGITAL COMMON (logic power return) Pin 8. The metal cover is internally grounded with respect to the power supplies, grounds and electrical signals. Do not externally ground the cover. Rev. D | Page 9 of 12 AD1380 +15V 300k -15V REF CONTROL 3 0.01F 7.5k 2 +15V 1F + IOS = 1.3mA + 1 -15V A 3.75k 8 1F 16-BIT DAC 29 30 4 5 IIN 7 6 SHA 32 31 +5V 10k TO 100k NOTE: ANALOG ( ) AND DIGITAL ( eIN 1.8M +15V (0V TO 10V) ZERO ADJ -15V ) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY. 00764-009 GAIN ADJ 3.75k 10k TO 100k KEEP/ REJECT 16-BIT SUCCESSIVE APPROMIXATION REGISTER AD1380 Figure 9. Analog and Power Connections for Unipolar 0 V to 10 V Input Range +15V 300k GAIN ADJ -15V REF CONTROL 3 0.01F 7.5k 2 +15V 1F + IOS = 1.3mA 1F A 3.75k 8 -15V 16-BIT DAC 3.75k 10k TO 100k KEEP/ REJECT 16-BIT SUCCESSIVE APPROMIXATION REGISTER AD1380 + 1 29 30 4 5 SHA IIN 7 6 +5V +15V 1.8M 32 31 eIN (-10V TO +10V) NOTE: ANALOG ( ) AND DIGITAL ( ZERO ADJ -15V ) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY. Figure 10. Analog and Power Connections for Bipolar -10 V to +10 V Input Range Rev. D | Page 10 of 12 00764-010 10k TO 100k AD1380 APPLICATIONS High performance sampling analog-to-digital converters like the AD1380 require dynamic characterization to ensure that they meet or exceed their desired performance parameters for signal processing applications. Key dynamic parameters include signal-to-noise ratio (SNR) and total harmonic distortion (THD), which are characterized using Fast Fourier Transform (FFT) analysis techniques. Increasing the input signal amplitude to -0.4 dB of full scale causes THD to increase to -80.6 dB as shown in Figure 12. At lower input frequencies, however, THD performance is improved. Figure 13 shows a full-scale (-0.3 dB) input signal at 1.41 kHz. THD is now -96.0 dB. 0 FUNDAMENTAL = 1416 SAMPLE RATE = 50000 SIGNAL (dB) = -0.3 NOISE (dB) = -91.9 THD (dB) = -96.0 -10 The results of that characterization are shown in Figure 11. In the test, a 13.2 kHz sine wave is applied as the analog input (fO) at a level of 10 dB below full scale; the AD1380 is operated at a word rate of 50 kHz (its maximum sampling frequency). The results of a 1024-point FFT demonstrate the exceptional performance of the converter, particularly in terms of low noise and harmonic distortion. REL PWR DENSITY (dB) -30 -40 -50 -60 -70 2f (dB) = -97.8 3f (dB) = -102.8 4f (dB) = -106.9 -80 -90 -100 00764-013 In Figure 11, the vertical scale is based on a full-scale input referenced as 0 dB. In this way, all (frequency) energy cells can be calculated with respect to full-scale rms inputs. The resulting signal-to-noise ratio is 83.2 dB, which corresponds to a noise floor of -93.2 dB. Total harmonic distortion is calculated by adding the rms energy of the first four harmonics and equals -97.5 dB. -20 -110 -120 1 44 86 129 171 214 257 299 342 384 427 469 512 FREQUENCY (x48.8281Hz) 20V SPAN Figure 13. FFT of 1.4 kHz Input Signal at -0.3 dB with a 50 kHz Sample Rate 0 -30 -40 0 -50 -10 -60 -20 -70 -80 REL PWR DENSITY (dB) REL PWR DENSITY (dB) -20 The ultimate noise floor can be seen with low level input signals of any frequency. In Figure 14, the noise floor is at -94 dB, as demonstrated with an input signal of 24 kHz at -39.8 dB. = 13232 = 50000 = -10.0 = -93.2 = -97.5 2f (dB) = -100.9 3f (dB) = -101.8 4f (dB) = -111.9 -90 00764-012 -100 -110 -120 1 44 86 129 171 214 257 299 342 384 427 469 512 FREQUENCY (x48.8281Hz) FUNDAMENTAL = 23975 SAMPLE RATE = 50000 SIGNAL (dB) = -39.8 NOISE (dB) = -94.3 THD (dB) = -107.9 -30 -40 -50 -60 -70 2f (dB) = -116.0 3f (dB) = -113.6 4f (dB) = -112.4 -80 -90 -100 Figure 11. FFT of 13.2 kHz Input Signal at -10 dB with a 50 kHz Sample Rate 00764-014 FUNDAMENTAL SAMPLE RATE SIGNAL (dB) NOISE (dB) THD (dB) -10 -110 0 FUNDAMENTAL SAMPLE RATE SIGNAL (dB) NOISE (dB) THD (dB) -10 REL PWR DENSITY (dB) -20 -30 -120 = 13232 = 50000 = -0.4 = -91.0 = -80.6 1 44 86 129 171 214 257 299 342 384 427 469 512 FREQUENCY (x48.8281Hz) 20V SPAN Figure 14. FFT of 24 kHz Input Signal at -39.8 dB with a 50 kHz Sample Rate -40 -50 -60 -70 -80 2f (dB) = -80.7 3f (dB) = -99.9 4f (dB) = -102.9 -90 00764-011 -100 -110 -120 1 44 86 129 171 214 257 299 342 384 427 469 512 FREQUENCY (x48.8281Hz) Figure 12. FFT of 13.2 kHz Input Signal at -0.4 dB with a 50 kHz Sample Rate Rev. D | Page 11 of 12 AD1380 OUTLINE DIMENSIONS 1.728 (43.89) MAX 32 17 1.102 (27.99) 1.079 (27.41) 16 1 0.225 (5.72) MAX PIN 1 INDICATOR (NOTE 1) 0.025 (0.64) 0.015 (0.38) 0.206 (5.23) 0.186 (4.72) 0.192 (4.88) 0.152 (3.86) 0.025 (0.64) MIN 0.100 (2.54) BSC 0.023 (0.58) 0.014 (0.36) 0.120 (3.05) MAX 0.910 (23.11) 0.890 (22.61) 0.015 (0.38) 0.008 (0.20) 0.070 (1.78) 0.030 (0.76) NOTES: 1. INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE. 2. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 15. 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] (DH-32E) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model AD1380JD AD1380KD Max Linearity Error 0.006% FSR 0.003% FSR Temperature Range 0C to 70C 0C to 70C (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00764-0-6/05(D) Rev. D | Page 12 of 12 Package Option Ceramic (DH-32E) Ceramic (DH-32E)