1. General description
The 74AUP2G07 provi des two non-inver ting bu f fers with op en-drain ou tput. The ou tput of
the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range fr om 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the outpu t, pr eve n tin g the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1. 95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exce ed s 200 V
CDM JESD22-C101E exceeds 1000 V
Low static-power consumption; ICC = 0.9 A (maximum)
Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides par tial power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
74AUP2G07
Low-power dual buffer with open-drain output
Rev. 6 — 2 December 2011 Product data sheet
74AUP2G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 2 December 2011 2 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature ra nge Name Description Version
74AUP2G07GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74AUP2G07GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm SOT886
74AUP2G07GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 10.5 mm SOT891
74AUP2G07GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74AUP2G07GS 40 C to +125 C XSON6 extre mely thin sma ll outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
Table 2. Marking
Type number Marking code[1]
74AUP2G07GW p7
74AUP2G07GM p7
74AUP2G07GF p7
74AUP2G07GN p7
74AUP2G07GS p7
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mnb092
1A 1Y
16
2A 2Y
34
6
1
1A 1Y
mnb093
4
3
2A 2Y
mna625
A
Y
GND
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Product data sheet Rev. 6 — 2 December 2011 3 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF state.
Fig 4. Pin configuration
SOT363-1 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891,
SOT1115 and SOT1202
74AUP2G07
1A 1Y
GND
2A 2Y
001aad706
1
2
3
6
VCC
5
4
74AUP2G07
GND
001aad707
1A
2A
VCC
1Y
2Y
Transparent top view
2
3
1
5
4
6
74AUP2G07
GND
001aad665
1A
2A
VCC
1Y
2Y
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
1A 1 data input
GND 2 ground (0 V)
2A 3 data input
2Y 4 data output
VCC 5 supply voltage
1Y 6 data output
Table 4. Function table[1]
Input Output
nA nY
LL
HZ
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Product data sheet Rev. 6 — 2 December 2011 4 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 package: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
10. Static characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [1] 0.5 +4.6 V
IOK output clamping current VO<0V 50 - mA
VOoutput voltage Active mode and Power-down mode [1] 0.5 +4.6 V
IOoutput curren t VO=0 VtoV
CC -20mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[2] -250mW
Table 6. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.8 3.6 V
VIinput voltage 0 3.6 V
VOoutput voltage Active mode and Power-down mode 0 3.6 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 0.8 V to 3.6 V 0 200 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70 VCC -- V
VCC = 0.9 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 VCC V
VCC = 0.9 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
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Product data sheet Rev. 6 — 2 December 2011 5 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A
IOZ OFF-state output current VI = VIH; VO = 0 V to 3.6 V; VCC = 0 V
to 3.6 V --0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V ; VCC = 0 V - - 0.2 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2 V --0.2 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V --0.5A
ICC additional supply current VI = VCC 0. 6 V ; IO = 0 A; VCC =3.3V - - 40 A
CIinput capacitance VCC = 0 V to 3.6 V; VI = GND or VCC -0.7-pF
COoutput capacitance VO = GND; VCC = 0 V - 0.9 - pF
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70 VCC -- V
VCC = 0.9 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 VCC V
VCC = 0.9 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A
IOZ OFF-state output current VI = VIH; VO = 0 V to 3.6 V; VCC = 0 V
to 3.6 V --0.5 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 6 — 2 December 2011 6 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
IOFF power-off leakage current VI or VO = 0 V to 3.6 V ; VCC = 0 V - - 0.5 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2 V --0.6 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V --0.9A
ICC additional supply current VI = VCC 0. 6 V ; IO = 0 A; VCC =3.3V - - 50 A
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 0.8 V 0.75 VCC -- V
VCC = 0.9 V to 1.95 V 0.70 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.25 VCC V
VCC = 0.9 V to 1.95 V - - 0.30 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A
IOZ OFF-state output current VI = VIH; VO = 0 V to 3.6 V; VCC = 0 V
to 3.6 V --0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V ; VCC = 0 V - - 0.75 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2 V --0.75 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V --1.4A
ICC additional supply current VI = VCC 0. 6 V ; IO = 0 A; VCC =3.3V - - 75 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 6 — 2 December 2011 7 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
CL = 5 pF
tpd propagation delay nA to nY; see Figure 7 [2]
VCC = 0.8 V - 11.6 - - - - ns
VCC = 1.1 V to 1.3 V 2.1 4.1 7.5 1.7 9.1 10.0 ns
VCC = 1.4 V to 1.6 V 1.6 3.0 5.1 1.3 6.1 6.7 ns
VCC = 1.65 V to 1.95 V 1.6 2.7 4.0 1.2 5.0 5.5 ns
VCC = 2.3 V to 2.7 V 1.1 2.1 3.2 0.9 4.0 4.4 ns
VCC = 3.0 V to 3.6 V 1.4 2.2 2.8 1.1 3.3 3.6 ns
CL = 10 pF
tpd propagation delay nA to nY; see Figure 7 [2]
VCC = 0.8 V - 14.7 - - - - ns
VCC = 1.1 V to 1.3 V 3.0 5.1 9.0 2.4 11.2 12.3 ns
VCC = 1.4 V to 1.6 V 2.3 3.8 6.1 2.0 7.4 8.1 ns
VCC = 1.65 V to 1.95 V 2.4 3.6 4.8 1.8 6.1 6.7 ns
VCC = 2.3 V to 2.7 V 1.7 2.8 3.8 1.3 4.8 5.3 ns
VCC = 3.0 V to 3.6 V 2.2 3.1 4.2 1.6 4.5 5.0 ns
CL = 15 pF
tpd propagation delay nA to nY; see Figure 7 [2]
VCC = 0.8 V - 17.7 - - - - ns
VCC = 1.1 V to 1.3 V 3.5 6.1 10.4 3.2 13.1 14.5 ns
VCC = 1.4 V to 1.6 V 3.0 4.5 6.8 2.6 8.6 9.4 ns
VCC = 1.65 V to 1.95 V 2.8 4.4 6.7 2.2 7.8 8.6 ns
VCC = 2.3 V to 2.7 V 2.4 3.4 4.5 1.9 5.3 5.8 ns
VCC = 3.0 V to 3.6 V 2.2 4.0 5.7 1.9 6.1 6.7 ns
CL = 30 pF
tpd propagation delay nA to nY; see Figure 7 [2]
VCC = 0.8 V - 26.7 - - - - ns
VCC = 1.1 V to 1.3 V 4.8 9.0 15.6 4.3 18.8 20.7 ns
VCC = 1.4 V to 1.6 V 4.1 6.7 9.4 3.7 11.8 13.0 ns
VCC = 1.65 V to 1.95 V 3.8 6.8 9.7 3.2 11.0 12.1 ns
VCC = 2.3 V to 2.7 V 3.7 5.2 6.7 3.0 7.1 7.8 ns
VCC = 3.0 V to 3.6 V 3.6 6.4 9.7 2.8 10.4 11.4 ns
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Product data sheet Rev. 6 — 2 December 2011 8 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPZL and tPLZ.
[3] All specified values are the average typical values over all stated loads.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiNwhere:
fi= input frequency in MHz;
VCC = supply voltage in V;
N = number of inputs switching.
12. Waveforms
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation
capacitance fi = 1 MHz; VI=GNDtoV
CC [3][4]
VCC = 0.8 V - 0.5 - - - - pF
VCC = 1.1 V to 1.3 V - 0.6 - - - - pF
VCC = 1.4 V to 1.6 V - 0.6 - - - - pF
VCC = 1.65 V to 1.95 V - 0.7 - - - - pF
VCC = 2.3 V to 2.7 V - 0.9 - - - - pF
VCC = 3.0 V to 3.6 V - 1.2 - - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
Measurement points are given in Table 9.
Logic level: VOL is the typical output voltage drops that occur with the output load.
Fig 7. T he d ata input (nA) to output (nY) propagation delays
mna528
tPLZ
VX
nY output
nA input
VI
VCC
VMVM
VOL
GND tPZL
VM
Table 9. Measurement points
Supply voltage Input Output
VCC VMVMVX
0.8 V to 1.6 V 0.5 VCC 0.5 VCC VOL +0.1V
1.65 V to 2.7 V 0.5 VCC 0.5 VCC VOL +0.15V
3.0 V to 3.6 V 0.5 VCC 0.5 VCC VOL +0.3V
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Product data sheet Rev. 6 — 2 December 2011 9 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
[1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, set-up and hold times and pulse width
RL=1M.
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
001aac521
DUT
RT
VIVO
V
EXT
V
CC
RL
5 kΩ
CL
G
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
0.8 V to 3.6 V VCC 3 ns 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 Mopen GND 2 VCC
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Product data sheet Rev. 6 — 2 December 2011 10 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
13. Package outline
Fig 9. Package outline SOT363 (SC-88)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
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Product data sheet Rev. 6 — 2 December 2011 11 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
Fig 10. Package outline SOT886 (XSON6)
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Product data sheet Rev. 6 — 2 December 2011 12 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
Fig 11. Package outline SOT891 (XSON6)
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Product data sheet Rev. 6 — 2 December 2011 13 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
Fig 12. Package outline SOT11 15 (XSON6)
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Product data sheet Rev. 6 — 2 December 2011 14 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
Fig 13. Package outline SOT1202 (XSON6)
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Product data sheet Rev. 6 — 2 December 2011 15 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AUP2G07 v.6 20111202 Product data sheet - 74AUP2G07 v.5
Modifications: •Legal pages updated.
74AUP2G07 v.5 20100909 Product data sheet - 74AUP2G07 v.4
74AUP2G07 v.4 20090611 Product data sheet - 74AUP2G07 v.3
74AUP2G07 v.3 20071016 Product data sheet - 74AUP2G07 v.2
74AUP2G07 v.2 20070612 Product data sheet - 74AUP2G07 v.1
74AUP2G07 v.1 20061121 Product data sheet - -
74AUP2G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 2 December 2011 16 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
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representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
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Notwithstanding any damages that customer might incur for any reason
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changes to information published in this document, including without
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NXP Semiconductors products in such equipment or applications and
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Applications — Applications that are described herein for any of these
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representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Te rms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly ob jects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specificatio n.
74AUP2G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 2 December 2011 17 of 18
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specificatio ns, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specificat ions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AUP2G07
Low-power dual buffer with open-drain output
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 December 2011
Document identifier: 74AUP2G07
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
17 Contact information. . . . . . . . . . . . . . . . . . . . . 17
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18