QPL4C381KMB45 - E2V Technologies (UK), Ltd.

QPL4C381

August 11, 2008

2945 Oakmead Village Ct, Santa Clara, CA 95051 • Phone: (408) 737-0992 • Fax: (408) 736—8708 • Internet: www.qpsemi.com

QPL4C381 16-bit Cascadable Arithmetic/Logic Unit

General Description

The QPL4C381 is designed as a pin for pin replacement for the Logic Devices L4C381 device. The QPL4C381 is a

high speed 16-bit ALU (Arithmetic/Logic Unit). It combines four (4) 381 4-bit ALUs, a lookahead carry generator and

miscellaneous interface logic into a single 68 pin device. It supports high speed pipelined architectures and single 16-

bit bus architectures. It retains full functional and performance compatibility with the Logic Devices L4C381 and even

older 381 bipolar devices.

- Replacement for the Logic Devices L4C381.

- High-speed, 16-bit ALU

- Input and Output registers can be made transparent

- Cascadeable with or without carry lookahead

- Extension to the 54S381 instruction set

- Force A or B → 0 allows two’s complement, PASSA, PASSB instructions

- Internal feedback path for accumulation

- Low-power, high speed CMOS Technology

- All status and carry outputs available.

Architecture

The QPL4C381 operates on the 16-bit operands ”A” and “B”, and produces a single 16-bit result “F”. Three select lines

control the ALU and provide 3 arithmetic, 3 logical and 2 initialization functions. Full ALU status is provided, allowing the

device to be cascaded to form longer word lengths. Registers are provided on both the ALU inputs and the output, and

may be bypassed. An internal feedback path allows the registered ALU output to be routed to one of the ALU inputs for

use in chain operations and accumulation. The A or B input to the ALU can be forced to zero allowing unary functions

to be performed on either operand.

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ALU Operation

Select lines S0-S2 determine the operation to be performed. The ALU functions and their select codes are:

S2 S1 S0 Function

0 0 0 CLEAR (F = 0000 0000 0000 0000)

0 0 1 NOT (A) + B

0 1 0 A + NOT (B)

0 1 1 A + B

1 0 0 A XOR B

1 0 1 A OR B

1 1 0 A AND B

1 1 1 PRESET (F = 1111 1111 1111 1111)

The functions B minus A, and A minus B

can be achieved by setting the carry

input (C0) of the least significant slice and

selecting codes 001 and 010

respectively.

ALU Status

The ALU provides Overflow and Zero status bits. Carry, Propagate and Generate outputs are provided for cascading.

These outputs are defined for the three arithmetic functions only. The ALU sets the Zero output when all sixteen

outputs bits are zero. The Generate, Propagate, C16 and Overflow Flags for the A + B operation are defined:

Bit Carry Generate = gi = AiBi for i = 0, 1, … , 15

Bit Carry Propagate = pi = Ai + Bi for i = 0, 1, … , 15

P0 = p0

Pi = pi(Pi-1)

for i = 1, 2, … , 15

and

G0 = g0

Gi=gi+pi(Gi-1)

Ci=Gi-1+Pi-1(Ci-1)

for i = 1,2,…,15

then

G¯ = NOT(G15)

P¯ = NOT(P15)

C16 = G15 + P15C15

OVF = C15 XOR C16

Operand Registers

The QPL4C381 has two 16-bit wide input registers for operands A and B. These are triggered by a rising edge on the

common clock pin. Each register is independently enabled by control signals EN¯¯ A and EN¯¯ B.

This allows the QPL4C381 to accept arguments from a single 16-bit data bus. For those applications that do not require

registered inputs, both the A and B operand registers can be made transparent with the FTAB control line. When FTAB

control is asserted, the A and B input registers are bypassed. However, they continue to function normally via the EN¯¯ A

and EN¯¯ B controls. The contents of the input registers will be available to the ALU if the FTAB control is released.

Output Register

The output of the ALU drives the input of a 16-bit register. This rising-edge triggered register is clocked by the same

clock as the input registers. The output register is enabled by the EN¯¯ F control signal. By disabling the output register,

QPL4C381

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intermediate results can be held while loading new input operands. Tri-state drivers controlled by the OE¯¯ input allow the

QPL4C381 to be used in a single bidirectional bus system. The output register can be made transparent by asserting

the FTF control signal. When FTF is asserted, the output register is bypassed, however, it continues to function normally

via the EN¯¯ F control signal. The contents of the output register will be available on the output pins if FTF is released.

With both FTAB and FTF true (high) the QPL4C381 is functionally identical to four cascaded 54S381 devices.

Operand Selection

The two operand selection lines OSA/OSB control multiplexers immediately preceding the ALU inputs. The multiplexers

provide an operand force to zero function as well as provide a result feedback to the B input. Either A or B operands

can be forced to zero.

OSA OSB Operand B Operand A

0 0 F A

0 1 0 A

1 0 B 0

1 1 B A

When both operand select lines are zero/low, the QPL4C381 is configured as a chain calculation ALU. The registered

ALU output is passed back to the B input of the ALU. This allows accumulation operations to be performed by providing

new operands via the A inputs. The accumulator can be preloaded from the A input by setting OSA as a one/high. By

forcing the function select lines to the CLEAR state (000), the accumulator may be cleared. This feedback operation is

not effected by the state of the FTF control. The F outputs may be driven directly by the ALU (FTF = one/high). The

output register continues to function and provides the ALU B operand source.

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Block Diagram

QPL4C381

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Connection Diagrams

LCC PGA

FUNCTION DIP/

LCC PGA FUNCTION DIP/

LCC PGA

AO 1 F02 VCC 18 B06 F8 35 F10 EN ¯¯A 52 K06

A1 2 F01 GND 19 A06 F7 36 F11 B0 53 L06

A2 3 E02 C16 20 B07 F6 37 G10 B1 54 K05

A3 4 E01 P¯ 21 A07 F5 38 G11 B2 55 L05

A4 5 D02 G¯ 22 B08 F4 39 H10 B3 56 K04

A5 6 D01 ZERO 23 A08 F3 40 H11 B4 57 L04

A6 7 C02 OVF 24 B09 F2 41 J10 B5 58 K03

A7 8 C01 ENF ¯¯¯ 27 A09 F1 42 J11 B6 59 L03

A8 9 B01 FTF 26 A10 F0 43 K11 B7 60 L02

A9 10 B02 OE ¯¯ 27 B10 C0 44 K10 B8 61 K02

A10 11 A02 F15 28 B11 S0 45 L10 B9 62 K01

A11 12 B03 F14 29 C10 S1 46 K09 B10 63 J02

A12 13 A03 F13 30 C11 S2 47 L09 B11 64 J01

A13 14 B04 F12 31 D10 OSA 48 K08 B12 65 H02

A14 15 A04 F11 32 D11 OSB 49 L08 B13 66 H01

A15 16 B05 F10 33 E10 FTAB 50 K07 B14 67 G02

CLK 17 A05 F9 34 E11 EN ¯¯B 51 L07 B15 68 G01

Pin Name Function

A0-A15 "A" data input bus. The 16-bit "A" input data bus to the ALU.

B0-B15 "B" data input bus. The 16-bit "B" input data bus to the ALU.

F0-F15 "F" data output bus. The 16-bit "F" output data bus from the ALU.

CO Carry input. This input is used in arithmetic operations.

C16 Carry out. Output flag that provides the carry propagate information from an arithmetic

operation.

P¯ Carry propagate output. Output flag that provides the carry propagate information from an

arithmetic operation. Used in cascaded systems.

G¯ Carry generate output. Output flag that provides the carry generate information from an

arithmetic operation. Used in cascaded systems

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Pin Name Function

OVF Overflow output. Output flag tht provides ALU result overflow information from an arithmetic

operation.

ZERO Zero output. Output flag that provides ALU result overflow information from an arithmetic

operation.

EN ¯¯A "A" register enable input. Control input used to either load or hold data into the "A" register.

EN ¯¯B "B" register enable input. Control input used to either load or hold data into the "B" register.

FTAB Feedthrough "AB" input. Control input used to select whether the input registers are bypassed

or not.

ENF ¯¯¯ "F" register enable output. Control input used to either load or hold data into the "F" register.

FTF Feedthrough "F" input. Control input used to select whether the output register is bypassed or

not.

OSA, OSB Operand select inputs. Selects input data to the ALU on the "A" and "B" ports.

S0-S2 Instruction select inputs. Controls which operation the ALU will perform

OE ¯¯ Output enable input. Controls the "F" output bus by enabling and disabling the outputs.

CLK Clock input. The master clock input for all device registers.

VCC, GND Power supply.

Absolute Maximum Ratings

Stresses above the AMR may cause permanent damage, extended operation at AMR may degrade performance and affect reliability

Condition Units Notes

VCC Supply Voltage with respect to GND -0.5 to +7.0 Volts DC

Input Signal with respect to GND -0.5 to VCC+0.5 V

Signal applied to high impedance outputs -0.5 to VCC+0.5 V

Maximum Power Dissapation (PD) 420 mW /1

Current into Low Outputs 25 mA

Storage Temperature Range -65 to +150 ºC

Operating Temperature (Ambient) -55 to +125 ºC

Lead Temperature (soldering, 10 seconds) +300 ºC

Junction Temperature (TJ) +175 ºC

1/ - Must withstand the added PD due to IOS

Recommended Operating Conditions

Condition Units Notes

Supply Voltage Range (VCC) 4.5 to 5.5 Volts DC

Case Operating Range (Tc) -55C to +125 ºC /2

2/ – Maximum PD, Maximum TJ Are Not to Be Exceeded

QPL4C381

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TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS

Test Symbol Conditions 3/

-55ºC≤TA≤+125ºC,VSS=0V

4.5V ≤ VCC ≤ 5.5V

Unless Otherwise Specified

Device Min Max Unit

Output High Voltage VOH V

CC= 4.5V, IOH= -2mA All 2.4 V

Output Low Voltage VOL V

CC= 4.5V, IOL= 8mA All 0.5 V

Input High Voltage VIH All 2.0 V

Input Low Voltage VIL All 0 V

Input Current IIX V

CC= 5.5V All ±20 μA

Output Leakage

Current

IOZ V

CC= 5.5V All ±20 μA

Dynamic Supply

Current

ICC1 V

CC= 5.5V /5 All 30 mA

Quiescent Power

Supply Current

ICC2 V

CC = 5.5V /6 All 1.5 mA

Input Capacitance

/8 CIN V

IN = 0V, VCC = 5.0V

TA = 25°C, f = 1MHz

All 5 pF

OUT = 0V, VCC = 5.0V

TA = 25°C, f = 1MHz

All 8 pF

Clock to F0-F15 1

FTAB=0, FTF=0, QPL4C381-45 28 ns

CL=30pF, VCC=4.5V QPL4C381-35 26 ns

Clock to P¯, G¯ 2

FTAB=0, FTF=0, QPL4C381-45 34 ns

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

Clock to OVF, ZERO 3 FTAB=0, FTF=0, QPL4C381-45 50 ns

CL=30pF, VCC=4.5V QPL4C381-35 34 ns

Clock to C16 4

FTAB=0, FTF=0, QPL4C381-45 34 ns

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

C0 to OVF, ZERO 5 FTAB=0, FTF=0, QPL4C381-45 32 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

C0 to C16 6

FTAB=0, FTF=0, QPL4C381-45 23 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

S0-S2,OSA,OSB to P¯,G¯ 7

FTAB=0, FTF=0, QPL4C381-45 38 ns

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to 8 FTAB=0, FTF=0, QPL4C381-45 38 ns

OVF, ZERO CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to C16 9

FTAB=0, FTF=0, QPL4C381-45 38 ns

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

Clock to F0-F15 10

FTAB=0, FTF=1, QPL4C381-45 56 ns

CL=30pF, VCC=4.5V QPL4C381-35 34 ns

Clock to P¯,G¯ 11

FTAB=0, FTF=1, QPL4C381-45 34 ns

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

Clock to OVF, ZERO 12 FTAB=0, FTF=1, QPL4C381-45 50 ns

CL=30pF, VCC=4.5V QPL4C381-35 34 ns

QPL4C381

QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 8 of 11

TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS

Test Symbol Conditions 3/

-55ºC≤TA≤+125ºC,VSS=0V

4.5V ≤ VCC ≤ 5.5V

Unless Otherwise Specified

Device Min Max Unit

Clock to C16 13

FTAB=0, FTF=1, QPL4C381-45 34 ns

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

C0 to F0-F15 14

FTAB=0, FTF=1, QPL4C381-45 32 ns

CL=30pF, VCC=4.5V QPL4C381-35 26 ns

C0 to OVF, ZERO 15 FTAB=0, FTF=1, QPL4C381-45 32 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

C0 to C16 16

FTAB=0, FTF=1, QPL4C381-45 23 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

S0-S2,OSA,OSB to 17 FTAB=0, FTF=1, QPL4C381-45 46 ns

F0-F15

CL=30pF, VCC=4.5V QPL4C381-35 30 ns

S0-S2,OSA,OSB to 18 FTAB=0, FTF=1, QPL4C381-45 38 ns

P¯,G¯

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to 19 FTAB=0, FTF=1, QPL4C381-45 38 ns

OVF, ZERO CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to 20 FTAB=0, FTF=1, QPL4C381-45 38 ns

C16

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

A0-A15, B0-B15 to 21 FTAB=1, FTF=0, QPL4C381-45 32 ns

P¯,G¯

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

A0-A15, B0-B15 to 22 FTAB=1, FTF=0, QPL4C381-45 46 ns

OVF, ZERO CL=30pF, VCC=4.5V QPL4C381-35 28 ns

A0-A15, B0-B15 to 23 FTAB=1, FTF=0, QPL4C381-45 36 ns

C16

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

Clock to F0-F15 24

FTAB=1, FTF=0, QPL4C381-45 28 ns

CL=30pF, VCC=4.5V QPL4C381-35 26 ns

C0 to OVF, ZERO 25 FTAB=1, FTF=0, QPL4C381-45 32 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

C0 to C16 26

FTAB=1, FTF=0, QPL4C381-45 23 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

S0-S2,OSA,OSB to 27 FTAB=1, FTF=0, QPL4C381-45 38 ns

P¯,G¯

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to 28 FTAB=1, FTF=0, QPL4C381-45 38 ns

OVF, ZERO CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to 29 FTAB=1, FTF=0, QPL4C381-45 38 ns

C16

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

A0-A15, B0-B15 to 30 FTAB=1, FTF=1, QPL4C381-45 45 ns

F0-F15

CL=30pF, VCC=4.5V QPL4C381-35 30 ns

A0-A15, B0-B15 to 31 FTAB=1, FTF=1, QPL4C381-45 32 ns

P¯,G¯

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

A0-A15, B0-B15 to 32 FTAB=1, FTF=1, QPL4C381-45 46 ns

OVF, ZERO CL=30pF, VCC=4.5V QPL4C381-35 28 ns

QPL4C381

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TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS

Test Symbol Conditions 3/

-55ºC≤TA≤+125ºC,VSS=0V

4.5V ≤ VCC ≤ 5.5V

Unless Otherwise Specified

Device Min Max Unit

A0-A15, B0-B15 to 33 FTAB=1, FTF=1, QPL4C381-45 36 ns

C16

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

C0 to F0-F15 34

FTAB=1, FTF=1, QPL4C381-45 32 ns

CL=30pF, VCC=4.5V QPL4C381-35 26 ns

C0 to OVF, ZERO 35 FTAB=1, FTF=1, QPL4C381-45 32 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

C0 to C16 36

FTAB=1, FTF=1, QPL4C381-45 23 ns

CL=30pF, VCC=4.5V QPL4C381-35 22 ns

S0-S2,OSA,OSB to 37 FTAB=1, FTF=0, QPL4C381-45 46 ns

F0-F15

CL=30pF, VCC=4.5V QPL4C381-35 30 ns

S0-S2,OSA,OSB to 38 FTAB=1, FTF=1, QPL4C381-45 38 ns

P¯,G¯

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to 39 FTAB=1, FTF=1, QPL4C381-45 38 ns

OVF, ZERO CL=30pF, VCC=4.5V QPL4C381-35 28 ns

S0-S2,OSA,OSB to 40 FTAB=1, FTF=1, QPL4C381-45 38 ns

C16

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

Clock (OSA,OSB=0) to 65 FTAB=0, FTF=0, QPL4C381-45 56 ns

F0-F15

CL=30pF, VCC=4.5V QPL4C381-35 34 ns

Clock (OSA,OSB=0) to 41 FTAB=0, FTF=0, QPL4C381-45 34 ns

P¯,G¯

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

Clock (OSA,OSB=0) to 42 FTAB=0 FTF=0, QPL4C381-45 50 ns

OVF, ZERO CL=30pF, VCC=4.5V QPL4C381-35 34 ns

Clock (OSA,OSB=0) to 43 FTAB=0 FTF=0, QPL4C381-45 34 ns

C16

CL=30pF, VCC=4.5V QPL4C381-35 28 ns

A0-A15, B0-B15 44 FTAB=0 QPL4C381-45

8 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 8 ns

A0-A15, B0-B15 45 FTAB=0 QPL4C381-45

3 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 3 ns

A0-A15, B0-B15 46 FTAB=1 QPL4C381-45

33 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 20 ns

A0-A15, B0-B15 47 FTAB=1 QPL4C381-45

3 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 3 ns

EN¯¯ A, EN¯¯ B 48

FTAB=0 QPL4C381-45

10 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 10 ns

EN¯¯ A, EN¯¯ B 49

FTAB=0 QPL4C381-45

2 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 2 ns

ENF¯¯¯ 50

QPL4C381-45

10 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 10 ns

ENF¯¯¯ 51

QPL4C381-45

2 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 2 ns

QPL4C381

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TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS

Test Symbol Conditions 3/

-55ºC≤TA≤+125ºC,VSS=0V

4.5V ≤ VCC ≤ 5.5V

Unless Otherwise Specified

Device Min Max Unit

C0 52

FTAB=0 QPL4C381-45

20 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 12 ns

C0 53

FTAB=0 QPL4C381-45

0 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 0 ns

C0 54

FTAB=1 QPL4C381-45

20 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 12 ns

C0 55

FTAB=1 QPL4C381-45

0 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 0 ns

S0-S2,OSA,OSB 56

FTAB=0 QPL4C381-45

36 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 20 ns

S0-S2,OSA,OSB 57

FTAB=0 QPL4C381-45

0 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 0 ns

S0-S2,OSA,OSB 58

FTAB=1 QPL4C381-45

36 ns

Setup Time CL=30pF, VCC=4.5V QPL4C381-35 20 ns

S0-S2,OSA,OSB 59

FTAB=1 QPL4C381-45

0 ns

Hold Time CL=30pF, VCC=4.5V QPL4C381-35 0 ns

Minimum Cycle Time 60 CL=30pF, VCC=4.5V QPL4C381-45

38 ns

QPL4C381-35 26 ns

High Going Pulse 61 CL=30pF, VCC=4.5V QPL4C381-45

15 ns

QPL4C381-35 12 ns

Low Going Pulse 62 CL=30pF, VCC=4.5V QPL4C381-45

15 ns

QPL4C381-35 12 ns

Tri-State Enable Time 63 CL=30pF, VCC=4.5V QPL4C381-45

20 ns

QPL4C381-35 18 ns

Tri-State Disable Time 64 CL=30pF, VCC=4.5V QPL4C381-45

20 ns

/7 QPL4C381-35 18 ns

NOTES

3/ Test Conditions assume signal transition times of 5ns or less, timing reference levels of 1.5V,

input pulse levels of 0 to 3.0V and output loading of the specified IOH, IOL and 30pF. Input

voltages should be adjusted to compensate for inductive ground and VCC noise to maintain

required device input levels relative to device supply pins. All tests must be performed using

worst-case test conditions, unless otherwise specified.

4/ For test purposes, not more than one output should be tested at a time. Duration of the short

circuit should not exceed 1 second. Guaranteed if not tested.

5/ Tested with all outputs changing every cycle and no load at a 5MHz clock rate.

6/ Tested with all inputs within 0.1V of VCC or GND, no load.

7/ Tested with IOL = 10mA, IOH = 10mA.

8/ Tested only for initial qualification and after process or design changes which may effect

capacitance.

Ordering Information

QPL4C381

QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 11 of 11

Part Number Package (Mil-Std-1835) Generic

QPL4C381KMB45-MIL

(Similar to: 5962-8995901YA) CMGA3-P68 QPL4C381KMB45

QPL4C381GMB45-MIL

(Similar to: 5962-8995901ZC) CQCC1-N68 QPL4C381GMB45

QPL4C381KMB30-MIL

(Similar to: 5962-8995902YA) CMGA3-P68 QPL4C381KMB30

QPL4C381GMB30-MIL

(Similar to: 5962-8995902ZA) CQCC1-N68 QPL4C381GMB30

QP Semiconductor supports Source Control Drawing (SCD), and custom package development for this product family.

Notes:

Package outline information and specifications are defined by Mil-Std-1835 package dimension requirements.

“-MIL” products manufactured by QP Semiconductor are compliant to the assembly, burn-in, test and quality co nformance

requirements of Test Methods 50 04 & 5005 of Mil-Std-883 for Class B devices. This datasheet defines the electrical test

requirements for the device(s).

The listed drawings, Mil-PRF-38535, Mil-Std-88 3 and Mil-Std-1835 are available online at http://www.dscc.dla.mil/

Additional information is available at our website http://www.qpsemi.com