QPL4C381 August 11, 2008 QPL4C381 16-bit Cascadable Arithmetic/Logic Unit General Description The QPL4C381 is designed as a pin for pin replacement for the Logic Devices L4C381 device. The QPL4C381 is a high speed 16-bit ALU (Arithmetic/Logic Unit). It combines four (4) 381 4-bit ALUs, a lookahead carry generator and miscellaneous interface logic into a single 68 pin device. It supports high speed pipelined architectures and single 16bit bus architectures. It retains full functional and performance compatibility with the Logic Devices L4C381 and even older 381 bipolar devices. - Replacement for the Logic Devices L4C381. - High-speed, 16-bit ALU - Input and Output registers can be made transparent - Cascadeable with or without carry lookahead - Extension to the 54S381 instruction set - Force A or B 0 allows two's complement, PASSA, PASSB instructions - Internal feedback path for accumulation - Low-power, high speed CMOS Technology - All status and carry outputs available. Architecture The QPL4C381 operates on the 16-bit operands "A" and "B", and produces a single 16-bit result "F". Three select lines control the ALU and provide 3 arithmetic, 3 logical and 2 initialization functions. Full ALU status is provided, allowing the device to be cascaded to form longer word lengths. Registers are provided on both the ALU inputs and the output, and may be bypassed. An internal feedback path allows the registered ALU output to be routed to one of the ALU inputs for use in chain operations and accumulation. The A or B input to the ALU can be forced to zero allowing unary functions to be performed on either operand. 2945 Oakmead Village Ct, Santa Clara, CA 95051 * Phone: (408) 737-0992 * Fax: (408) 736--8708 * Internet: www.qpsemi.com QPL4C381 ALU Operation Select lines S0-S2 determine the operation to be performed. The ALU functions and their select codes are: S2 S1 S0 Function 0 0 0 CLEAR (F = 0000 0000 0000 0000) 0 0 1 NOT (A) + B 0 1 0 A + NOT (B) 0 1 1 A+B 1 0 0 A XOR B 1 0 1 A OR B 1 1 0 A AND B 1 1 1 PRESET (F = 1111 1111 1111 1111) The functions B minus A, and A minus B can be achieved by setting the carry input (C0) of the least significant slice and selecting codes 001 and 010 respectively. ALU Status The ALU provides Overflow and Zero status bits. Carry, Propagate and Generate outputs are provided for cascading. These outputs are defined for the three arithmetic functions only. The ALU sets the Zero output when all sixteen outputs bits are zero. The Generate, Propagate, C16 and Overflow Flags for the A + B operation are defined: Bit Carry Generate = gi = AiBi for i = 0, 1, ... , 15 Bit Carry Propagate = pi = Ai + Bi for i = 0, 1, ... , 15 P0 = p0 for i = 1, 2, ... , 15 Pi = pi(Pi-1) and G0 = g0 Gi=gi+pi(Gi-1) Ci=Gi-1+Pi-1(Ci-1) then G = NOT(G15) P = NOT(P15) C16 = G15 + P15C15 OVF = C15 XOR C16 for i = 1,2,...,15 for i = 1,2,...,15 Operand Registers The QPL4C381 has two 16-bit wide input registers for operands A and B. These are triggered by a rising edge on the common clock pin. Each register is independently enabled by control signals EN A and EN B. This allows the QPL4C381 to accept arguments from a single 16-bit data bus. For those applications that do not require registered inputs, both the A and B operand registers can be made transparent with the FTAB control line. When FTAB control is asserted, the A and B input registers are bypassed. However, they continue to function normally via the EN A and EN B controls. The contents of the input registers will be available to the ALU if the FTAB control is released. Output Register The output of the ALU drives the input of a 16-bit register. This rising-edge triggered register is clocked by the same clock as the input registers. The output register is enabled by the EN F control signal. By disabling the output register, QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 2 of 11 QPL4C381 intermediate results can be held while loading new input operands. Tri-state drivers controlled by the OE input allow the QPL4C381 to be used in a single bidirectional bus system. The output register can be made transparent by asserting the FTF control signal. When FTF is asserted, the output register is bypassed, however, it continues to function normally via the EN F control signal. The contents of the output register will be available on the output pins if FTF is released. With both FTAB and FTF true (high) the QPL4C381 is functionally identical to four cascaded 54S381 devices. Operand Selection The two operand selection lines OSA/OSB control multiplexers immediately preceding the ALU inputs. The multiplexers provide an operand force to zero function as well as provide a result feedback to the B input. Either A or B operands can be forced to zero. OSA OSB Operand B Operand A 0 0 F A 0 1 0 A 1 0 B 0 1 1 B A When both operand select lines are zero/low, the QPL4C381 is configured as a chain calculation ALU. The registered ALU output is passed back to the B input of the ALU. This allows accumulation operations to be performed by providing new operands via the A inputs. The accumulator can be preloaded from the A input by setting OSA as a one/high. By forcing the function select lines to the CLEAR state (000), the accumulator may be cleared. This feedback operation is not effected by the state of the FTF control. The F outputs may be driven directly by the ALU (FTF = one/high). The output register continues to function and provides the ALU B operand source. QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 3 of 11 QPL4C381 Block Diagram QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 4 of 11 QPL4C381 Connection Diagrams LCC PGA FUNCTION DIP/ LCC PGA FUNCTION DIP/ LCC PGA FUNCTION DIP/ LCC PGA FUNCTION DIP/ LCC PGA AO A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 F02 F01 E02 E01 D02 D01 C02 C01 B01 B02 A02 B03 A03 B04 A04 B05 A05 VCC GND C16 P G ZERO OVF ENF FTF OE F15 F14 F13 F12 F11 F10 F9 18 19 20 21 22 23 24 27 26 27 28 29 30 31 32 33 34 B06 A06 B07 A07 B08 A08 B09 A09 A10 B10 B11 C10 C11 D10 D11 E10 E11 F8 F7 F6 F5 F4 F3 F2 F1 F0 C0 S0 S1 S2 OSA OSB FTAB EN B 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 F10 F11 G10 G11 H10 H11 J10 J11 K11 K10 L10 K09 L09 K08 L08 K07 L07 EN A B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 K06 L06 K05 L05 K04 L04 K03 L03 L02 K02 K01 J02 J01 H02 H01 G02 G01 Pin Name Function A0-A15 "A" data input bus. The 16-bit "A" input data bus to the ALU. B0-B15 "B" data input bus. The 16-bit "B" input data bus to the ALU. F0-F15 "F" data output bus. The 16-bit "F" output data bus from the ALU. CO Carry input. This input is used in arithmetic operations. C16 Carry out. Output flag that provides the carry propagate information from an arithmetic operation. P Carry propagate output. Output flag that provides the carry propagate information from an arithmetic operation. Used in cascaded systems. G Carry generate output. Output flag that provides the carry generate information from an arithmetic operation. Used in cascaded systems QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 5 of 11 QPL4C381 Pin Name OVF ZERO Function Overflow output. Output flag tht provides ALU result overflow information from an arithmetic operation. Zero output. Output flag that provides ALU result overflow information from an arithmetic operation. EN A "A" register enable input. Control input used to either load or hold data into the "A" register. EN B "B" register enable input. Control input used to either load or hold data into the "B" register. FTAB Feedthrough "AB" input. Control input used to select whether the input registers are bypassed or not. ENF "F" register enable output. Control input used to either load or hold data into the "F" register. FTF Feedthrough "F" input. Control input used to select whether the output register is bypassed or not. OSA, OSB S0-S2 Operand select inputs. Selects input data to the ALU on the "A" and "B" ports. Instruction select inputs. Controls which operation the ALU will perform OE Output enable input. Controls the "F" output bus by enabling and disabling the outputs. CLK Clock input. The master clock input for all device registers. VCC, GND Power supply. Absolute Maximum Ratings Stresses above the AMR may cause permanent damage, extended operation at AMR may degrade performance and affect reliability Condition VCC Supply Voltage with respect to GND Input Signal with respect to GND Signal applied to high impedance outputs Maximum Power Dissapation (PD) Current into Low Outputs Storage Temperature Range Operating Temperature (Ambient) Lead Temperature (soldering, 10 seconds) Junction Temperature (TJ) Units -0.5 to +7.0 -0.5 to VCC+0.5 -0.5 to VCC+0.5 420 25 -65 to +150 -55 to +125 +300 +175 Volts DC V V mW mA C C C C Notes /1 1/ - Must withstand the added PD due to IOS Recommended Operating Conditions Condition Supply Voltage Range (VCC) Case Operating Range (Tc) Units 4.5 to 5.5 Volts DC -55C to +125 C Notes /2 2/ - Maximum PD, Maximum TJ Are Not to Be Exceeded QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 6 of 11 QPL4C381 TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Symbol Conditions 3/ -55CTA+125C,VSS=0V 4.5V VCC 5.5V Device Min 2.4 Max Unit Unless Otherwise Specified Output High Voltage VOH VCC= 4.5V, IOH= -2mA All Output Low Voltage VOL VCC= 4.5V, IOL= 8mA All Input High Voltage VIH All 2.0 V Input Low Voltage VIL All 0 V Input Current IIX VCC= 5.5V All 20 A Output Leakage Current IOZ VCC= 5.5V All 20 A Dynamic Supply Current ICC1 VCC= 5.5V /5 All 30 mA Quiescent Power Supply Current ICC2 VCC = 5.5V /6 All 1.5 mA Input Capacitance CIN VIN = 0V, VCC = 5.0V TA = 25C, f = 1MHz VOUT = 0V, VCC = 5.0V TA = 25C, f = 1MHz All 5 pF All 8 pF FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 28 26 34 28 50 34 34 28 32 22 23 22 38 28 38 28 38 28 56 34 34 28 50 34 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns /8 Clock to F0-F15 Clock to P, G Clock to OVF, ZERO Clock to C16 C0 to OVF, ZERO C0 to C16 S0-S2,OSA,OSB to P,G S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 Clock to F0-F15 Clock to P,G Clock to OVF, ZERO 1 2 3 4 5 6 7 8 9 10 11 12 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 V 0.5 Page 7 of 11 V QPL4C381 TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Symbol Conditions 3/ -55CTA+125C,VSS=0V 4.5V VCC 5.5V Device Min Max Unit 34 28 32 26 32 22 23 22 46 30 38 28 38 28 38 28 32 28 46 28 36 28 28 26 32 22 23 22 38 28 38 28 38 28 45 30 32 28 46 28 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unless Otherwise Specified Clock to C16 C0 to F0-F15 C0 to OVF, ZERO C0 to C16 S0-S2,OSA,OSB to F0-F15 S0-S2,OSA,OSB to P,G S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15, B0-B15 to P,G A0-A15, B0-B15 to OVF, ZERO A0-A15, B0-B15 to C16 Clock to F0-F15 C0 to OVF, ZERO C0 to C16 S0-S2,OSA,OSB to P,G S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15, B0-B15 to F0-F15 A0-A15, B0-B15 to P,G A0-A15, B0-B15 to OVF, ZERO 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 8 of 11 QPL4C381 TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Symbol Conditions 3/ -55CTA+125C,VSS=0V 4.5V VCC 5.5V Device Min Max Unit 36 28 32 26 32 22 23 22 46 30 38 28 38 28 38 28 56 34 34 28 50 34 34 28 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unless Otherwise Specified A0-A15, B0-B15 to C16 C0 to F0-F15 C0 to OVF, ZERO C0 to C16 S0-S2,OSA,OSB to F0-F15 S0-S2,OSA,OSB to P,G S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 Clock (OSA,OSB=0) to F0-F15 Clock (OSA,OSB=0) to P,G Clock (OSA,OSB=0) to OVF, ZERO Clock (OSA,OSB=0) to C16 A0-A15, B0-B15 Setup Time A0-A15, B0-B15 Hold Time A0-A15, B0-B15 Setup Time A0-A15, B0-B15 Hold Time EN A, EN B Setup Time EN A, EN B Hold Time ENF Setup Time ENF Hold Time 33 34 35 36 37 38 39 40 65 41 42 43 44 45 46 47 48 49 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1, FTF=1, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0, FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 FTF=0, QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 QPL4C381-45 50 CL=30pF, VCC=4.5V QPL4C381-35 QPL4C381-45 51 CL=30pF, VCC=4.5V QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 QPL4C381-35 8 8 3 3 33 20 3 3 10 10 2 2 10 10 2 2 Page 9 of 11 QPL4C381 TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Symbol Conditions 3/ -55CTA+125C,VSS=0V 4.5V VCC 5.5V Device Min FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 20 12 0 0 20 12 0 0 36 20 0 0 36 20 0 0 38 26 15 12 15 12 Max Unit 20 18 20 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unless Otherwise Specified C0 Setup Time C0 Hold Time C0 Setup Time C0 Hold Time S0-S2,OSA,OSB Setup Time S0-S2,OSA,OSB Hold Time S0-S2,OSA,OSB Setup Time S0-S2,OSA,OSB Hold Time Minimum Cycle Time 52 53 54 55 56 57 58 59 60 FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=0 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 FTAB=1 QPL4C381-45 CL=30pF, VCC=4.5V QPL4C381-35 CL=30pF, VCC=4.5V QPL4C381-45 QPL4C381-35 High Going Pulse 61 CL=30pF, VCC=4.5V 62 CL=30pF, VCC=4.5V QPL4C381-45 QPL4C381-35 Low Going Pulse QPL4C381-45 QPL4C381-35 Tri-State Enable Time 63 CL=30pF, VCC=4.5V QPL4C381-45 QPL4C381-35 Tri-State Disable Time 64 CL=30pF, VCC=4.5V QPL4C381-45 /7 QPL4C381-35 NOTES 3/ Test Conditions assume signal transition times of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOH, IOL and 30pF. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required device input levels relative to device supply pins. All tests must be performed using worst-case test conditions, unless otherwise specified. 4/ For test purposes, not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. Guaranteed if not tested. 5/ Tested with all outputs changing every cycle and no load at a 5MHz clock rate. 6/ Tested with all inputs within 0.1V of VCC or GND, no load. 7/ Tested with IOL = 10mA, IOH = 10mA. 8/ Tested only for initial qualification and after process or design changes which may effect capacitance. Ordering Information QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 10 of 11 QPL4C381 Part Number Package (Mil-Std-1835) Generic QPL4C381KMB45-MIL (Similar to: 5962-8995901YA) QPL4C381GMB45-MIL (Similar to: 5962-8995901ZC) QPL4C381KMB30-MIL (Similar to: 5962-8995902YA) QPL4C381GMB30-MIL (Similar to: 5962-8995902ZA) CMGA3-P68 QPL4C381KMB45 CQCC1-N68 QPL4C381GMB45 CMGA3-P68 QPL4C381KMB30 CQCC1-N68 QPL4C381GMB30 QP Semiconductor supports Source Control Drawing (SCD), and custom package development for this product family. Notes: Package outline information and specifications are defined by Mil-Std-1835 package dimension requirements. "-MIL" products manufactured by QP Semiconductor are compliant to the assembly, burn-in, test and quality conformance requirements of Test Methods 5004 & 5005 of Mil-Std-883 for Class B devices. This datasheet defines the electrical test requirements for the device(s). The listed drawings, Mil-PRF-38535, Mil-Std-883 and Mil-Std-1835 are available online at http://www.dscc.dla.mil/ Additional information is available at our website http://www.qpsemi.com QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 11 of 11