PRELIMINARY DATA SHEET MICRONAS Edition Jan. 8, 2002 6251-575-1PD DAC 3555A Stereo Audio DAC MICRONAS DAC 3555A PRELIMINARY DATA SHEET Contents Page Section Title 3 3 3 1. 1.1. 1.2. Introduction Main Features Differences between DAC 3555A and DAC 3550A 6 6 7 7 7 7 7 7 8 8 9 9 9 10 10 10 11 11 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.10.1. 2.10.2. 2.11. 2.12. 2.13. 2.14. 2.15. Functional Description I2S Interface Interpolation Filter Variable Sample and Hold 3rd-order Noise Shaper and Multibit DAC Analog Low-pass Input Select and Mixing Matrix Postfilter Op Amps, Deemphasis Op Amps, and Line-Out Analog Volume Headphone Amplifier Clock System Standard Mode MPEG Mode I2C Bus Interface Registers Chip Select Power Modes Oscillator 12 12 13 15 15 15 15 16 16 17 18 20 20 21 23 3. 3.1. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.3.5. 3.4. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.3. Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Audio Pins Oscillator and Clock Pins Other Pins Pin Configuration Pin Circuits Control Registers Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics 28 28 28 29 29 30 30 30 31 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.5.1. 4.5.2. 4.6. Applications Line Output Details Recommended Low-Pass Filters for Analog Outputs Recommendations for Filters and Deemphasis Recommendations for MegaBass Filter without Deemphasis Power-up/down Sequence Power-up Sequence Power-down Sequence Typical Applications 34 5. Data Sheet History 2 Micronas DAC 3555A PRELIMINARY DATA SHEET Stereo Audio DAC 1. Introduction The DAC 3555A is a single-chip, high-precision, stereo digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping. With Micronas' unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio have been achieved. The DAC 3555A is controlled via I2C bus. 2 Digital audio input data is received by a versatile I S interface. The analog back-end consists of internal analog filters and op amps for cost-effective additional external sound processing. The DAC 3555A provides line-out, headphone/speaker amplifiers, and volume control. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported. The DAC 3555A is designed for all kinds of applications in the audio and multimedia field, such as: MPEG players, CD players, DVD players, CD-ROM players, mobile phones, etc. - SNR of 103 dB(A) - I2C bus, I2S bus - internal clock oscillator - sample rates from 8 kHz to 96 kHz - analog deemphasis for 44.1 kHz - analog volume and balance: +18...-75 dB and mute - THD better than 0.01% - two additional analog stereo inputs (AUX) with source selection and mixing - supply range: 2.7 V...5.5 V - zero-power mode - additional line-out - on-chip op amps for cost-effective external analog sound processing - pin-compatible to DAC 3550A The DAC 3555A ideally complements the MP3 audio decoders MAS 3507D, MAS 35x9F, and PUC 303xA. - PMQFP44 or PQFN40 package No crystal or external clock required for standard applications with sample rates from 32 to 48 kHz and 96 kHz. It is required for automatic sample rate detection below 32 kHz, MPEG mode (refer to Section 2.10.1.), and use of clock output CLKOUT. 1.2. Differences between DAC 3555A and DAC 3550A - new zero-power mode - operation in I2C mode only. Stand-alone operation is not supported. - no master main input clock required - new quiet wake-up mode: after power-on, the DAC 3555A switches into zero-power mode. Waking-up is done via I2C command. This feature avoids audible "plops". - no external crystal required - sample rates up to 96 kHz - integrated stereo headphone amplifier and mono speaker amplifier - not register-compatible to DAC 3550A 1.1. Main Features Analog Inputs WSI CLI I 2S DRI SDA SCL Interpolation Filter DAC Input Select and Mixing Volume and Headphone Amplifier OUTL OUTR Line Out 2 I C Fig. 1-1: Block diagram of the DAC 3555A Micronas 3 DAC 3555A PRELIMINARY DATA SHEET Display, Keyboard I2C USB PC PUC 303xA clock input1) MP3, WMA, AAC Line Out DAC 3555A I2S UART SDMI compliant SD-Card, MMC Compact Flash Microdrive IDE R/W Line in 1) only necessary for automatic sample rate detection Fig. 1-2: Typical application: Secure Music Player 4 Micronas DAC 3555A PRELIMINARY DATA SHEET CLI DAI WSI 23 24 25 I2S Sample Rate Detection Digital Supply Interpolation Filter Analog Supply PLL Variable S & H CLKOUT 14 XTO 13 XTI 12 3rd-order Noise Shaper & Multibit DAC Osc. AUX2L 29 AUX1L 31 DEEML 34 FOPL 38 FOUTL 37 FINL 39 Input Select Switch Matrix Postfilter Op Amps Deemphasis Op Amps Line-Out Vdd 17 Vss 9 AVDD0 10 AVDD1 3 AVSS0 2 AVSS1 44 VREF 1 I2C Control Analog Low-pass Filter 18 AGNDC 16 SDA 15 SCL 27 TESTEN 26 PORQ 21 DEECTRL 19 MCS1 20 MCS2 32 AUX1R 30 AUX2R 35 DEEMR 42 FOPR 41 FOUTR 43 FINR Analog Volume Headphone Amplifier 5 7 OUTL OUTR Fig. 1-3: Block diagram of the DAC 3555A Micronas 5 DAC 3555A PRELIMINARY DATA SHEET 2. Functional Description 2.1. I2S Interface The I2S interface is the digital audio interface between the DAC 3555A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It covers most of the I2S-compatible formats. Automatic Detection No I2C control is required to switch between 16- and 32-bit mode. It is recommended to switch the DAC 3555A into mute position during changing between 16- and 32-bit mode. For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available). All modes have two common features: 1. The MSB is left justified to an I2S frame identification (WSI) transition. 2. Data is valid on the rising edge of the bit clock CLI. 16-bit mode In this case, the bit clock is 32 x fsaudio. Maximum word length is 16 bit. 32-bit mode In this case, the bit clock is 64 x fsaudio. Maximum word length is 32 bit. Left-Right Selection Standard I2S format defines an audio frame always starting with left channel and low-state of WSI. However, I2C control allows changing the polarity of WSI. Delay Bit Standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I2C control. Note: Volume mute should be applied before changing I2S mode in order to avoid audible clicks. Vh CLI Vl Vh DAI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Vl programmable delay bit WSI Vh Vl left 16-bit audio sample right 16-bit audio sample Fig. 2-1: I2S 16-bit mode (LR_SEL = 0) Vh CLI Vl Vh DAI 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0 Vl programmable delay bit WSI Vh Vl left 32-bit audio sample right 32-bit audio sample Fig. 2-2: I2S 32-bit mode (LR_SEL = 0) 6 Micronas DAC 3555A PRELIMINARY DATA SHEET 2.2. Interpolation Filter 2.6. Input Select and Mixing Matrix The interpolation filter increases the sampling rate by a factor of 8. The characteristic for fsaudio = 48 kHz is shown in Fig. 2-1. This block is used to switch between or mix the auxiliary inputs and the signals coming from the DAC. A switch matrix allows to select between mono and stereo mode as shown in Fig. 2-1. dB 0 '$' '$, :6, -0.02 -0.04 )287/ '$ )2875 -0.06 -0.08 $8;/ - -0.1 $8;5 - -0.12 $8;/ - $8;5 - -0.14 0 5000 10000 15000 20000 f/Hz Fig. 2-1: 18 Interpolation filter; frequency range: 0...22 kHz $8;B06 ,16(/B$8; ,16(/B$8; ,16(/B'$& Fig. 2-1: Switch matrix 2.3. Variable Sample and Hold The advantage of this system is that even at low sample frequencies the out-of-band noise is not scaled down to audible frequencies. Mono mode is realized by adding left and right channel. 2.4. 3rd-order Noise Shaper and Multibit DAC 2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out The 3rd-order noise shaper converts the oversampled audio signal into a 5-bit noise-shaping signal at a high sampling rate. This technique results in extremely low quantization noise in the audio band. This block contains the active components for the analog postfilters and the deemphasis network. The op amps and all I/O-pins for this block are shown in Fig. 2-2. 2.5. Analog Low-pass The analog low-pass is a first order filter with a cut-off frequency of approximately 1.4 MHz which removes the high-frequency components of the noise-shaping signal. Micronas 7 DAC 3555A PRELIMINARY DATA SHEET AGNDC + For external components, see section "Applications" 3.3 F/100 nF + OUTL VREF FOUTL DEEML FOPL FOUTR DEEMR FOPR - Speaker 1.5 k 150 F AVSS AVOL_R optional line-out >16 @5 VAVDD >10 @3 VAVDD 10 ...47 FINL from switch matrix 16...32 10 ...47 FINR - Headphones 150 F - IRPA AVOL_L + For external components, see section "Applications" AVDD 1.5 k OUTR to mC (HP-switch) Fig. 2-2: Postfilter op amps, deemphasis op amps, and line-out 2.8. Analog Volume Table 2-1: Volume Control The analog volume control covers a range from +18 dB to -75 dB. The lowest step is the mute position. Volume/dB AVOL 18.0 111000 Step size is split into a 3-dB and a 1.5-dB range: 16.5 110111 -75 dB...-54 dB: 3 dB step size -54 dB...+18 dB: 1.5 dB step size 15.0 110110 13.5 110101 2.9. Headphone Amplifier - - The headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or a mono loudspeaker. The stereo headphones require external 10...47- serial resistors in both channels. If a loudspeaker is connected to these outputs, the power amplifier for the right channel must be switched to inverse polarity. In order to optimize the available power, the source of the two output amplifiers should be identical, i.e. a monaural signal. 0.0 101100 (default) -1.5 101011 - - -54.0 001000 -57.0 000111 - - -75 000001 Mute 000000 Please note, that if a speaker is connected, it should strictly be connected as shown in Fig. 2-2. Never use a separate connector for the speaker, because electrostatic discharge could damage the output transistors. 8 Micronas DAC 3555A PRELIMINARY DATA SHEET 2.10. Clock System 2.10.1. Standard Mode The advantage of the DAC 3555A clock system is that no external master clock is needed. Most DACs need 256 x fsaudio, 384 x fsaudio, or at least an asynchronous clock. In standard mode, sample rates from 48 kHz to 32 kHz are handled without I2C control automatically. The setting for this range is the default setting. Other sample rates require an I2C control to set the PLL divider. This ensures that even at low sample rates, the DAC 3555A runs at a high clock rate. This avoids audible effects due to the noise-shaping technique of the DAC 3555A. Sample rate range is continuous from 8 to 48 kHz. The I2C setting of non-standard sample rates must follow Table 2-2. All internal clocks are generated by a PLL circuit, which locks to the I2S bit clock (CLI). If no I2S clock is present, the PLL runs free, and it is guaranteed that there is always a clock to keep the IC controllable by I2C. The device can be set to two different modes: - Standard mode - MPEG mode In the standard mode, I2C subaddressing is possible (ADR0, ADR1, ADR2). MPEG mode always uses ADR3. To select the modes, the MCS1/MCS2 pins must be set according to Table 2-2. Table 2-2: Operation Modes An additional mode allows automatic sample rate detection. In this case, the clock oscillator is required and must run at frequencies between 13.3 MHz to 17 MHz. This mode, however, does not support continuous sample rates. Only the following sample rates are allowed: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz 22.05 kHz, The sample rate detection allows a tolerance of 200 ppm at WSI. 2.10.2. MPEG Mode MCS1 MCS2 Mode Subaddress Default Sample Rate 0 0 Standard ADR0 32-48 kHz 0 1 Standard ADR1 32-48 kHz 1 0 Standard ADR2 32-48 kHz 1 1 MPEG ADR3 Automatic This mode should be used in conjunction with PUC 30x3A in MPEG player applications. All MPEG sample rates from 8 to 48 kHz can be detected if the PUC 30x3A sends a clock signal between 13.3 MHz and 17 MHz to the DAC 3555A. The internal processing and the DAC itself are automatically adjusted to keep constant performance throughout the entire range. I2C control for sample rate adjustment is not needed in this case. The MPEG sample rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz As in standard mode, the sample rate detection allows a tolerance of 200 ppm at WSI. Subaddressing is not possible in MPEG mode; this means, in multi-DAC systems, only one DAC 3555A can run in MPEG mode. Micronas 9 DAC 3555A PRELIMINARY DATA SHEET 2.11. I2C Bus Interface Table 2-3: I2C Register Address The DAC 3555A is equipped with an I2C bus slave interface. The I2C bus interface uses one level of subaddressing: The I2C bus address is used to address the IC. The subaddress allows chip select in multi DAC applications and selects one of the three internal registers. The registers are write-only. The I2C bus chip address is given below. RA1 RA0 Mnemonics 0 1 SR_REG 1 0 AVOL 1 1 GCFG Device Address = 4Dhex. The registers of the DAC 3555A have 8- or 16-bit data size; 16-bit registers are accessed by writing two 8-bit data words. 2.12. Registers In Section 3.5. "Control Registers" on page 18, a definition of the DAC 3555A control registers is shown. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in the table. 2.13. Chip Select Chip select allows to connect up to four DAC 3555A to an I2C control bus. The chip subaddresses are defined by the MCS1/MCS2 (Mode and Chip Select) pins. Only in standard mode, chip select is possible. MPEG mode always uses chip subaddress 3. Register address and chip select are mapped into the subaddress field in Table 2-4. Table 2-4: I2C Subaddress All registers are write-only. The register address is coded by 3 bits (RA1, RA0) according to Table 2-3. 7 6 MCS2 MCS1 S 4Dhex w Ack sub_adr Ack 1 byte data Ack P S 4Dhex w Ack sub_adr Ack 1 byte data Ack SDA SCL S 1 0 P 5 4 3 2 1 0 RA1 RA0 8-bit I2C write access 1 byte data Ack W R Ack Nak S P = = = = = = P 16-bit I2C write access 0 1 0 1 Start Stop Fig. 2-1: I2C bus protocols for write operations 10 Micronas DAC 3555A PRELIMINARY DATA SHEET 2.14. Power Modes 2.15. Oscillator The DAC 3555A supports four different power modes, which can be selected by I2C. The I2C-controlled oscillator (see Section 3.5. "Control Registers" on page 18) switches on in the following modes, only: 1. Zero Power This is the default mode after power up. In this mode digital and analog blocks are inactive. Please note that minimum power consumption is only achieved if all digital input pins connected to peripheral circuits are low or tristate. 2. Analog Stand-by This mode activates the internal analog reference system and allows a fast and quiet transition to the active modes below. 3. Aux to Line This active mode is used, if no digital audio signals are present. Only the analog back-end is active. 1. DAC ON - Standard Mode - automatic sample rate detection 2. DAC ON - MPEG Mode In all other modes the oscillator is not required internally and therefore switched off. For test purpose it is possible to switch on the oscillator in all modes (control register AVOL, bit 15). It is not recommended to use this option in normal applications. 4. Full Power All blocks are active in this mode. Start-up sequence: The recommended sequence for stepping through the power modes is shown in Section 4.5. "Power-up/down Sequence" on page 30. Micronas 11 DAC 3555A PRELIMINARY DATA SHEET 3. Specifications 3.1. Outline Dimensions 10 x 0.8 = 8 0.1 0.17 0.06 0.8 23 10 0.1 0.34 0.05 13.2 0.2 12 44 0.8 22 34 10 x 0.8 = 8 0.1 33 1 11 2.0 0.1 13.2 0.2 2.15 0.2 0.1 10 0.1 SPGS706000-5(P44)/1E Fig. 3-1: 44-Pin Plastic Metric Quad Flat Package (PMQFP44) Weight approximately 0.4 g Dimensions in mm exposed die pad SPGS709000-1(P40)/2E Fig. 3-2: 40-Pin Plastic Quad Flat No leads package (PQFN40) Weight approximately 0.096 g Dimensions in mm 12 Micronas DAC 3555A PRELIMINARY DATA SHEET 3.2. Pin Connections and Short Descriptions NC LV VSS X VDD = not connected, leave vacant = if not used, leave vacant = if not used, connect to VSS = obligatory; connect as described in application diagram = connect to VDD Pin No. Pin Name Type Connection Short Description PMQFP 44-pin PQFN 40-pin 1 31 AGNDC IN/OUT X Analog reference Voltage 2 32 AVSS1 IN X VSS 1 for audio back-end 3 33 AVSS0 IN X VSS 0 for audio output amplifiers 4 16 NC LV Not connected 5 34 OUTL LV Audio Output: Headphone left or Speaker + 6 26 NC LV Not connected 7 37 OUTR LV Audio Output: Headphone right or Speaker - 8 35 NC LV Not connected 9 38 AVDD0 IN X VDD 0 for audio output amplifiers 10 40 AVDD1 IN X VDD 1 for audio back-end 11 36 NC LV Not connected 12 1 XTI IN X Quartz oscillator pin 1 13 2 XTO IN/OUT X Quartz oscillator pin 2 14 3 CLKOUT OUT LV Clock Output 15 4 SCL IN LV I2C clock 16 5 SDA IN/OUT LV I2C data 17 6 VSS IN X Digital VSS 18 7 VDD IN X Digital VDD 19 8 MCS1 IN X I2C Chip Select 1 20 9 MCS2 IN X I2C Chip Select 2 21 10 DEECTRL IN VSS Deemphasis on/off Control 22 39 NC IN LV Not connected 23 11 CLI VSS I2S Bit Clock 24 12 DAI IN VSS I2S Data 25 13 WSI IN VSS I2S Frame Identification Micronas (If not used) OUT OUT 13 DAC 3555A Pin No. PRELIMINARY DATA SHEET Pin Name Type Connection Short Description PMQFP 44-pin PQFN 40-pin 26 14 PORQ IN VDD Power-On Reset, active-low 27 15 TESTEN IN X Test Enable 28 16 NC LV Not connected 29 17 AUX2L IN LV AUX2 left input for external analog signals (e.g. tape) 30 18 AUX2R IN LV AUX2 right input for external analog signals (e.g. tape) 31 19 AUX1L IN LV AUX1 left input for external analog signals (e.g. FM) 32 20 AUX1R IN LV AUX1 right input for external analog signals (e.g. FM) 33 - NC LV Not connected 34 21 DEEML OUT LV Deemphasis Network Left 35 22 DEEMR OUT LV Deemphasis Network Right 36 - NC LV Not connected 37 23 FOUTL OUT X Output to left external filter 38 24 FOPL IN/OUT X Filter op amp inverting input, left 39 25 FINL IN/OUT X Input for FOUTL or filter op amp output (line out) 40 - NC LV Not connected 41 27 FOUTR OUT X Output to right external filter 42 28 FOPR IN/OUT X Right Filter op amp inverting input 43 29 FINR IN/OUT X Input for FOUTR or filter op amp output (line out) 44 30 VREF IN X Analog reference Ground 14 (If not used) Micronas PRELIMINARY DATA SHEET 3.3. Pin Descriptions 3.3.1. Power Supply Pins The DAC 3555A combines various analog and digital functions which may be used in different modes. For optimized performance, major parts have their own power supply pins. All VSS power supply pins must be connected. VDD VSS The VDD and VSS power supply pair are connected internally with all digital parts of the DAC 3555A. AVDD0 AVSS0 AVDD0 and AVSS0 are separate power supply pins that are exclusively used for the on-chip headphone/ loudspeaker amplifiers. AVDD1 AVSS1 The AVDD1 and AVSS1 pins supply the analog audio processing parts, except for the headphone/loudspeaker amplifiers. 3.3.2. Analog Audio Pins AGNDC Reference for analog audio signals. This pin is used as reference for the internal op amps. This pin must be blocked against VREF with a 3.3 F capacitor. Note: The pin has a typical DC-level of 1.5/2.25 V. It can be used as reference input for external op amps when no current load is applied. VREF Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean ground potential. Any external distortions on this pin will affect the analog performance of the DAC 3555A. AUX1L AUX1R AUX2L AUX2R The AUX pins provide two analog stereo inputs. Auxiliary input signals, e.g. the output of a conventional receiver circuit or the output of a tape recorder can be connected with these inputs. The input signals have to be connected by capacitive coupling. DAC 3555A FOUTL FOPL FINL FOUTR FOPR FINR Filter op amps are provided in the analog baseband signal paths. These inverting op amps are freely accessible for external use by these pins. The FOUTL/R pins are connected with the buffered output of the internal switch matrix. The FOPL/R-pins are directly connected with the inverting inputs of the filter op amps. The FINL/R pins are connected with the outputs of the op amps. The driving capability of the FOUTL/R pins is not sufficient for standard line output signals. Only the FINL/R pins are suitable for line output. OUTL OUTR The OUTL/R pins are connected to the internal output amplifiers. They can be used for either stereo headphones or a mono loudspeaker. The signal of the right channel amplifier can be inverted for mono loudspeaker operation. Caution: A short circuit at these pins for more than a momentary period may result in destruction of the internal circuits. 3.3.3. Oscillator and Clock Pins XTI XTO The XTI pin is connected to the input of the internal crystal oscillator, the XTO pin to its output. Both pins should be directly connected to the crystal and two ground-connected capacitors (see application diagram). CLKOUT The CLKOUT pin provides a buffered output of the crystal oscillator. Caution: Power dissipation limit may be exceeded in case of short to VSS or VDD. CLI DAI WSI These three pins are inputs for the digital audio data DAI, frame indication signal WSI, and bit clock CLI. The digital audio data is transmitted in an I2S-compatible format. Audio word lengths of 16 and 32 bits are supported, as well as SONY and Philips I2S protocol. SCL SDA SCL (serial clock) and SDA (serial data) provide the connection to the serial control interface (I2C). Micronas 15 DAC 3555A PRELIMINARY DATA SHEET 3.3.4. Other Pins TESTEN Test enable. This pin is for test purposes only and must always be connected to VSS. PORQ This pin may be used to reset the chip. If not used, this pin must be connected to VDD. DEEML DEEMR These pins connect an external analog deemphasis network to the signal path in the analog back-end. This connection can be switched on and off by an internal switch which is controlled either by I2C or the DEECTRL-pin. DEECTRL Deemphasis can be switched on and off with this pin. MCS1 MCS2 Mode select pins to select MPEG, Standard Mode, and I2C subaddress. 3.3.5. Pin Configuration NC NC AUX2L TESTEN AUX2R PORQ AUX1L FOPL FOPR WSI AUX1R FINL FOUTR FOUTL FINR DAI NC DEEMR VREF DEEML CLI 30 29 28 27 26 25 24 23 22 21 20 AUX1R DEEML 34 22 NC AVSS1 32 19 AUX1L DEEMR 35 21 DEECTRL AVSS0 33 18 AUX2R NC 36 20 MCS2 OUTL 34 17 AUX2L FOUTL 37 19 MCS1 NC 35 16 NC FOPL 38 18 VDD NC 36 15 TESTEN FINL 39 17 VSS OUTR 37 14 PORQ NC 40 16 SDA AVDD0 38 13 WSI FOUTR 41 15 SCL NC 39 12 DAI FOPR 42 14 CLKOUT AVDD1 40 11 CLI FINR 43 13 XTO VREF 44 12 XTI 33 32 31 30 29 28 27 26 25 24 23 DAC 3555A 1 2 3 4 5 6 7 8 9 10 11 AGNDC 31 DAC 3555A 1 2 3 4 5 6 7 8 9 XTI DEECTRL XTO AGNDC NC AVSS1 AVDD1 AVSS0 AVDD0 NC 10 MCS2 CLKOUT MCS1 SCL SDA VDD VSS NC OUTL OUTR Fig. 3-2: PQFN40 package NC Fig. 3-1: PMQFP44 package 16 Micronas DAC 3555A PRELIMINARY DATA SHEET 3.4. Pin Circuits VDD FOUTn N VSS Fig. 3-3: Input/Output Pins SDA, SCL AGNDC Fig. 3-9: Output Pins FOUTL, FOUTR AGNDC 125 k Fig. 3-4: Input Pins PORQ, DAI VREF AVSS0/1 Fig. 3-10: Pins AGNDC, VREF 15 k XTO Fig. 3-5: Input Pins WSI, CLI 500 k VDD XTI P Fig. 3-11: Input/Output Pins XTI, XTO N VSS Fig. 3-6: Output Pin CLKOUT sel/nonsel AUXnL mono/stereo AGNDC ext. filter network AGNDC FOUTn DEEM FOPn FINn mono/stereo AUXnR sel/nonsel (DEEMCTRL) AGNDC Fig. 3-7: Pins FINR, FOPR, FINL, FOPL, DEEML, DEEMR Fig. 3-12: Input Pins AUX1R, AUX1L, AUX2R, AUX2L, AGNDC VDD AGNDC OUTn VSS Fig. 3-13: Input Pins MCS1, MCS2, DEECTRL Fig. 3-8: Output Pins OUTL, OUTR Micronas 17 DAC 3555A PRELIMINARY DATA SHEET 3.5. Control Registers I2C Subaddress (hex) Number of Bits Mode Function Default Values (hex) Name SAMPLE RATE CONTROL SR_REG 01 8 w sample rate control 0hex bit[7:5] not used, set to 0 bit[4] L/R-bit 0 (WSI = 0 left channel)1) 1 (WSI = 0 right channel)1) LR_SEL bit[3] Delay-Bit 0 No Delay 1 1 bit Delay SP_SEL bit[2:0] sample rate control 000 32-48 kHz 001 26-32 kHz 010 20-26 kHz 011 14-20 kHz 100 10-14 kHz 101 8-10 kHz 110 96 kHz2) 111 automatic detection3) SRC_48 SRC_32 SRC_24 SRC_16 SRC_12 SRC_8 SRC_96 SRC_A ANALOG VOLUME AVOL 02 16 w audio volume control bit[15] Oscillator on/off (for test purpose only) 0 Oscillator on if internally required 1 Oscillator always on OSC bit[14] deemphasis on/off 0 deemphasis off 1 deemphasis on DEEM bit[13:8] analog audio volume level left: 000000 mute 000001 -75 dB 101100 +0 dB (default) 111000 +18 dB 1) 2) 3) 18 0hex bit[7:6] not used, set to 0 bit[5:0] analog audio volume level right 000000 mute -75 dB 000001 101100 +0 dB (default) 111000 +18 dB AVOL_L AVOL_R see Fig. 2-1 and Fig. 2-2 on page 6 96 kHz allowed for VDD =5 V only 96 kHz is not supported by automatic detection Micronas DAC 3555A PRELIMINARY DATA SHEET I2C Subaddress (hex) Number of Bits Mode Function Default Values (hex) Name Global Configuration GCFG 03 8 w global configuration bit[7] select 3 V - 5 V mode 0 3V 1 5V SEL_53V bit[6:4] DAC and Power-Mode PWMD bit[6] 0 0 1 1 0 1 1) 0hex bit[5] 0 1 0 1 x1) x1) bit[4] 0 0 0 0 1 1 DAC off - Zero Power DAC off - Analog Standby DAC off - Aux to Line DAC off - Full Power DAC on - Aux to Line DAC on - Full Power bit[3] AUX2 select 0 AUX2 off 1 AUX2 on INSEL_AUX2 bit[2] AUX1 select 0 AUX1 off 1 AUX1 on INSEL_AUX1 bit[1] aux-mono/stereo 0 stereo 1 mono AUX_MS bit[0] invert right power amplifier 0 not inverted 1 inverted IRPA don't care Micronas 19 DAC 3555A PRELIMINARY DATA SHEET 3.6. Electrical Characteristics 3.6.1. Absolute Maximum Ratings Symbol Parameter TA Min. Max. Unit Ambient Temperature Range -40 85 C TS Storage Temperature -40 125 C Pmax Power Dissipation 500 mW VSUPA Analog Supply Voltage1) AVDD0/1 -0.3 6 V VSUPD Digital Supply Voltage VDD -0.3 6 V VIdig1 Input Voltage, digital inputs MCS1, MCS2, DEECTRL -0.3 VSUPD + 0.3 V VIdig2 Input Voltage, digital inputs WSI, CLI, DAI, PORQ, SCL, SCI -0.3 6 V IIdig Input Current, all digital inputs -5 +5 mA VIana Input Voltage, all analog inputs -0.3 VSUPA + 0.3 V IIana Input Current, all analog inputs -5 +5 mA IOaudio Output Current, audio output2) -0.2 0.2 A IOdig Output Current, all digital outputs3) -10 10 mA 1) 2) 3) Pin Name OUTL/R Both pins have to be connected together! These pins are NOT short-circuit proof! Total chip power dissipation must not exceed absolute maximum rating Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 20 Micronas DAC 3555A PRELIMINARY DATA SHEET 3.6.2. Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit Temperature Ranges and Supply Voltages TA Ambient Temperature Range1) 0 70 C TAE Extended Ambient Temperature Range1) -40 85 C VSUPA1 Analog Audio Supply Voltage AVDD0/1 3.02) 3.3 5.5 V VSUPD Digital Supply Voltage VDD 2.7 3.3 5.5 V VSUPD96 Digital Supply Voltage (if sample rate is 96 kHz) VDD 4.75 5.0 5.5 V AVDD0/1 VSUPD -0.25 V 5.5 V 1.0 Relative Supply Voltages VSUPA Analog Audio Supply Voltage in relation to the Digital Supply Voltage Analog Reference 3.3 F AGNDC 10 nF CAGNDC1 Analog Reference Capacitor AGNDC CAGNDC2 Analog Reference Capacitor Analog Audio Inputs VAI Analog Input Voltage AC, SEL_53V = 0 AUXnL/R3) 0.35 0.7 Vrms VAI Analog Input Voltage AC, SEL_53V = 1 AUXnL/R3) 0.525 1.05 Vrms 6 k pF 7.5 k pF Analog Filter Input and Output ZAFLO ZAFLI 1) 2) 3) 4) Analog Filter Load Output4) Analog Filter Load Input4) FOUTL/R FINL/R 7.5 5.0 The functionality of the IC in the extended temperature range has been verified by electrical characterization based on sample tests. All data sheet parameters are valid for normal operating temperature range, only. typically operable down to 2.7 V, without loss of performance n = 1 or 2 Please refer to Section 4.2. "Recommended Low-Pass Filters for Analog Outputs" on page 28. Micronas 21 DAC 3555A Symbol Parameter PRELIMINARY DATA SHEET Pin Name Min. Typ. Max. Unit Audio Line Output1) (680 Series Resistor required) FINL/R 10 1.0 k nF ZAOL_HP Analog Output Load HP (47 Series Resistor required) OUTL/R 32 400 pF ZAOL_SP Analog Output Load SP (bridged) OUTL/R 32 50 pF 16 100 pF 400 kHz Analog Audio Output ZLO Analog Output Load SP (Stereo) I2C Input I2C Clock Frequency SCL VIH Input High Voltage VIL Input Low Voltage CLI, WSI, DAI, PORQ, SCL, SDA fI2C Digital Inputs 0.5x VDD V 0.2 x VDD V External Clock Input VIHx2) Ext. Clock High Voltage XTI 0.25 x VDDmax V VIL Input Low Ext. Clock XTI 0.75 x VDDmin V I2SDut1_96 Duty Cycle of I2S input clock (sample rate=96 kHz) CLI 45 55 % I2SDut1_48 Duty Cycle of I2S input clock (sample rate <=48 kHz) CLI 40 60 % 14.725 17 MHz Crystal Characteristics FP Load Resonance Frequency at Cl = 20 pF REQ Equivalent Series Resistance 12 30 C0 Shunt (parallel) Capacitance 3 5 pF 50 pF 13.3 Load at CLKOUT Output Cload 1) 2) 22 Capacitance CLKOUT 0 Please refer to Section 4.1. "Line Output Details" on page 28. extended clock should be AC-coupled via 10 nF Micronas DAC 3555A PRELIMINARY DATA SHEET 3.6.3. Characteristics At TA = 0 to 70 C, VSUPD = 2.7 to 5.5 V, VSUPA = 3.0 to 5.5 V; typical values at TJ = 27 C, VSUPD = VSUPA = 3.3 V, positive current flows into the IC Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions mA A DAC ON1) DAC OFF2) Digital Supply IVDD Current Consumption VDD 3.7 5.0 VSUPD = 3.3 V (see I2C register GCFG) 7.0 5.0 mA A DAC ON1) DAC OFF2) VSUPD = 5 V Digital Input Pin - Leakage II Input Leakage Current 1 DAI, TESTEN, PORQ, DEECTRL, MCS1/2 A VGND VI VSUP V no load at output Digital Output Pin - Clock Out VOH Output High Voltage VOL Output Low Voltage CLKOUT VSUPD -0.3 0.3 V 60 Iload = 5 mA, VSUPD = 2.7 V A A mA mA Zero Power Analog Standby Aux to Line Full Power I2C Bus Ron Output Impedance SCL, SDA Analog Supply IAVDD Current Consumption Analog Audio AVDD0/1 1.0 630 3.6 8.2 SEL_53 = 0 AVDD = 3.3 V3) 1.0 750 6.0 12.9 A A mA mA Zero Power Analog Standby Aux to Line Full Power SEL_53 = 1 AVDD = 5 V3) (see I2C register GCFG) 1) 2 I S active, 32-bit 2) No I2C traffic 3) 2 mode, fs = 48 kHz DAC on, I S active, 32-bit mode, fs = 48 kHz, 1 kHz @ 0 dBFS volume = 0 dB Micronas 23 DAC 3555A PRELIMINARY DATA SHEET Symbol Parameter Pin Name PSRRAA Power Supply Rejection Ratio for Analog Audio Output AVDD0/1, OUTL/R PSRRLO Power Supply Rejection Ratio for Line Output Min. AVDD0/1, FINL/R Typ. Max. Unit Test Conditions 50 dB 1 kHz sine at 100 mVrms 20 dB 100 kHz sine at 100 mVrms 50 dB 1 kHz sine at 100 mVrms 40 dB 100 kHz sine at 100 mVrms Reference Frequency Generation VDCXTI DC Voltage at Oscillator Pins XTI/O 0.5 x VSUPA V CLI Input Capacitance at Oscillator Pin XTI/O 3 pF Vxtalout Voltage Swing at Oscillator Pins, pp XTI/O 60 Oscillator Start-Up Time 100 % VSUPA 50 ms AVDD/VDD 2.5 V 0.75 Vrms SEL_53V = 0, Analog Audio VAO Analog Output Voltage AC OUTL/R, FOUTL/R, FINL/R GAUX Gain from Auxiliary Inputs to Line Outputs AUXnL/R, FINL/R PHP Output Power (Headphone) OUTL/R 0.65 0.7 RL > 5 k, Analog Gain = 0 dB Input = 0 dBFS digital 1.0 1.05 1.1 Vrms SEL_53V = 1 -0.5 0 0.5 dB f = 1 kHz, sine wave, RL > 5 k 0.5 Vrms to AUXnL/R mW SEL_53V = 0, 5 RL = 32 , Analog Gain = +3 dB, distortion < 1%, external 47 series resistor required PSP Output Power (Speaker) OUTL/R 12 mW SEL_53V = 1 120 mW RL = 32 (bridged), Analog Gain = +3 dB, distortion < 10%, SEL_53V = 0, IRPA = 1 280 mW SEL_53V = 1 -75 GAO Analog Output Gain Setting Range OUTL/R dGAO1 Analog Output Gain Step Size OUTL/R 3.0 dB dGAO2 Analog Output Gain Step Size OUTL/R 1.5 dB EGA1 Analog Output Gain Error OUTL/R 24 -2 18 2 dB dB Analog Gain: -75 dB...-54 dB Analog Gain: -54 dB...+18 dB -46.5 dB Analog Gain -54 dB Micronas DAC 3555A PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. EGA2 Analog Output Gain Error OUTL/R EGA3 Analog Output Gain Error EdGA SNRAUX SNR1 Typ. Max. Unit Test Conditions -1 1 dB -40.5 dB Analog Gain -45 dB OUTL/R -0.5 0.5 dB +18 dB Analog Gain -39 dB Analog Output Gain Step Size Error OUTL/R -0.5 0.5 dB +18 dB Analog Gain -48 dB Signal-to-Noise Ratio from Analog Input to Line Output AUXn, FINL/R 98 dB Signal-to-Noise Ratio from Analog Input to Headphone Output AUXn, OUTn 93 dB SEL_53V = 0: input -40 dB below 0.7 Vrms Signal-to-Noise Ratio OUTL/R Analog Gain = 0 dB, BW =20 Hz...20 kHz unweighted 89 91 dB RL 32 (external 47 series resistor required) BW =20 Hz...0.5 fs1) unweighted, Analog Gain = 0 dB, Input = -20 dBFS FINL/R 90 92 dB RL 5 k, Rdec 612 BW etc. as above 16 bit I2S, SEL_53V = 0 SNR2 Signal-to-Noise Ratio OUTL/R 94 dB 32 bit I2S, SEL_53V = 0 96 dB 16 bit I2S, SEL_53V = 1 98 dB 32 bit I2S, SEL_53V = 1 103 dB(A) 32 bit I2S, SEL_53V = 1 62 dB RL 32 (external 47 series resistor required) BW = 20 Hz..0.5 fs1) unweighted Analog Gain= -40.5 dB, Input = -3 dBFS LevMute Mute Level OUTL/R -110 dBV BW = 20 Hz...22 kHz unweighted, no digital input signal, Analog Gain = Mute RD/A D/A Pass Band Ripple OUTL/R, FOUTL/R -0.1 dB 0...0.446 fs (no external filters used) AD/A D/A Stop Band Attenuation 40 dB 0.55...7.533 fs (no external filters used) BWAUX Bandwidth for Auxiliary Inputs 760 kHz (no external filters used) 1) AUXnL/R, FINL/R BW = 20 Hz...22 kHz if fs = 96 kHz Micronas 25 DAC 3555A PRELIMINARY DATA SHEET Symbol Parameter Pin Name THDALO Total Harmonic Distortion from Auxiliary Inputs to Line Outputs THDDLO Min. Typ. Max. Unit Test Conditions AUXnL/R, FINL/R 0.01 % BW = 20 Hz...22 kHz, unweighted, RL > 5 k Input 1 kHz at 0.5 Vrms Rdec 612 Total Harmonic Distortion (D/A converter to Line Output) FINL/R 0.01 % BW = 20 Hz...0.5 fs1), unweighted, RL > 5 k Input 1 kHz at -3 dBFS Rdec 612 THDHP Total Harmonic Distortion (Headphone) OUTL/R 0.05 % BW = 20 Hz...0.5 fs1), unweighted, RL 32 (47 series resistor required), Analog Gain = 0 dB, Input 1 kHz at -3 dBFS THDSP Total Harmonic Distortion (Speaker) OUTL/R 0.5 % BW = 20 Hz...0.5 fs1), unweighted, RL 32 (speaker bridged), Analog Gain = 0 dB, Input 1 kHz at -3 dBFS XTALKLO Cross-Talk Left/Right Channel (Line Output) AUXnL/R, FOUTL/R, FINL/R -70 -80 dB f = 1 kHz, sine wave, RL > 7.5 k Analog Gain = 0 dB, Input = -3 dBFS or 0.5 Vrms to AUXnL/R XTALKHP Crosstalk Left/Right Channel OUTL/R -70 -80 dB f = 1 kHz, sine wave, OUTL/R: RL 32 (47 series resistor required) Analog Gain = 0 dB, Input = -3 dBFS or 0.5 Vrms to AUXnL/R -70 -80 dB f = 1 kHz, sine wave, FOUTL/R: RL > 7.5 k OUTL/R: RL 32 (47 series resistor required) Analog Gain = 0 dB, Input = -3 dBFS and 0.5 Vrms to AUXnL/R 1.5 V SEL_53V = 0 RL >> 10 M, referred to VREF 2.25 V SEL_53V = 1 RL >> 10 M, referred to VREF (Headphone) XTALK2 Crosstalk between Input Signal Pairs AUXnL/R VAGNDC Analog Reference Voltage AGNDC 1) 26 BW = 20 Hz...22 kHz if fs = 96 kHz Micronas DAC 3555A PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions RIAUX Input Resistance at Input Pins AUXnL/R 12.1 11.6 15 17.9 19.0 k k TJ = 27 C TA = 0 to 70 C1) Input selected, Aux to Line i = 10 A, referred to VREF 24.2 23.3 30 35.8 37.9 k k TJ = 27 C TA = 0 to 70 C1) Input not selected i = 10 A, referred to VREF ROOUT Output Resistance at Output Pins OUTL/R 700 TJ = 27 C Analog Standby i = 200 A, referred to VREF ROFILT Output Resistance of Filter Pins FINL 15 k FINR 11.25 k full power, Mute i = 10 A, referred to VREF VOffI Offset Voltage at Input Pins AUXnL/R -20 20 mV referred to AGNDC VOffO Offset Voltage at Output Pins OUTL/R -10 10 mV Mute referred to AGNDC VOffFO Offset Voltage at Filter Output Pins FOUTL/R -20 20 mV analog standby, referred to AGNDC VOffFI Offset Voltage at Filter Input Pins FINL/R -20 20 mV analog standby, referred to AGNDC dVDCPD Difference of DC Voltage at Output Pins OUTL/R -10 10 mV Analog Gain = Mute, switched from analog standby to full power 1) BW = 20 Hz...22 kHz if fs = 96 kHz Micronas 27 DAC 3555A PRELIMINARY DATA SHEET 4. Applications 11 k 2nd-order 4.1. Line Output Details 11 k 11 k Rdec 220 pF 1.0 nF FINL(R) Cline Rin AVSS FOUTL(R) FOPL(R) FINL(R) AVSS - Fig. 4-1: Use of FINL/R as Line Outputs Table 4-1: Load at FINL/R when used as Line Output for external amplifier Fig. 4-2: 2nd-order low-pass filter Table 4-3: Attenuation of 2nd-order low-pass filter Filter Order Rdec Rin 1st, 2nd, 3rd 680 > 10 k Rdec:Resistor used for decoupling Cline from FINL(R) to achieve stability Frequency Gain 24 kHz -1.5 dB 30 kHz -3.0 dB Cline: Capacitive load according to e.g. cable, amplifier Rin: Input resistance of amplifier 3rd-order 7.5 k 4.2. Recommended Low-Pass Filters for Analog Outputs1) 1st-order 7.5 k 1.8 nF 7.5 k 120 pF 1.8 nF AVSS 330 pF 15 k 15 k FOUTL(R) 15 k FOPL(R) FINL(R) - FOUTL(R) FOPL(R) FINL(R) Fig. 4-3: 3rd-order low-pass filter - Table 4-4: Attenuation of 3rd-order low-pass filter Fig. 4-1: 1st-order low-pass filter Table 4-2: Attenuation of 1st-order low-pass filter Frequency Gain 24 kHz -2.2 dB 30 kHz -3.0 dB 1) 28 Frequency Gain 18 kHz 0.17 dB 24 kHz -0.23 dB 30 kHz -3.00 dB without deemphasis circuit Micronas DAC 3555A PRELIMINARY DATA SHEET 4.3. Recommendations for Filters and Deemphasis 4.4. Recommendations for MegaBass Filter without Deemphasis R3 R1 R1 R2 R4 C3 R5 R2 R3 R4 C1 C2 ON C1 R5 C4 C2 OFF AVSS AVSS AVSS FOUTL(R) FOPL(R) FINL(R) DEEML(R) FOUTL(R) FINL(R) FOPL(R) - - Fig. 4-4: General circuit schematic Fig. 4-1: General circuit schematic Table 4-5: Resistor and Capacitor values Table 4-6: Resistor and Capacitor values 1st order 2nd order 3rd order DC-Gain = 10 dB fc1 = 100 Hz fc2 = 330 Hz R1 (k) 0 7.5 C1 (pF) open 560 R1 (k) 13 R2 (k) 18 11 7.5 C1 (nF) 47 C2 (pF) open 1000 270 R2 (k) 0 R3 (k) 18 11 15 R3 (k) 15 C3 (pF) 180 180 82 R4 (k) 15 R4 (k) 0 11 7.5 R5 (k) 13 R5 (k) 18 22 22 C2 (nF) 47 C4 (nF) 1.8 1.0 1.0 Micronas 29 DAC 3555A PRELIMINARY DATA SHEET 4.5. Power-up/down Sequence VDD In order to get a click-free power-up/down characteristic, it is recommended to use the following sequences: 90% VDDmax PORQ 4.5.1. Power-up Sequence 1. Start VDD from 0 to +3.3 V and start AVDD0/1 from 0 to +3.3 V/+5 V. See Fig. 4-2. <0.4 x VDD >1 ms 2. Release PORQ from 0 to VDD. See Fig. 4-2. 3. Follow the logical power-up sequence in Fig. 4-3. 4.5.2. Power-down Sequence 0.6 x VDD AVDD0/1 90% VDD Fig. 4-2: Electrical power-up sequence Follow the logical power-down sequence in Fig. 4-3. Power-on Sequence: (Power-down Sequence: vice versa) Zero Power muted - release PORQ - prepare analog back-end for line mode or headphone mode. Note: wait 0.5 s before transition to active modes Analog Stand-by muted Power-down Sequence - switch on VDD and AVDD0/1 Power-up Sequence Wait Period t 0s 0s 0s 0s 0.5 s 0s 0s 0s 0s 0s - no wait time required to go back to zero-power mode - switch on active modes Note: Direct transition from zero-power mode to active modes causes plops. - set volume - start I2S if applicable1) - mute before leaving this state 1 DAC off Aux to Line muted DAC off Aux to Line unmuted DAC on Full Power muted DAC on Full Power unmuted ) if the application allows switching on and off the I2S input, it should be done here Fig. 4-3: Logical power-up/down sequence 30 Micronas DAC 3555A PRELIMINARY DATA SHEET n A 4.6. Typical Applications Fig. 4-4: Application circuit schematic 1: Standard application with analog deemphasis. Oscillator not needed. Package: PMQFP44 Micronas 31 DAC 3555A A PUC 303xA extCLK optional n A PRELIMINARY DATA SHEET Fig. 4-5: Application circuit schematic 2: MPEG application with analog Megabass and 14.31818 MHz clock input. Package: PMQFP44 32 Micronas PRELIMINARY DATA SHEET Micronas DAC 3555A 33 DAC 3555A PRELIMINARY DATA SHEET 5. Data Sheet History 1. Preliminary data sheet: "DAC 3555A Stereo Audio DAC", Jan. 8, 2002, 6251-575-1PD. First release of the preliminary data sheet. Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-575-1PD 34 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Micronas