DAC 3555A
Stereo Audio DAC
Edition Jan. 8, 2002
6251-575-1PD
PRELIMINARY DATA SHEET
MICRONAS
MICRONAS
DAC 3555A PRELIMINARY DATA SHEET
2Micronas
Contents
Page Section Title
3 1. Introduction
3 1.1. Main Features
3 1.2. Differences between DAC 3555A and DAC 3550A
6 2. Functional Description
62.1.I
2S Interface
7 2.2. Interpolation Filter
7 2.3. Variable Sample and Hold
7 2.4. 3rd-order Noise Shaper and Multibit DAC
7 2.5. Analog Low-pass
7 2.6. Input Select and Mixing Matrix
7 2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out
8 2.8. Analog Volume
8 2.9. Headphone Amplifier
9 2.10. Clock System
9 2.10.1. Standard Mode
9 2.10.2. MPEG Mode
10 2.11. I2C Bus Interface
10 2.12. Registers
10 2.13. Chip Select
11 2.14. Power Modes
11 2.15. Oscillator
12 3. Specifications
12 3.1. Outline Dimensions
13 3.2. Pin Connections and Short Descriptions
15 3.3. Pin Descriptions
15 3.3.1. Power Supply Pins
15 3.3.2. Analog Audio Pins
15 3.3.3. Oscillator and Clock Pins
16 3.3.4. Other Pins
16 3.3.5. Pin Configuration
17 3.4. Pin Circuits
18 3.5. Control Registers
20 3.6. Electrical Characteristics
20 3.6.1. Absolute Maximum Ratings
21 3.6.2. Recommended Operating Conditions
23 3.6.3. Characteristics
28 4. Applications
28 4.1. Line Output Details
28 4.2. Recommended Low-Pass Filters for Analog Outputs
29 4.3. Recommendations for Filters and Deemphasis
29 4.4. Recommendations for MegaBass Filter without Deemphasis
30 4.5. Power-up/down Sequence
30 4.5.1. Power-up Sequence
30 4.5.2. Power-down Sequence
31 4.6. Typical Applications
34 5. Data Sheet History
PRELIMINARY DATA SHEET DAC 3555A
Micronas 3
Stereo Audio DAC
1. Introduction
The DAC 3555A is a single-chip, high-precision, ste-
reo digital-to-analog converter designed for audio
applications. The employed conversion technique is
based on oversampling with noise-shaping. With Mic-
ronas’ unique multibit sigma-delta technique, less sen-
sitivity to clock jitter, high linearity, and a superior S/N
ratio have been achieved. The DAC 3555A is con-
trolled via I2C bus.
Digital audio input data is received by a versatile I2S
interface. The analog back-end consists of internal
analog filters and op amps for cost-effective additional
external sound processing. The DAC 3555A provides
line-out, headphone/speaker amplifiers, and volume
control. Moreover, mixing additional analog audio
sources to the D/A-converted signal is supported.
The DAC 3555A is designed for all kinds of applica-
tions in the audio and multimedia field, such as:
MPEG players, CD players, DVD players, CD-ROM
players, mobile phones, etc.
The DAC 3555A ideally complements the MP3 audio
decoders MAS 3507D, MAS 35x9F, and PUC 303xA.
No crystal or external clock required for standard
applications with sample rates from 32 to 48 kHz
and 96 kHz.
It is required for automatic sample rate detection below
32 kHz, MPEG mode (refer to Section 2.10.1.), and
use of clock output CLKOUT.
1.1. Main Features
– no master main input clock required
– no external crystal required
– integrated stereo headphone amplifier and mono
speaker amplifier
–SNR of 103dB(A)
–I
2C bus, I2S bus
– internal clock oscillator
– sample rates from 8 kHz to 96 kHz
– analog deemphasis for 44.1 kHz
– analog volume and balance: +18…−75 dB and mute
– THD better than 0.01%
– two additional analog stereo inputs (AUX) with
source selection and mixing
– supply range: 2.7 V…5.5 V
– zero-power mode
– additional line-out
– on-chip op amps for cost-effective external analog
sound processing
– pin-compatible to DAC 3550A
– PMQFP44 or PQFN40 package
1.2. Differences between DAC 3555A and
DAC 3550A
– new zero-power mode
– operation in I2C mode only. Stand-alone operation
is not supported.
– new quiet wake-up mode: after power-on, the
DAC 3555A switches into zero-power mode. Wak-
ing-up is done via I2C command. This feature
avoids audible “plops”.
– sample rates up to 96 kHz
– not register-compatible to DAC 3550A
Fig. 1–1: Block diagram of the DAC 3555A
WSI
CLI
DRI
OUTL
Inter-
DAC
Input
Select
polation
Filter
Volume
and
Headphone
Amplifier
I2S
Analog Inputs
and
Mixing
SDA
SCL I2C
Line Out
OUTR
DAC 3555A PRELIMINARY DATA SHEET
4Micronas
Fig. 1–2: Typical application: Secure Music Player
PC
Display,
Keyboard
PUC 303xA
SD-Card, MMC
MP3, DAC 3555A
Compact Flash
Microdrive
IDE R/W
USB clock input1)
I2S
I2C
UART
SDMI compliant
Line Out
Line inLine in
WMA,
AAC
1) only necessary for
automatic sample rate detection
PRELIMINARY DATA SHEET DAC 3555A
Micronas 5
Fig. 1–3: Block diagram of the DAC 3555A
3rd-order Noise Shaper
I
2
S
Input Select
Interpolation Filter
Variable S & H
Osc.
Postfilter Op Amps
Analog Volume
Headphone Amplifier
Digital Supply
Analog
Control
I
2
C
Analog Low-pass Filter
Sample Rate
PLL
&
Multibit DAC
Deemphasis Op Amps
Vdd
Vss
AVDD0
AVDD1
AVSS0
AVSS1
VREF
AGNDC
SDA
SCL
PORQ
DEECTRL
MCS1
MCS2
AUX1R
AUX2R
DEEMR
FOPR
FOUTR
FINR
OUTROUTL
FINL
FOUTL
DEEML
AUX2L
AUX1L
XTO
XTI
CLKOUT
CLI DAI WSI
TESTEN
Switch Matrix
FOPL
Line-Out
9
10
3
2
44
1
16
15
27
26
19
21
20
32
30
35
42
41
43
18
17
57
39
37
38
34
31
29
12
13
14
23 24 25
Detection
Supply
DAC 3555A PRELIMINARY DATA SHEET
6Micronas
2. Functional Description
2.1. I2S Interface
The I2S interface is the digital audio interface between
the DAC 3555A and external digital audio sources
such as CD/DAT players, MPEG decoders etc. It cov-
ers most of the I2S-compatible formats.
All modes have two common features:
1. The MSB is left justified to an I2S frame identifica-
tion (WSI) transition.
2. Data is valid on the rising edge of the bit clock CLI.
16-bit mode
In this case, the bit clock is 32 ×fsaudio. Maximum
word length is 16 bit.
32-bit mode
In this case, the bit clock is 64 ×fsaudio. Maximum
word length is 32 bit.
Automatic Detection
No I2C control is required to switch between 16- and
32-bit mode. It is recommended to switch the
DAC 3555A into mute position during changing
between 16- and 32-bit mode.
For high-quality audio, it is recommended to use the
32-bit mode of the I2S interface to make use of the full
dynamic range (if more than 16 bits are available).
Left-Right Selection
Standard I2S format defines an audio frame always
starting with left channel and low-state of WSI. How-
ever, I2C control allows changing the polarity of WSI.
Delay Bit
Standard I2S format requires a delay of one clock
cycle between transitions of WSI and data MSB. In
order to fit other formats, however, this characteristic
can be switched off and on by I2C control.
Note: Volume mute should be applied before changing
I2S mode in order to avoid audible clicks.
Fig. 2–1: I2S 16-bit mode (LR_SEL = 0)
Fig. 2–2: I2S 32-bit mode (LR_SEL = 0)
CLI
DAI
Vh
Vl
WSI left 16-bit audio sample right 16-bit audio sample
15141312111098 76543210
13 12 11 10 9876543210
15 14
Vh
Vl
Vh
Vl
programmable delay bit
CLI
DAI
Vh
Vl
WSI left 32-bit audio sample right 32-bit audio sample
29 28 27 26 25 24 76543210
31 30
Vh
Vl
Vh
Vl
programmable delay bit
29 28 27 26 25 24 76543210
31 30
PRELIMINARY DATA SHEET DAC 3555A
Micronas 7
2.2. Interpolation Filter
The interpolation filter increases the sampling rate by a
factor of 8. The characteristic for fsaudio = 48 kHz is
shown in Fig. 2–1.
Fig. 2–1: 1→8 Interpolation filter; frequency range:
0...22 kHz
2.3. Variable Sample and Hold
The advantage of this system is that even at low sam-
ple frequencies the out-of-band noise is not scaled
down to audible frequencies.
2.4. 3rd-order Noise Shaper and Multibit DAC
The 3rd-order noise shaper converts the oversampled
audio signal into a 5-bit noise-shaping signal at a high
sampling rate. This technique results in extremely low
quantization noise in the audio band.
2.5. Analog Low-pass
The analog low-pass is a first order filter with a cut-off
frequency of approximately 1.4 MHz which removes
the high-frequency components of the noise-shaping
signal.
2.6. Input Select and Mixing Matrix
This block is used to switch between or mix the auxil-
iary inputs and the signals coming from the DAC. A
switch matrix allows to select between mono and ste-
reo mode as shown in Fig. 2–1.
Fig. 2–1: Switch matrix
Mono mode is realized by adding left and right chan-
nel.
2.7. Postfilter Op Amps, Deemphasis Op Amps,
and Line-Out
This block contains the active components for the ana-
log postfilters and the deemphasis network. The
op amps and all I/O-pins for this block are shown in
Fig. 2–2.
05000 10000 15000 20000
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
dB
f/Hz
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DAC 3555A PRELIMINARY DATA SHEET
8Micronas
Fig. 2–2: Postfilter op amps, deemphasis op amps, and line-out
2.8. Analog Volume
The analog volume control covers a range from
+18 dB to −75 dB. The lowest step is the mute posi-
tion.
Step size is split into a 3-dB and a 1.5-dB range:
−75 dB...−54 dB: 3 dB step size
−54 dB...+18 dB: 1.5 dB step size
2.9. Headphone Amplifier
The headphone amplifier output is provided at the
OUTL and OUTR pins connected either to stereo
headphones or a mono loudspeaker. The stereo head-
phones require external 10...47-Ω serial resistors in
both channels. If a loudspeaker is connected to these
outputs, the power amplifier for the right channel must
be switched to inverse polarity. In order to optimize the
available power, the source of the two output amplifi-
ers should be identical, i.e. a monaural signal.
Please note, that if a speaker is connected, it should
strictly be connected as shown in Fig. 2–2. Never use
a separate connector for the speaker, because electro-
static discharge could damage the output transistors.
FOPL
AVOL_R
FINL
FOPR
AVOL_L
IRPA
-
--
-
AGNDC
VREF Speaker
Headphones
OUTL
OUTR
150
µ
F
1.5 kΩ
10 Ω…47 Ω
150
µ
F
FOUTL
FOUTR
from switch matrix
3.3 µF/100 nF
+
+
+
AVSS
AVDD
>16 Ω@5 VAVDD
to mC (HP-switch)
1.5 kΩ
10 Ω…47 Ω
optional line-out
DEEML
For external components,
DEEMR
16…32 Ω
FINR
see section “Applications”
For external components,
see section “Applications”
>10 Ω@3 VAVDD
Table 2–1: Volume Control
Volume/dB AVOL
18.0 111000
16.5 110111
15.0 110110
13.5 110101
−−
0.0 101100 (default)
−1.5 101011
−−
−54.0 001000
−57.0 000111
−−
−75 000001
Mute 000000
PRELIMINARY DATA SHEET DAC 3555A
Micronas 9
2.10. Clock System
The advantage of the DAC 3555A clock system is that
no external master clock is needed. Most DACs need
256 ×fsaudio, 384 ×fsaudio, or at least an asynchro-
nous clock.
All internal clocks are generated by a PLL circuit,
which locks to the I2S bit clock (CLI). If no I2Sclock is
present, the PLL runs free, and it is guaranteed that
there is always a clock to keep the IC controllable by
I2C.
The device can be set to two different modes:
–Standard mode
–MPEG mode
In the standard mode, I2C subaddressing is possible
(ADR0, ADR1, ADR2).
MPEG mode always uses ADR3.
To select the modes, the MCS1/MCS2 pins must be
set according to Table 2–2.
2.10.1. Standard Mode
In standard mode, sample rates from 48 kHz to 32 kHz
are handled without I2C control automatically. The set-
ting for this range is the default setting. Other sample
rates require an I2C control to set the PLL divider. This
ensures that even at low sample rates, the
DAC 3555A runs at a high clock rate. This avoids audi-
ble effects due to the noise-shaping technique of the
DAC 3555A. Sample rate range is continuous from 8
to 48 kHz. The I2C setting of non-standard sample
rates must follow Table 2–2.
An additional mode allows automatic sample rate
detection. In this case, the clock oscillator is required
and must run at frequencies between 13.3 MHz to
17 MHz. This mode, however, does not support contin-
uous sample rates. Only the following sample rates
are allowed:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, and 48 kHz
The sample rate detection allows a tolerance of
±200 ppm at WSI.
2.10.2. MPEG Mode
This mode should be used in conjunction with
PUC 30x3A in MPEG player applications. All MPEG
sample rates from 8 to 48 kHz can be detected if the
PUC 30x3A sends a clock signal between 13.3 MHz
and 17 MHz to the DAC 3555A. The internal process-
ing and the DAC itself are automatically adjusted to
keep constant performance throughout the entire
range. I2C control for sample rate adjustment is not
needed in this case.
The MPEG sample rates:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, 48 kHz
As in standard mode, the sample rate detection allows
a tolerance of ±200 ppm at WSI.
Subaddressing is not possible in MPEG mode; this
means, in multi-DAC systems, only one DAC 3555A
can run in MPEG mode.
Table 2–2: Operation Modes
MCS1 MCS2 Mode Sub-
address Default
Sample
Rate
00Stan-
dard ADR0 32–48 kHz
01Stan-
dard ADR1 32–48 kHz
10Stan-
dard ADR2 32–48 kHz
1 1 MPEG ADR3 Automatic
DAC 3555A PRELIMINARY DATA SHEET
10 Micronas
2.11. I2C Bus Interface
The DAC 3555A is equipped with an I2C bus slave
interface. The I2C bus interface uses one level of sub-
addressing: The I2C bus address is used to address
the IC. The subaddress allows chip select in multi DAC
applications and selects one of the three internal regis-
ters. The registers are write-only. The I2Cbus chip
address is given below.
Device Address = 4Dhex.
The registers of the DAC 3555A have 8- or 16-bit data
size; 16-bit registers are accessed by writing two 8-bit
data words.
2.12. Registers
In Section 3.5. “Control Registers” on page 18, a defi-
nition of the DAC 3555A control registers is shown. A
hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of reg-
isters with the default values given in the table.
All registers are write-only.
The register address is coded by 3 bits (RA1, RA0)
according to Table 2–3.
2.13. Chip Select
Chip select allows to connect up to four DAC 3555A to
an I2C control bus. The chip subaddresses are defined
by the MCS1/MCS2 (Mode and Chip Select) pins.
Only in standard mode, chip select is possible. MPEG
mode always uses chip subaddress 3.
Register address and chip select are mapped into the
subaddress field in Table 2–4.
Fig. 2–1: I2C bus protocols for write operations
Table 2–3: I2C Register Address
RA1 RA0 Mnemonics
01SR_REG
10AVOL
11GCFG
Table 2–4: I2C Subaddress
7 6 5 4 3 2 1 0
MCS2 MCS1 RA1 RA0
8-bit I2C write access
SDA
SCL
1
0
SP
Start
Stop
W
R
Ack
Nak
S
P
=
1
0
=
=
=
=
=
0
1
1 byte dataS4D
hex Ack sub_adr Ack Ack P
Ack sub_adr Ack 1 byte data Ack 1 byte data Ack P 16-bit I2Cwrite acces
s
S 4Dhex
w
w
PRELIMINARY DATA SHEET DAC 3555A
Micronas 11
2.14. Power Modes
The DAC 3555A supports four different power modes,
which can be selected by I2C.
1. Zero Power
This is the default mode after power up. In this mode
digital and analog blocks are inactive.
Please note that minimum power consumption is only
achieved if all digital input pins connected to peripheral
circuits are low or tristate.
2. Analog Stand-by
This mode activates the internal analog reference sys-
tem and allows a fast and quiet transition to the active
modes below.
3. Aux to Line
This active mode is used, if no digital audio signals are
present. Only the analog back-end is active.
4. Full Power
All blocks are active in this mode.
Start-up sequence: The recommended sequence for
stepping through the power modes is shown in Section
4.5. “Power-up/down Sequence” on page 30.
2.15. Oscillator
The I2C-controlled oscillator (see Section 3.5. “Control
Registers” on page 18) switches on in the following
modes, only:
1. DAC ON - Standard Mode - automatic sample rate
detection
2. DAC ON - MPEG Mode
In all other modes the oscillator is not required inter-
nally and therefore switched off.
For test purpose it is possible to switch on the oscilla-
tor in all modes (control register AVOL, bit 15). It is not
recommended to use this option in normal applica-
tions.
DAC 3555A PRELIMINARY DATA SHEET
12 Micronas
3. Specifications
3.1. Outline Dimensions
Fig. 3–1:
44-Pin Plastic Metric Quad Flat Package
(PMQFP44)
Weight approximately 0.4 g
Dimensions in mm
Fig. 3–2:
40-Pin Plastic Quad Flat No leads package
(PQFN40)
Weight approximately 0.096 g
Dimensions in mm
SPGS706000-5(P44)/1E
34
44 1
11
12
22
2333
0.1
0.8
0.8
13.2 0.2±
13.2 0.2±
0.17 0.06±
2.15 0.2±
2.0 0.1±
0.34 0.05±
10 0.1±
10 0.1±
10 x 0.8 = 8 0.1±
10 x 0.8 = 8 0.1±
SPGS709000-1(P40)/2E
exposed
die pad
PRELIMINARY DATA SHEET DAC 3555A
Micronas 13
3.2. Pin Connections and Short Descriptions
NC = not connected, leave vacant
LV = if not used, leave vacant
VSS = if not used, connect to VSS
X = obligatory; connect as described in application diagram
VDD = connect to VDD
Pin No. Pin Name Type Connection Short Description
PMQFP
44-pin PQFN
40-pin (If not used)
1 31 AGNDC IN/OUT X Analog reference Voltage
2 32 AVSS1 IN X VSS 1 for audio back-end
3 33 AVSS0 IN X VSS 0 for audio output amplifiers
4 16 NC LV Not connected
5 34 OUTL OUT LV Audio Output: Headphone left or
Speaker +
6 26 NC LV Not connected
7 37 OUTR OUT LV Audio Output: Headphone right or
Speaker −
8 35 NC LV Not connected
9 38 AVDD0 IN X VDD 0 for audio output amplifiers
10 40 AVDD1 IN X VDD 1 for audio back-end
11 36 NC LV Not connected
12 1 XTI IN X Quartz oscillator pin 1
13 2 XTO IN/OUT X Quartz oscillator pin 2
14 3 CLKOUT OUT LV Clock Output
15 4 SCL IN LV I2C clock
16 5 SDA IN/OUT LV I2C data
17 6 VSS IN X Digital VSS
18 7 VDD IN X Digital VDD
19 8 MCS1 IN X I2C Chip Select 1
20 9 MCS2 IN X I2C Chip Select 2
21 10 DEECTRL IN VSS Deemphasis on/off Control
22 39 NC IN LV Not connected
23 11 CLI VSS I2S Bit Clock
24 12 DAI IN VSS I2S Data
25 13 WSI IN VSS I2S Frame Identification
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14 Micronas
26 14 PORQ IN VDD Power-On Reset, active-low
27 15 TESTEN IN X Test Enable
28 16 NC LV Not connected
29 17 AUX2L IN LV AUX2 left input for external analog
signals (e.g. tape)
30 18 AUX2R IN LV AUX2 right input for external analog
signals (e.g. tape)
31 19 AUX1L IN LV AUX1 left input for external analog
signals (e.g. FM)
32 20 AUX1R IN LV AUX1 right input for external analog
signals (e.g. FM)
33 –NC LV Not connected
34 21 DEEML OUT LV Deemphasis Network Left
35 22 DEEMR OUT LV Deemphasis Network Right
36 –NC LV Not connected
37 23 FOUTL OUT X Output to left external filter
38 24 FOPL IN/OUT X Filter op amp inverting input, left
39 25 FINL IN/OUT X Input for FOUTL or
filter op amp output (line out)
40 –NC LV Not connected
41 27 FOUTR OUT X Output to right external filter
42 28 FOPR IN/OUT X Right Filter op amp inverting input
43 29 FINR IN/OUT X Input for FOUTR or
filter op amp output (line out)
44 30 VREF IN X Analog reference Ground
Pin No. Pin Name Type Connection Short Description
PMQFP
44-pin PQFN
40-pin (If not used)
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Micronas 15
3.3. Pin Descriptions
3.3.1. Power Supply Pins
The DAC 3555A combines various analog and digital
functions which may be used in different modes. For
optimized performance, major parts have their own
power supply pins. All VSS power supply pins must be
connected.
VDD
VSS
The VDD and VSS power supply pair are connected
internally with all digital parts of the DAC 3555A.
AVDD0
AVSS0
AVDD0 and AVSS0 are separate power supply pins
that are exclusively used for the on-chip headphone/
loudspeaker amplifiers.
AVDD1
AVSS1
The AVDD1 and AVSS1 pins supply the analog audio
processing parts, except for the headphone/loud-
speaker amplifiers.
3.3.2. Analog Audio Pins
AGNDC
Reference for analog audio signals. This pin is used as
reference for the internal op amps. This pin must be
blocked against VREF with a 3.3 µF capacitor.
Note: The pin has a typical DC-level of 1.5/2.25 V. It
can be used as reference input for external op amps
when no current load is applied.
VREF
Reference ground for the internal band-gap and bias-
ing circuits. This pin should be connected to a clean
ground potential. Any external distortions on this pin
will affect the analog performance of the DAC 3555A.
AUX1L
AUX1R
AUX2L
AUX2R
The AUX pins provide two analog stereo inputs. Auxil-
iary input signals, e.g. the output of a conventional
receiver circuit or the output of a tape recorder can be
connected with these inputs. The input signals have to
be connected by capacitive coupling.
FOUTL
FOPL
FINL
FOUTR
FOPR
FINR
Filter op amps are provided in the analog baseband
signal paths. These inverting op amps are freely
accessible for external use by these pins.
The FOUTL/R pins are connected with the buffered
output of the internal switch matrix. The FOPL/R-pins
are directly connected with the inverting inputs of the
filter op amps. The FINL/R pins are connected with the
outputs of the op amps. The driving capability of the
FOUTL/R pins is not sufficient for standard line output
signals. Only the FINL/R pins are suitable for line out-
put.
OUTL
OUTR
The OUTL/R pins are connected to the internal output
amplifiers. They can be used for either stereo head-
phones or a mono loudspeaker. The signal of the right
channel amplifier can be inverted for mono loud-
speaker operation.
Caution: A short circuit at these pins for more than a
momentary period may result in destruction of the
internal circuits.
3.3.3. Oscillator and Clock Pins
XTI
XTO
The XTI pin is connected to the input of the internal
crystal oscillator, the XTO pin to its output. Both pins
should be directly connected to the crystal and two
ground-connected capacitors (see application dia-
gram).
CLKOUT
The CLKOUT pin provides a buffered output of the
crystal oscillator.
Caution: Power dissipation limit may be exceeded in
case of short to VSS or VDD.
CLI
DAI
WSI
These three pins are inputs for the digital audio data
DAI, frame indication signal WSI, and bit clock CLI.
The digital audio data is transmitted in an I2S-compati-
ble format. Audio word lengths of 16 and 32 bits are
supported, as well as SONY and Philips I2Sprotocol.
SCL
SDA
SCL (serial clock) and SDA (serial data) provide the
connection to the serial control interface (I2C).
DAC 3555A PRELIMINARY DATA SHEET
16 Micronas
3.3.4. Other Pins
TESTEN
Test enable. This pin is for test purposes only and
must always be connected to VSS.
PORQ
This pin may be used to reset the chip. If not used, this
pin must be connected to VDD.
DEEML
DEEMR
These pins connect an external analog deemphasis
network to the signal path in the analog back-end. This
connection can be switched on and off by an internal
switch which is controlled either by I2C or the
DEECTRL-pin.
DEECTRL
Deemphasis can be switched on and off with this pin.
MCS1
MCS2
Mode select pins to select MPEG, Standard Mode,
and I2C subaddress.
3.3.5. Pin Configuration
Fig. 3–1: PMQFP44 package
Fig. 3–2: PQFN40 package
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1234567891011
33 32 31 30 29 28 27 26 25 24 23
DEEML
DEEMR
NC
FOUTL
FOPL
FINL
NC
FOUTR
FOPR
FINR
VREF
NC
DEECTRL
MCS2
MCS1
VDD
VSS
SDA
SCL
CLKOUT
XTO
XTI
AUX1R
AUX1L
AUX2R
AUX2L
NC
NC
TESTEN
PORQ
WSI
DAI
CLI
AVSS1
AVSS0
NC
OUTL
NC
AGNDC
OUTR
NC
AVDD0
AVDD1
NC
DAC 3555A
AGNDC
AVSS1
AVSS0
OUTL
NC
NC
OUTR
AVDD0
NC
AVDD1
AUX1R
AUX1L
AUX2R
AUX2L
NC
TESTEN
PORQ
WSI
DAI
CLI
FINR
FOPR
FOUTR
NC
VREF
FINL
FOPL
FOUTL
DEEMR
DEEML
XTO
CLKOUT
SCL
SDA
XTI
VSS
VDD
MCS1
MCS2
DEECTRL
DAC 3555A
12345678910
30 29 28 27 26 25 24 23 22 21
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
PRELIMINARY DATA SHEET DAC 3555A
Micronas 17
3.4. Pin Circuits
Fig. 3–3: Input/Output Pins SDA, SCL
Fig. 3–4: Input Pins PORQ, DAI
Fig. 3–5: Input Pins WSI, CLI
Fig. 3–6: Output Pin CLKOUT
Fig. 3–7: Pins FINR, FOPR, FINL, FOPL, DEEML,
DEEMR
Fig. 3–8: Output Pins OUTL, OUTR
Fig. 3–9: Output Pins FOUTL, FOUTR
Fig. 3–10: Pins AGNDC, VREF
Fig. 3–11: Input/Output Pins XTI, XTO
Fig. 3–12: Input Pins AUX1R, AUX1L, AUX2R,
AUX2L, AGNDC
Fig. 3–13: Input Pins MCS1, MCS2, DEECTRL
N
VSS
VDD
15 kΩ
P
VDD
N
VSS
AGNDC
FOPn FINn
FOUTn
ext. filter network
DEEM
(DEEMCTRL)
OUTn
AGNDC
AGNDC
FOUTn
125 kΩ
AVSS0/1
AGNDC
VREF
500 kΩ
XTI
XTO
AUXnL
AUXnR
AGNDC
sel/nonsel
sel/nonsel
mono/stereo
mono/stereo
AGNDC
VDD
VSS
DAC 3555A PRELIMINARY DATA SHEET
18 Micronas
3.5. Control Registers
I2C Sub-
address
(hex)
Number
of Bits Mode Function Default
Values
(hex)
Name
SAMPLE RATE CONTROL SR_REG
01 8 w sample rate control
bit[7:5] not used, set to 0
bit[4] L/R-bit
0(WSI = 0 → left channel)1)
1(WSI = 0 → right channel)1)
bit[3] Delay-Bit
0No Delay
1 1 bit Delay
bit[2:0] sample rate control
000 32−48 kHz
001 26−32 kHz
010 20−26 kHz
011 14−20 kHz
100 10−14 kHz
101 8−10 kHz
110 96 kHz2)
111 automatic detection3)
0hex
LR_SEL
SP_SEL
SRC_48
SRC_32
SRC_24
SRC_16
SRC_12
SRC_8
SRC_96
SRC_A
ANALOG VOLUME AVOL
02 16 w audio volume control
bit[15] Oscillator on/off (for test purpose only)
0 Oscillator on if internally required
1 Oscillator always on
bit[14] deemphasis on/off
0 deemphasis off
1 deemphasis on
bit[13:8] analog audio volume level left:
000000 mute
000001 −75 dB
101100 +0 dB (default)
111000 +18 dB
bit[7:6] not used, set to 0
bit[5:0] analog audio volume level right
000000 mute
000001 −75 dB
101100 +0 dB (default)
111000 +18 dB
0hex
OSC
DEEM
AVOL_L
AVOL_R
1) see Fig. 2–1 and Fig. 2–2 on page 6
2) 96 kHz allowed for VDD=5 V only
3) 96 kHz is not supported by automatic detection
PRELIMINARY DATA SHEET DAC 3555A
Micronas 19
Global Configuration GCFG
03 8 w global configuration
bit[7] select 3 V − 5 V mode
03V
15V
bit[6:4] DAC and Power-Mode
bit[6] bit[5] bit[4]
0 0 0 DAC off - Zero Power
0 1 0 DAC off - Analog Standby
1 0 0 DAC off - Aux to Line
1 1 0 DAC off - Full Power
0x
1) 1 DAC on - Aux to Line
1x
1) 1 DAC on - Full Power
bit[3] AUX2 select
0AUX2 off
1AUX2 on
bit[2] AUX1 select
0AUX1 off
1AUX1 on
bit[1] aux-mono/stereo
0stereo
1mono
bit[0] invert right power amplifier
0 not inverted
1inverted
0hex
SEL_53V
PWMD
INSEL_AUX2
INSEL_AUX1
AUX_MS
IRPA
1) don’t care
I2C Sub-
address
(hex)
Number
of Bits Mode Function Default
Values
(hex)
Name
DAC 3555A PRELIMINARY DATA SHEET
20 Micronas
3.6. Electrical Characteristics
3.6.1. Absolute Maximum Ratings
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
Symbol Parameter Pin Name Min. Max. Unit
TAAmbient Temperature Range −40 85 °C
TSStorage Temperature −40 125 °C
Pmax Power Dissipation 500 mW
VSUPA Analog Supply Voltage1) AVDD0/1 −0.3 6 V
VSUPD Digital Supply Voltage VDD −0.3 6 V
VIdig1 Input Voltage, digital inputs MCS1,
MCS2,
DEECTRL
−0.3 VSUPD + 0.3 V
VIdig2 Input Voltage, digital inputs WSI,
CLI,
DAI,
PORQ,
SCL,
SCI
−0.3 6 V
IIdig Input Current, all digital inputs −5+5 mA
VIana Input Voltage, all analog inputs −0.3 VSUPA + 0.3 V
IIana Input Current, all analog inputs −5+5 mA
IOaudio Output Current, audio output2) OUTL/R −0.2 0.2 A
IOdig Output Current, all digital outputs3) −10 10 mA
1) Both pins have to be connected together!
2) These pins are NOT short-circuit proof!
3) Total chip power dissipation must not exceed absolute maximum rating
PRELIMINARY DATA SHEET DAC 3555A
Micronas 21
3.6.2. Recommended Operating Conditions
Symbol Parameter Pin Name Min. Typ. Max. Unit
Temperature Ranges and Supply Voltages
TAAmbient Temperature Range1) 070°C
TAE Extended Ambient Temperature
Range1) −40 85 °C
VSUPA1 Analog Audio Supply Voltage AVDD0/1 3.02) 3.3 5.5 V
VSUPD Digital Supply Voltage VDD 2.7 3.3 5.5 V
VSUPD96 Digital Supply Voltage
(if sample rate is 96 kHz)
VDD 4.75 5.0 5.5 V
Relative Supply Voltages
VSUPA Analog Audio Supply Voltage in
relation to the Digital Supply Volt-
age
AVDD0/1 VSUPD
−0.25 V
5.5 V
Analog Reference
CAGNDC1 Analog Reference Capacitor AGNDC 1.0 3.3 µF
CAGNDC2 Analog Reference Capacitor AGNDC 10 nF
Analog Audio Inputs
VAI Analog Input Voltage AC,
SEL_53V = 0
AUXnL/R3) 0.35 0.7 Vrms
VAI Analog Input Voltage AC,
SEL_53V = 1
AUXnL/R3) 0.525 1.05 Vrms
Analog Filter Input and Output
ZAFLO Analog Filter Load Output4) FOUTL/R 7.5
6
kΩ
pF
ZAFLI Analog Filter Load Input4) FINL/R 5.0 7.5 kΩ
pF
1) The functionality of the IC in the extended temperature range has been verified by electrical characterization
based on sample tests. All data sheet parameters are valid for normal operating temperature range, only.
2) typically operable down to 2.7 V, without loss of performance
3) n = 1 or 2
4) Please refer to Section 4.2. “Recommended Low-Pass Filters for Analog Outputs” on page 28.
DAC 3555A PRELIMINARY DATA SHEET
22 Micronas
Analog Audio Output
ZLO Audio Line Output1)
(680 Ω Series Resistor required)
FINL/R 10
1.0
kΩ
nF
ZAOL_HP Analog Output Load HP
(47 Ω Series Resistor required)
OUTL/R 32
400 Ω
pF
ZAOL_SP Analog Output Load SP (bridged) OUTL/R 32
50 Ω
pF
Analog Output Load SP (Stereo) 16
100 Ω
pF
I2C Input
fI2C I2C Clock Frequency SCL 400 kHz
Digital Inputs
VIH Input High Voltage CLI,
WSI,
DAI,
PORQ,
SCL,
SDA
0.5×
VDD
V
VIL Input Low Voltage 0.2×
VDD
V
External Clock Input
VIHx2) Ext. Clock High Voltage XTI 0.25×
VDDmax
V
VIL Input Low Ext. Clock XTI 0.75×
VDDmin
V
I2SDut1_96 Duty Cycle of I2S input clock
(sample rate=96 kHz) CLI 45 55 %
I2SDut1_48 Duty Cycle of I2S input clock
(sample rate <=48 kHz) CLI 40 60 %
Crystal Characteristics
FPLoad Resonance Frequency
at Cl = 20 pF
13.3 14.725 17 MHz
REQ Equivalent Series Resistance 12 30 Ω
C0Shunt (parallel) Capacitance 3 5 pF
Load at CLKOUT Output
Cload Capacitance CLKOUT 0 50 pF
1) Please refer to Section 4.1. “Line Output Details” on page 28.
2) extended clock should be AC-coupled via 10 nF
Symbol Parameter Pin Name Min. Typ. Max. Unit
PRELIMINARY DATA SHEET DAC 3555A
Micronas 23
3.6.3. Characteristics
At TA= 0 to 70 °C, VSUPD = 2.7 to 5.5 V, VSUPA = 3.0 to 5.5 V; typical values at TJ=27°C, VSUPD =V
SUPA =3.3V,
positive current flows into the IC
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Digital Supply
IVDD Current Consumption VDD 3.7
5.0 mA
µADAC ON1)
DAC OFF2)
VSUPD = 3.3 V
(see I2C register
GCFG)
7.0
5.0 mA
µADAC ON1)
DAC OFF2)
VSUPD = 5 V
Digital Input Pin – Leakage
IIInput Leakage Current DAI,
TESTEN,
PORQ,
DEECTRL,
MCS1/2
±1µAV
GND ≤ VI ≤ VSUP
Digital Output Pin – Clock Out
VOH Output High Voltage CLKOUT VSUPD
−0.3 V no load at output
VOL Output Low Voltage 0.3 V
I2C Bus
Ron Output Impedance SCL, SDA 60 ΩIload =5mA,
VSUPD =2.7V
Analog Supply
IAVDD Current Consumption
Analog Audio AVDD0/1 1.0
630
3.6
8.2
µA
µA
mA
mA
Zero Power
Analog Standby
Aux to Line
Full Power
SEL_53 = 0
AVDD = 3.3 V3)
1.0
750
6.0
12.9
µA
µA
mA
mA
Zero Power
Analog Standby
Aux to Line
Full Power
SEL_53 = 1
AVDD = 5 V3)
(see I2C register
GCFG)
1) I2S active, 32-bit mode, fs = 48 kHz
2) No I2C traffic
3) DAC on, I2S active, 32-bit mode, fs = 48 kHz, 1 kHz @ 0 dBFS volume = 0 dB
DAC 3555A PRELIMINARY DATA SHEET
24 Micronas
PSRRAA Power Supply Rejection
Ratio for Analog Audio
Output
AVDD0/1,
OUTL/R 50 dB 1 kHz sine at
100 mVrms
20 dB ≤100 kHz sine at
100 mVrms
PSRRLO Power Supply Rejection
Ratio for Line Output AVDD0/1,
FINL/R 50 dB 1 kHz sine at
100 mVrms
40 dB ≤100 kHz sine at
100 mVrms
Reference Frequency Generation
VDCXTI DC Voltage at Oscillator
Pins XTI/O 0.5×
VSUPA
V
CLI Input Capacitance at
Oscillator Pin XTI/O 3 pF
Vxtalout Voltage Swing at Oscillator
Pins, pp XTI/O 60 100 %
VSUPA
Oscillator Start-Up Time 50 ms AVDD/VDD ≥ 2.5 V
Analog Audio
VAO Analog Output Voltage AC OUTL/R,
FOUTL/R,
FINL/R
0.65 0.7 0.75 Vrms SEL_53V = 0,
RL > 5 kΩ,
Analog Gain = 0 dB
Input = 0 dBFS digital
1.0 1.05 1.1 Vrms SEL_53V = 1
GAUX Gain from Auxiliary Inputs to
Line Outputs AUXnL/R,
FINL/R −0.5 0 0.5 dB f = 1 kHz, sine wave,
RL>5kΩ
0.5 Vrms to AUXnL/R
PHP Output Power (Headphone) OUTL/R 5 mW SEL_53V = 0,
RL = 32 Ω,
Analog Gain = +3 dB,
distortion < 1%,
external 47 Ω series
resistor required
12 mW SEL_53V = 1
PSP Output Power (Speaker) OUTL/R 120 mW RL = 32 Ω (bridged),
Analog Gain = +3 dB,
distortion < 10%,
SEL_53V = 0, IRPA = 1
280 mW SEL_53V = 1
GAO Analog Output Gain
Setting Range OUTL/R −75 18 dB
dGAO1 Analog Output Gain
Step Size OUTL/R 3.0 dB Analog Gain:
−75 dB...−54 dB
dGAO2 Analog Output Gain
Step Size OUTL/R 1.5 dB Analog Gain:
−54 dB...+18 dB
EGA1 Analog Output Gain Error OUTL/R −22dB−46.5 dB≥Analog Gain
≥−54 dB
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET DAC 3555A
Micronas 25
EGA2 Analog Output Gain Error OUTL/R −11dB−40.5 dB≥Analog Gain
≥−45 dB
EGA3 Analog Output Gain Error OUTL/R −0.5 0.5 dB +18 dB≥Analog Gain
≥−39 dB
EdGA Analog Output Gain
Step Size Error OUTL/R −0.5 0.5 dB +18 dB≥Analog Gain
≥−48 dB
SNRAUX Signal-to-Noise Ratio from
Analog Input to Line Output AUXn,
FINL/R 98 dB SEL_53V = 0:
input −40 dB below
0.7 Vrms
Analog Gain = 0 dB,
BW =20 Hz...20 kHz
unweighted
Signal-to-Noise Ratio from
Analog Input to Headphone
Output
AUXn,
OUTn 93 dB
SNR1Signal-to-Noise Ratio OUTL/R 89 91 dB RL≥32 Ω
(external 47 Ω series
resistor required)
BW =20 Hz...0.5 fs1)
unweighted,
Analog Gain = 0 dB,
Input = −20 dBFS
FINL/R 90 92 dB RL≥5kΩ,
Rdec ≥ 612 Ω
BW etc. as above
16 bit I2S, SEL_53V = 0
94 dB 32 bit I2S, SEL_53V = 0
96 dB 16 bit I2S, SEL_53V = 1
98 dB 32 bit I2S, SEL_53V = 1
103 dB(A) 32 bit I2S, SEL_53V = 1
SNR2Signal-to-Noise Ratio OUTL/R 62 dB RL≥32 Ω (external
47 Ω series resistor
required)
BW = 20 Hz..0.5 fs1)
unweighted
Analog Gain= −40.5dB,
Input = −3dB
FS
LevMute Mute Level OUTL/R −110 dBV BW = 20 Hz...22 kHz
unweighted, no digital
input signal,
Analog Gain = Mute
RD/A D/A Pass Band Ripple OUTL/R,
FOUTL/R −0.1 dB 0...0.446 fs
(no external filters
used)
AD/A D/A Stop Band Attenuation 40 dB 0.55...7.533 fs
(no external filters
used)
BWAUX Bandwidth for
Auxiliary Inputs AUXnL/R,
FINL/R 760 kHz (no external filters
used)
1) BW = 20 Hz...22 kHz if fs = 96 kHz
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
DAC 3555A PRELIMINARY DATA SHEET
26 Micronas
THDALO Total Harmonic Distortion
from Auxiliary Inputs to
Line Outputs
AUXnL/R,
FINL/R 0.01 % BW = 20 Hz...22 kHz,
unweighted,
RL> 5 kΩ
Input 1 kHz at 0.5 Vrms
Rdec ≥ 612 Ω
THDDLO Total Harmonic Distortion
(D/A converter to Line
Output)
FINL/R 0.01 % BW = 20 Hz...0.5 fs1),
unweighted,
RL>5kΩ
Input 1 kHz at −3dB
FS
Rdec ≥ 612 Ω
THDHP Total Harmonic Distortion
(Headphone) OUTL/R 0.05 % BW = 20 Hz...0.5 fs1),
unweighted, RL≥32 Ω
(47 Ω series resistor
required),
Analog Gain = 0 dB,
Input 1 kHz at −3dB
FS
THDSP Total Harmonic Distortion
(Speaker) OUTL/R 0.5 % BW = 20 Hz...0.5 fs1),
unweighted, RL≥32 Ω
(speaker bridged),
Analog Gain = 0 dB,
Input 1 kHz at −3dB
FS
XTALKLO Cross-Talk
Left/Right Channel
(Line Output)
AUXnL/R,
FOUTL/R,
FINL/R
−70 −80 dB f = 1 kHz, sine wave,
RL>7.5kΩ
Analog Gain = 0 dB,
Input = −3dB
FS or
0.5 Vrms to AUXnL/R
XTALKHP Crosstalk
Left/Right Channel
(Headphone)
OUTL/R −70 −80 dB f = 1 kHz, sine wave,
OUTL/R: RL ≥ 32 Ω
(47 Ω series resistor
required)
Analog Gain = 0 dB,
Input = −3dB
FS or
0.5 Vrms to AUXnL/R
XTALK2Crosstalk between
Input Signal Pairs AUXnL/R −70 −80 dB f = 1 kHz, sine wave,
FOUTL/R: RL > 7.5 kΩ
OUTL/R: RL ≥ 32 Ω
(47 Ω series resistor
required)
Analog Gain = 0 dB,
Input = −3dB
FS and
0.5 Vrms to AUXnL/R
VAGNDC Analog Reference Voltage AGNDC 1.5 V SEL_53V = 0
RL >> 10 MΩ,
referred to VREF
2.25 V SEL_53V = 1
RL >> 10 MΩ,
referred to VREF
1) BW = 20 Hz...22 kHz if fs = 96 kHz
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET DAC 3555A
Micronas 27
RIAUX Input Resistance at
Input Pins AUXnL/R 12.1
11.6 15 17.9
19.0 kΩ
kΩTJ = 27 °C
TA = 0 to 70 °C1)
Input selected,
Aux to Line
i = ±10 µA,
referred to VREF
24.2
23.3 30 35.8
37.9 kΩ
kΩTJ = 27 °C
TA = 0 to 70 °C1)
Input not selected
i = ±10 µA,
referred to VREF
ROOUT Output Resistance at
Output Pins OUTL/R 700 ΩTJ = 27 °C
Analog Standby
i = ±200 µA,
referred to VREF
ROFILT Output Resistance of
Filter Pins FINL 15 kΩfull power, Mute
i = ±10 µA,
referred to VREFFINR 11.25 kΩ
VOffI Offset Voltage at Input Pins AUXnL/R −20 20 mV referred to AGNDC
VOffO Offset Voltage at
Output Pins OUTL/R −10 10 mV Mute
referred to AGNDC
VOffFO Offset Voltage at
Filter Output Pins FOUTL/R −20 20 mV analog standby,
referred to AGNDC
VOffFI Offset Voltage at
Filter Input Pins FINL/R −20 20 mV analog standby,
referred to AGNDC
dVDCPD Difference of DC Voltage at
Output Pins OUTL/R −10 10 mV Analog Gain = Mute,
switched from analog
standby to full power
1) BW = 20 Hz...22 kHz if fs = 96 kHz
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
DAC 3555A PRELIMINARY DATA SHEET
28 Micronas
4. Applications
4.1. Line Output Details
Fig. 4–1: Use of FINL/R as Line Outputs
4.2. Recommended Low-Pass Filters for Analog
Outputs1)
Fig. 4–1: 1st-order low-pass filter
Fig. 4–2: 2nd-order low-pass filter
Fig. 4–3: 3rd-order low-pass filter
Table 4–1: Load at FINL/R when used as Line Output
for external amplifier
Filter Order Rdec Rin
1st, 2nd, 3rd 680 Ω> 10 kΩ
Rdec:Resistor used for decoupling Cline from
FINL(R) to achieve stability
Cline: Capacitive load according to e.g. cable,
amplifier
Rin: Input resistance of amplifier
1) without deemphasis circuit
Table 4–2: Attenuation of 1st-order low-pass filter
Frequency Gain
24 kHz −2.2 dB
30 kHz −3.0 dB
FINL(R)
AVSS
Cline
Rdec
Rin
330 pF
15 kΩ15 kΩ
1st-order
-
FINL(R)FOPL(R)
FOUTL(R)
Table 4–3: Attenuation of 2nd-order low-pass filter
Frequency Gain
24 kHz −1.5 dB
30 kHz −3.0 dB
Table 4–4: Attenuation of 3rd-order low-pass filter
Frequency Gain
18 kHz 0.17 dB
24 kHz −0.23 dB
30 kHz −3.00 dB
11 kΩ
220 pF11 kΩ11 kΩ
1.0 nF
-
FINL(R)FOPL(R)
FOUTL(R)
2nd-order
AVSS
-
FINL(R)FOPL(R)
FOUTL(R)
15 kΩ
120 pF
7.5 kΩ7.5 kΩ
1.8 nF1.8 nF
7.5 kΩ
3rd-order
AVSS
PRELIMINARY DATA SHEET DAC 3555A
Micronas 29
4.3. Recommendations for Filters and Deemphasis
Fig. 4–4: General circuit schematic
4.4. Recommendations for MegaBass Filter
without Deemphasis
Fig. 4–1: General circuit schematic
Table 4–5: Resistor and Capacitor values
1st order 2nd order 3rd order
R1 (kΩ)0 7.5
C1 (pF) open 560
R2 (kΩ)18 11 7.5
C2 (pF) open 1000 270
R3 (kΩ)18 11 15
C3 (pF) 180 180 82
R4 (kΩ)0 11 7.5
R5 (kΩ)182222
C4 (nF) 1.8 1.0 1.0
-
FINL(R)FOPL(R)
FOUTL(R)
R3
C3R2 R4
C2C1
R1
AVSS
R5 C4
DEEML(R)
Table 4–6: Resistor and Capacitor values
DC-Gain = 10 dB
fc1 = 100 Hz
fc2 = 330 Hz
R1 (kΩ)13
C1 (nF) 47
R2 (kΩ)0
R3 (kΩ)15
R4 (kΩ)15
R5 (kΩ)13
C2 (nF) 47
-
FINL(R)
FOPL(R)
FOUTL(R)
R4R2 R3
C2C1
R1
AVSS
R5
AVSS
ON OFF
DAC 3555A PRELIMINARY DATA SHEET
30 Micronas
4.5. Power-up/down Sequence
In order to get a click-free power-up/down characteris-
tic, it is recommended to use the following sequences:
4.5.1. Power-up Sequence
1. Start VDD from 0 to +3.3 V and start AVDD0/1 from 0
to +3.3 V/+5 V. See Fig. 4–2.
2. Release PORQ from 0 to VDD. See Fig. 4–2.
3. Follow the logical power-up sequence in Fig. 4–3.
4.5.2. Power-down Sequence
Follow the logical power-down sequence in Fig. 4–3.
Fig. 4–2: Electrical power-up sequence
Fig. 4–3: Logical power-up/down sequence
VDD
AVDD0/1
PORQ
≥90% VDDmax
≥90% VDD
<0.4×VDD
>1 ms
0.6×VDD
Zero Power
Analog Stand-by
DAC off DAC on
Full Power
muted
DAC on
Full Power
unmuted
DAC off
muted
Aux to Line
muted
Aux to Line
unmuted
muted
–switch on VDD and AVDD0/1
–release PORQ
–prepare analog back-end for line
mode or headphone mode.
Note: wait 0.5 s before transition
to active modes
–no wait time required to go back
to zero-power mode
–switch on active modes
Note: Direct transition from
zero-power mode to active
modes causes plops.
–set volume
–start I2S if applicable1)
–mute before leaving this state
1) if the application allows switching on and off the I2S input, it should be done here
Power-up
Sequence
Power-down
Sequence
0.5 s
0 s
0 s
0 s
0 s
0 s
0 s
0 s
0 s
0 s
Wait Period t
Power-on Sequence:
(Power-down Sequence: vice versa)
PRELIMINARY DATA SHEET DAC 3555A
Micronas 31
4.6. Typical Applications
Fig. 4–4: Application circuit schematic 1: Standard application with analog deemphasis. Oscillator not needed.
Package: PMQFP44
n
A
DAC 3555A PRELIMINARY DATA SHEET
32 Micronas
Fig. 4–5: Application circuit schematic 2: MPEG application with analog Megabass and 14.31818 MHz clock input.
Package: PMQFP44
n
A
A
optional
PUC 303xA
extCLK
PRELIMINARY DATA SHEET DAC 3555A
Micronas 33
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
DAC 3555A PRELIMINARY DATA SHEET
34 Micronas
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-575-1PD
5. Data Sheet History
1. Preliminary data sheet: “DAC 3555A Stereo Audio
DAC”, Jan. 8, 2002, 6251-575-1PD. First release of
the preliminary data sheet.
