TOSHIBA SILICON STACKED GATE CMOS 1,048,576 WORD x 16 BIT/2,097,152 WORD x 8 BIT CMOS MASK ROM Description TC5316210BP/BF The TC5316210BP/BF is a 16,777,216 bit read only memory organized as 1,048,576 words by 16 bits when BYTE is logical high, or as 2,097,152 words by 8 bits when BYTE is logical low. The TC5316210BP/BF is suitable for use as program memory, data memory, or as a character generator. A page read mode allows up to 8 words (16 bits) or 16 bytes of data to be quickly read in the same page. CE and (A3...A19) must not change. Page access time is 6Ons. The TC5316210BP/BF is packaged in a standard 600mil 42-pin DIP or 600mil 44-pin SOP. Features * Single 5V power supply Access time (normal mode) : 150ns (max.) (page access mode) : 60ns (max.) * Power dissipation - Operating current : 150mA (max.) - Standby current 1mA (max.) * Fully static operation * Inputs and outputs TTL compatible Three state outputs e Package - TC5316210BP : DIP42-P-600 - 1C5316210BF : SOP44-P-600 Pin Names AO ~ A19 | Address Inputs Do ~ 014 | Data Outputs CE Chip Enable Input dE Output Enable Input D15/A-1 | Data Output/Address Input BYTE | Word, Byte Selection Input Vop Power Supply Voltage (+5V) GND Ground NC No Connection TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. Pin Connection (Top View) Aisi 42[a19 Ai7Q2 410A8 A793 400) A9 ac4 391) A10 asds 38) All Ate 37D A12 a3Q7 36) A13 A2ts 35f)Al4 Ail} 34[JA15 Ao] 10 33) A16 cegis 32 BYTE GND Q 12 311GND OEY 13 30]] D1S/A-1 poG 14 29]} 07 os fis 28[) 014 oi 16 27/} 06 o9 017 269013 020 18 25/105 pi0Q} 19 247]012 o3 J 20 23) 04 pi1Q21 220 Voo 7C53162108P ncgi /% g4 J NC Aig (2 43 JAI A173 42 [148 a7 4 41 flA9 a6 5 40 J) A10 as 6 39 pAi A4(|7 38 PAl2 A3(/8 37 PAt3 A219 36 PAt4 mide asDAR Agog 11 34 CE {| 12 33 DP BYTE GND J] 13 32 [) GND DE {| 14 31 1 O15/A-1 oo 9 15 30 ) 97 ps (j 16 29 DP 014 pi q17 2g [} 06 pg 4) 18 27 013 02419 26 1105 p10 J 20 25 J) O12 03 421 24 1) 04 pit (22 23 1) Yoo TC53 162 10BF D-59TC5316210BP/BF Non-Volatile Memory Block Diagram Voo | GND i oe [ B15 r i 1 BYTE oO TPUT BUFFER BYTE, CE, OF CIRCUIT -o-| OUTPUT 8 5 mo 1 TE o 7 | _ PAGE MODE penuuccssusccsscsseeseeeed 72-----3|A41 pecove ciRCUIT ' | ( | h -1 or A-\ = Tuan SENSE AMP 5 CIRCUIT ao <>| DECODER 32 } ADDRESS >| _ COLUMN GATE BUFFERS | ROW MEMORY CELL 13 | DECODER | 8192 ARRAY > p> | 1,048,576 x 16 BITS Al9 o Operating Mode MODE CE uE BYTE 00 ~ D7 | D8 ~ 014 D15/A-1 | POWER Read (16 Bits) L L H Data Out Read (Lower Bits) | L L L (Lower 2 Bits) High Impedance | L cine Read (Upper Bits) | L L L Wpper 2 Bits) High Impedance | Output Deselect L H * High impedance Standby H . . High Impedance Standby H= Vin, b= Vi. * = Vie OF Vi Maximum Ratings SYMBOL ITEM RATING UNIT Vop Power Supply Voltage -0.5 ~ 7.0 VIN Input Voltage -0.5 ~ Vop Vv Vout | Output Voltage 0~Vop Pp Power Dissipation 1.0/0.6" Ww Tstrag | Storage Temperature -55 ~ 150 C Topr Operating Temperature 0~70 Tso_per | Soldering Temperature Time 260 + 10 C *sec "SOP D-60 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Non-Volatile Memory TC5316210BP/8F Dc Recommended Operating Conditions SYMBOL PARAMETER MIN. TYP. MAX. UNIT Vop Power Supply Voltage 45 5.0 5.5 Vin Input High Voltage 2.2 - Vop + 0.3 Vv Vit Input Low Voltage -0.3 - 0.8 DC Characteristics (Ta = 0 ~ 70C, Vpp = 5V+10%) SYMBOL PARAMETER TEST CONDITION MIN. MAX. UNIT lu Input Leakage Current Vin = 0 ~ Vop - +5.0 yA lLo Output Leakage Current Vout = 0 ~ Vop - +5.0 lou Output High Current Von = 2.4V -1.0 - lou Output Low Current Voy = 0.4V 2.0 - mA post Standby Current * : oe ~O2V - mA lppo1 | DC Current Vin = Vinic - 100 lopoe Operating Current Vin = Vin/Vit, Normal (toycie = 150ns) - 150 mA lpp03 Vin = ViVi, Page (toycte = 60ns) - 150 AC Characteristics ' (Ta = 0 ~ 70C, Vpp = 5V+10%) SYMBOL PARAMETER MIN. MAX. UNIT teyc | Cycle Time 150 ~ tace Address Access Time - 150 tpac Page Access Time - 60 toe Chip Enable Access Time ~ 150 tar | BYTE Access Time - 150 toe Output Enable Access Time - 60 tcee | Output Enable Time from TE 0 - toce | Output Enable Time from OE 0 - ns tare | Output Enable Time from BYTE 0 - tcep _| Output Disable Time from TE - 35 toep | Output Disable Time from OF - 25 tstp | Output Disable Time from BYTE - 35 ton Output Hold Time (Normal) 10 - tpou | Output Hold Time (Page) 5 - AC Test Conditions Input Pulse Levels 2.4V/0.6V Input Pulse Rise and Fall Times 5ns max. Input Timing Measurement Reterence Levels 2.2V/0.8V Output Timing Measurement Reference Levels 2.0V/0.8V Output Load 1 TTL Gate and C, = 100 pF Capacitance* (Ta = 25C, f = 1MHz) SYMBOL PARAMETER TEST CONDITION MIN. MAX. UNIT Cw Input Capacitance Vin = OV - 10 Cour | Output Capacitance Vout = 0V - 12 pF This parameter is periodically sampled and is not 100% tested. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. D-61TC5316210BP/BF Non-Volatile Memory Timing Waveforms Word-Wide (16 Bit) Read Mode A0~Ai9 DO~D15 Note 1: BYTE = Vin Word-Wide (16 Bit) Page Read Mode A3~A19 A0~A2 po~p15 = High-Z High - D-62 TOSHIBA AMERICA ELECTRONIG COMPONENTS, INC.Non-Volatile Memory 7TC5316210BP/BF Byte-Wide (8 Bit) Read Mode A~1~A19 High -Z 00~07 Note 3: BYTE = Vit Byte-Wide (8 Bit) Page Read Mode a7 A3~A19 Valid Xx ACC tpac | z NET 2) oS ton tron Yt: _| Mim Zz ~ ~ (6) (6) toce r+ toro << po~p7 = High-Z - " ? ; F High - ____ Valid DN Valid Valid )_Higt | 4 < - (6) 7? | cee Note 4: BYTE = Vit TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. D-63TC5316210BP/BF Non-Volatile Memory BYTE Transition A0N~A19 High Z tacc ton . > BYTE \ ter - a 7 ~ * 4 ton (6) tote \ High Z D8~D15 ) Dour VALID - _ taro ) Note 5: CE = Vie. OE = Vic Note 6: These parameters are specified as follows: (A) tcee, tore. tare Output Enabie Time (B) tcep: toep. tarp Output Disable Time CE, OF BYTE (A) High Impedance H Dour = ote OUTPUT DATA VALID NKNOWN UNKNOWN 0 15V D-64 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.