DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT597
8-bit shift register with input
flip-flops
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
FEATURES
•8-bit parallel storage register inputs
•Shift register has direct overriding load and clear
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT597 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT597 consist each of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register.
Both the storage register and the shift register have
positive edge-triggered clocks. The shift register also has
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑ (CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CL= 15 pF; VCC =5V
SHCP to Q 17 20 ns
STCP to Q 25 29 ns
PL to Q 21 26 ns
fmax maximum clock frequency SHCP 96 83 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 29 32 pF
December 1990 3
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
8 GND ground (0 V)
9 Q serial data output
10 MR asynchronous reset input (active LOW)
11 SHCP shift clock input (LOW-to-HIGH, edge-triggered)
12 STCP storage clock input (LOW-to-HIGH, edge-triggered)
13 PL parallel load input (active LOW)
14 DSserial data input
15, 1, 2, 3, 4, 5, 6, 7 D0 to D7parallel data inputs
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑= LOW-to-HIGH CP transition
STCP SHCP PL MR FUNCTION
↑X X X data loaded to input latches
↑X L H data loaded from inputs to shift register
no clock edge X L H data transferred from input flip-flops to shift register
X X L L invalid logic, state of shift register indeterminate when signals removed
X X H L shift register cleared
X↑H H shift register clocked Qn=Q
n
−
1
, Q0=D
S
Fig.4 Functional diagram.
December 1990 5
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
Fig.5 Logic diagram.
December 1990 6
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
Fig.6 Timing diagram.
December 1990 7
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
SHCP to Q 55
20
16
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.7
tPHL propagation delay
MR to Q 58
21
17
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.8
tPHL/ tPLH propagation delay
STCP to Q 80
29
23
250
50
43
315
63
54
375
75
64
ns 2.0
4.5
6.0
Fig.7
tPHL/ tPLH propagation delay
PL to Q 69
25
20
215
43
37
270
54
46
325
65
55
ns 2.0
4.5
6.0
Fig.9
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.9
tWSTCP pulse width
HIGH or LOW 80
16
14
11
4
3
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
tWSHCP pulse width
HIGH or LOW 80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
tWMR pulse width
LOW 80
16
14
22
8
6
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.8
tWPL pulse width
LOW 80
16
14
22
8
6
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.9
trem removal time
MR to SHCP
60
12
10
−3
−1
−1
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.10
tsu set-up time
Dnto STCP
60
12
10
8
3
2
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.11
December 1990 8
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
tsu set-up time
DSto SHCP
60
12
10
11
4
3
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.11
tsu set-up time
PL to SHCP
60
12
10
11
4
3
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.12
thhold time
Dnto STCP
5
5
5
−3
−1
−1
5
5
5
5
5
5
ns 2.0
4.5
6.0
Fig.11
thhold time
PL, DS to SHCP
5
5
5
−6
−2
−2
5
5
5
5
5
5
ns 2.0
4.5
6.0
Fig.11
fmax maximum pulse frequency
SHCP
6.0
30
35
29
87
104
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
December 1990 9
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
DS
Dn
PL, MR
STCP, SHCP
0.25
0.30
1.50
1.50
December 1990 10
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
AC WAVEFORMS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
SHCP to Q 23 40 50 60 ns 4.5 Fig.7
tPHL propagation delay
MR to Q 28 49 61 74 ns 4.5 Fig.8
tPHL/ tPLH propagation delay
STCP to Q 33 57 71 86 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
PL to Q 30 52 65 78 ns 4.5 Fig.9
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.9
tWSHCP pulse width
HIGH or LOW 16 7 20 24 ns 4.5 Fig.7
tWSTCP pulse width
HIGH or LOW 16 6 20 24 ns 4.5 Fig.7
tWMR pulse width
LOW 25 14 31 38 ns 4.5 Fig.8
tWPL pulse width
LOW 20 10 25 30 ns 4.5 Fig.9
trem removal time
MR to SHCP
12 −2 15 18 ns 4.5 Fig.10
tsu set-up time
Dnto STCP
12 5 15 18 ns 4.5 Fig.11
tsu set-up time
DSto SHCP
12 2 15 18 ns 4.5 Fig.11
tsu set-up time
PL to SHCP
12 4 15 18 ns 4.5 Fig.12
thhold time
Dnto STCP
5−1 5 5 ns 4.5 Fig.11
thhold time
PL, DS to SHCP
5−2 5 5 ns 4.5 Fig.11
fmax maximum pulse frequency
SHCP
30 75 24 20 MHz 4.5 Fig.7
December 1990 11
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
AC WAVEFORMS
Fig.7 Waveforms showing the SHCP and STCP
inputs to Q output propagation delays, the
SHCP and STCP pulse widths and maximum
clock pulse frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the MR input to Q
output propagation delays and the MR
pulse width.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.9 Waveforms showing the PL input to Q
output propagation delays, PL pulse width
and output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.10 Waveforms showing the MR input to SHCP,
STCP removal times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
December 1990 12
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
Fig.11 Waveforms showing hold and set-up times
for DS, Dn inputs to SHCP, STCP inputs.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.12 Waveforms showing set-up times for PL
input to SHCP input.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
