1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Central office quality DTMF transmitter/receiver
• Low power consumptio n
• High speed Intel micro interface
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30 dBm
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers
Description
The MT8888C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8888C utilizes an Intel micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external lo gic.
September 2005
Ordering Informati on
MT8888CE 20 Pin PDIP Tubes
MT8888CS 20 Pin SOIC Tubes
MT8888CN 24 Pin SSOP Tubes
MT8888CP 28 Pin PLCC Tubes
MT8888CE1 20 Pin PDIP* Tubes
MT8888CS1 20 Pin SOIC* Tubes
MT8888CN1 24 Pin SSOP* Tubes
MT8888CP1 28 Pin PLCC* Tubes
MT8888CPR 28 Pin PLCC Tape & Reel
MT8888CSR 20 Pin SOIC Tape & Reel
MT8888CSR1 20 Pin SOIC* Tape & Reel
MT8888CPR1 28 Pin PLCC* Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
MT8888C
Integrated DTMF Transceiver
with Intel Micro Interface
Data Sheet
Figure 1 - Functional Block Diagram
TONE
IN+
IN-
GS
OSC1
OSC2
VDD VRef VSS ESt St/GT
D0
D1
D2
D3
IRQ/CP
RD
CS
WR
RS0
∑D/A
Converters Row and
Column
Counters Transmit Data
Register
Data
Bus
Buffer
Tone Burst
Gating Cct.
+
-
Oscillator
Circuit
Bias
Circuit
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Logic
Steering
Logic
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Interrupt
Logic
I/O
Control
Low Group
Filter
High Group
Filter
Dial
Tone
Filter
MT8888C Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
20 24 28
11 1 IN+Non-inverting op-amp input.
22 2 IN-Inverting op-amp input.
33 4 GSGain Select. Gives access to output of front end dif fe rential amplifier for
connection of feedback resistor.
44 6V
Ref Reference Voltage output (VDD/2).
55 7 V
SS Ground (0V ).
6 6 8 OSC1 DTMF clock/osc illator input. Connect a 4.7 MΩ resistor to VSS if crystal oscillator is
used.
77 9OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
8 10 12 TONE Output from internal DTMF transmitter.
91113 WR
Write microprocessor input. TTL compatible.
10 12 14 CS Chip Select input. Active Low. This signal must be qualified externally by address
latch enable (ALE) signal, see Figure 14.
11 13 15 RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12 14 17 RD Read microprocessor input. TTL compatible.
13 15 18 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this
output goes low when a valid DTMF tone burst has been transmitted or received.
In call progress mode, this pin will output a rec tangu lar signal represent ative of the
input signal applied at the input op-amp. The input signal must be within the
bandwidt h limits of the call progress filter, see Figure 8.
14-17 18-21 19-22 D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.
TTL compatible.
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
RD
RS0
NC
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
TONE
WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
RD
RS0
24 PIN SSOP
20 PIN PLASTIC DIP/SOIC 28 PIN PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
•
GS
NC
NC
NC
D3
D2
D1
NC
VRef
VSS
OSC1
OSC2
NC
NC
RD
3
2
1
28
27
26
12
13
14
15
16
17
18
NC
IN-
IN+
VDD
St/GT
EST
TONE
WR
CS
RSO
NC
IRQ/CP
D0
MT8888C Data Sheet
3
Zarlink Semiconductor Inc.
1.0 Functional Description
The MT8888C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The Intel micro interface allows microcontrollers, such as the 8080, 80C31/51 and 8085, to access the MT8888C
internal registers.
2.0 Input Configuration
The input arrangement of the MT8888C provides a differential-input operational amplifier as well as a bias source
(VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in
Figure 3. Figure 4 shows the necessary connections for a differential input configura tion.
3.0 Receiver Section
Separation of th e low and high g roup tones is ach ieved by applying the DT MF signal to the inp ut s of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Table 1). These filters incorporate notches at 35 0 Hz and 440 Hz for exceptional dial tone rejection. Each filter
output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
18 22 26 ESt Early Steering output. Presents a logic high once the dig ital algorithm has
detected a valid tone pair (signal condition). Any momentary loss of signal
condition will cause ESt to return to a logic low.
19 23 27 St/GT S teering Input/Guard Time output (bidirectional). A voltage greater than VTSt
detected at St causes the device to register the detected tone pair and update the
output latch. A voltage less than VTSt frees the device to accept a new tone pair.
The GT output acts to reset the external steering time-constant; it s state is a
function of ESt and the voltage on St.
20 24 28 VDD Positive power supply (5 V typical).
8, 9,
16,17 3,5,10,
11,16,
23,25
NC No Connection.
Pin Description (continued)
Pin #
Name Description
20 24 28
MT8888C Data Sheet
4
Zarlink Semiconductor Inc.
Figure 3 - Single-Ended Input Configuration
Figure 4 - Differential Input Configuration
CRIN
RF
IN+
IN-
GS
VRef
VOLTAGE GAIN
(AV) = RF / RIN
MT8888C
C1
C2
R1
R2
R3
R4 R5
IN+
IN-
GS
VRef
MT8888C
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(AV diff) - R5/R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
MT8888C Data Sheet
5
Zarlink Semiconductor Inc.
Note: 0= LOGIC LOW, 1= LOGIC HIGH
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
4.0 Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT
output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registere d. The status of the delayed steering flag can be monitored b y checking the app ropriate
bit in the status register. If Interrupt mode has been selected, th e IRQ/CP pin will pull low when the delayed steering
flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit paus e between signals . Thus, as w ell as re jectin g signals too short to be considered va lid, the
FLOW FHIGH DIGIT D3D2D1D0
697 1209 1 0 0 0 1
697 1336 2 0 0 1 0
697 1477 3 0 0 1 1
770 1209 4 0 1 0 0
770 1336 5 0 1 0 1
770 1477 6 0 1 1 0
852 1209 7 0 1 1 1
852 1336 8 1 0 0 0
852 1477 9 1 0 0 1
941 1336 0 1 0 1 0
941 1209 * 1 0 1 1
941 1477 # 1 1 0 0
697 1633 A 1 1 0 1
770 1633 B 1 1 1 0
852 1633 C 1 1 1 1
941 1633 D 0 0 0 0
Table 1 - Functional Encode/Deco de Table
MT8888C Data Sheet
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Zarlink Semiconductor Inc.
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirement s.
Figure 5 - Basi c Steering Circuit
5.0 Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the following inequalities (see Figure 7):
tREC ≥ tDPmax+tGTPmax - tDAmin
tREC ≤ tDPmin+tGTPmin - tDAmax
tID ≥ tDAmax+tGTAmax - tDPmin
tDO ≤ tDAmin+tGTAmin - tDPmax
VDD
VDD
St/GT
ESt
C1
Vc
R1
MT8888C
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
MT8888C Data Sheet
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Zarlink Semiconductor Inc.
Figure 6 - Guard Time Adjustment
The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP)
and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both accept
and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor
system parameters such as talk off and noise immunity.
Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will
maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs
are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
6.0 Call Progress Filter
A call progress mode, using the MT8888C, can be selected allowing the detection of various tones, which identify
the progress of a telephone call on the network. The call progress tone input and DTMF input are common,
however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be
detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call
progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are
hard-limited by a high gain comparator with the IRQ/CP pin serv in g as the outpu t. The squarewa ve outpu t obtained
from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of
the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and
consequently the IRQ/CP pin will remain low.
VDD
St/GT
ESt
VDD
St/GT
ESt
C1
R1 R2
C1
R1 R2
tGTA = (R1C1) In (VDD/VTSt)
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
tGTA = (RpC1) In (VDD/VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
a) decreasing tGTP; (tGTP < tGTA)
b) decreasing tGTA ; (tGTP > tGTA)
MT8888C Data Sheet
8
Zarlink Semiconductor Inc.
Figure 7 - Receiver Timing Diagram
Figure 8 - Call Progress Response
Vin
ESt
St/GT
RX0-RX3
b3
b2
Read
Status
Register
IRQ/CP
EVENTS ABCDEF
tREC tREC tID tDO
TONE #n TONE
#n + 1 TONE
#n + 1
tDP tDA
tGTP tGTA
tPStRX
tPStb3
DECODED TONE # (n-1) # n # (n + 1)
VTSt
LEVEL
(dBm)
FREQUENCY (Hz)
-25
0 250 500 750
= Reject
= May Accept
= Accept
MT8888C Data Sheet
9
Zarlink Semiconductor Inc.
Figure 9 - Description o f Timing Events
7.0 DTMF Generator
The DTMF transmitter employed in the MT8888C is capable of generating all sixteen standard DTMF tone pairs
with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The
sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable
dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a
DTMF signal with low tota l harmonic distortion and high accuracy. To specify a DTMF signal, data c onforming to the
encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the
receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and
High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 94 Hz. The high group
frequencies are 1209, 1336, 147 7 and 1633 Hz. T ypically, the high group to low group amplitude ratio (twist) is 2 dB
to compensate for high group attenuation on long loops.
The period of each tone consist s of 32 equal tim e segment s. The period of a tone is controlled by varying the length
of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched
and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time
segment length, which will ultimately determine the fre quency of the tone. When the divide r reaches the approp riate
count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time
segments is fixed at 32, however, by varying the segment length as described above the frequency can also be
varied. The divider output clocks anothe r counter, which addresses the sinewave lookup ROM.
EXPLANATION OF EVENTS
A) TONE BURSTS DETECTED, TONE DURATION I NVALID, RX DATA REGISTER N OT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED U NTIL NEXT VALID TONE PAIR.
D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION IN VALID, D ATA REMAINS UNCHANGED.
F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED U NTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTIO N OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX0-RX34-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CO NSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.
b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS
REGISTER IS READ.
IRQ/CP INTERRUPT IS ACTIVE INDICATIN G THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRU PT IS
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC MAXIMUM DTMF SIGNAL DURATION NO T DETECTED AS VALID.
tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID R ECOGNITION.
tID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
tDO MAXIMUM ALLOWABLE DROPOUT DURING VALID D TMF SIGNAL.
tDP TIME TO DETECT VALID FREQUENCIES PRESENT.
tDA TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP GUARD TIME, TONE PRESENT.
tGTA GUARD TIME, TONE ABSENT.
MT8888C Data Sheet
10
Zarlink Semiconductor Inc.
The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and
highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which
are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other
DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst
accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can
be seen from Figure 8 that the distortion products are very low in amplitude.
Figure 10 - Spectrum Plot
8.0 Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration
determined either by the particular application or by any one of the exchange transmitter specifications currently
existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is
capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1ms,
which is a st andard interv al for autodialer and cen tral office applica tions. Af ter the bur st/p ause has been issued, the
appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing
described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode)
is selected, the burst/pause duration is doubled to 102 ms ±2 ms. Note that when CP mode and Burst mode have
been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard
burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses
when the burst mode is disabled by enabling and disabling the transmitter.
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
MT8888C Data Sheet
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Zarlink Semiconductor Inc.
9.0 Single Ton e Generation
A single tone mode is available whereby individual tones from the low group or high group can be generated. This
mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion
measurements. Refer to Control Register B description for details.
10.0 Distortion Calculations
The MT8888C is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The
internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic
components and intermodulation products. The total harmonic distortion for a single tone can be calculated using
Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental
frequency expressed as a percentage.
Figure 11 - Equation 1. THD (%) For a Single Tone
The Fourier components o f the tone output co rrespond to V2f.... Vnf as measured on the output waveform. The total
harmonic distortion for a dual tone can be calculated using Equation 2. VL and VH correspond to the low group
amplitude and high group amplitude, respectively and V2IMD is the sum of all the intermodulation components. The
internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as
shown in Figure 10.
Figure 12 - Equation 2. THD (%) For a Dual Tone
ACTIVE
INPUT
OUTPUT FREQUENCY (Hz) %ERROR
SPECIFIED ACTUAL
L1 697 699.1 +0.30
L2 770 766.2 -0.49
L3 852 847.4 -0.54
L4 941 948.0 +0.74
H1 1209 1215.9 +0.57
H2 1336 1331.7 -0.32
H3 1477 1471.9 -0.35
H4 1633 1645.0 +0.73
Table 2 - Actual Frequencies Versus Stan dard Requirements
THD (%) = 100 Vfundamental
V22f + V23f + V24f + .... V2nf
V2L + V2H
V22L + V23L + .... V2nL + V22H +
V23H + .. V2nH + V2IMD
THD (%) = 100
MT8888C Data Sheet
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Zarlink Semiconductor Inc.
11.0 DTMF Clock Circuit
The internal clock circuit is completed with the addition of a standard television color burst crystal. The crystal
specification is as follows:
Frequency: 3.579545 MHz
Frequency Tolerance: ±0.1%
Resonance Mode: Parallel
Load Capacitance: 18pF
Maximum Series Resistance: 150 ohms
Maximum Drive Level: 2mW
e.g. CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8888C devices can be connected as shown in Figure 13 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left
unconnected.
Figure 13 - Common Crystal Connection
12.0 Microprocessor Interface
The MT8888C incorporates an Intel microprocessor interface which is compa tible with fast versions (16 MHz) of the
80C51. No wait cycles need to be inserted.
Figure 19 and Figure 20 are the timing diagrams for the Intel 8031, 8051 and 8085 (5 MHz) microcontrollers. By
NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS is generated.
Figure 14 summarizes the connection of these Intel proces sors to the MT8888C transceiver.
The microprocessor interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two control registers (see Table 6 and Table 7), CRA and CRB, which have the same address. A
write operation to CRB is executed b y first setting th e most significant bit (b3) in CRA. The following write operation
to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The
read-only status register indicates the current transceiver state (see Table 8).
A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 19). Refer to Tables 4-7 for bit descriptions of the two control registers.
The multiplexed IRQ/CP pin can be pro grammed to generate an interrupt upon v alidation of DTMF signals or when
the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a
squarewave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external
pull-up resistor (see Figure 15).
MT8888C
OSC1 OSC2
MT8888C
OSC1 OSC2
MT8888C
OSC1 OSC2
3.579545 MHz
MT8888C Data Sheet
13
Zarlink Semiconductor Inc.
RS0 WR RD FUNCTION
0 0 1 Write to Transmit Data Register
0 1 0 Read from Receive Data Register
1 0 1 Write to Cont rol Register
1 1 0 Read from Status Register
Table 3 - Internal Register Functions
b3 b2 b1 b0
RSEL IRQ CP/DTMF TOUT
Table 4 - CRA Bit Positions
b3 b2 b1 b0
C/R S/D TEST BURST
ENABLE
Table 5 - CRB Bit Positions
BIT NAME DESCRIPTION
b0 TOUT Tone Output Control. A logic high enables th e tone output; a logic lo w turns the tone output
off. This bit controls all transmit tone functions.
b1 CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a rectangu lar wave representation of the receive d
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be dete cted when CP mode is selected.
b2 IRQ Interrupt Enable. A logic high ena bles the interrupt function; a logic low deactivates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
b3 RSEL Register Select. A logic high selects control register B for the next write cycle to the contro l
register address. Af ter writing to control register B, the fo llowing contro l register write cycle
will be directed to control register A.
Table 6 - Control Register A Description
MT8888C Data Sheet
14
Zarlink Semiconductor Inc.
BIT NAME DESCRIPTION
b0 BURST Burst Mode Select. A logic high deactivates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the p ause, the st atus register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (deac tivated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1 TEST Test Mode Control. A logic high enables the test mode; a logic low deactivates the test
mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the
signal present on the IRQ/CP pin will be analogous to the state of the DELAYED
STEERING bit of the status register (s ee Figure 7, signal b3).
b2 S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) th rough the C/R bit (control
register B, b3).
b3 C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7 - Control Register B Description
BIT NAME STATUS FLAG SET STATUS FLAG CLEARED
b0 IRQ Interrupt has occurred. Bit one
(b1) or bit two (b2) is set. Interrupt is inactive. Cleared after
Status Register is read.
b1 TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2 RECEIVE DATA REGISTER
FULL Valid data is in the Receive Data
Register. Cleared after Status Register is
read.
b3 DELAYED STEERING Set upon the valid detection of
the absence of a DTMF signal. Cleared upon the detection of a
valid DTMF signal.
Table 8 - Status Register Description
MT8888C Data Sheet
15
Zarlink Semiconductor Inc.
Figure 14 - MT8888C Interface Connections for Various Intel Micros
Figure 15 - Application Circuit (Single-Ended Input)
8031/8051
8080/8085 MT8888C
A8-A15
PO
RD
WR
CS
RD
WR
RS0
D0-D3
A8
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8888C can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
RD
RS0
DTMF/CP
INPUT
DTMF
OUTPUT
C1 R1
R2
X-tal
C4 RL
VDD
C3
C2
R4
R3
To µP
or µC
MT8880C
R5
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 kΩ 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 10 nF 10%
X-tal = 3.579545 MHz
R5 = 4.7 MΩ 10%
MT8888C Data Sheet
16
Zarlink Semiconductor Inc.
Figure 16 - Test Circuits
Figure 17 - Application Notes
TEST POINT
MMD6150 (or
equivalent)
5.0 VDC
2.4 kΩ
24 kΩ
130 pF MMD7000 (or
equivalent)
TEST POINT
5.0 VDC
3 kΩ
100 pF
Tes t lo ad fo r IRQ /CP pinTest load for D0-D3 pins
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after power up.The
initialization procedure should be implemented 100ms after power up.
Description: Control Data
RS0 WR RD b3 b2 b1 b0
1) Read Status Register 1 1 0 X X X X
2) Write to Control Register 1 0 1 0 0 0 0
3) Write to Control Register 1 0 1 0 0 0 0
4) Write to Control Register 1 0 1 1 0 0 0
5) Write to Control Register 1 0 1 0 0 0 0
6) Read Status Register 1 1 0 X X X X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence: RS0 WR RD b3 b2 b1 b0
1) Write to Control Register A 1 0 1 1 1 0 1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B 1 0 1 0 0 0 0
(burst mode)
3) Write to Transmit Data Register 0 0 1 0 1 1 1
(send a digit 7)
4) Wait for an interrupt or poll Status Register
5) Read the Status Register 1 1 0 X X X X
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register 0 0 1 0 1 0 1
(send a digit 5)
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register 0 1 0 X X X X
-if both bits are set...
Read the Receive Data Register 0 1 0 X X X X
Write to Transmit Data Register 0 0 1 0 1 0 1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER TH
E
DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED T
O
200 ms (± 4 ms).
MT8888C Data Sheet
17
Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditi ons is not implied.
‡ Typical figures are at 25 °C and f or design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings*
Parameter Symbol Min. Max. Units
1 Power supply voltage VDD-VSS VDD 6V
2 Voltage on any pin VIVSS-0.3 VDD+0.3 V
3 Current at any pin (Except VDD and VSS)10mA
4 Storage temperature TST -65 +150 °C
5 Package power dissipation PD1000 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym. Min. Typ.‡Max. Units Test Conditions
1 Positive power supply VDD 4.75 5.00 5.25 V
2 Operating temperature TO-40 +85 °C
3 Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz
DC Electrical Characteristics - † - VSS=0 V.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1S
U
P
Operating supply voltage VDD 4.75 5.0 5.25 V
2 Operating supply current IDD 7.0 11 mA
3 Power consumption PC57.8 mW
4I
N
P
U
T
S
High level input volt age
(OSC1) VIHO 3.5 V Note 9*
5 Low level input voltage
(OSC1) VILO 1.5 V Note 9*
6 Steering threshold voltage VTSt 2.2 2.3 2.5 V VDD=5V
7
O
U
T
P
U
T
S
Low level output voltage
(OSC2) VOLO 0.1 V No load
Note 9*
8 High level output voltage
(OSC2) VOHO 4.9 V No load
Note 9*
9 Output leakage current
(IRQ) IOZ 110µAV
OH=2.4 V
10 VRef output voltage VRef 2.4 2.5 2.6 V No load, VDD=5V
11 VRef output resistance ROR 1.3 kΩ
12 D
i
g
i
t
a
l
Low level input voltage VIL 0.8 V
13 High level input voltage V IH 2.0 V
14 Input leakage current IIZ 10 µAV
IN=VSS to VDD
15 Data
Bus Source current IOH -1.4 -6.6 mA VOH=2.4V
16 Sink current IOL 2.0 4.0 mA VOL=0.4V
MT8888C Data Sheet
18
Zarlink Semiconductor Inc.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
Figures are for design aid only: not guaranteed and not subject to production testing.
Characterist ics are over recomme nded operating conditions unless otherwise stated.
† Characteristics are over recommended opera ting conditions (unless otherwise stated) using the test circuit shown in Figure 15.
17 ESt
and
St/Gt
Source current IOH -0.5 -3.0 mA VOH=4.6V
18 Sink current IOL 24 mAV
OL=0.4V
19 IRQ/
CP Sink current IOL 416 mAV
OL=0.4V
Electrical Characteristics Gai n Setting Amplifier - Voltages are with resp ect to ground (VSS) unless otherwise stated,
VSS= 0V.
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1 Input leakage current IIN 100 nA VSS ≤ VIN ≤ VDD
2 Input resistance RIN 10 MΩ
3 Input offset voltage VOS 25 mV
4 Power supply rejectio n PSRR 50 dB 1 kHz
5 Common mode rejection CMRR 40 dB
6 DC open loop voltage ga in AVOL 40 dB CL = 20p
7 Unity gain bandwidth BW 1.0 MHz CL = 20p
8 Output voltage swing VO0.5 VDD-0.5 V RL ≥ 100 kΩ to VSS
9 Allowa ble capacitive loa d (GS ) CL100 pF PM>40°
10 Allowable resistive load (GS) RL50 kΩVO = 4Vpp
11 Common mode range VCM 1.0 VDD-1.0 V RL = 50kΩ
MT8888C AC Electrical Characteristics † - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Notes*
1R
X
Valid input signal levels
(each tone of composite
signal)
-29 +1 dBm 1,2,3,5,6
27.5 869 mVRMS 1,2,3,5,6
DC Electrical Characteristics (continued) - † - VSS=0 V. (continued)
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
MT8888C Data Sheet
19
Zarlink Semiconductor Inc.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 5 V, and for design aid only: not guaran teed and not subj ect to production testing.
* *See “Notes” following AC Electrical Characteristics Tables.
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5 V, and for design aid only: not gu aranteed and not subject to production testing
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5 V, and for design aid only: not gu aranteed and not subject to production testing
AC Electrical Characteristics † - Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz
Characteristics Sym. Min. Typ.‡Max. Units Notes*
1
R
X
Positive twist accept 8 dB 2,3,6,9
2 Negative twist accept 8 dB 2,3,6,9
3 Freq. deviation accept ±1.5%± 2Hz 2,3,5
4 Freq. deviation reject ±3.5% 2,3,5
5 Third tone tolerance -16 dB 2,3,4,5,9,10
6 Noise tolerance -12 dB 2,3,4,5,7,9,10
7 Dial tone tolerance 22 dB 2,3,4,5,8,9
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1 Accept Bandwidth fA310 500 Hz @ -25 dBm,
Note 9
2 Lower freq. (REJECT) fLR 290 Hz @ -25 dBm
3 Upper freq. (REJECT) fHR 540 Hz @ -25 dBm
4 Call progress tone detect level (total
power) -30 dBm
AC Electrical Characteristics †- DTMF Reception - Typical DTMF tone accept and reject requirements. Actual values are
user selectable as per Figures 5, 6 and 7.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1 Minimum tone accept duration tREC 40 ms
2 Maximum tone reject duration tREC 20 ms
3 Minimum interdigit pause duration tID 40 ms
4 Maximum tone drop-out duration tDO 20 ms
MT8888C Data Sheet
20
Zarlink Semiconductor Inc.
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1T
O
N
E
I
N
Tone present detect time tDP 3 11 14 ms Note 11
2 Tone absent detect time tDA 0.5 4 8.5 ms Note 11
3 Delay St to b3 tPStb3 13 µs See Figure 7
4 Delay St to RX0-RX3tPStRX 8µs See Figure 7
5
T
O
N
E
O
U
T
Tone burst duration tBST 50 52 ms DTMF mode
6 Tone pause duration tPS 50 52 ms DTMF mode
7 Tone burst duration (extended) tBSTE 100 104 ms Call Progress mode
8 Tone pause duration (extended) tPSE 100 104 ms Call Progress mode
9 High group output level VHOUT -6.1 -2.1 dBm RL=10kΩ
10 Low group output level VLOUT -8.1 -4.1 dBm RL=10kΩ
11 Pre-emphasis dBP023dBR
L=10kΩ
12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth
13 RL=10kΩ
14 Frequency deviation fD±0.7 ±1.5 % fC=3.579545 MHz
15 Output load resistance RLT 10 50 kΩ
16 X
T
A
L
Crystal/clock frequency fC3.5759 3.5795 3.5831 MHz
17 Clock input rise and fall time tCLRF 110 ns Ext. clock
18 Clock input duty cycle DCCL 40 50 60 % Ext. clock
19 Capacitive load (OSC2) CLO 30 pF
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (V SS), unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1RD
/WR clock frequency fCYC 4.0 MHz Figure 18
2RD
/WR cycle period tCYC 250 ns Figure 18
3RD
/WR rise and fall time tR, tF20 ns Figure 18
4 Address setup time tAS 23 ns Figures 19 & 20
5 Address hold time tAH 26 ns Figures 19 & 20
6 Data hold time (read) tDHR 22 ns Figures 19 & 20
7RD
to valid data delay (read) tDDR 100 ns Figures 19 & 20
8RD
, WR pulse width low tPWL 150 ns Figures 18, 19 & 20
9RD
, WR pulse width high tPWH 100 ns Figures 18, 19 & 20
10 Data setup time (write) tDSW 45 ns Figure s 19 & 20
11 Data hold time (write) tDHW 10 ns Figures 19 & 20
12 Input Capacitance (data bus) CIN 5pF
MT8888C Data Sheet
21
Zarlink Semiconductor Inc.
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5 V, and for design aid only: not gu aranteed and not subject to production testing
Notes:
1. dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration=40 ms. Tone pause=40 ms.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have an equal amplitude.
6. The tone pair is deviated by ± 1.5%±2 Hz.
7. Bandwidth limited (3 kHz) Gaussian noise.
8. The precise dial tone frequencies are 350 and 440 Hz (±2%).
9. Guaranteed by design and characterization. Not su bject to production testing.
10. Referenced to the lowest amplitude tone in the DTMF signal.
11. For guard time calculation purposes.
Figure 18 - RD/WR Clock Pulse
Figure 19 - 8031/8051/8085 Read Timing Diagram
Figure 20 - 8031/8051/8085 Write Timing Diagram
13 Output Capacitance (IRQ/CP) COUT 5pF
AC Electrical Characteristics†- MPU Interface (continued)- Volt a ges ar e w it h resp ect t o g round ( V SS), unles s otherwi se
Characteristics Sym. Min. Typ.‡Max. Units Conditions
tCYC
tR
tPWH tPWL
RD/WR
tF
RD
CS, RS0
DATA BUS
tPWL
tAS tAH
tPWH
tDDR tDHR
WR
CS, RS0
DATA BUS
tPWL
tAS tAH
tPWH
tDSW tDHW
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