This document contains information on a new product. Specifications and information herein are subject to change
without notice. © Motorola, Inc., 2003. All rights reserved.
1 Introduction
Motorola’s i.MX family of microprocessors has demonstrated leadership in the portable
handheld market. Continuing this legacy, the i.MX series provides a leap in performance
with an ARM9™ microprocessor core and highly integrated system functions. The i.MX
products specifically address the requirements of the personal, portable product market by
providing intelligent integrated peripherals, an advanced processor core, and power
management capabilities.
The new MC9328MX1 features the advanced and power-efficient ARM920T™ core that
operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller,
static RAM, USB support, an A/D converter (with touch panel control), and an MMC/SD
host controller, support a suite of peripherals to enhance any product seeking to provide a
rich multimedia experience. In addition, the MC9328MX1 is the first Bluetooth™
technology-ready applications processor. It is packaged in a 256-pin Mold Array Process-
Ball Grid Array (MAPBGA). Figure 1 on page 1 shows the functional block diagram of the
MC9328MX1.
Figure 1. MC9328MX1 Functional Block Diagram
Watchdog
GPIO
LCD Controller
JTAG/ICE CGM
Timer 1 & 2
PWM
Standard
Bootstrap
Connectivity
System Control
I2C
MMC/SD
SPI 1 and
UART 1
UART 2 & 3
USB Device
SmartCard I/F
Bluetooth
Memory Stick®
SSI/I2S 1 & 2
Analog Signal
Human Interface
Video Port
Multimedia
Multimedia
Power
RTC
BusDMAC
Interrupt
VMMU
CPU Complex
I Cache
AIPI 1
AIPI 2
D Cache
eSRAMEIM &
ARM9TDMI™
System I/O
Control (DPLLx2)
Controller
Control(11 Chnl)
(128K)SDRAMC
Accelerator
Accelerator
Processor
SPI 2
Host Controller
MC9328MX1
Advance Information
MC9328MX1/D
Rev. 3.0, 12/2003
MC9328MX1
(i.MX1) Integrated
Portable System
Processor
Contents
1 Introduction . . . . . . . . . . . 1
2 Signals and
Connections . . . . . . . . . . 5
3 Specifications . . . . . . . . 13
4 Pin-Out and Package
Information . . . . . . . . . . 91
Contact Information
. . . . . . . . . . . . . .Last Page
2MC9328MX1 Advance Information MOTOROLA
Introduction
1.1 Conventions
This document uses the following conventions:
• OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
•Logic level one is a voltage that corresponds to Boolean true (1) state.
•Logic level zero is a voltage that corresponds to Boolean false (0) state.
•To set a bit or bits means to establish logic level one.
•To clear a bit or bits means to establish logic level zero.
•A signal is an electronic construct whose state conveys or changes in state convey information.
•A pin is an external physical connection. The same pin can be used to connect a number of signals.
•Asserted means that a discrete signal is in active logic state.
—Active low signals change from logic level one to logic level zero.
—Active high signals change from logic level zero to logic level one.
•Negated means that an asserted discrete signal changes logic state.
—Active low signals change from logic level zero to logic level one.
—Active high signals change from logic level one to logic level zero.
• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x
are hexadecimal.
1.2 Features
To support a wide variety of applications, the MC9328MX1 provides a robust array of features, including
the following:
• ARM920T Microprocessor Core
• AHB to IP Bus Interfaces (AIPIs)
• External Interface Module (EIM)
• SDRAM Controller (SDRAMC)
• DPLL Clock and Power Control Module
• Three Universal Asynchronous Receiver/Transmitters (UART 1 UART 2 and UART 3)
• Two Serial Peripheral Interfaces (SPI)
• Two General-Purpose 32-bit Counters/Timers
• Watchdog Timer
• Real-Time Clock/Sampling Timer (RTC)
• LCD Controller (LCDC)
• Pulse-Width Modulation (PWM) Module
• Universal Serial Bus (USB) Device
• Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
• Memory Stick® Host Controller (MSHC)
Introduction
MOTOROLA MC9328MX1 Advance Information 3
• SmartCard Interface Module (SIM)
• Direct Memory Access Controller (DMAC)
• Two Synchronous Serial Interfaces and Inter-IC Sound (SSI 1 and SSI 2/I2S) Module
• Inter-IC (I2C) Bus Module
•Video Port
• General-Purpose I/O (GPIO) Ports
• Bootstrap Mode
• Analog Signal Processing (ASP) Module
• Bluetooth Accelerator (BTA)
• Multimedia Accelerator (MMA)
• 256-pin MAPBGA Package
1.3 Target Applications
The MC9328MX1 is targeted for advanced information appliances, smart phones, Web browsers, digital
MP3 audio players, handheld computers based on the popular Palm OS platform, and messaging
applications such as Motorola's wireless cellular products, including the AccompliTM 008 GSM/GPRS
interactive communicator.
1.4 Document Revision History
The following table provides revision history for this release. This history includes technical content
revisions only and not stylistic or grammatical changes.
Table 1. MC9328MX1 Data Sheet Revision History Rev. 3.0
Revision Location Revision
Throughout data sheet Changed all references to USB from self-powered only to self-powered
and bus-powered.
Changed all references to DragonBall to i.MX.
SDRAM timing in
Section 3.17, “SDRAM Memory
Controller,” on page 71
SDRAM clock cycle time changed from 11.4 ns to 10.4 ns at 1.8V in all
three tables.
Maximum ratings Table 4 on page 13 Change to maximum operation temperature range from 70°C to 85°C in
table and throughout data sheet.
32 k/16 MHz Osc signal timing.
Table 8 on page 15
Changed EXTAL32k input jitter (peak to peak) data/
Section Section 3.8.2, “DTACK Signal
Timing,” on page 23
Updated DTACK waveform and timing tables and figures.
Signals Table 3 Corrected MS_CLKI and MS_CLKO pin descriptions.
Removed descriptions of SVDD and SGND.
Section 3.8.3, “EIM External Bus
Timing,” on page 28
Clarified signal naming on all waveform diagrams
Specification updates Max temperature ratings and part numbers were updated.
4MC9328MX1 Advance Information MOTOROLA
Introduction
1.5 Product Documentation
The following documents are required for a complete description of the MC9328MX1 and are necessary to
design properly with the device. Especially for those not familiar with the ARM920T processor or
previous DragonBall products, the following documents are helpful when used in conjunction with this
manual.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MX1 Product Brief (order number MC9328MX1P/D)
MC9328MX1S Reference Manual (order number MC9328MX1SRM/D)
MC68VZ328 Product Brief (order number MC68VZ328P/D)
MC68VZ328 User’s Manual (order number MC68VZ328UM/D)
MC68VZ328 User’s Manual Addendum (order number MC68VZ328UMAD/D)
MC68SZ328 Product Brief (order number MC68SZ328P/D)
MC68SZ328 User’s Manual (order number MC68SZ328UM/D)
The Motorola manuals are available on the Motorola Semiconductors Web site at http://
www.motorola.com/semiconductors. These documents may be downloaded directly from the Motorola
Web site, or printed versions may be ordered. The ARM documentation is available from
http://www.arm.com.
1.6 Ordering Information
Table 2 provides ordering information for the 256-lead mold array process ball grid array (MAPBGA)
package.
Table 2. MC9328MX1 Ordering Information
Package Type Frequency Temperature Solderball Type Order Number
256-lead MAPBGA 200 MHz 0°C to 70°C Standard MC9328MX1VH20(R2)
256-lead MAPBGA 200 MHz 0°C to 70°C Pb-free MC9328MX1VM20(R2)
256-lead MAPBGA 200 MHz -30°C to 70°C Standard MC9328MX1DVH20(R2)
256-lead MAPBGA 200 MHz -30°C to 70°C Pb-free MC9328MX1DVM20(R2)
256-lead MAPBGA 150 MHz -40°C to 85°C Standard MC9328MX1CVH15(R2)
256-lead MAPBGA 150 MHz -40°C to 85°C Pb-free MC9328MX1CVM15(R2)
Signals and Connections
MOTOROLA MC9328MX1 Advance Information 5
2 Signals and Connections
Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 3. Signal Names and Descriptions
Signal Name Function/Notes
External Bus/Chip Select (EIM)
A [24:0] Address bus signals
D [31:0] Data bus signals
EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]
EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16]
EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8]
EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]
OE Memory Output Enable—Active low output enables external data bus
CS [5:0] Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are
selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is
selected.
ECB Active low input signal sent by flash device to the EIM whenever the flash device must
terminate an on-going burst sequence and initiate a new (long first access) burst
sequence.
LBA Active low signal sent by flash device causing the external burst device to latch the starting
burst address.
BCLK Clock signal sent to external synchronous memories (such as burst flash) during burst
mode.
RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used
as a WE input signal by external DRAM.
Bootstrap
BOOT [3:0] System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon
system reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A
[15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM/
SyncFlash cycles.
SDIBA [3:0] SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address
signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in
SDRAM/SyncFlash cycles.
MA [11:10] SDRAM address signals
6MC9328MX1 Advance Information MOTOROLA
Signals and Connections
MA [9:0] SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are
selected on SDRAM/SyncFlash cycles.
DQM [3:0] SDRAM data enable
CSD0 SDRAM/SyncFlash Chip Select signal which is multiplexed with the CS2 signal. These two
signals are selectable by programming the system control register.
CSD1 SDRAM/SyncFlash Chip Select signal which is multiplex with CS3 signal. These two
signals are selectable by programming the system control register. By default, CSD1 is
selected, so it can be used as SyncFlash boot chip select by properly configuring BOOT
[3:0] input pins.
RAS SDRAM/SyncFlash Row Address Select signal
CAS SDRAM/SyncFlash Column Address Select signal
SDWE SDRAM/SyncFlash Write Enable signal
SDCKE0 SDRAM/SyncFlash Clock Enable 0
SDCKE1 SDRAM/SyncFlash Clock Enable 1
SDCLK SDRAM/SyncFlash Clock
RESET_SF SyncFlash Reset
Clocks and Resets
EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit
is shut down.
XTAL16M Crystal output
EXTAL32K 32 kHz crystal input
XTAL32K 32 kHz crystal output
CLKO Clock Out signal selected from internal clock signals. Please refer to clock controller for
internal clock selection.
RESET_IN Master Reset—External active low Schmitt trigger input signal. When this signal goes
active, all modules (except the reset module and the clock control module) are reset.
RESET_OUT Reset Out—Internal active low output signal from the Watchdog Timer module and is
asserted from the following sources: Power-on reset, External reset (RESET_IN), and
Watchdog time-out.
POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is
normally generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG
controller.
TDO Serial Output for test instructions and data. Changes on the falling edge of TCK.
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes
Signals and Connections
MOTOROLA MC9328MX1 Advance Information 7
TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK Test Clock to synchronize test logic and control register access through the JTAG port.
TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the
rising edge of TCK.
System
BIG_ENDIAN BIG_ENDIAN—This signal determines the memory endian configuration. BIG_ENDIAN is
a static pin to inner module. If the pin is driven logic-high the memory system is configured
into big endian. If it is driven logic-low the memory system is configured into little endian.
The pin is not supposed to be changed on the fly.
ETM
ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM
mode.
ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM
mode.
ETMPIPESTAT [2:0] ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in
ETM mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplex with ECB, LBA, BCLK, PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0] Sensor port data
CSI_MCLK Sensor port master clock
CSI_VSYNC Sensor port vertical sync
CSI_HSYNC Sensor port horizontal sync
CSI_PIXCLK Sensor port data latch clock
LCD Controller
LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for gate.
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC Line Pulse or H Sync
LSCLK Shift Clock
ACD/OE Alternate Crystal Direction/Output Enable
CONTRAST This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal).
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes
8MC9328MX1 Advance Information MOTOROLA
Signals and Connections
PS Control signal output for source driver (Sharp panel dedicated signal).
CLS Start signal output for gate driver. This signal is invert version of PS (Sharp panel
dedicated signal).
REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SIM
SIM_CLK SIM Clock
SIM_RST SIM Reset
SIM_RX Receive Data
SIM_TX Transmit Data
SIM_PD Presence Detect Schmitt trigger input
SIM_SVEN SIM Vdd Enable
SPI
SPI1_MOSI Master Out/Slave In
SPI1_MISO Slave In/Master Out
SPI1_SS Slave Select (Selectable polarity)
SPI1_SCLK Serial Clock
SPI1_SPI_RDY Serial Data Ready
SPI2_TXD SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin however it does
show up as a primary or alternative signal in the signal multiplex scheme table. Refer to
Chapter 16, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29,
“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to
the assigned pin.
SPI2_RXD SPI2 master RxData input—This signal is multiplexed with a GPI/O pin however it does
show up as a primary or alternative signal in the signal multiplex scheme table. Refer to
Chapter 16, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29,
“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to
the assigned pin.
SPI2_SS SPI2 Slave Select—This signal is multiplexed with a GPI/O pin, however it does show up
as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16,
“Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module
and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned
pin.
SPI2_SCLK SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin however it does show up as
a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16,
“Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module
and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned
pin.
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes
Signals and Connections
MOTOROLA MC9328MX1 Advance Information 9
General Purpose Timers
TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT Timer 2 Output
USB Device
USBD_VMO USB Minus Output
USBD_VPO USB Plus Output
USBD_VM USB Minus Input
USBD_VP USB Plus Input
USBD_SUSPND USB Suspend Output
USBD_RCV USB RxD
USBD_OE USB OE
USBD_AFE USB Analog Front End Enable
Secure Digital Interface
SD_CMD SD Command—If the system designer does not want to make use of the internal pull-up,
via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added.
SD_CLK MMC Output Clock
SD_DAT [3:0] Data—If the system designer does not want to make use of the internal pull-up, via the
Pull-up enable register, a 50 K–69K external pull up resistor must be added.
Memory Stick Interface
MS_BS Memory Stick Bus State (Output)—Serial bus control signal
MS_SDIO Memory Stick Serial Data (Input/Output)
MS_SCLKO Memory Stick Serial Clock (Output)—Serial Protocol clock output
MS_SCLKI Memory Stick External Clock (Input)—Test clock input pin for SCLK divider. This pin is
only for test purposes, not for use in application mode.
MS_PI0 General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
MS_PI1 General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
UART1_RXD Receive Data
UART1_TXD Transmit Data
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes
10 MC9328MX1 Advance Information MOTOROLA
Signals and Connections
UART1_RTS Request to Send
UART1_CTS Clear to Send
UART2_RXD Receive Data
UART2_TXD Transmit Data
UART2_RTS Request to Send
UART2_CTS Clear to Send
UART2_DSR Data Set Ready
UART2_RI Ring Indicator
UART2_DCD Data Carrier Detect
UART2_DTR Data Terminal Ready
UART3_RXD Receive Data
UART3_TXD Transmit Data
UART3_RTS Request to Send
UART3_CTS Clear to Send
UART3_DSR Data Set Ready
UART3_RI Ring Indicator
UART3_DCD Data Carrier Detect
UART3_DTR Data Terminal Ready
Serial Audio Ports – SSI (configurable to I2S protocol)
SSI1_TXDAT TxD
SSI1_RXDAT RxD
SSI1_TXCLK Transmit Serial Clock
SSI1_RXCLK Receive Serial Clock
SSI1_TXFS Transmit Frame Sync
SSI1_RXFS Receive Frame Sync
SSI2_TXDAT TxD
SSI2_RXDAT RxD
SSI2_TXCLK Transmit Serial Clock
SSI2_RXCLK Receive Serial Clock
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes
Signals and Connections
MOTOROLA MC9328MX1 Advance Information 11
SSI2_TXFS Transmit Frame Sync
SSI2_RXFS Receive Frame Sync
I2C
I2C_SCL I2C Clock
I2C_SDA I2C Data
PWM
PWMO PWM Output
ASP
UIN Positive U analog input (for low voltage, temperature measurement)
UIP Negative U analog input (for low voltage, temperature measurement)
PX1 Positive pen-X analog input
PY1 Positive pen-Y analog input
PX2 Negative pen-X analog input
PY2 Negative pen-Y analog input
R1A Positive resistance input (a)
R1B Positive resistance input (b)
R2A Negative resistance input (a)
R2B Negative resistance input (b)
RVP Positive reference for pen ADC
RVM Negative reference for pen ADC
AVDD Analog power supply
AGND Analog ground
BlueTooth
BT1 I/O clock signal
BT2 Output
BT3 Input
BT4 Input
BT5 Output
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes
12 MC9328MX1 Advance Information MOTOROLA
Signals and Connections
BT6 Output
BT7 Output
BT8 Output
BT9 Output
BT10 Output
BT11 Output
BT12 Output
BT13 Output
TRISTATE Sets all I/O pins to tristate; Can be used for flash loading and is pulled low for normal
operations.
BTRF VDD Power supply from external BT RFIC
BTRF GND Ground from external BT RFIC
Noisy Supply Pins
NVDD Noisy Supply for the I/O pins
NVSS Noisy Ground for the I/O pins
Supply Pins – Analog Modules
AVDD Supply for analog blocks
AVSS Quiet GND for analog blocks
Internal Power Supply
QVDD Power supply pins for silicon internal circuitry
QVSS GND pins for silicon internal circuitry
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes
Specifications
MOTOROLA MC9328MX1 Advance Information 13
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings.
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MX1 processor
has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for
internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and
VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels
in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data
transmit/receive accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used
in the system, these Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as
other NVDD pins.
Table 4. Maximum Ratings
Rating Symbol Minimum Maximum Unit
Supply voltage Vdd -0.3 3.3 V
Maximum operating temperature range
MC9328MX1VH20/MC9328MX1VM20
TA070°C
Maximum operating temperature range
MC9328MX1DVH20/MC9328MX1DVM20
TA-30 70 °C
Maximum operating temperature range
MC9328MX1CVH15/MC9328MX1CVM15
TA-40 85 °C
ESD at human body model (HBM) VESD_HBM – 2000 V
ESD at machine model (MM) VESD_MM – 100 V
Latch-up current ILatchup – 200 mA
Storage temperature Test -55 150 °C
Power Consumption Pmax 8001
1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction
fetches from the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
13002
2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and
instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These
calculations are based on the core running its heaviest OS application at 200MHz, and where the whole
image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst
measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle
GPIO consuming 4mA.
mW
14 MC9328MX1 Advance Information MOTOROLA
Specifications
For more information about I/O pads grouping per VDD, please refer to Table 3 on page 5.
3.3 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the MC9328MX1.
Table 5. Recommended Operating Range
Rating Symbol Minimum Maximum Unit
I/O supply voltage, MSHC, SPI, BTA, USBd, LCD and CSI are
only 3V interface
NVDD 2.70 3.30 V
I/O supply voltage NVDD 1.70 3.30 V
Internal supply voltage (Core = 150 MHz) QVDD 1.70 1.90 V
Internal supply voltage (Core = 200 MHz) QVDD 1.80 2.00 V
Analog supply voltage AVDD 1.70 3.30 V
Bluetooth I/O voltage (Bluetooth) BTRFVDD11.70 3.10 V
Bluetooth I/O voltage (Non Bluetooth applications) BTRFVDD21.70 3.30 V
Table 6. Maximum and Minimum DC Characteristics
Number
or Symbol Parameter Minimum Typical Maximum Unit
Iop Full running operating current at 1.8V
for QVDD, 3.3V for NVDD/AVDD (Core
= 96 MHz, System = 96 MHz, MPEG4
decoding playback from external
memory card to both external SSI
audio decoder and TFT display panel,
and OS with MMU enabled memory
system is running on external SDRAM)
Please refer to application note:
AN2537, Power Performance of
MC9328MX1.
– QVDD at 1.8v
= 120mA; NVDD+AVDD
at 3.0v = 30mA
–mA
Sidd1Standby current (QVDD = 1.8V,
temp = 25°C)
–25–µA
Sidd2Standby current (QVDD = 1.8V,
temp = 55°C)
–45–µA
Sidd3Standby current (QVDD = 2.0V,
temp = 25°C)
–35–µA
Sidd4Standby current (QVDD = 2.0V,
temp = 55°C)
–60–µA
VIH Input high voltage 0.7VDD –Vdd+0.2V
VIL Input low voltage – – 0.4 V
Specifications
MOTOROLA MC9328MX1 Advance Information 15
3.4 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an
operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All
timing is measured at 30 pF loading.
VOH Output high voltage (IOH =2.0mA) 0.7V
DD –VddV
VOL Output low voltage (IOL =-2.5mA) – – 0.4 V
Vit+ Positive input threshold voltage,
Vi=Vih
– – 1.126 V
Vit- Negative input threshold voltage,
Vi=Vil
0.640 – – V
Vhys Hysteresis (Vit+ −Vit-) =V
ih –0.3––
IIL Input low leakage current
(VIN = GND, no pull-up or pull-down)
––±1µA
IIH Input high leakage current
(VIN =V
DD, no pull-up or pull-down)
––±1µA
IOH Output high current
(VOH =0.8V
DD, VDD =1.8V)
––4.0mA
IOL Output low current
(VOL =0.4V, V
DD =1.8V) −4.0 ––mA
IOZ Output leakage current
(Vout =V
DD, output is tri-stated)
––±5µA
CiInput capacitance – – 5 pF
CoOutput capacitance – – 5 pF
Table 7. Tri-State Signal Timing
Pin Parameter Minimum Maximum Unit
TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z – 20.8 ns
Table 8. 32k/16M Oscillator Signal Timing
Parameter Minimum RMS Maximum Unit
EXTAL32k input jitter (peak to peak) for both System PLL and
MCUPLL
– 5 20 ns
Table 6. Maximum and Minimum DC Characteristics (Continued)
Number
or Symbol Parameter Minimum Typical Maximum Unit
16 MC9328MX1 Advance Information MOTOROLA
Specifications
EXTAL32k input jitter (peak to peak) for MCUPLL only – 5 100 ns
EXTAL32k startup time 800 – – ms
EXTAL16M input jitter (peak to peak) – TBD TBD –
EXTAL16M startup time TBD – – –
Table 9. CLKO Rise/Fall Time (at 30pF Loaded)
Best
Case Typical Worst
Case Units
Rise Time 0.80 1.00 1.40 ns
Fall Time 0.74 1.08 1.67 ns
Table 8. 32k/16M Oscillator Signal Timing (Continued)
Parameter Minimum RMS Maximum Unit
Specifications
MOTOROLA MC9328MX1 Advance Information 17
3.5 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
• 32-bit data field
• 7-bit address field
• A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 10 on page 17 for the ETM9 timing
parameters used in Figure 2.
Figure 2. Trace Port Timing Diagram
Table 10. Trace Port Timing Diagram Parameter Table
Ref No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
MinimumMaximumMinimumMaximum
1 CLK frequency 0 85 0 100 MHz
2a Clock high time 1.3 – 2 – ns
2b Clock low time 3 – 2 – ns
3a Clock rise time – 4 – 3 ns
3b Clock fall time – 3 – 3 ns
4a Output hold time 2.28 – 2 – ns
4b Output setup time 3.42 – 3 – ns
TRACECLK
4b
4a
3b
2a 1
Output Trace Port
3a
Valid Data Valid Data
2b
TRACECLK
(Half-Rate Clocking Mode)
18 MC9328MX1 Advance Information MOTOROLA
Specifications
3.6 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 11. DPLL Specifications
Parameter Test Conditions Minimum Typical Maximum Unit
Reference clock freq range Vcc = 1.8V 5 – 100 MHz
Pre-divider output clock
freq range
Vcc = 1.8V 5 – 30 MHz
Double clock freq range Vcc = 1.8V 80 – 220 MHz
Pre-divider factor (PD) – 1 – 16 –
Total multiplication factor
(MF)
Includes both integer
and fractional parts
5–15–
MF
integer part
–5–15–
MF
numerator
Should be less than the
denominator
0 – 1022 –
MF
denominator
– 1 – 1023 –
Pre-multiplier lock-in time – – – 312.5 µsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-must lock-in
time)
250 280
(56 µs)
300 Tref
Freq lock-in time after
partial reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
220 250
(~50 µs)
270 Tref
Phase lock-in time after
full reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
300 350
(70 µs)
400 Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
270 320
(64 µs)
370 Tref
Freq jitter (p-p) – – 0.005
(0.01%)
0.01 2•Tdck
Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V – 1.0
(10%)
1.5 ns
Power supply voltage – 1.7 – 2.5 V
Power dissipation FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
––4mW
Specifications
MOTOROLA MC9328MX1 Advance Information 19
3.7 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4. Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent
forward biasing.
Figure 3. Timing Relationship with POR
Figure 4. Timing Relationship with RESET_IN
POR
RESET_POR
RESET_DRAM
HRESET
RESET_OUT
CLK32
HCLK
90% AVDD
10% AVDD
Could be adjust due to 32kHz
Crystal start-up time
1
2
3
4
Exact 300ms
7 cycles @ CLK32
14 cycles @ CLK32
14 cycles @ CLK32
RESET_IN
CLK32
HCLK
5
4
HRESET
RESET_OUT
6
20 MC9328MX1 Advance Information MOTOROLA
Specifications
1 Timing waveforms shown are dependent on crystal start-up time. If a stable clock source is used instead of
a crystal, the width of the POR should be ignored in calculating timing for the startup process.
Table 12. Reset Module Timing Parameter Table
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Min Max Min Max
1 Width of input POWER_ON_RESET 1800 – 800 – ns
2 Width of internal POWER_ON_RESET
(9600 *CLK32 at 32 KHz)
300 300 300 300 ms
3 7K to 32K-cycle stretcher for SDRAM reset 7 7 7 7 Cycles of
CLK32
4 14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
14 14 14 14 Cycles of
CLK32
5 Width of external hard-reset RESET_IN 4 – 4 – Cycles of
CLK32
6 4K to 32K-cycle qualifier 4 4 4 4 Cycles of
CLK32
Specifications
MOTOROLA MC9328MX1 Advance Information 21
3.8 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1,
including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM
is shown in Figure 5, and Table 13 defines the parameters of signals.
Figure 5. EIM Bus Timing Diagram
Table 13. EIM Bus Timing Parameter Table
Ref No. Parameter
1.8 ± 0.10V 3.0 ± 0.3V
Unit
Min Typical Max Min Typical Max
1a Clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns
1b Clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns
1a 1b
2a 2b
3b3a
4a 4b
4c 4d
5a 5b
5c 5d
6a
6a
6b
6c
7a 7b
7c
8a
8b
9b
9c
9a
9a
7d
(HCLK) Bus Clock
Address
Chip-select
Read (Write)
OE (rising edge)
LBA (negated rising edge)
OE (falling edge)
Burst Clock (rising edge)
LBA (negated falling edge)
EB (falling edge)
EB (rising edge)
Burst Clock (falling edge)
Read Data
Write Data (negated falling)
Write Data (negated rising)
DTACK_B
10a 10a
22 MC9328MX1 Advance Information MOTOROLA
Specifications
2a Clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns
2b Clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns
3a Clock fall to Read (Write) Valid 1.35 2.79 6.52 1.3 2.7 6.3 ns
3b Clock fall to Read (Write) Invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns
4a Clock1 rise to Output Enable Valid 2.32 2.62 6.85 2.3 2.6 6.8 ns
4b Clock1 rise to Output Enable Invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns
4c Clock1 fall to Output Enable Valid 2.38 2.69 7.04 2.3 2.6 6.8 ns
4d Clock1 fall to Output Enable Invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns
5a Clock1 rise to Enable Bytes Valid 1.91 2.52 5.54 1.9 2.5 5.5 ns
5b Clock1 rise to Enable Bytes Invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns
5c Clock1 fall to Enable Bytes Valid 1.97 2.59 5.69 1.9 2.5 5.5 ns
5d Clock1 fall to Enable Bytes Invalid 1.76 2.48 5.38 1.7 2.4 5.2 ns
6a Clock1 fall to Load Burst Address Valid 2.07 2.79 6.73 2.0 2.7 6.5 ns
6b Clock1 fall to Load Burst Address Invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns
6c Clock1 rise to Load Burst Address Invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns
7a Clock1 rise to Burst Clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns
7b Clock1rise to Burst Clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns
7c Clock1 fall to Burst Clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns
7d Clock1 fall to Burst Clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns
8a Read Data setup time 5.54 – – 5.5 – – ns
8b Read Data hold time 0 – – 0 – – ns
9a Clock1 rise to Write Data Valid 1.81 2.72 6.85 1.8 2.7 6.8 ns
9b Clock1 fall to Write Data Invalid 1.45 2.48 5.69 1.4 2.4 5.5 ns
9c Clock1 rise to Write Data Invalid 1.63 – – 1.62 – – ns
10a DTACK setup time 2.52 – – 2.5 – – ns
1. Clock refers to the system clock signal, HCLK, generated from the System DPLL
Table 13. EIM Bus Timing Parameter Table (Continued)
Ref No. Parameter
1.8 ± 0.10V 3.0 ± 0.3V
Unit
Min Typical Max Min Typical Max
Specifications
MOTOROLA MC9328MX1 Advance Information 23
3.8.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed Only CS5 group supports
DTACK signal function when using the external DTACK signal for data acknowledgement.
3.8.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units
of measure for this figure are found in the associated tables.
3.8.2.1 DTACK READ Cycle without DMA
Figure 6. DTACK READ Cycle without DMA
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
1OE
and EB assertion time See note 2 – ns
2CS5
pulse width 3T – ns
3OE
negated to address inactive 46.44 – ns
4 DTACK
asserted after CS5 asserted – 1019T ns
5 DTACK
asserted to OE negated 3T+2.2 4T+6.86 ns
6 Data hold timing after OE negated 0 – ns
DTACK
Address
EB
CS5
OE
Databus
programmable
min 0ns
(1)
(5)
(6)
(3)
(2)
(4)
(7)
(input to MX1)
(8)
(9)
(10)
24 MC9328MX1 Advance Information MOTOROLA
Specifications
3.8.2.2 DTACK Read Cycle DMA Enabled
Figure 7. DTACK Read Cycle DMA Enabled
7 Data ready after DTACK asserted 0 T ns
8 OE negated to CS negated 0.5T+0.24 0.5T+0.67 ns
9 OE negated after EB negated 0.5 1.5 ns
10 DTACK pulse width 1T 3T ns
Note:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
1OE and EB assertion time See note 2 – ns
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
RW
DTACK
Address
EB
CS5
OE
(logic high)
Databus
programmable
min 0ns
(1)
(6)
(7)
(3)
(4)
(2)
(5)
(8)
(input to MX1)
(9)
(10)
(11)
Specifications
MOTOROLA MC9328MX1 Advance Information 25
2CS pulse width 3T – ns
3OE
negated before CS5 is negated 0.5T+0.24 0.5T+0.67 ns
4 Address inactive before CS negated – 0.93 ns
5 DTACK
asserted after CS5 asserted – 1019T ns
6 DTACK
asserted to OE negated 3T+2.2 4T+6.86 ns
7 Data hold timing after OE negated 0 – ns
8 Data ready after DTACK is asserted – T ns
9CS
deactive to next CS active T – ns
10 OE negate after EB negate 0.5 1.5 ns
11 DTACK pulse width 1T 3T ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only
when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
26 MC9328MX1 Advance Information MOTOROLA
Specifications
3.8.2.3 DTACK Write Cycle without DMA
Figure 8. DTACK Write Cycle without DMA
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
1CS5
assertion time See note 2. – ns
2EB
assertion time See note 2 – ns
3CS5 pulse width 3T – ns
4RW negated before CS5 is negated 1.5T+0.58 1.5T+1.58 ns
5RW
negated to Address inactive 57.31 – ns
6 DTACK asserted after CS5 asserted – 1019T ns
7 DTACK
asserted to RW negated 2T+1.8 3T+5.26 ns
8 Data hold timing after RW negated 1.5T-0.59 – ns
9 Data ready after CS5 is asserted – T ns
10 EB negated before CS5 is negated 0.5T+0.74 0.5T+2.17 ns
11 DTACK pulse width 1T 3T ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
OE
DTACK
Address
EB
CS5
RW
(logic high)
Databus
programmable
min 0ns
programmable
min 0ns
(1)
(2)
(7)
(8)
(4)
(5)
(3)
(6)
(9)
(output from MX1)
(10)
(11)
Specifications
MOTOROLA MC9328MX1 Advance Information 27
3.8.2.4 DTACK Write Cycle DMA Enabled
Figure 9. DTACK Write Cycle DMA Enabled
Table 17. WSC = Parameters for Write Cycle 111111, DTACK_SEL=0, HCLK=96MHz
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
1 CS5
assertion time See note 2 – ns
2EB
assertion time See note 2 – ns
3CS5
pulse width 3T – ns
4RW
negated before CS5 is negated 1.5T+0.58 1.5T+1.58 ns
5 Address inactive before CS negated – 0.93 ns
6 DTACK
asserted after CS5 asserted – 1019T ns
7 DTACK
asserted to RW negated 2T+1.8 3T+5.26 ns
8 Data hold timing after RW negated 1.5T-0.59 – ns
9 Data ready after CS5 is asserted – T ns
10 CS deactive to next CS active T – ns
11 EB negate to CS negate 0.5T+0.74 0.5T+2.17 ns
12 DTACK pulse width 1T 3T ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
OE
DTACK
Address
EB
CS5
RW
(logic high)
Databus
programmable
min 0ns
programmable
min 0ns
(1)
(2)
(7)
(8)
(4)
(5)
(3)
(6)
(9)
(output from MX1)
(10)
(11)
(12)
28 MC9328MX1 Advance Information MOTOROLA
Specifications
3.8.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral.
Figure 10. WSC = 1, A.HALF/E.HALF
hclk
hsel_weim_cs[0]
htrans
hwrite
haddr
hready
weim_hrdata
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
Read
Seq/Nonseq
V1
Last Valid Data
Last Valid Address
Read
V1
V1
V1
Internal signals - shown only for illustrative purposes
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Specifications
MOTOROLA MC9328MX1 Advance Information 29
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
hclk
hsel_weim_cs[0]
htrans
hwrite
haddr
hready
hwdata
weim_hready
Write
Nonseq
V1
Last Valid Data
Last Valid Address
weim_hrdata
Write Data (V1) Unknown
Last Valid Data
V1
Write
Last Valid Data Write Data (V1)
BCLK
ADDR
CS0
R/W
LBA
OE
EB
DATA
Internal
signals
-
shown
only
for
illustrative
purposes
30 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
hclk
hsel_weim_cs[0]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS0
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Last Valid Data
Address V1
V1 Word
Read
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Internal signals - shown only for illustrative purposes
EBx1 (EBC2=0)
EBx1 (EBC2=1)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Specifications
MOTOROLA MC9328MX1 Advance Information 31
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
hclk
hsel_weim_cs[0]
htrans
hwrite
haddr
hready
weim_hready
weim_hrdata
hwdata
Write
Nonseq
V1
Last Valid Data
Address V1
Write Data (V1 Word)
Write
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
BCLK
ADDR
CS0
R/W
LBA
OE
EB
DATA
Internal signals - shown only for illustrative purposes
32 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
hclk
hsel_weim_cs[3]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS[3]
R/W
BA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Last Valid Data
Address V1
V1 Word
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Read
Internal signals - shown only for illustrative purposes
EBx1 (EBC2=0)
EBx1 (EBC2=1)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Specifications
MOTOROLA MC9328MX1 Advance Information 33
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
hclk
hsel_weim_cs[3]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS3
R/W
LBA
OE
DATA
weim_hrdata
EB
hwdata
Write
Nonseq
V1
Last Valid
Data
Address V1
Write Data (V1 Word)
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
Write
Last Valid Data
Internal signals - shown only for illustrative purposes
34 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
weim_data_in
weim_hrdata
Read
Nonseq
V1
Address V1
V1 Word
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
Read
EBx1 (EBC2=0)
EBx1 (EBC2=1)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 35
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
hwdata
EB
weim_hrdata
Write
Nonseq
V1
Address V1
Write Data (V1 Word)
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
Write
Last Valid Data
Last Valid
Data
Internal signals - shown only for illustrative purposes
36 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Address V1
V1 Word
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
Read
Internal signals - shown only for illustrative purposes
EBx1 (EBC2=0)
EBx1 (EBC2=1)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Specifications
MOTOROLA MC9328MX1 Advance Information 37
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Address V1
V1 Word
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
Read
Internal signals - shown only for illustrative purposes
EBx1 (EBC2=0)
EBx1 (EBC2=1)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
38 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
weim_hrdata
EB
DATA
hwdata
Write
Nonseq
V1
Address V1
Unknown
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
Last Valid Data
Write Data (V1 Word)
Write
Last Valid
Data
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 39
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
weim_hrdata
EB
DATA
hwdata
Write
Nonseq
V1
Address V1
Unknown
Address V1 + 2Last Valid Addr
1/2 Half Word 2/2 Half Word
Last Valid Data
Last Valid Data
Write Data (V1 Word)
Write
Last Valid
Data
Internal signals - shown only for illustrative purposes
40 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Address V1
Write Data
Address V8Last Valid Addr
Last Valid Data
Read
Write
Nonseq
V8
Last Valid Data Read Data
Write
Read Data
Last Valid Data Write Data
hwdata
DATA
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 41
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Address V1 Address V8Last Valid Addr
Read Data
Last Valid Data
Read
Write
Nonseq
V8
DATA
hwdata
Last Valid Data
Write Data
Read Data
Write
Last Valid Data Write Data
Read WriteIdle
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
42 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
Write
Nonseq
V1
Address V1 Address V1 + 2Last Valid Addr
Last Valid Data
Write Data (Word)
Write
Last Valid Data Write Data (1/2 Half Word) Write Data (2/2 Half Word)
hclk
hsel_weim_cs[4]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS
R/W
LBA
OE
weim_hrdata
EB
DATA
hwdata Last Valid
Data
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 43
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
hclk
hsel_weim_cs[4]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS4
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Address V1 Address V8Last Valid Addr
Last Valid Data
Read
Last Valid Data Read Data
Write Data
Write
Nonseq
V8
Write
Read Data
Write DataLast Valid DataDATA
hwdata
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
44 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
hclk
hsel_weim_cs[4]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS4
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Address V1
Read Data (V1)
Address V2Last Valid
Last Valid Data
Read
Read
Seq
V2
Idle
Read Data (V2)
CNC
Read Data
(V1) Read Data
(V2)
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 45
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
hclk
hsel_weim_cs[4]
htrans
hwrite
haddr
hready
weim_hready
bclk
ADDR
CS4
R/W
LBA
OE
DATA
weim_hrdata
Read
Nonseq
V1
Address V1 Address V8Last Valid Addr
Read Data
Last Valid Data
Read
DATA
hwdata
Write
Nonseq
V8
Idle
Last Valid Data
Write Data
Read Data
Write
CNC
Last Valid Data Write Data
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
46 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
Nonseq Nonse
Read Read
Idle
V1 V5
Address V1Last Valid Addr Address V5
Read
V1 Word V2 Word V5 Word V6 Word
ECB
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 47
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
ECB
Nonseq Seq
Read
Idle
V1
Seq Seq
Read Read Read
V2 V3 V4
Last Valid Data V1 Word V2 Word V3 Word V4 Word
Address V1Last Valid Addr
Read
V1 Word V2 Word V3 Word V4 Word
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
48 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
ECB
Address V1Last Valid
Read
V1 1/2 V1 2/2 V2 1/2 V2 2/2
Address V2
Nonseq Seq
Read
Idle
V1
Read
V2
Last Valid Data V1 Word V2 Word
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 49
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
Non
seq Seq
Read
Idle
V1
Read
V2
Last Valid Data V1 Word V2 Word
Address V1
Last
Read
V1 1/2 V1 2/2 V2 1/2 V2 2/2
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
ECB
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
50 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hready
BCLK
ADDR
CS2
R/W
LBA
OE
DATA
weim_hrdata
ECB
Non
seq Seq
Read
Idle
V1
Read
V2
Last Valid Data V1 Word V2 Word
Address V1
Last
Read
V1 1/2 V1 2/2 V2 1/2 V2 2/2
EBx1 (EBC2=0)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
EBx1 (EBC2=1)
Internal signals - shown only for illustrative purposes
Specifications
MOTOROLA MC9328MX1 Advance Information 51
Figure 33. SCLK to LD Timing Diagram
3.8.4 Non-TFT Panel Timing
Figure 34. Non-TFT Panel Timing
Table 18. LCDC SCLK Timing
Num Characteristic
3.0 +/- 0.3V
Unit
Minimum Maximum
1 SCLK to LD valid – 3 ns
Table 19. Non TFT Panel Timing Diagram
Symbol Parameter Allowed Register Minimum
Value Actual Value Unit
T1 HSYN to VSYN delay 0 HWAIT2+2 Tpix
T2 HSYN pulse width 0 HWIDTH+1 Tpix
T3 VSYN to SCLK – 0<= T3<=Ts –
T4 SCLK to HSYN 0 HWAIT1+1 Tpix
LSCLK
LD[15:0]
1
T1
T2 T4
T3 XMAX
VSYN
SCLK
HSYN
LD[15:0]
T2
T1
Ts
52 MC9328MX1 Advance Information MOTOROLA
Specifications
• VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing
diagram, all these 3 signals are active high.
• Ts is the shift clock period.
• Ts = Tpix * (panel data bus width).
• Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
• Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider
Register.
• Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
Specifications
MOTOROLA MC9328MX1 Advance Information 53
3.9 Pen ADC Specifications
The specifications for the pen ADC are shown in Table 20 through Table 22.
3.10 ASP Touch Panel Controller
The following sections contain the electrical specifications of the ASP touch panel controller. The value of
parameters and their corresponding measuring conditions are mentioned as well.
3.10.1 Electrical Specifications
Test conditions: Temperature = 25ºC, QVDD = 1800mV.
Table 20. Pen ADC System Performance
Full Range Resolution1
1. Tested under input = 0~1.8V at 25°C
13 bits
Non-Linearity Error14 bits
Accuracy 19 bits
Table 21. Pen ADC Test Conditions
Vp max 1800 mV ip max +7 µA
Vp min GND ip min 1.5 µA
Vn GND in 1.5 µA
Sample frequency 12 MHz
Sample rate 1.2 KHz
Input frequency 100 Hz
Input range 0–1800 mV
Note: Ru1 = Ru2 = 200K
Table 22. Pen ADC Absolute Rating
ip max +9.5 µA
ip min -2.5 µA
in max +9.5 µA
in min -2.5 µA
Table 23. ASP Touch Panel Controller Electrical Spec
Parameter Minimum Type Maximum Unit
Offset – 32768 – –
Offset Error – – 8199 –
54 MC9328MX1 Advance Information MOTOROLA
Specifications
Note that QVDD should be 1800mV.
3.10.2 Gain Calculations
The ideal mapping of input voltage to output digital sample is defined as follows:
Figure 35. Gain Calculations
In general, the mapping function is:
S = G * V + C
Where V is input, S is output, G is the slope, and C is the y-intercept.
Nominal Gain G0 = 65535 / 4800 = 13.65mV-1
Nominal Offset C0 = 65535 / 2 = 32767
Gain – 13.65 – mV-1
Gain Error – – 33% –
DNL 89–Bits
INL –0–Bits
Accuracy
(without missing code)
89–Bits
Operating Voltage Range (Pen) ––QVDDmV
Operating Voltage Range (U) Negative
QVDD
–QVDDmV
On-resistance of switches SW[8:1] –10–Ohm
Table 23. ASP Touch Panel Controller Electrical Spec (Continued)
Parameter Minimum Type Maximum Unit
2400
1800
Smax
65535
C0
G0
Sample
Vi
-2400
Specifications
MOTOROLA MC9328MX1 Advance Information 55
3.10.3 Offset Calculations
The ideal mapping of input voltage to output digital sample is defined as:
Figure 36. Offset Calculations
In general, the mapping function is:
S = G * V + C
Where V is input, S is output, G is the slope, and C is the y-intercept.
Nominal Gain G0 = 65535 / 4800 = 13.65mV-1
Nominal Offset C0 = 65535 / 2 = 32767
3.10.4 Gain Error Calculations
Gain error calculations are made using the information in this section.
Figure 37. Gain Error Calculations
Assuming the offset remains unchanged, the mapping is rotated around y-intercept to determine the
maximum gain allowed. This occurs when the sample at 1800mV has just reached the ceiling of the 16-bit
range, 65535.
2400
1800
Smax
65535
C0
G0
Sample
Vi
-2400
2400
1800
Smax
65535
C0
G0
Sample
Vi
- 2400
Gmax
56 MC9328MX1 Advance Information MOTOROLA
Specifications
Maximum Offset Gmax,
Gmax = (65535 - C0) / 1800
= (65535 - 32767) / 1800
= 18.20
Gain Error Gr,
Gr= (Gmax - G0) / G0 * 100%
= (18.20 - 13.65) / 13.65 * 100%
= 33%
3.11 Bluetooth Accelerator
The Bluetooth Accelerator (BTA) radio interface supports the Motorola Radio, MC13180 using an SPI
interface. This section provides the data bus timing diagrams and SPI interface timing diagrams shown in
Figure 38 and Figure 39 on page 57, and the associated parameters shown in Table 24 and Table 25 on
page 57.
Figure 38. Motorola MC13180 Data Bus Timing Diagram
Table 24. Motorola MC13180 Data Bus Timing Parameter Table
Ref No. Parameter Minimum Typical Maximum Unit
1 FrameSync setup time relative to BT CLK rising edge1–4–ns
2 FrameSync hold time relative to BT CLK rising edge1–12 –ns
3 Receive Data setup time relative to BT CLK rising edge1–6 –ns
4 Receive Data hold time relative to BT CLK rising edge1–13–ns
5 Transmit Data setup time relative to RXTX_EN rising edge2172.5 – 192.5 µs
BT CLK (BT1)
FS (BT5)
PKT DATA (BT3)
RXTX_EN (BT9)
PKT DATA (BT2)
5
4
3
Receive
Transmit
6
7
8
1
2
Specifications
MOTOROLA MC9328MX1 Advance Information 57
Figure 39. SPI Interface Timing Diagram Using Motorola MC13180
6 TX DATA period 1000 +/- 0.02 ns
7 BT CLK duty cycle 40 – 60 %
8 Transmit Data hold time relative to RXTX_EN falling edge 4 – 10 µs
1. Please refer to Motorola 2.4 GHz RF Transceiver Module (MC13180) Technical Data documentation.
2. The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register
(0x00216050) and RF_Status (0x0021605C) registers.
Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180
Ref No. Parameter Minimum Maximum Unit
1 SPI_EN setup time relative to rising edge of SPI_CLK 15 – ns
2 Transmit data delay time relative to rising edge of SPI_CLK 0 15 ns
3 Transmit data hold time relative to rising edge of SPI_EN 0 15 ns
4 SPI_CLK rise time 0 25 ns
5 SPI_CLK fall time 0 25 ns
6 SPI_EN hold time relative to falling edge of SPI_CLK 15 – ns
7 Receive data setup time relative to falling edge of SPI_CLK1
1. The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by
programming SPI_Control (0x00216138) register together with system clock.
15 – ns
8 Receive data hold time relative to falling edge of SPI_CLK115 – ns
9 SPI_CLK frequency, 50% duty cycle required1–20MHz
Table 24. Motorola MC13180 Data Bus Timing Parameter Table (Continued)
Ref No. Parameter Minimum Typical Maximum Unit
SPI_EN (BT11)
SPI_DATA_OUT (BT12)
SPI CLK (BT13)
SPI_DATA_IN (BT4)
1
7
45
8
2
3
6
9
58 MC9328MX1 Advance Information MOTOROLA
Specifications
3.12 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or
SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1 Control Register
(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input
signal, and is used to latch data into or load data out to the internal data shift registers, as well as to
increment the data FIFO.
.
Figure 40. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
Figure 41. Master SPI Timing Diagram Using SPI_RDY Level Trigger
Figure 42. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
Figure 43. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
1
235
4
SS
SPIRDY
SCLK, MOSI, MISO
SS
SPIRDY
SCLK, MOSI, MISO
SCLK, MOSI, MISO
SS (output)
SS (input)
SCLK, MOSI, MISO
Specifications
MOTOROLA MC9328MX1 Advance Information 59
Figure 44. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
3.13 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MX1
Reference Manual.
Figure 45. SCLK to LD Timing Diagram
Table 26. Timing Parameter Table for Figure 40 through Figure 44
Ref
No. Parameter Minimum Maximum Unit
1 SPI_RDY to SS output low 2T 1
1. T = CSPI system clock period (PERCLK2).
–ns
2SS
output low to first SCLK edge 3·Tsclk 2
2. Tsclk = Period of SCLK.
–ns
3 Last SCLK edge to SS output high 2·Tsclk – ns
4SS
output high to SPI_RDY low 0 – ns
5SS
output pulse width Tsclk + WAIT 3
3. WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample
Period Control Register.
–ns
6SS
input low to first SCLK edge T – ns
7SS
input pulse width T – ns
Table 27. LCDC SCLK Timing Parameter Table
Ref No. Parameter Minimum Maximum Unit
1 SCLK to LD valid – 2 ns
6 7
SS (input)
SCLK, MOSI, MISO
1
LSCLK
LD[15:0]
60 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 46. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Diagram
Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table
Symbol Description Minimum Corresponding Register Value Unit
T1 End of OE to beginning of VSYN T5+T6
+T7+T9
(VWAIT1·T2)+T5+T6+T7+T9 Ts
T2 HSYN period XMAX+5 XMAX+T5+T6+T7+T9+T10 Ts
T3 VSYN pulse width T2 VWIDTH·(T2) Ts
T4 End of VSYN to beginning of OE 2 VWAIT2·(T2) Ts
T5 HSYN pulse width 1 HWIDTH+1 Ts
T6 End of HSYN to beginning to T9 1 HWAIT2+1 Ts
T7 End of OE to beginning of HSYN 1 HWAIT1+1 Ts
T8 SCLK to valid LD data -3 3 ns
T9 End of HSYN idle2 to VSYN edge
(for non-display region)
22Ts
T9 End of HSYN idle2 to VSYN edge
(for Display region)
11Ts
Line 1 Line Y
T1 T4
T3
(1,1) (1,2) (1,X)
T5 T7
T6 XMAX
VSYN
HSYN
OE
LD[15:0]
SCLK
HSYN
OE
LD[15:0]
T2
T8
VSYN
Display regionNon-display region
Line Y
Specifications
MOTOROLA MC9328MX1 Advance Information 61
3.14 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/
SD module (inner system) and the application (user programming).
Figure 47. Chip-Select Read Cycle Timing Diagram
T10 VSYN to OE active (Sharp = 0),
when VWAIT2 = 0
11Ts
T10 VSYN to OE active (Sharp = 1),
when VWAIT2 = 0
22Ts
Note:
• Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
• VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals are active low.
• The polarity of SCLK and LD[15:0] can also be programmed.
• SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 46, SCLK is
always active.
• For T9 non-display region, VSYN is non-active. It is used as an reference.
• XMAX is defined in pixels.
Table 29. SDHC Bus Timing Parameter Table
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Min Max Min Max
1 CLK frequency at Data transfer Mode (PP)1—10/30
cards
0 25/5 0 25/5 MHz
2 CLK frequency at Identification Mode20 400 0 400 KHz
3a Clock high time1—10/30 cards 6/33 – 10/50 – ns
Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table (Continued)
Symbol Description Minimum Corresponding Register Value Unit
Bus Clock
5b
6b
6a
7
5a
4a
3a
CMD_DAT Input
CMD_DAT Output
4b
3b
Valid Data Valid Data
Valid DataValid Data
1 2
62 MC9328MX1 Advance Information MOTOROLA
Specifications
3.14.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 48. The symbols for Figure 48 through Figure 52
are defined in Table 30.
3b Clock low time1—10/30 cards 15/75 – 10/50 – ns
4a Clock fall time1—10/30 cards – 10/50
(5.00)3
– 10/50 ns
4b Clock rise time1—10/30 cards – 14/67
(6.67)3
– 10/50 ns
5a Input hold time3—10/30 cards 5.7/5.7 – 5/5 – ns
5b Input setup time3—10/30 cards 5.7/5.7 – 5/5 – ns
6a Output hold time3—10/30 cards 5.7/5.7 – 5/5 – ns
6b Output setup time3—10/30 cards 5.7/5.7 – 5/5 – ns
7 Output delay time30 16 0 14 ns
1. CL≤100 pF / 250 pF (10/30 cards)
2. CL≤250 pF (21 cards)
3. CL≤25 pF (1 card)
Table 30. State Signal Parameters for Figure 48 through Figure 52
Card Active Host Active
Symbol Definition Symbol Definition
Z High impedance state S Start bit (0)
D Data bits T Transmitter bit
(Host = 1, Card = 0)
* Repetition P One-cycle pull-up (1)
CRC Cyclic redundancy check bits (7 bits) E End bit (1)
Table 29. SDHC Bus Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Min Max Min Max
Specifications
MOTOROLA MC9328MX1 Advance Information 63
Figure 48. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 49
on page 63, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods NRC and NCC.
Figure 49. Timing Diagrams at Data Transfer Mode
Figure 50 on page 64 shows basic read operation timing. In a read operation, the sequence starts with a
single block read command (which specifies the start address in the argument field). The response is sent
on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC,
beginning from the last bit of the read command. If the system is in multiple block read mode, the card
sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command.
The data stops two clock cycles after the end bit of the stop command.
SET_RCA Timing
Identification Timing
Host Command CID/OCR
NID cycles
CMD Content
S T E Z Z S T Content Z Z
******
CRC Z
Host Command CID/OCR
NCR cycles
CMD Content
S T E Z Z S T Content Z Z
******
CRC Z
Timing of command sequences (all modes)
Timing response end to next CMD start (data transfer mode)
Command response timing (data transfer mode)
Host Command Response
NCR cycles
CMD Content
S T E Z Z P P S T Content CRC E Z Z
******
CRC Z
Response Host Command
NRC cycles
CMD Content
S T E Z Z S T Content CRC E Z Z
******
CRC Z
Host Command Host Command
NCC cycles
CMD Content
S T E Z Z S T Content CRC E Z Z
******
CRC Z
64 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 50. Timing Diagrams at Data Read
Figure 51 on page 65 shows the basic write operation timing. As with the read operation, after the card
response, the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the
card to check for transmission errors. The card sends back the CRC check result as a CC status token on
the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a
positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured
to multiple block mode, with the flow terminated by a stop transmission command.
NAC cycles Read Data
Timing of single block read
NAC cycles
Read Data
Timing of multiple block read
NAC cycles
NST
Timing of stop command
(CMD12, data transfer mode)
Host Command Response
NCR cycles
CMD Content
S T E Z Z P P S T Content CRC E Z
******
CRC
DAT Z****Z Z Z P P S D *****
D D D
DAT Z****Z Z Z P P S D *****
****** D D D P ***** P S D D D D
******
Host Command Response
NCR cycles
CMD Content
S T E Z Z P P S T Content CRC E Z
******
CRC
*****
Read Data
Host Command Response
NCR cycles
CMD Content
S T E Z Z P P S T Content CRC E Z
******
CRC
Valid Read Data
DAT ***** ZZE *****
D D D D D D D D Z
Specifications
MOTOROLA MC9328MX1 Advance Information 65
Figure 51. Timing Diagrams at Data Write
Write Data Busy
Write Data
Write Data
Host Command Response
NCR cycles
CMD
DAT
Timing of the block write command
NWR cycles
Busy
CRC status
CMD
DAT
Timing of the multiple block write command
Content
CRC status
NWR cycles
CRC status
E Z Z P P P P
******
Z Z P P S CRC E Z Z S E Z P P S Content CRC E Z Z S E S E Z
X X X X X X
L*L
X X X X X X
Status Status
DAT Content
Z Z P P S CRC E Z Z X X Z P P S Content CRC E Z Z X X X X X X XX X X Z
NWR cycles
X X X X X X
Z****Z Z Z Z P P S Content CRC E Z Z S E S E Z
L*L
Status
X X X X X X X ZX XXE Z ZP P S Content CRC
Z Z Z
DAT Z****Z
Content
S T CRC E Z Z P P S T Content CRC E Z Z P ******
****** P P P
66 MC9328MX1 Advance Information MOTOROLA
Specifications
The stop transmission command may occur when the card is in different states. Figure 52 shows the
different scenarios on the bus.
Figure 52. Stop Transmission During Different Scenarios
Write Data Stop transmission during data transfer
from the host.
Busy (Card is programming)
Stop transmission during CRC status transfer
from the card.
Stop transmission received after last data block.
Card becomes busy programming.
Stop transmission received after last data block.
Card becomes busy programming.
Host Command Card Response
NCR cycles
CMD Content
S T E Z Z P P S T Content CRC E Z Z
******
Host Command
Content
S T CRC E
DAT ******
D D D D D D Z Z Z ZD D D D D D D E Z Z S L Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE
DAT ******
D D D D D D Z Z Z ZD Z Z S Z Z S L Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE
CRC E
CRC
DAT ******
S L Z Z Z Z Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE
DAT ******
Z Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z S L Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE
Z
Specifications
MOTOROLA MC9328MX1 Advance Information 67
3.14.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt
Period" during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
Figure 53. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the
clock running, and allows the user to submit commands as normal. After all commands are submitted, the
user can switch back to the data transfer operation and all counter and status values are resumed as access
continues.
Table 31. Timing Values for Figure 48 through Figure 52
Parameter Symbol Minimum Maximum Unit
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Command response cycle NCR 2 64 Clock cycles
Identification response cycle NID 5 5 Clock cycles
Access time delay cycle NAC 2 TAAC + NSAC Clock cycles
Command read cycle NRC 8 – Clock cycles
Command-command cycle NCC 8 – Clock cycles
Command write cycle NWR 2 – Clock cycles
Stop transmission cycle NST 2 2 Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]
Interrupt Period IRQ IRQ
DAT[1]
For 4-bit
L H
Interrupt Period
DAT[1]
For 1-bit
CMD Content
S T E Z Z P E Z Z ****** Z Z
Response
CRC S Z Z
ES Block Data ES Block Data
68 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 54. SDIO ReadWait Timing Diagram
3.15 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
DAT[1]
For 4-bit
DAT[2]
For 4-bit
CMD ****** P S T E Z Z ******
CMD52 Z
CRC
E Z ZS Block Data L L L L L L L L L L L L L L L L L L L L L H Z S
ES Block Data
E
Block Data
Z Z L H ES Block Data
Specifications
MOTOROLA MC9328MX1 Advance Information 69
Figure 55. MSHC Signal Timing Diagram
Table 32. MSHC Signal Timing Parameter Table
Ref No. Parameter Minimum Maximum Unit
1 MS_SCLKI frequency – 25 MHz
2 MS_SCLKI high pulse width 20 – ns
3 MS_SCLKI low pulse width 20 – ns
4 MS_SCLKI rise time – 3 ns
5 MS_SCLKI fall time – 3 ns
6 MS_SCLKO frequency1–25MHz
7 MS_SCLKO high pulse width120 – ns
8 MS_SCLKO low pulse width115 – ns
9 MS_SCLKO rise time1–5ns
10 MS_SCLKO fall time1–5ns
11 MS_BS delay time1–3ns
MS_SCLKO
11
MS_BS
MS_SDIO (output)
MS_SDIO (input)
MS_SDIO (input)
11
12 12
13 14
15 16
(RED bit = 0)
(RED bit = 1)
MS_SCLKI
1
6
23
78
4 5
910
70 MC9328MX1 Advance Information MOTOROLA
Specifications
3.16 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin.
Figure 56. PWM Output Timing Diagram
12 MS_SDIO output delay time1,2 –3ns
13 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)318 – ns
14 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)30–ns
15 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit =
1)4
23 – ns
16 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)40–ns
1. Loading capacitor condition is less than or equal to 30pF.
2. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the
MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick
SDIO pin when the pin direction changes.
3. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
4. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
Table 33. PWM Output Timing Parameter Table
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
1 System CLK frequency1 0870100MHz
2a Clock high time1 3.3 – 5/10 – ns
2b Clock low time1 7.5 – 5/10 – ns
3a Clock fall time1–5–5/10ns
3b Clock rise time1–6.67–5/10ns
Table 32. MSHC Signal Timing Parameter Table (Continued)
Ref No. Parameter Minimum Maximum Unit
System Clock
2a 1
PWM Output
3b
2b
3a 4b
4a
Specifications
MOTOROLA MC9328MX1 Advance Information 71
3.17 SDRAM Memory Controller
A write to an address within the memory region initiates the program sequence. The first command issued
to the SyncFlash is Load Command Register. A [7:0] determine which operation the command performs.
For this write setup operation, an address of 0x40 is hardware generated. The bank and other address lines
are driven with the address to be programmed. The next command is Active which registers the row
address and confirms the bank address. The third command supplies the column address, re-confirms the
bank address, and supplies the data to be written. SyncFlash does not support burst writes, therefore a
Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash
is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register
operation. The bank and other address lines are driven to the selected address. The second command is
Active which sets up the status register read. The bank and row addresses are driven during this command.
The third command of the triplet is Read. Bank and column addresses are driven on the address bus during
this command. Data is returned from memory on the low order 8 data bits following the CAS latency.
4a Output delay time15.7 – 5 – ns
4b Output setup time15.7 – 5 – ns
1. CL of PWMO = 30 pF
Table 33. PWM Output Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
72 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 57. SDRAM/SyncFlash Read Cycle Timing Diagram
Table 34. SDRAM Timing Parameter Table
Ref
No. Parameter
1.8V 3.3V
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width 2.67 – 4 – ns
2 SDRAM clock low-level width 6–4–ns
3 SDRAM clock cycle time 10.4 – 10 – ns
3S CS, RAS, CAS, WE, DQM setup time 3.42 – 3 – ns
3H CS, RAS, CAS, WE, DQM hold time 2.28 – 2 – ns
4S Address setup time 3.42 – 3 – ns
SDCLK
WE
ADDR
DQ
DQM
ROW/BA COL/BA
3S
3H
3S
3H
3S
3S
3H
3H
3H
4S 4H
5
3S
3
2
1
8
Data
7
6
CS
CAS
RAS
Note: CKE is high during the read/write cycle.
Specifications
MOTOROLA MC9328MX1 Advance Information 73
4H Address hold time 2.28 – 2 – ns
5 SDRAM access time (CL = 3) – 6.84 – 6 ns
5 SDRAM access time (CL = 2) – 6.84 – 6 ns
5 SDRAM access time (CL = 1) – 22 – 22 ns
6 Data out hold time 2.85 – 2.5 – ns
7 Data out high-impedance time (CL = 3) – 6.84 – 6 ns
7 Data out high-impedance time (CL = 2) – 6.84 – 6 ns
7 Data out high-impedance time (CL = 1) – 22 – 22 ns
8 Active to read/write command period (RC = 1) tRCD1–tRCD1–ns
1. tRCD = SDRAM clock cycle time. The tRCD setting can be found in the MC9328MX1 reference manual.
Table 34. SDRAM Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V 3.3V
Unit
Minimum Maximum Minimum Maximum
74 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 58. SDRAM/SyncFlash Write Cycle Timing Diagram
Table 35. SDRAM Write Timing Parameter Table
Ref
No. Parameter
1.8V 3.3V
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width 2.67 – 4 – ns
2 SDRAM clock low-level width 6–4–ns
3 SDRAM clock cycle time 10.4 – 10 – ns
4 Address setup time 3.42 – 3 – ns
5 Address hold time 2.28 – 2 – ns
6 Precharge cycle period1tRP2–tRP2–ns
7 Active to read/write command delay tRCD2–tRCD2–ns
8 Data setup time 4.0 – 2 – ns
SDCLK
CS
CAS
WE
RAS
ADDR
DQ
DQM
/ BA ROW/BA
3
4
6
1
COL/BA
DATA
2
5 7
89
Specifications
MOTOROLA MC9328MX1 Advance Information 75
Figure 59. SDRAM Refresh Timing Diagram
9 Data hold time 2.28 – 2 – ns
1. Precharge cycle timing is included in the write timing diagram.
2. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference
manual.
Table 36. SDRAM Refresh Timing Parameter Table
Ref
No. Parameter
1.8V 3.3V
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width 2.67 – 4 – ns
2 SDRAM clock low-level width 6–4–ns
3 SDRAM clock cycle time 10.4 – 10 – ns
Table 35. SDRAM Write Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V 3.3V
Unit
Minimum Maximum Minimum Maximum
SDCLK
CS
CAS
WE
RAS
ADDR
DQ
DQM
BA
3
4
6
1 2
5
7
ROW/BA
7
76 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 60. SDRAM Self-Refresh Cycle Timing Diagram
4 Address setup time 3.42 – 3 – ns
5 Address hold time 2.28 – 2 – ns
6 Precharge cycle period tRP1–tRP1–ns
7 Auto precharge command period tRC1–tRC1–ns
1. tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference
manual.
Table 36. SDRAM Refresh Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V 3.3V
Unit
Minimum Maximum Minimum Maximum
SDCLK
CS
CAS
RAS
ADDR
DQ
DQM
BA
WE
CKE
Specifications
MOTOROLA MC9328MX1 Advance Information 77
3.18 USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous
transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is
identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section
covers the transfer modes and how they work from the ground up.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same
packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved
in the form of packets, however, because isochronous pipes are given a fixed portion of the USB
bandwidth at all times, there is no end-of-transfer.
Figure 61. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)
Table 37. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
Ref No. Parameter Minimum Maximum Unit
1t
ROE_VPO; USBD_ROE active to USBD_VPO low 83.14 83.47 ns
2t
ROE_VMO; USBD_ROE active to USBD_VMO high 81.55 81.98 ns
3t
VPO_ROE; USBD_VPO high to USBD_ROE deactivated 83.54 83.80 ns
4t
VMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes
SE0)
248.90 249.13 ns
5t
FEOPT; SE0 interval of EOP 160.00 175.00 ns
6t
PERIOD; Data transfer rate 11.97 12.03 Mb/s
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
(Output)
USBD_RCV
(Input)
USBD_VP
(Input)
USBD_VM
(Input)
t ROE_VPO t VMO_ROE
tVPO_ROE
tFEOPT
tROE_VMO
tPERIOD
1
2
3
4
5
6
78 MC9328MX1 Advance Information MOTOROLA
Specifications
Figure 62. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
Table 38. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
Ref
No. Parameter Minimum Maximum Unit
1t
FEOPR; Receiver SE0 interval of EOP 82 – ns
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
USBD_VMO
(Output)
(Output)
USBD_SUSPND
(Input)
USBD_VP
USBD_RCV
(Input)
USBD_VM
(Input)
tFEOPR
1
Specifications
MOTOROLA MC9328MX1 Advance Information 79
3.19 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 63. Definition of Bus Timing for I2C
3.20 Synchronous Serial Interface
The MC9328MX1 processor contains two identical SSI modules. The transmit and receive sections of the
SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a
common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each
have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected.
In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during
transmission. The internal and external clock timing diagrams are shown in Figure 65 through Figure 67
on page 81.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
Table 39. I2C Bus Timing Parameter Table
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
1 Hold time (repeated) START condition 182 – 160 – ns
2 Data hold time 01710150ns
3 Data setup time 11.4 – 10 – ns
4 HIGH period of the SCL clock 80 – 120 – ns
5 LOW period of the SCL clock 480 – 320 – ns
6 Setup time for STOP condition 182.4 – 160 – ns
SDA
SCL
12
34
6
5
80 MC9328MX1 Advance Information MOTOROLA
Specifications
Note: SRXD input in synchronous mode only.
Figure 64. SSI Transmitter Internal Clock Timing Diagram
Figure 65. SSI Receiver Internal Clock Timing Diagram
STCK Output
STFS (bl) Output
STFS (wl) Output
1
2
68
10 11
STXD Output
SRXD Input
32
31
4
12
SRCK Output
SRFS (bl) Output
SRFS (wl) Output
3
7
SRXD Input
13
14
1
5
9
Specifications
MOTOROLA MC9328MX1 Advance Information 81
Figure 66. SSI Transmitter External Clock Timing Diagram
Figure 67. SSI Receiver External Clock Timing Diagram
Table 40. SSI 1 Timing Parameter Table
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation1 (Port C Primary Function)2
1 STCK/SRCK clock period1 95 – 83.3 – ns
2 STCK high to STFS (bl) high3 1.5 4.5 1.3 3.9 ns
3 SRCK high to SRFS (bl) high3 -1.2 -1.7 -1.1 -1.5 ns
STCK Input
16
STFS (bl) Input
STFS (wl) Input
17
18
22 24
26
STXD Output
SRXD Input
27
28
34
Note: SRXD Input in Synchronous mode only.
33
20
15
SRCK Input
16
SRFS (bl) Input
SRFS (wl) Input
17
19
23
SRXD Input
29 30
21
25
15
82 MC9328MX1 Advance Information MOTOROLA
Specifications
4 STCK high to STFS (bl) low3 2.5 4.3 2.2 3.8 ns
5 SRCK high to SRFS (bl) low3 0.1 -0.8 0.1 -0.8 ns
6 STCK high to STFS (wl) high3 1.48 4.45 1.3 3.9 ns
7 SRCK high to SRFS (wl) high3 -1.1 -1.5 -1.1 -1.5 ns
8 STCK high to STFS (wl) low3 2.51 4.33 2.2 3.8 ns
9 SRCK high to SRFS (wl) low3 0.1 -0.8 0.1 -0.8 ns
10 STCK high to STXD valid from high
impedance
14.25 15.73 12.5 13.8 ns
11a STCK high to STXD high 0.91 3.08 0.8 2.7 ns
11b STCK high to STXD low 0.57 3.19 0.5 2.8 ns
12 STCK high to STXD high impedance 12.88 13.57 11.3 11.9 ns
13 SRXD setup time before SRCK low 21.1 – 18.5 – ns
14 SRXD hold time after SRCK low 0 – 0 – ns
External Clock Operation (Port C Primary Function)2
15 STCK/SRCK clock period1 92.8 – 81.4 – ns
16 STCK/SRCK clock high period 27.1 – 40.7 – ns
17 STCK/SRCK clock low period 61.1 – 40.7 – ns
18 STCK high to STFS (bl) high3– 92.8 0 81.4 ns
19 SRCK high to SRFS (bl) high3– 92.8 0 81.4 ns
20 STCK high to STFS (bl) low3– 92.8 0 81.4 ns
21 SRCK high to SRFS (bl) low3– 92.8 0 81.4 ns
22 STCK high to STFS (wl) high3– 92.8 0 81.4 ns
23 SRCK high to SRFS (wl) high3– 92.8 0 81.4 ns
24 STCK high to STFS (wl) low3– 92.8 0 81.4 ns
25 SRCK high to SRFS (wl) low3– 92.8 0 81.4 ns
26 STCK high to STXD valid from high
impedance
18.01 28.16 15.8 24.7 ns
27a STCK high to STXD high 8.98 18.13 7.0 15.9 ns
27b STCK high to STXD low 9.12 18.24 8.0 16.0 ns
Table 40. SSI 1 Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
Specifications
MOTOROLA MC9328MX1 Advance Information 83
28 STCK high to STXD high impedance 18.47 28.5 16.2 25.0 ns
29 SRXD setup time before SRCK low 1.14 – 1.0 – ns
30 SRXD hole time after SRCK low 0 – 0 – ns
Synchronous Internal Clock Operation (Port C Primary Function)2
31 SRXD setup before STCK falling 15.4 – 13.5 – ns
32 SRXD hold after STCK falling 0 – 0 – ns
Synchronous External Clock Operation (Port C Primary Function)2
33 SRXD setup before STCK falling 1.14 – 1.0 – ns
34 SRXD hold after STCK falling 0 – 0 – ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (PC3 – PC8)
and Port B alternate function (PB14 – PB19). When SSI signals are configured as outputs, they can be
viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as
input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.
3. bl = bit length; wl = word length.
Table 41. SSI 2 Timing Parameter Table
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation1 (Port B Alternate Function)2
1 STCK/SRCK clock period1 95 – 83.3 – ns
2 STCK high to STFS (bl) high31.7 4.8 1.5 4.2 ns
3 SRCK high to SRFS (bl) high3 -0.1 1.0 -0.1 1.0 ns
4 STCK high to STFS (bl) low3 3.08 5.24 2.7 4.6 ns
5 SRCK high to SRFS (bl) low3 1.25 2.28 1.1 2.0 ns
6 STCK high to STFS (wl) high31.71 4.79 1.5 4.2 ns
7 SRCK high to SRFS (wl) high3-0.1 1.0 -0.1 1.0 ns
8 STCK high to STFS (wl) low3 3.08 5.24 2.7 4.6 ns
Table 40. SSI 1 Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
84 MC9328MX1 Advance Information MOTOROLA
Specifications
9 SRCK high to SRFS (wl) low31.25 2.28 1.1 2.0 ns
10 STCK high to STXD valid from high
impedance
14.93 16.19 13.1 14.2 ns
11a STCK high to STXD high 1.25 3.42 1.1 3.0 ns
11b STCK high to STXD low 2.51 3.99 2.2 3.5 ns
12 STCK high to STXD high impedance 12.43 14.59 10.9 12.8 ns
13 SRXD setup time before SRCK low 20 – 17.5 – ns
14 SRXD hold time after SRCK low 0 – 0 – ns
External Clock Operation (Port B Alternate Function)2
15 STCK/SRCK clock period1 92.8–81.4–ns
16 STCK/SRCK clock high period 27.1 – 40.7 – ns
17 STCK/SRCK clock low period 61.1 – 40.7 – ns
18 STCK high to STFS (bl) high3–92.8081.4ns
19 SRCK high to SRFS (bl) high3–92.8081.4ns
20 STCK high to STFS (bl) low3–92.8081.4ns
21 SRCK high to SRFS (bl) low3–92.8081.4ns
22 STCK high to STFS (wl) high3–92.8081.4ns
23 SRCK high to SRFS (wl) high3–92.8081.4ns
24 STCK high to STFS (wl) low3–92.8081.4ns
25 SRCK high to SRFS (wl) low3–92.8081.4ns
26 STCK high to STXD valid from high
impedance
18.9 29.07 16.6 25.5 ns
27a STCK high to STXD high 9.23 20.75 8.1 18.2 ns
27b STCK high to STXD low 10.60 21.32 9.3 18.7 ns
28 STCK high to STXD high impedance 17.90 29.75 15.7 26.1 ns
29 SRXD setup time before SRCK low 1.14 – 1.0 – ns
30 SRXD hole time after SRCK low 0 – 0 – ns
Table 41. SSI 2 Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
MOTOROLA MC9328MX1 Advance Information 85
NOTES
Synchronous Internal Clock Operation (Port B Alternate Function)2
31 SRXD setup before STCK falling 18.81 – 16.5 – ns
32 SRXD hold after STCK falling 0 – 0 – ns
Synchronous External Clock Operation (Port B Alternate Function)2
33 SRXD setup before STCK falling 1.14 – 1.0 – ns
34 SRXD hold after STCK falling 0 – 0 – ns
1. All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP =
0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2. There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 –
PC24). When SSI signals are configured as outputs, they can be viewed at Port C alternate function a.
When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits
in the Clock controller module (CRM). By default, the input is selected from Port C alternate function.
3. bl = bit length; wl = word length
Table 41. SSI 2 Timing Parameter Table (Continued)
Ref
No. Parameter
1.8V +/- 0.10V 3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
86 MC9328MX1 Advance Information MOTOROLA
Specifications
3.21 CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for
statistic data generation, a status register, interface logic, a 32 ×32 image data receive FIFO, and a 16 ×32
statistic data FIFO.
3.21.1 Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 69 on page 87 shows the timing
diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to
received data in negative edge. The parameters for the timing diagrams are listed in Table 42 on page 87.
Figure 68. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
3
65
VSYNC
HSYNC
PIXCLK
DATA[7:0] Valid Data Valid Data Valid Data
4
7
2
Specifications
MOTOROLA MC9328MX1 Advance Information 87
Figure 69. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
Table 42. Gated Clock Mode Timing Parameters
Ref No. Parameter Minimum Maximum Unit
1 csi_vsync to csi_hsync 9 * THCLK –ns
2 csi_hsync to csi_pixclk 3 (Tp / 2) - 3 ns
3 csi_d setup time 1 – ns
4 csi_d hold time 1 – ns
5 csi_pixclk high time 10.42 – ns
6 csi_pixclk low time 10.42 – ns
7 csi_pixclk frequency 0 48 MHz
1
3
65
VSYNC
HSYNC
PIXCLK
DATA[7:0] Valid Data Valid Data Valid Data
4
7
2
88 MC9328MX1 Advance Information MOTOROLA
Specifications
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
3.21.2 Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 71 on page 89 shows the timing
diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to
received data in negative edge. The parameters for the timing diagrams are listed in Table 43 on page 89.
Figure 70. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
PIXCLK
DATA[7:0]
23
6
45
Valid Data Valid Data Valid Data
Specifications
MOTOROLA MC9328MX1 Advance Information 89
Figure 71. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Table 43. Non-Gated Clock Mode Parameters
Ref No. Parameter Minimum Maximum Unit
1 csi_vsync to csi_pixclk 9 * THCLK –ns
2 csi_d setup time 1 – ns
3 csi_d hold time 1 – ns
4 csi_pixclk high time 10.42 – ns
5 csi_pixclk low time 10.42 – ns
6 csi_pixclk frequency 0 48 MHz
1
VSYNC
PIXCLK
DATA[7:0]
23
6
54
Valid Data Valid Data Valid Data
90 MC9328MX1 Advance Information MOTOROLA
Specifications
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
Pin-Out and Package Information
MOTOROLA MC9328MX1 Advance Information 91
4 Pin-Out and Package Information
Table 44. MC9328MX1 BGA Pin Assignments
12 3 4 5 6 7 8 910111213141516
AVS
S
SD_D
AT3
SD_C
LK
VSS USBD_
AFE
NVDD
4
VSS UART
1_RT
S
UART
1_RX
D
NVDD
3
BT5 BT3 QVDD
4
RVP UIP NC
BA2
4
SD_D
AT1
SD_C
MD
SIM_T
X
USBD_
OE
USBD
_VP
SSI_R
XCLK
SSI_T
XCLK
SPI1_
SCLK
BT11 BT7 BT1 VSS RVM UIN NC
CA2
3
D31 SD_D
AT0
SIM_P
D
USBD_
RCV
UART
2_CT
S
UART
2_RX
D
SSI_R
XFS
UART
1_TX
D
BTRF
GND
BT8 BTRFV
DD
NC AVDD
2
VSS R1B
DA2
2
D30 D29 SIM_S
VEN
USBD_
SUSPN
D
USBD
_VPO
USBD
_VMO
SSI_R
XDAT
SPI1_
SPI_R
DY
BT13 BT6 NC NC NC R1A R2B
EA2
0
A21 D28 D26 SD_DA
T2
USBD
_VM
UART
2_RT
S
SSI_T
XDAT
SPI1_
SS
BT12 BT4 NC NC PY2 PX2 R2A
FA1
8
D27 D25 A19 A16 SIM_R
ST
UART
2_TX
D
SSI_T
XFS
SPI1_
MISO
BT10 BT2 REV PY1 PX1 LSCLK SPL_
SPR
GA1
5
A17 D24 D23 D21 SIM_R
X
SIM_C
LK
UART
1_CT
S
SPI1_
MOSI
BT9 CLS CONTR
AST
ACD/
OE
LP/
HSYN
C
FLM/
VSYNC
LD1
HA1
3
D22 A14 D20 NVDD1 NVDD
1
VSS VSS QVDD
1
PS LD0 LD2 LD4 LD5 LD9 LD3
JA1
2
A11 D18 D19 NVDD1 NVDD
1
VSS NVDD
1
VSS VSS LD6 LD7 LD8 LD11 QVDD3 VSS
KA1
0
D16 A9 D17 NVDD1 VSS VSS NVDD
1
NVDD
2
NVDD
2
LD10 LD12 LD13 LD14 TMR2O
UT
LD15
92 MC9328MX1 Advance Information MOTOROLA
LA8 A7 D13 D15 D14 NVDD
1
VSS CAS TCK TIN PWM
O
CSI_M
CLK
CSI_D
0
CSI_D
1
CSI_D2 CSI_D
3
MA5 D12 D11 A6 SDCLK VSS RW MA10 RAS RESE
T_IN
BIG_E
NDIA
N
CSI_D4 CSI_H
SYNC
CSI_V
SYNC
CSI_D6 CSI_D
5
NA4 EB1 D10 D7 A0 D4 PA17 D1 DQM1 RESE
T_SF
RESE
T_OU
T
BOOT2 CSI_P
IXCLK
CSI_D
7
TMS TDI
PA3 D9 EB0 CS3 D6 ECB D2 D3 DQM3 SDCK
E1
BOOT
3
BOOT0 TRST I2C_S
CL
I2C_SD
A
XTAL
32K
REB
2
EB3 A1 CS4 D8 D5 LBA BCLK D0 DQM0 SDCK
E0
POR BOOT
1
TDO QVDD2 EXTA
L32K
TVS
S
A2 OE CS5 CS2 CS1 CS0 MA11 DQM2 SDWE CLKO AVDD1 TRIST
ATE
EXTA
L16M
XTAL16
M
VSS
Table 44. MC9328MX1 BGA Pin Assignments (Continued)
12 3 4 5 6 7 8 910111213141516
Pin-Out and Package Information
MOTOROLA MC9328MX1 Advance Information 93
4.1 MAPBGA Package Dimensions
Figure 72 illustrates the MAPBGA 14 mm × 14 mm × 1.30 mm package, which has 0.8 mm spacing
between the pads. The device designator for the MAPBGA package is VH.
Figure 72. MC9328MX1 MAPBGA Mechanical Drawing
MC9328MX1/D
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