© Semiconductor Components Industries, LLC, 2016
September, 2019 − Rev. 24
1Publication Order Number:
MC34063A/D
MC34063A, MC33063A,
SC34063A, SC33063A,
NCV33063A
Inverting Regulator - Buck,
Boost, Switching
1.5 A
The MC34063A Series is a monolithic control circuit containing the
primary functions required for DC−to−DC converters. These devices
consist of an internal temperature compensated reference, comparator,
controlled duty cycle oscillator with an active current limit circuit,
driver and high current output switch. This series was specifically
designed to be incorporated in Step−Down and Step−Up and
Voltage−Inverting applications with a minimum number of external
components. Refer to Application Notes AN920A/D and AN954/D
for additional design information.
Features
•Operation from 3.0 V to 40 V Input
•Low Standby Current
•Current Limiting
•Output Switch Current to 1.5 A
•Output Voltage Adjustable
•Frequency Operation to 100 kHz
•Precision 2% Reference
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Figure 1. Representative Schematic Diagram
SQ
R
Q2
Q1
100
Ipk
Oscillator CT
Comparator
+
-
1.25 V
Reference
Regulator
1
2
3
45
6
7
8
Drive
Collector
Ipk
Sense
VCC
Comparator
Inverting
Input
Switch
Collector
Switch
Emitter
Timing
Capacitor
GND
(Bottom View)
This device contains 79 active transistors.
SOIC−8
D SUFFIX
CASE 751
PDIP−8
P, P1 SUFFIX
CASE 626
1
8
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING INFORMATION
www.onsemi.com
x = 3 or 4
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G= Pb−Free Package
1
8
3x063AP1
AWL
YYWWG
1
8
33063AVP
AWL
YYWWG
MARKING
DIAGRAMS
1
8
3x063
ALYWA
G
1
8
3x063V
ALYWA
G
1
8
1
DFN8
CASE 488AF
33063
ALYWA
G
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
2
1
Switch
Collector
Switch
Emitter
Timing
Capacitor
GND
Driver
Collector
Ipk Sense
VCC
Comparator
Inverting
Input
(Top View)
2
3
45
6
7
8
Figure 2. Pin Connections
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
(Top View)
EP Flag
Switch Collector
Switch Emitter
Timing Capacitor
GND
Ipk Sense
Driver Collector
Comparator
Inverting Input
VCC
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 40 Vdc
Comparator Input Voltage Range VIR −0.3 to +40 Vdc
Switch Collector Voltage VC(switch) 40 Vdc
Switch Emitter Voltage (VPin 1 = 40 V) VE(switch) 40 Vdc
Switch Collector to Emitter Voltage VCE(switch) 40 Vdc
Driver Collector Voltage VC(driver) 40 Vdc
Driver Collector Current (Note 1) IC(driver) 100 mA
Switch Current ISW 1.5 A
Power Dissipation and Thermal Characteristics
Plastic Package, P, P1 Suffix
TA = 25°C PD1.25 W
Thermal Resistance RqJA 115 °C/W
SOIC Package, D Suffix
TA = 25°C PD625 mW
Thermal Resistance RqJA 160 °C/W
Thermal Resistance RqJC 45 °C/W
DFN Package
TA = 25°C PD1.25 mW
Thermal Resistance RqJA 80 °C/W
Operating Junction Temperature TJ+150 °C
Operating Ambient Temperature Range TA°C
MC34063A, SC34063A 0 to +70
MC33063AV, NCV33063A −40 to +125
MC33063A, SC33063A −40 to + 85
Storage Temperature Range Tstg −65 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum package power dissipation limits must be observed.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per MIL−STD−883, Method 3015.
Machine Model Method 400 V.
3. NCV prefix is for automotive and other applications requiring site and change control.
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
3
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = Tlow to Thigh [Note 4], unless otherwise specified.)
Characteristics Symbol Min Typ Max Unit
OSCILLATOR
Frequency (VPin 5 = 0 V, CT = 1.0 nF, TA = 25°C) fosc 24 33 42 kHz
Charge Current (VCC = 5.0 V to 40 V, TA = 25°C) Ichg 24 35 42 mA
Discharge Current (VCC = 5.0 V to 40 V, TA = 25°C) Idischg 140 220 260 mA
Discharge to Charge Current Ratio (Pin 7 to VCC, TA = 25°C) Idischg/Ichg 5.2 6.5 7.5 −
Current Limit Sense Voltage (Ichg = Idischg, TA = 25°C) Vipk(sense) 250 300 350 mV
OUTPUT SWITCH (Note 5)
Saturation Voltage, Darlington Connection
(I
SW = 1.0 A, Pins 1, 8 connected)
VCE(sat) −1.0 1.3 V
Saturation Voltage (Note 6)
(ISW = 1.0 A, RPin 8 = 82 W to VCC, Forced b ] 20)
VCE(sat) −0.45 0.7 V
DC Current Gain (ISW = 1.0 A, VCE = 5.0 V, TA = 25°C) hFE 50 75 − −
Collector Off−State Current (VCE = 40 V) IC(off) −0.01 100 mA
COMPARATOR
Threshold Voltage
TA = 25°C
TA = Tlow to Thigh
Vth
1.225
1.21
1.25
−
1.275
1.29
V
Threshold Voltage Line Regulation (VCC = 3.0 V to 40 V)
MC33063, MC34063
MC33063V, NCV33063
Regline
−
−
1.4
1.4
5.0
6.0
mV
Input Bias Current (Vin = 0 V) IIB − −20 −400 nA
TOTAL DEVICE
Supply Current (VCC = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = VCC,
VPin 5 > Vth, Pin 2 = GND, remaining pins open)
ICC − − 4.0 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Tlow = 0°C for MC34063, SC34063; −40°C for MC33063, SC33063, MC33063V, NCV33063
Thigh = +70°C for MC34063, SC34063; +85°C for MC33063, SC33063; +125°C for MC33063V, NCV33063
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
6. If the output switch is driven into hard saturation (non−Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents
(≥30 mA), it may take up to 2.0 ms for it to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is
magnified at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a
non−Darlington configuration is used, the following output drive condition is recommended:
Forced bof output switch : ICoutput
ICdriver – 7.0 mA * w10
* The 100 W resistor in the emitter of the driver device requires about 7.0 mA before the output switch conducts.
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
4
0
2
4
6
8
10
12
14
16
18
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
20
40
60
80
100
120
140
160
180
Figure 3. Oscillator Frequency
VCC = 5.0 V, Pin 7 = VCC
Pin 5 = GND, TA = 25°C
Ct, TIMING CAPACITOR CAPACITANCE (nF)
OFF TIME (ms)
ON TIME (ms), FREQUENCY (kHz)
ON TIME (ms)
OFF TIME (ms)
FREQUENCY (kHz)
VCC = 5.0 V
Pin 7 = VCC
Pin 2 = GND
Pins 1, 5, 8 = Open
CT = 1.0 nF
TA = 25°C
Figure 4. Timing Capacitor Waveform
10 ms/DIV
, OSCILLATOR VOLTAGE (V)
OSC
200 mV/DIV
V
Figure 5. Emitter Follower Configuration Output
Saturation Voltage versus Emitter Current
Figure 6. Common Emitter Configuration Output
Switch Saturation Voltage versus
Collector Current
Figure 7. Current Limit Sense Voltage
versus Temperature
Figure 8. Standby Supply Current versus
Supply Voltage
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
, SATURATION VOLTAGE (V)
CE(sat)
IE, EMITTER CURRENT (A)
V
VCC = 5.0 V
Pins 1, 7, 8 = VCC
Pins 3, 5 = GND
TA = 25°C
(See Note 7)
, SATURATION VOLTAGE (V)
CE(sat)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
IC, COLLECTOR CURRENT(A)
V
Darlington Connection
Forced b = 20
-55 -25 0 25 50 75 100 125
, CURRENT LIMIT SENSE VOLTAGE (V)
IPK(sense)
TA, AMBIENT TEMPERATURE (°C)
V
VCC = 5.0 V
Ichg = Idischg
0 5.0 10 15 20 25 30 35 40
, SUPPLY CURRENT (mA)
CC
VCC, SUPPLY VOLTAGE (V)
I
CT = 1.0 nF
Pin 7 = VCC
Pin 2 = GND
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
380
360
340
320
300
280
260
240
220
200
3.6
3.2
2.4
2.0
1.6
1.2
0.8
0.4
0
1.0
2.8
VCC = 5.0 V
Pin 7 = VCC
Pins 2, 3, 5 = GND
TA = 25°C
(See Note 7)
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
5
170 mH
L
8
180
7
Rsc
0.22
6
Vin
12 V
100
+
5
R1 2.2 k
R2
47 k
SQ
R
Q2
Q1
Ipk
OSC
CT
VCC
+
-Comp.
1.25 V
Ref
Reg
1
2
3
4
1N5819
CT
1500
pF
330 CO
+
Vout
28 V/175 mA Vout
1.0 mH
+100
Optional Filter
Test Conditions Results
Line Regulation Vin = 8.0 V to 16 V, IO = 175 mA 30 mV = ±0.05%
Load Regulation Vin = 12 V, IO = 75 mA to 175 mA 10 mV = ±0.017%
Output Ripple Vin = 12 V, IO = 175 mA 400 mVpp
Efficiency Vin = 12 V, IO = 175 mA 87.7%
Output Ripple With Optional Filter Vin = 12 V, IO = 175 mA 40 mVpp
Figure 9. Step−Up Converter
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
6
9a. External NPN Switch 9b. External NPN Saturated Switch
(See Note 8)
8
7
6
Rsc
Vin
1
2
Vout R
R ³ 0 for
constant Vin
8. If the output switch is driven into hard saturation (non−Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents
(≥30 mA), it may take up to 2.0 ms to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is magnified
at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a
non−Darlington configuration is used, the following output drive condition is recommended.
8
7
6
Rsc
Vin
1
2
Vout
Figure 10. External Current Boost Connections for IC Peak Greater than 1.5 A
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
7
1.25 V
Ref
Reg
Vout
5.0 V/500 mA
1.0 mH
Vout
+100
Optional Filter
8
7
Rsc
0.33
6
Vin
25 V
100 +
R1 1.2 k
R2
3.6 k
SQ
R
Q2
Q1
Ipk
OSC CT
VCC
+
-Comp.
1
2
3
4
CT
470
pF
470 CO
+
5
L
1N5819
220 mH
Test Conditions Results
Line Regulation Vin = 15 V to 25 V, IO = 500 mA 12 mV = ±0.12%
Load Regulation Vin = 25 V, IO = 50 mA to 500 mA 3.0 mV = ±0.03%
Output Ripple Vin = 25 V, IO = 500 mA 120 mVpp
Short Circuit Current Vin = 25 V, RL = 0.1 W1.1 A
Efficiency Vin = 25 V, IO = 500 mA 83.7%
Output Ripple With Optional Filter Vin = 25 V, IO = 500 mA 40 mVpp
Figure 11. Step−Down Converter
11a. External NPN Switch 11b. External PNP Saturated Switch
8
7
6
Rsc
Vin
1
2
Vout
8
7
6
Rsc
Vin
1
2
V
Figure 12. External Current Boost Connections for IC Peak Greater than 1.5 A
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
8
1.25 V
Ref
Reg
Vout
-12 V/100 mA Vout
1.0 mH
+100
Optional Filter
8
7
Rsc
0.24
6
Vin
4.5 V to 6.0 V
100
+
5
R2 8.2 k
SQ
R
Q2
Q1
Ipk
OSC CT
Comp.
R1
953
1
2
3
4
+1500
pF
+
-
1N5819
1000 mf+
88 mH
VCC
CO
L
Test Conditions Results
Line Regulation Vin = 4.5 V to 6.0 V, IO = 100 mA 3.0 mV = ±0.012%
Load Regulation Vin = 5.0 V, IO = 10 mA to 100 mA 0.022 V = ±0.09%
Output Ripple Vin = 5.0 V, IO = 100 mA 500 mVpp
Short Circuit Current Vin = 5.0 V, RL = 0.1 W910 mA
Efficiency Vin = 5.0 V, IO = 100 mA 62.2%
Output Ripple With Optional Filter Vin = 5.0 V, IO = 100 mA 70 mVpp
Figure 13. Voltage Inverting Converter
13a. External NPN Switch 13b. External PNP Saturated Switch
8
7
6
Vin
1
2
Vout
8
7
6
Vin
1
2
Vout
Figure 14. External Current Boost Connections for IC Peak Greater than 1.5 A
3
4
+
3
4
+
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
9
Figure 15. Printed Circuit Board and Component Layout
(Circuits of Figures 9, 11, 13)
INDUCTOR DATA
Converter Inductance (mH) Turns/Wire
Step−Up 170 38 Turns of #22 AWG
Step−Down 220 48 Turns of #22 AWG
Voltage−Inverting 88 28 Turns of #22 AWG
All inductors are wound on Magnetics Inc. 55117 toroidal core.
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
10
Figure 16. Printed Circuit Board for DFN Device
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
11
Calculation Step−Up Step−Down Voltage−Inverting
ton/toff Vout )VF*Vin(min)
Vin(min) *Vsat
Vout )VF
Vin(min) *Vsat *Vout
|Vout|)VF
Vin *Vsat
(ton + toff)1
f
1
f
1
f
toff ton )toff
ton
toff )1
ton )toff
ton
toff )1
ton )toff
ton
toff )1
ton (ton + toff) − toff (ton + toff) − toff (ton + toff) − toff
CT4.0 x 10−5 ton 4.0 x 10−5 ton 4.0 x 10−5 ton
Ipk(switch)
2Iout(max) ǒton
toff )1Ǔ2Iout(max) 2Iout(max) ǒton
toff )1Ǔ
Rsc 0.3/Ipk(switch) 0.3/Ipk(switch) 0.3/Ipk(switch)
L(min) ǒ(Vin(min) *Vsat)
Ipk(switch) Ǔton(max) ǒ(Vin(min) *Vsat *Vout)
Ipk(switch) Ǔton(max
)
ǒ(Vin(min) *Vsat)
Ipk(switch) Ǔton(max)
CO9Ioutton
Vripple(pp)
Ipk(switch)(ton )toff)
8Vripple(pp)
9Ioutton
Vripple(pp)
Vsat = Saturation voltage of the output switch.
VF = Forward voltage drop of the output rectifier.
The following power supply characteristics must be chosen:
Vin − Nominal input voltage.
Vout − Desired output voltage,
Iout − Desired output current.
fmin − Minimum desired output switching frequency at the selected values of Vin and IO.
Vripple(pp) − Desired peak−to−peak output ripple voltage. In practice, the calculated capacitor value will need to be increased due to its
equivalent series resistance and board layout. The ripple voltage should be kept to a low value since it will directly affect the
line and load regulation.
NOTE: For further information refer to Application Note AN920A/D and AN954/D.
|Vout|+1.25 ǒ1)R2
R1Ǔ
Figure 17. Design Formula Table
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
www.onsemi.com
12
ORDERING INFORMATION
Device Package Shipping†
MC33063ADG SOIC−8
(Pb−Free)
98 Units / Rail
MC33063ADR2G SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
SC33063ADR2G SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC33063AP1G PDIP−8
(Pb−Free)
50 Units / Rail
MC33063AVDG SOIC−8
(Pb−Free)
98 Units / Rail
MC33063AVDR2G SOIC−8
(Pb−Free)
NCV33063AVDR2G* SOIC−8
(Pb−Free) 2500 Units / Tape & Reel
MC33063AVPG PDIP−8
(Pb−Free)
50 Units / Rail
MC34063ADG SOIC−8
(Pb−Free)
98 Units / Rail
MC34063ADR2G SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
SC34063ADR2G SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC34063AP1G PDIP−8
(Pb−Free)
50 Units / Rail
SC34063AP1G PDIP−8
(Pb−Free)
50 Units / Rail
MC33063MNTXG DFN8
(Pb−Free)
4000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NCV33063A: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and
change control.
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ÉÉ
ÉÉ
ÉÉ
DFN8, 4x4
CASE 488AF−01
ISSUE C
DATE 15 JAN 2009
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CON-
STRUCTIONS FOR TERMINALS.
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.25 0.35
D4.00 BSC
D2 1.91 2.21
E4.00 BSC
E2 2.09 2.39
e0.80 BSC
K0.20 −−−
L0.30 0.50
D
B
E
C0.15
A
C0.15
2X
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Ç
Ç
ÇÇ
ÇÇ
Ç
Ç
Ç
C
A
(A3)
A1
8X
SEATING
PLANE
C0.08
C0.10
Ç
ÇÇ
Ç
Ç
Ç
e
8X L
K
E2
D2
b
NOTE 3
14
58
8X
0.10 C
0.05 C
AB
1
SCALE 2:1
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
ALYWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
PIN ONE
REFERENCE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8X
0.63
2.21
2.39
8X
0.80
PITCH
4.30
0.35
(Note: Microdot may be in either location)
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÇÇÇ
A1
A3
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
L1 −−− 0.15
DETAIL B
NOTE 4
DETAIL A
DIMENSIONS: MILLIMETERS
PACKAGE
OUTLINE
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON15232D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
DFN8, 4X4, 0.8P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
14
58
b2
NOTE 8
D
b
L
A1
A
eB
XXXXXXXXX
AWL
YYWWG
E
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A−−−− 0.210
A1 0.015 −−−−
b0.014 0.022
C0.008 0.014
D0.355 0.400
D1 0.005 −−−−
e0.100 BSC
E0.300 0.325
M−−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L0.115 0.150 2.92 3.81
°°
H
NOTE 5
e
e/2 A2
NOTE 3
MBMNOTE 6
M
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42420B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
PDIP−8
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(Pb−Free)
XXXXX
ALYWX
G
1
8
IC
(Pb−Free)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊