CAT523WI-TE13 - Catalyst Semiconductor, Inc.

RDY/BSY

PROG PROGRAM

CONTROL

CLK SERIAL

CONTROL

SERIAL

DATA

OUTPUT

GND

VDD

12 OU

OUT1

6DO

REFH

REFL

28KΩ

WIPER

CONTROL

AND

NVRAM

Characteristics subject to change without notice

FEATURES

■ Two 8-bit DPPs configured as programmable

voltage sources in DAC-like applications

■ Common reference inputs

■Non-volatile NVRAM memory wiper storage

■Output voltage range includes both supply rails

■2 independently addressable buffered

output wipers

■1 LSB accuracy, high resolution

■Serial microwire-like interface

■Single supply operation: 2.7V - 5.5V

■Setting read-back without effecting outputs

APPLICATIONS

■Automated product calibration.

■Remote control adjustment of equipment

■Offset, gain and zero adjustments in self-

calibrating and adaptive control systems.

■Tamper-proof calibrations.

■DAC (with memory) substitute

DESCRIPTION

The CAT523 is a dual, 8-bit digitally-programmable

potentiometer (DPP™) configured for programmable

voltage and DAC-like applications. Intended for final

calibration of products such as camcorders, fax

machines and cellular telephones on automated high

volume production lines, it is also well suited for systems

capable of self calibration, and applications where

equipment which is either difficult to access or in a

hazardous environment, requires periodic adjustment.

The two independently programmable DPPs have a

common output voltage range which includes both

supply rails. The wipers are buffered by rail to rail op

amps. Wiper settings, stored in non-volatile NVRAM

memory, are not lost when the device is powered down

and are automatically reinstated when power is

returned. Each wiper can be dithered to test new output

values without effecting the stored settings and stored

settings can be read back without disturbing the

DPP’s output.

Control of the CAT523 is accomplished with a simple 3-

wire, Microwire-like serial interface. A Chip Select pin

allows several CAT523's to share a common serial

interface and communication back to the host controller

is via a single serial data line thanks to the CAT523’s Tri-

Stated Data Output pin. A RDY/BSY output working in

concert with an internal low voltage detector signals

proper operation of non-volatile NVRAM memory Erase/

Write cycle.

The CAT523 is available in the 0°C to 70°C Commercial

and -40°C to + 85°C Industrial operating temperature

ranges and offered in 14-pin plastic DIP and SOIC

mount packages.

FUNCTIONAL DIAGRAM PIN CONFIGURATION

CAT523

Configured Digitally Programmable Potentiometer (DPP™):

Programmable Voltage Applications

DIP Package (P, L) SOIC Package (J, W)

CAT523

Doc. No. 2005, Rev. D

RDY/BSY

CLK

PROG

VDD 2

114

GND

VREFH

VOUT1

VOUT2

VREFL

CLK

PROG

VDD 2

114

GND

VREFH

VOUT1

VOUT2

VREFL

CAT

523

CAT

523

RDY/BSY

NC NC

CAT523

Doc. No. 2005, Rev. D

ABSOLUTE MAXIMUM RATINGS

Supply Voltage*

VDD to GND -0.5V to +7V

Inputs

CLK to GND -0.5V to VDD +0.5V

CS to GND -0.5V to VDD +0.5V

DI to GND -0.5V to VDD +0.5V

RDY/BSY to GND -0.5V to VDD +0.5V

PROG to GND -0.5V to VDD +0.5V

VREFH to GND -0.5V to VDD +0.5V

VREFL to GND -0.5V to VDD +0.5V

Outputs

D0 to GND -0.5V to VDD +0.5V

VOUT 1– 4 to GND -0.5V to VDD +0.5V

Operating Ambient Temperature

Commercial (‘C’ or Blank suffix) 0°C to +70°C

Industrial (‘I’ suffix) -40°C to +85°C

Junction Temperature +150°C

Storage Temperature -65°C to +150°C

Lead Soldering (10 sec max) +300°C

* Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Absolute

Maximum Ratings are limited values applied individually while

other parameters are within specified operating conditions,

and functional operation at any of these conditions is NOT

implied. Device performance and reliability may be impaired by

exposure to absolute rating conditions for extended periods of

time.

RELIABILITY CHARACTERISTICS

Symbol Parameter Min Max Units Test Method

VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015

ILTH(1)(2) Latch-Up 100 mA JEDEC Standard 17

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.

Symbol Parameter Conditions Min Typ Max Units

IDD1 Supply Current (Read) Normal Operating — 400 600 µA

IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA

VDD = 3V — 1000 1600 µA

VDD Operating Voltage Range 2.7 — 5.5 V

Symbol Parameter Conditions Min Typ Max Units

VOH High Level Output Voltage IOH = -40µAV

DD -0.3 — — V

VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V

IOL = 0.4 mA, VDD = +3V — — 0.4 V

LOGIC INPUTS

Symbol Parameter Conditions Min Typ Max Units

IIH Input Leakage Current VIN = VDD ——10µA

IIL Input Leakage Current VIN = 0V — — -10 µA

VIH High Level Input Voltage 2 — VDD V

VIL Low Level Input Voltage 0 — 0.8 V

POWER SUPPLY

LOGIC OUTPUTS

CAT523

3Doc. No. 2005, Rev. D

Symbol Parameter Conditions Min Typ Max Units

tCSMIN Minimum CS Low Time 150 — — ns

tCSS CS Setup Time 100 — — ns

tCSH CS Hold Time 0 — — ns

tDIS DI Setup Time 50 — — ns

tDIH DI Hold Time 50 — — ns

tDO1 Output Delay to 1 — — 150 ns

tDO0 Output Delay to 0 — — 150 ns

tHZ Output Delay to High-Z — 400 — ns

tLZ Output Delay to Low-Z — 400 — ns

tBUSY Erase/Write Cycle Time — 4 5 ms

tPS PROG Setup Time 150 — — ns

tPROG Minimum Pulse Width 700 — — ns

tCLKHMinimum CLK High Time 500 — — ns

tCLKLMinimum CLK Low Time 300 — — ns

fCClock Frequency DC — 1 MHz

tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs

CLOAD = 10 pF, VDD = +3V — 6 10 µs

NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.

2. These parameters are periodically sampled and are not 100% tested.

AC ELECTRICAL CHARACTERISTICS:

VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified

CL=100pF,

see note 1

Digital

Analog

POTENTIOMETER CHARACTERISTICS

VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

RPOT Potentiometer Resistance 28 kΩ

RPOT to RPOT Match — +0.5 +1 %

Pot Resistance Tolerance +20 %

Voltage on VREFH pin 2.7 VDD V

Voltage on VREFL pin OV VDD - 2.7 V

Resolution 0.4 %

INL Integral Linearity Error 0.5 1 LSB

DNL Differential Linearity Error 0.25 0.5 LSB

ROUT Buffer Output Resistance 10 Ω

IOUT Buffer Output Current 3 mA

TCRPOT TC of Pot Resistance 300 ppm/˚C

TCRATIO Ratiometric TC ppm/˚C

RISO Isolation Resistance Ω

VNNoise nV/√Hz

CH/CLPotentiometer Capacitances 8/8 pF

fc Frequency Response Passive Attenuator MHz

CAT523

Doc. No. 2005, Rev. D

A. C. TIMING DIAGRAM

to1 2 3 4 5

CLK

PROG

t H

CLK

t L

CLK tCSH

tCSS

tCSMIN

tDIS

tDIH

tDO0

tLZ

tDO1 tHZ

RDY/BSY

tPROG

tPS

to1 2 3 4 5

tBUSY

CAT523

5Doc. No. 2005, Rev. D

DPP addressing is as follows:

DPP OUTPUT A0 A1

VOUT1 0 0

VOUT2 1 0

PIN DESCRIPTION

Pin Name Function

DD Power supply positive.

2 CLK Clock input pin.Clock input pin.

3 RDY/BSY Ready/Busy Output

4 CS Chip Select

5 DI Serial data input pin.

6 DO Serial data output pin.

7 PROG EEPROM Programming Enable

Input

8 GND Power supply ground.

REFL Minimum DPP output voltage.

10 NC No Connect.

11 NC No Connect.

12 VOUT2 DPP output channel 2.

13 VOUT1 DPP output channel 1.

14 VREFH Maximum DPP output voltage.

DEVICE OPERATION

The CAT523 is a dual 8-bit configured digitally

programmable potentiometer (DPP) whose outputs can

be programmed to any one of 256 individual voltage

steps. Once programmed, these output settings are

retained in non-volatile memory and will not be lost

when power is removed from the chip. Upon power up

the DPPs return to the settings stored in non-volatile

memory. Each DPP can be written to and read from

independently without effecting the output voltage during

the read or write cycle. Each output can also be

temporarily adjusted without changing the stored output

setting, which is useful for testing new output settings

before storing them in memory.

DIGITAL INTERFACE

The CAT523 employs a 3 wire, Microwire-like, serial

control interface consisting of Clock (CLK), Chip Select

(CS) and Data In (DI) inputs. For all operations, address

and data are shifted in LSB first. In addition, all digital

data must be preceded by a logic “1” as a start bit. The

DPP address and data are clocked into the DI pin on the

clock’s rising edge. When sending multiple blocks of

information a minimum of two clock cycles is required

between the last block sent and the next start bit.

Multiple devices may share a common input data line by

selectively activating the CS control of the desired IC.

Data Outputs (DO) can also share a common line

because the DO pin is Tri-Stated and returns to a high

impedance when not in use.

CHIP SELECT

Chip Select (CS) enables and disables the CAT523’s

read and write operations. When CS is high data may be

read to or from the chip, and the Data Output (DO) pin is

active. Data loaded into the DPP control registers will

remain in effect until CS goes low. Bringing CS to a logic

low returns all DPP outputs to the settings stored in non-

volatile memory and switches DO to its high impedance

Tri-State mode.

Because CS functions like a reset the CS pin has been

equipped with a 30 ns to 90 ns filter circuit to prevent

noise spikes from causing unwanted resets and the loss

of volatile data.

CLOCK

The CAT523’s clock controls both data flow in and out of

the IC and non-volatile memory cell programming. Serial

data is shifted into the DI pin and out of the DO pin on the

clock’s rising edge. While it is not necessary for the clock

to be running between data transfers, the clock must be

operating in order to write to non-volatile memory, even

though the data being saved may already be resident in

the DPP wiper control register.

No clock is necessary upon system power-up. The

CAT523’s internal power-on reset circuitry loads data

from non-volatile memory to the DPPs without using the

external clock.

As data transfers are edge triggered clean clock

transitions are necessary to avoid falsely clocking data

into the control registers. Standard CMOS and TTL logic

families work well in this regard and it is recommended

that any mechanical switches used for breadboarding or

device evaluation purposes be debounced by a flip-flop

or other suitable debouncing circuit.

CAT523

Doc. No. 2005, Rev. D

followed by a two bit DPP address and eight data bits are

clocked into the DPP control register via the DI pin. Data

enters on the clock’s rising edge. The DPP output

changes to its new setting on the clock cycle following

D7, the last data bit.

Programming is achieved by bringing PROG high for a

minimum of 3 ms. PROG must be brought high some-

time after the start bit and at least 150 ns prior to the

rising edge of the clock cycle immediately following the

D7 bit. Two clock cycles after the D7 bit the DAC control

and data bits. The clock must be kept running through-

out the programming cycle. Internal control circuitry

takes care of ramping the programming voltage for data

transfer to the non-volatile memory cells. The CAT523’s

non-volatile memory cells will endure over 100,000 write

cycles and will retain data for a minimum of 100 years

without being refreshed.

READING DATA

Each time data is transferred into a DPP wiper control

thus in every data transaction a read cycle occurs. Note,

however, that the reading process is destructive. Data

must be removed from the register in order to be read.

Figure 2 depicts a Read Only cycle in which no change

occurs in the DPP’s output. This feature allows µPs to

poll DPPs for their current setting without disturbing the

output voltage but it assumes that the setting being read

is also stored in non-volatile memory so that it can be

restored at the end of the read cycle. In Figure 2 CS

returns low before the 13th clock cycle completes. In

doing so the non-volatile memory setting is reloaded into

the DPP wiper control register.

VREF

VREF, the voltage applied between pins VREFH andVREFL,

sets the DPP’s Zero to Full Scale output range where

VREFL = Zero and VREFH = Full Scale. VREF can span the

full power supply range or just a fraction of it. In typical

applications VREFH andVREFL are connected across the

power supply rails. When using less than the full supply

voltage VREFH is restricted to voltages between VDD and

VDD/2 and VREFL to voltages between GND and VDD/2.

READY/BUSY/BUSY

/BUSY/BUSY

/BUSY

When saving data to non-volatile memory, the Ready/

Busy output (RDY/BSY) signals the start and duration of

the non-volatile erase/write cycle. Upon receiving a

command to store data (PROG goes high) RDY/BSY

goes low and remains low until the programming cycle

is complete. During this time the CAT523 will ignore any

data appearing at DI and no data will be output on DO.

RDY/BSY is internally ANDed with a low voltage detector

circuit monitoring VDD. If VDD is below the minimum value

required for non-volatile programming, RDY/BSY will

remain high following the program command indicating

a failure to record the desired data in non-volatile memory.

DATA OUTPUT

Data is output serially by the CAT523, LSB first, via the

Data Out (DO) pin following the reception of a start bit

and two address bits by the Data Input (DI). DO

becomes active whenever CS goes high and resumes

its high impedance Tri-State mode when CS returns low.

Tri-Stating the DO pin allows several 523s to share a

single serial data line and simplifies interfacing multiple

523s to a microprocessor.

WRITING TO MEMORY

Programming the CAT523’s non-volatile memory is

accomplished through the control signals: Chip Select

(CS) and Program (PROG). With CS high, a start bit

Figure 2. Reading from MemoryFigure 1. Writing to Memory

RDY/BSY

NEW DPP DATA

CURRENT DPP DATA

DPP VALUE DPP VALUE DPP VALUE

DPP

OUTPUT

A0 A11

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12

CURRENT

DPP VALUE

NON-VOLATILE

D0 D1 D2 D3 D4 D5 D6 D7

CURRENT DPP DATA

CAT523

7Doc. No. 2005, Rev. D

CAT523

GND

VDD V

REFH

REFL

CONTROL

& DATA

–

OP 07

V = ( ) -V

OUT RF

R +

-15V

+15V

+5V

VDPP

For R =

iRF

V = 2V -V

OUT iDPP

VOUT

APPLICATION CIRCUITS

Since this value is the same as that which had been there

previously no change in the DPP’s output is noticed.

Had the value held in the control register been different

from that stored in non-volatile memory then a change

would occur at the read cycle’s conclusion.

TEMPORARILY CHANGE OUTPUT

The CAT523 allows temporary changes in DPP’s output

to be made without disturbing the settings retained in

non-volatile memory. This feature is particularly useful

when testing for a new output setting and allows for user

adjustment of preset or default values without losing the

original factory settings.

Figure 3 shows the control and data signals needed to

effect a temporary output change. DPP wiper settings

may be changed as many times as required and can be

made to any of the two DPPs in any order or sequence.

The temporary setting(s) remain in effect long as CS

remains high. When CS returns low all two DPPs will

return to the output values stored in non-volatile memory.

When it is desired to save a new setting acquired using

Figure 3. Temporary Change in Output

this feature, the new value must be reloaded into the

DPP wiper control register prior to programming. This is

because the CAT523’s internal control circuitry discards

the new data from the programming register two clock

cycles after receiving it (after reception is complete) if no

PROG signal is received.

D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 D0 D1 D2 D3 D4 D5 D6 D71

NEW DPP DATA

CURRENT DPP DATA

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

CURRENT

DP P V ALUE

NON-VOLATILE

NEW

DP P V ALUE

VOLATILE

CURRENT

DP P V ALUE

NON-VOLATILE

Bipolar DPP Output

MSB LSB

1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V

1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V

0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V

0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V

0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V

REF REF REF

V = 5V

REF

255

255 OUT

DPP INPUT DPP OUTPUT ANALOG

R = R

OUTPUT

REF REF REF OUT

128

255

127

255 REF REF REF OUT

REF REF REF OUT

255

V = 0.99 V

FS REF

V = 0.01 V

ZERO REF

V = ——— (V - V ) + V

DPP CODE

255 FS ZERO ZERO

Amplified DPP Output

CAT523

GND

VDD V

REFH

REFL

CONTROL

& DATA

–

OP 07

VOUT

-15V

+15V

+5V

V = (1 + –––) V

OUT DPP

CAT523

Doc. No. 2005, Rev. D

APPLICATION CIRCUITS (Cont.)

Coarse-Fine Offset Control by Averaging DPP Outputs

for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs

for Dual Power Supply Systems

–

FINE ADJUST

DPP

COARSE ADJUST

DPP

GND V

REFL

RE HF

VDD

127RC

+5V +VREF

-V

-VREF

R = ———————————

C 1 µA

OFFSET

VOFFSET

REF

(+V ) - (V )

R = ———————————

o 1 µA

OFFSETREF

(-V ) + (V )

Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference

CAT523

LT 1029

I > 2 mA

V+

GND

VDD V = 5.000V

REF

REFH

REFL

CONTROL

& DATA

CAT523

GND

VDD V

REFH

REFL

CONTROL

& DATA

–

15K 10 µF

5.1V

10K

4.02 K

1.00K 10 µF

35V

LM 324

1N5231B

MPT3055EL

28 - 32V

OUTPUT

0 - 25V

@ 1A

–

FINE ADJUST

DPP

COARSE ADJUST

DPP

GND V

REFL

REFH

VDD

127RC

+5V VREF

R = —————

C 256 1 µA

VREF

Fine adjust gives ± 1 LSB change in V

when V = ———

OFFSET

VREF

OFFSET

VOFFSET

CAT523

9Doc. No. 2005, Rev. D

APPLICATION CIRCUITS (Cont.)

Current Sink with 4 Decades of Resolution

Current Source with 4 Decades of Resolution

GND V

REFL

VDD VREFH

+5V

DPP

–

CAT523

CONTROL

& DATA

DPP

–

10K 10K 39Ω1W

LM385-2.5

5 µA steps

I = 2 - 255 mA

SINK

2N7000

10K 10K

TIP 30

39Ω 1W

5 meg 5 meg 3.9K

–

-15V

2N7000

+5V

+15V

4.7 µA

1 mA steps

2.2K

GND V

REFL

VDD V

REFH

+5V

DPP

–

CONTROL

& DATA

DPP

–

5 meg 5 meg 39 1W

39 1W

5 meg 5 meg 3.9K

LM385-2.5

-15V

5 µA steps

I = 2 - 255 mA

SOURCE

1 mA steps

–

10K 10K

+15V

TIP 29

BS170P

51K

Ω

CAT523

Doc. No. 2005, Rev. D

ORDERING INFORMATION

Notes:

(1) The device used in the above example is a CAT523JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)

Prefix Device # Suffix

523 J

Product

Number

CAT

Optional

Company ID

Temperature Range

Blank = Commercial (0°C to +70°C)

I = Industrial (-40°C to +85°C)

-TE13

Tape & Reel

TE13: 2000/Reel

Package

P: PDIP

J: SOIC

L: PDIP (Lead free, Halogen free)

W: SOIC (Lead free, Halogen free)

CAT523

11 Doc. No. 2005, Rev. D

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™ AE2 ™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catsemi.com

Publication #: 2005

Revison: D

Issue date: 3/16/04

Type: Final

REVISION HISTORY

Date Rev. Reason

3/16/2004 D Updated Potentiometer Characteristics