PHILIPS INTERNATIONAL Philips Semiconductors Mi SbE D MM 2420826 0039083 692 MEPHIN oller Prod CMOS single-chip 8-bit microcontroller with on-chip EEPROM Product specification 80C851/83C851 DESCRIPTION The Philips 80085 1/83C851 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The 80085 1/83C851 has the same instruction set as the 80051. The Philips FEATURES 80051 based architecture ~ 4k x8 ROM - 128x8 RAM ~ Two 16-bit counter/timers PIN CONFIGURATIONS P40 [4 P11 [2 | CMOS technology combines the high speed Full duplex serial channel P12 [3] 38] PO.WAD1 and density characteristics of HMOS with the - le 6 p Po.2AD2 low power attributes of CMOS. The Philips Boolean processor wid 2] Pos epitaxial substrate minimizes latch-up Non-volatile 256 x 8-bit EEPROM P14 [5] [36] Po.svAD3 sensitivity, (electrically erasable programmable read PLs {s] 35] PO.4/AD4 The 800851/83C851 contains a 4k x 8 ROM only memory) Iiotior for eraser pis (7] 34]. Po.S/ADS with mask-programmable ROM code - ip vo tage mu tiptier for erase/write p17 [a] 3] Po.evaDe protection, a 128 x 8 RAM, 258 x8 50,000 erase/write cycles per byte EEPROM, 32 /O lines, two 16-bit ~ 10 years non-volatile data retention rst [3] 22} Po.7/AD7 counter/timers, a seven-soutce, five vector, Infinite number of read cycles RxDP3.0 [10] DIP fai] EX two-priority level nested interrupt structure, ~ User selactable security mode TxDPa.1 [14] 30] ALE a serial I/O port for either multi-processor Block bil communications, I/O expansion or full duptex - erase capability InTUPS.2 [12 20] PSEN UART, and on-chip oscillator and clock Mask-programmable ROM code protection INTHP 2.3 [13 [28] P2.7/A15 aroun. Memory addressing capability Toms.4 [ial P2.B/A14 In addition, the 80C851/83C851 has two = 64k ROM and 64k RAM Tups.s [25 [26] P2.5/A13 software selectable modes of power reduction idle mode and power-down Power control modes: whras [ie [25] P2.4/A12 mode. The idle made freezes the CPU while Idle mode RDiPs.7 [17] joa] P2.a/A11 allowing the RAM, timers, serial port, and Power-down mode xTate [ial [23] P2.2/A10 interrupt system to continue functioning. The power-down mode saves the RAM and CMOS and TTL compatible XTALt [19] P2.1/A9 EEPROM contents but freezes the oscillator, 4 9 to 16MHz Vgg [20 21] P2.0/A8 causing all other chip functions to ba inoperative, Three package styles Three temperature ranges 6 a CL fi) 7 [| 39 LOGIC SYMBOL tec 7 29 UJ U ADDRESS AND DATA BUS 8 28 z 2 "4 = ADDRESS QUS a i SEE PAGE 612 FOR OFP AND LCG PIN FUNCTIONS. January 8, 1992 610 853-1466 05127PHILIPS INTERNATIONAL SBE D MM 7310826 0039184 529 MEPHIN, Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller 800851/83C851 with on-chip EEPROM T=49-19-08 PART NUMBER SELECTION PHILIPS PART ORDER NUMBER SIGNETICS PART PART MARKING ORDER NUMBER TEMPERATURE FREQUENCY ROMless Version ROM Version ROMiess Version | ROM Version AND PACKAGE (MHz) PCB80C851-2-16P PCB83C851-2P S80C851-4N40 $83C851-4N40 0 to +70C, plastic DIP 1.2 to 16 PCB80C851-2-16WP PCB83C851-2WP $80C851-4A44 $830851-4A44 0 to +70C, plastic PLCC 1.2 to 16 PCB80C851-2-16H PCB83C851-2H $80C851-4B44 $83C851-4B44 0 to +70C, plastic QFP 1.2 to 16 PCF80C851-2-16P PGF83C851-2P $80C851-5N40 $83C851-5N40 40 to +85C, plastic DIP 1.2 to 16 PCF80C851-2-16WP PCF83C851-2WP $800851-5A44 $83C851-5A44 -40 to 485C, plastic PLCC 1.2 to 16 PCF80C851-2-16H PGF83C851-2H $800851-5B44 S83C851-5B44 ~40 to +85C, plastic QFP 1.2 to 16 PCA80C851-2-16P PCA83C851-2P S80C851-6N40 | S83C851-6N40 ~40 to +125C, plastic DIP 1.2 to 16 PCA80C851-2-16WP PCA83C851-2WP $80C851-6A44 $83C851-6A44 40 to +125C, plastic PLCC 1.2 to 16 PCA80C851-2-16H PCA83C851-2H S80C851-6B44 $83C851-6B44 40 to +125C, plastic QFP 1.2 to 16 BLOCK DIAGRAM FREQUENCY REFERENCE COUNTERS cs XTAL2XTALA To qT pop . | j | OSCILLATOR PROGRAM DATA TWO 16-BiT 1 | AND MEMORY TIMER/EVENT EEPROM | | TIMING (4K x8 ROM) (123 x8 RAM) COUNTERS (256 x8) | - ZN ZN Z~ | : | | | i | | \ | | | | . | | cpu < 1 | | Ni I l yr a | TTT | | | I INTERNAL I | INTERRUPTS I | l | \Z NZ \Z 64k BYTE BUS }\J PROG SERIAL PORT PROGRAMMABLE LO | eat cS | | | | bot to + Hp { INTO $= NTT CONTROL PARALLEL PORTS, SERIALIN SERIAL OUT ADDRESSIDATA BUS L_____+4 SHARED WITH INTEROP PORTS January 8, 1992 611PHILIPS INTERNATIONAL SKE D MM 7120826 0039185 465 m@PHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 7=49-1 9 o8 LCC PIN FUNCTIONS QFP PIN FUNCTIONS 6 1 0 cb 7 39 Loc 7 lee 18 23 Pin = Function Pin = Function Pin = Function Pin Function 1 NC 23 NG 1 PL 23 P2.B/AI3 2 PLO 24 P2.0VAB 2 P16 24 PRGVAI4 3 PL 25 P2.1/A9 3 PL? 25 P2.7/A16 4 PL 26 P2.2/A10 4 AST 2 -BSEN 5 PL 27 P2.SIAit & P3.0RxD 27 ALE 6 PA 28 P2.4/A12 6 NO 23 =NC 7 PL 20 P2,6/A13 7 PaatxD 2 OEK a P16 90 P2.e/At4 8 = PS.2/NTO 30 PO,7/AD7 8 PL 3t) PATIAIS 9 P3.SINTT 31 PO,6/AD6 10 AST 320 PSEN 40 P3.4/TO 82 PO.S/ADS 11 P3O/AxD 33OALE. 1 P3871 83 PO.A/ADS 12 NC 34 NC 12 P36WR 34 PO.G/AD3 13 P3,t/TxD 35 EA 13 P3,7AD 35 PO.2/AD2 14 P3.2ANTO 38 PO,7/AD7 14 XTAL2 36 PO.W/AD1 15 P3.QANTT 87 PO./ADG 15 _XTAL 37 PO.YADO 16 P3,4/T0 38 PO.BADS 16 Vgg 38 Vo 17 P3871 39 POA/AD4 7 ONG Veg 18 P3.6ANR 40 = PO.WADS 19 P3.7/AD 41 PO.2AD2 18 PRAIA 4 Plo 20 XTALD 42 POLADI 49 P2.4/A9 4.0 Pad Bt XTALL . 20 = P2.2/A10 420 P12 oe a PO.W/ADO 21 PR.WANL 48 PL Vss Voc 22 P2.aiAt2 4a PLA January 8, 1992 612PHILIPS INTERNATIONAL SBE D MM 7110826 00391386 3T1 MPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller : : 80C851/83C851 with on-chip EEPROM ON T-49-19-08 PIN DESCRIPTION PIN NO. MNEMONIC | DIP Loc | QFP | TYPE NAME AND FUNCTION Vss 20 22 16,39 i Ground: OV reference. Veo 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0,0-0.7 39-32 | 43-36 | 37-30 | VO | Port 0: Port 0is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting is. P1.0-P1.7 1-8 2-9 |40-44,] VO {| Port: Port 1 is an 8-bit bidirectional /O port with intemal pull-ups. Port 1 pins that have 1-3 1s written to them are pulled high by the internal pull-ups and can be used as Inputs. As inputs, port 1 pins that are externally pulled low will source current because of the intemal pull-ups. (See DC Electrical Characteristics: ti,). P2.0-P2.7 21-28 | 24-31 | 18-25 | WYO | Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the intemal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: |\_). Port 2 emits the high-order address byte during fetches from extemal program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0-P3.7 10-17 | 11, 5, VO | Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 13-19 | 7-13 1s written to them are pulled high by the internal pull-ups and can be used as-inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: Ii). Port 3 also serves the special features of the SC80C51 family, as listed below: 10 u 5 l RxD (P3.0): Serial input port 1 13 7 | TxD (P3.1): Serial output port 12 14 8 I INTO (P3.2): External interrupt 13 15 9 I INTT (P3.3): External interrupt 14 16 10 ! TO (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O | WR(P3.6): External data memory write strabe 17 19 13 O | RD(P3.7): External data memory read strobe ! RST 9 10 4 Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to Ves permits a power-on reset using only an extemal capacitor to Voc. ALE 30 33 27 VQ | Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory, PSEN 29 32 26 fe) Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 35 29 t External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations OOOOH and OFFFH. If EA is held high, the davice executes from internal program memory unless the program counter contains an address greater than OFFFH. XTAL1 19 ai 15 ! Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits, XTAL2 18 20 14 O | Crystal 2: Output from the inverting oscillator amplifier. January 8, 1992 613SbE D MM 7110826 0039187 2386 MPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C8 ot T=49~19-08 EEPROM EADRH register address is F3H. The EADRL The ETIM register address is FSH, Table 1 Communications between the CPU and the EEPROM is accomplished via 5 special function registers; 2 address registers (high and low byte), 1 data register for read and write operations, 1 contro! register, and 1 timer register to adapt the erase/nrite time to the clock frequency. All registers can be read and written. Figure 1 shows a block diagram of the CPU, the EEPROM and the interface. Register and Functional Description Address Register (EADRH, EADRL) The lower byte contains the address of one of the 256 bytes. The higher byte (EAORH) is for future extensions and for addressing the security bits (soe Security Facilities). The register address is F2H. Data Register (EDAT) This register is required for read and write operations and also for row/block erase. In write mode, its contents are written to the addressed byte (for row erase" and block erase the contents are don't care). The write pulse starts all operations, except read. In tead mode, EDAT contains the data of the addressed byte. The EDAT register address is FAH, Timer Reglster (ETIM) The timer register is required to adapt the eraseMrite time to the oscillator. frequency. The user has to ensure that the erase or write (program) time is neither too short or too long. . contains the values which must be written to the ETIM register by software for various oscillator frequencies (the default value is O8H after RESET). The general formula is: Sms Write time: Value (decimal, _ fxrats [KHz] _ to be rounded up) 204.8 10ms Write time: Value (decimal) ~ eras 2] 2 Control Reglster (ECNTRL) See Figure 2 for a description of this register. The ECNTRL register address is F6H. Table 1. _ Values for the Timer Register (ETIM) VALUES FOR ETIM fxtaLa 5ms WRITE TIME 10ms WRITE TIME HEX DEC HEX DEC 1.0MHz 03 3 08 8 2.0MHz 08 8 13 19 3.0MHz oD 13 1D 29 4.0MHz 12 18 28 40 S.0MHz 17 23 32 50 6.0MHz 1 28 3c 60 7.0MHz a1 33 47 71 8.0MHz 26 38 51 81 9.0MHz 2A 42 50 92 10.0MHz 2F 47 66 102 11.0MHz 34 52 71 113 12,0MHz 39 57 7B 123 18.0MHz 3E 62 : 14,0MHz 43 67 15.0MHz 48 72 16.0MHz 4D 77 i INTERRUPT SEQUENCER a, POWER. DOWN IDLE , CLOCK RESET > ft GENERATOR oix oe cpu " ZN EDATA iNTERNAL BUS Figure 1. EEPROM Interface Block Diagram January 8, 1992 614PHILIPS INTERNATIONAL Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 LO T-49-19-08 7 6 5 4 3 2 1 0 | we | cewr | ewe | | contra] ecuTAt2] EcNTALS| ECNTRLO| Bit Symbol Function ECNTAL.7 = iFE Active high EEPROM interrupt flag: set by the sequencer or by soft.vare; reset by software. set and enabled, this flag forces an interrupt to the same vector as the serial port wren se (see Interrupt section). ECNTRLG EEINT EEPROM Interrupt enable: set and reset by software (active high). ECNTRLS EWP Erasedwrite In progress flag: set and reset by the sequencer (active high). When EWP Is set, access to the EEeROM Is not possible. EWP cannat be sat or reset by software. ECNTRL4 Reserved, ECCTRL.2- See table below, ECNTAL.O Operation ECNTAL3 Byte mode 0 Row erase 1 Page wrike* - 1 Page erasafwrite block erase Future products. Byte mode: Normal EEPROM mode, detauit mode after reset. In this mode, data can be tead and written to one byte at atime, Read mode: This Is the default mode when byte mode is selected, This means that the contents of the addressed byte ara available in the data register. Write mode: This mode Is activated by writing to the data register. The address register must be loaded first. Since the od contents are raad fist (by defauk), this allows the sequencer to decide whether an erasewiie of write cycle only (data = 00H) Is required. Row erase: In this mode, the addressed row Is cleared. Tha three LSBs of EADRL are not significant, i.e. the 8 bytes addrassed by EADRL are cleared in the same time normally needad to clear one byte (taowerase = te tw), For the following write modes, only the write and not the erasewrite cycle is required, For example, using the row efase mode, programming 8 bytes takes troton. = te + 8 x by compared to trom 8 Xte + 8 x tw (te = tenase tw = twee). Sling =-=!1100 e1loo Page write: For future products, Page eraseywrite: For future products Block erase: In this mode al! 256 bytes are cleared, The byte containing the securay bits Is also cleared. taracxenase = te. The contents of EADRH, EADRL and EDAT are insignificant. Program Sequences and Register Contents after Reset The contends of the EEPROM registers alter a Reset are the defauk values: EAD! = 1xc00B (security bit address) EADRL = OOH (security bit address) ETIM = Q8H (mlnimum erase time wih the lowest permissible oscillator frequency) ECNTRL =00H (Byte moda, read) EDAT a= xxH MOV ETIM, .. MOV EADRH, .. MOV EADAL, .. MOV .., EDAT MOV EADRL, .. MOV EDAT, .. MOV EADRL, .. Row address. SLSBs don't care MOV ECNTRL, #0CH Erase row moda. MOV EDAT, .. (EDAT) dont care MOV ECNTRL, OAH Erase block moda MOV EDAT, .. (EDAT) don't care Erase block: H the security bit ls to be altered, the program generally starts as follows: MOV EADAH, #80H MOV EADRL, #00H Figure 2. Control Register (ECNTRL) January 8, 1992 SKE D MM 7110626 0039188 174 MPHINPHILIPS INTERNATIONAL SBE D MM 7110626 0039189 000 MEPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM BOCEST/E3C851 7-49-11 9-08 Security Facilities EEPROM Protection The EEPROM is protected using four security bits which are contained in an extra EEPROM byte at address 8000H (EADRH/EADRL). They can be set or cleared by software. To activate the EEPROM protection, the program sequence in byte mode must be as follows: MOV EADRH, #80H MOV EADAL, #00H MOV EDAT, #FFH If two or more of these bits are reset, SB = 0, the security mode is disabled and the EEPROM is not protected. If three or four bits are set, SB = 1 and the EA mode differs from the Internal access mode. In this case, access to the EEPROM is only possible in one mode regardless of how the extemal access mode is reached (by pulling the EA pin tow or by passing the 4K boundary). For SB = 1 and external access only, the block erase mode is enabled. The program sequence has to be as follows: MOV EADRH, #80H (security byte address) MOV EADRL, #00H (security byte address) MOV EGNTRL, #0AH (block erase mode) MOV EDAT, #xxH (start block erase) All 256 data bytes, the security bits, and SB will be cleared after completing this mode (EWP = 0). SB will also be affected in byte mode when writing to the security byte (not for SB = 1 and extemal access"). Figure 3 illustrates the access to SB. ROM Code Protection Since the external access mode can only be selected by pulling the EA pin low during reset, it is not possible to read the internal program memory using the MOVC instruction while executing external program memory. Furthermore, it is not possible to change this mode to internal access within the MOVC cycle. Additionally, a mask-programmable ROM code protection facility is available. When the program memory passes the 4K boundary using both the internal and external ROMs, it is not possible to accass the internal ROM from the extemal program memory if the mask-programmable ROM security bit is set. An access to the lower 4K bytes of program memory using the MOVC instruction is only possible while executing internal program memory. Also the verification mode (test-mode which writes the ROM contents to a port for comparison with a reference code) is not implemented for security reasons. A different test-mode is implemented for test purposes. This mode allows every bit to be tested. However, the internal code cannot be accessed via a port, SECURITY BYTE ADDI SECURIT AND BYTE MODE FIMSH| RESET | REGISTERS. EADRY AND NTAIN THE PNADDEESS aT THE TY BYTE RESET RESS AND BLOCK ERASE FINSHED TY BYTE ADDRESS EADRH EADRL }*_ RESET , 4" EEPROM EAQ INHIBIT 'READ DATA REGISTER INHIBIT WRITE DATA REGISTER EXCEPT (ECNTAL) = BLOCK ERASE Figure 3. EEPROM Protection (Functional and Flowchart) [- Reser January 8, 1992 616PHILIPS INTERNATIONAL Philips Semiconductors Microcontroller Products S5bE D MM 7110826 00391390 &22 MPHIN Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 cr wasn sn wworo T+49-19-08 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol, page 610. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no Tequirements on the duty cyclo of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. RESET Areset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-up, the voltage on Voc and RST must come up at the same time for a proper start-up. Note: Before entering the idle or power-down modes, the user has to ensure that there is no EEPROM eraseAwrite cycle in progress (.a., the EWP bit has to be reset before activating the idle or power-down mades; otherwise EEPROM accesses will be aborted). IDLE MODE In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idie mode is the Jast instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. POWER-DOWN MODE In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed, Only the contents of the on-chip RAM and EEPROM are preserved. A hardware reset is the only way to terminate the power-down mode, The control bits for the reduced power modes are in the special function register PCON. Table 2 shows the state of the VO ports during low current operating modes. INTERRUPT SYSTEM Extemal events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution, a multiple-source, two-priority-level, nested interrupt system is provided. Interrupt response latency is from 3us to 7s when using a 12MHz crystal. The $83C851 acknowledges interrupt requests from 7 sources as follows: INTO and INTT: externally via pins 12 and 13, respectively, Timer 0 and timer 1: from the two intemal counters, Serial port: from the internal serial I/O port or EEPROM (1 vector}. Each interrupt vectors to a separate location in program memory for its service program. Each source can be individually enabled (the EEPROM interrupt can only be enabled when the serial port interrupt is enabled) or disabled and can be programmed to a high or low priority level. All enabled sources can also be globally disabled or enabled. Both external interrupts can be programmed to be level-activated and are active low to allow *wire-ORing of several interrupt.sources to one input pin. Note: The serial port and EEPROM interrupt flags must be cleared by software; all other flags are cleared by hardware. Table 2. External Pin Status During Idle and Power-Down Modes MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle Internal 1 1 Data Data Data Data Idle Extemal 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down Extemal 0 0 Float Data Data Data ABSOLUTE MAXIMUM RATINGS!: 2.3 PARAMETER RATING UNIT Storage temperature range -65 to +150 C Voltage on any other pin to Vgs -0.5 fo +6.5 v Input or output DC current on any single VO pin +6 mA Power dissipation (based on package heat transfer limitations, 1.0 Ww not device power consumption) NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied, . This product includes circuitry specifically designed for the protection of its intemal devices from the damaging effects of excessive static charge. Nonetheless, itis suggested that conventional precautions be taken to avoid applying greater than the rated maxima. . Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to Vsg unless otherwise noted. danuary 8, 1992 617PHILIPS INTERNATIONAL 5bE D MM 7110826 003915) 769 MEPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM BOCESTIESCBT 7+49-19-08 DC ELECTRICAL CHARACTERISTICS Tamiy = 0C to +70C (Vg = SV 420%), -40C to +85C (Voc = 5V 420%), or -40C to +125C (Veg = 5V 410%), Vag = OV PART TEST LIMITS SYMBOL PARAMETER TYPE CONDITIONS MIN MAX UNIT Vi Input low voltago, except EA 0 to +70C -0.5 0.2Ve-0.1 v ~40 to +85C -0.5 0.2Vec-0.15 Vv 40 to +125C 0.5 0.2Vec-0.25 Vv Viti Input low voltage to EA 0 to +70C -0.5 0.2Vec-0.3 V 40 to +85C 0.5 0.2Voc-0.35 Vv 40 to +125C 0.5 0.2Voc0.45 v Vu Input high voltage, except XTAL1, RST 0 to +70C 0.2Vc+0.9 Vect0.5 Vv 40 to +85C 0.2Vcoc+1.0 Voct0.5 Vv 40 to +125C 0.2Voc+1.0 Voo+0.5 Vv View Input high voltage, XTAL1, RST 0 to +70C 0.7Vcc Voct0.5 40 to +85C. 0.7Voc+0.1 Voct0.5 40 to +125C 0.7Vec+0.1 Voct0.5 Vou Output low voltage, ports 1, 2, 3 & lo, = 1.6mA4 _ 0.45 v Vout Output low voltage, port 0, ALE, PSEN & Io, = 3.2mA4 0.45 V Vou Output high vottage, ports 1, 2, 3, ALE, PSEN lon =60pLA, 2.4 Vv Jou =25pA, 0.75Vec Vv low = 10pA 0.9Vec Vv Vout Output high voltage, port 0 in external bus lou = -800pA, 24 v mode lou = -BOOpA, 0.78Vec V lon = -80pnA 0.9Vcc Vv fie Logical 0 input current, ports 1,2, 3 0 to +70C Vin = 0.45V ~50 HA ~40 to +85C -75 pA ~40 to +125C -75 pA In Logical 1-to-0 transition current, ports 1, 2, 3 0 to +70C Vin = 2.0V 650 pA 40 to +85C ~750 pA 40 to +125C -750 pA ta Input leakage current, port 0, EA 0.45V<Vi<Voc +10 pA loc Power supply current: See note 7 Active mode @ 16MHz ! 32 mA Idle mode @ 16MHz 2 6.5 mA Power down mode 3 100 pA Rast Internal reset pull-down resistor 50 150 kQ Cio Pin capacitance f= 1MHz 10 pF NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t, = t; = 5ns; Vi_ = Vgg +0.5V; Vit = Voc - 0.5V, XTAL2 not connected; EA = RST = Port 0 = Vgc. 2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t, = ty = 5ns; Vi, = Veg +0.5V; Vin = Voc 0.6V; XTAL2 not connected; EA = Port 0 = Voc; RST = Ves. 3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; EA = Port 0 = Vog; RST = XTAL1 = Veg. 4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port 1 and Port 3. The noise is due to extemal bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0 transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desireable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9Vce specification when the address bits are stabilizing. 6. Under steady state (non-transient) conditions, Io, must be extemally limited as follows: Maximum lo. per Port pin: 10mA Maximum Io, per 8-bit port PortO: 26mA Ports 1,2, and3: 15mA Maximum total Io), for all output pins: = 71mA. If lo, exceeds the test condition, Vo, may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. See Figures 11 through 14 for Igg test conditions. January 8, 1992 618PHILIPS INTERNATIONAL SbE D MM 7110826 0039192 GTS MMPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller 80C851/83C851 with on-chip EEPROM T-49-19-08 AC ELECTRICAL CHARACTERISTICS! 2 16MHz CLOCK VARIABLE CLOCK SYMBOL | FIGURE PARAMETER MIN MAX MIN MAX UNIT Toto 4 Oscillator frequency 1.2 16 MHz tHe 4 ALE pulse width 85 2teic_40 ns fav 4 Address valid to ALE low 8 tore.-55 ns fLLax 4 Address hold after ALE low ; 28 tetcL-35 ns tuv 4 ALE low to valid instruction in 150 4toic_-100 ns tip. 4 ALE low to PSEN low 23 torc.-40 . ns teLpy 4 PSEN pulse width 143 StercL-45 ns tory 4 PSEN low to valid instruction in 8a Stero-105 ns toxix 4 Input Instruction hold after PSEN 0 0 ns tpyiz 4 Input instruction float after PSEN 38 totcL-25 ns taviv 4 Address to valid instruction in 208 Stetct-105 ns teiaz 4 PSEN low to address float 10 10 ns Data Memory taLAH 5,6 RD pulse width 275 Stic 100 ns twowH 5,6 WR pulse width 275 6toice_-100 ns taLpv 5,6 RD low to valid data in 148 Stoic. -165 ns tanox 5,6 Data hold after RD 0 0 ns taupz 5,6 Data float after RD 55 2tetcL-70 ns tiov 5,6 ALE low to valid data in 350 8torc.-150 ns tavov 5,6 Address to valid data in s98 Stor -165 ns hiw. 5,6 ALE low to RD or WR low 138 238 3te1.c.-50 Sterol +50 ns taw 5,6 Address to RD or WR 120 4torc. 180 ns tow 5,6 Data setup time before WR 288 Ttevci_-150 ns tavwx 5,6 Data valid to WR transition 3 terc_-60 ns twHox 5,6 Data hold after WR 13 teici-50 ns taraz 5,6 RD low to address float 0 0 ns twHty 5,6 RD or WR high to ALE high 23 103 terc--40 ftotcL+40 ns External Clock toHex 8 High time 20 20 ns toLox 8 Low time 20 20 ns teLcH 8 Rise time 20 20 ns fone. 8 Fall time 20 20 ns Erase/write timer constant? teay EraseMrite cycle time 10 40 10 40 ms te Erase time 5 40 5 40 ms tw Write time 5 40 5 40 ms tg Data retention time* 10 10 years NEW EraseMwrite cycles 50,000 50,000 cycles NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. The power-off fall-time of Veg must be less than ims to prevent an overwrite pulse from being generated in the EEPROM which can cause spurious parasitic writing to EEPROM cells. if the Vcc power-off full-time is greater than ms, a power-off reset signal should be generated to prevent this condition from occurring. . Test condition: Tan = +55C. . Number of eraseMrite cycles for each EEPROM byte. an January 8, 1992 619BHILIPS INTERNATIONAL 5SbE D MM 7110826 0039193 531 MMPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller 800851/83C851 with on-chip EEPROM EO MOONS 1749-19-08 EXPLANATION OF THE L ~ Logic level low, or ALE AC SYMBOLS P PSEN Each timing symbol has five characters, The 27 eyo data first character is always 't (= time). The other RD signal characters, depending on their positions, V 7 Time indicate the name of a signal or the logical w_ ae status of that signal. The designations are: ~ WReignal A~ Address X No longer a valid logic level C~ Clock Z Float D Input data Examples: tay. = Time for address valid to H~ Logic level high ti Tima for ALE low t - i LPL= | = Instruction (program memory contents) PSEN low. teu > ALE taver . [ture k tpLpH L14 vy t SEN / PLIV tua: { < tp PXIZ {pxix Le ~ PORTO 40-47 INSTRIN AO-AT _~<X_ < taviv PORT 2 x AB-A1S x AG-AIS Figure 4, External Program Memory Read Cycle tWHLe tLupv > {RLRH > Y N / t [< tarpy > tanpx> vy rp DATAIN A0-A7 FROM PCL INSTR IN [< tavwe } tavov ~ PORT 2 x P2,0-P2,7 OR AS-A15 FROM DPH xX A8~-A15 FROM PCH Figure 5. External Data Memory Read Cycle January 8, 1992 620PHILIPS INTERNATIONAL S5bE D MM 71410826 0039194 478 MPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 800851/83C851 , T=+49-19-08 tovwx tow DATA OUT P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH Figure 6. External Data. Memory Write Cycle ONE MACHINE CYCLE ONE MACHINE CYCLE s2 S$3 34 83 4 S5 S86 ler pe | ler ee ler oe ler pe lor XTAL1 ee INPUT ALE PSEN RD WR EXTERNAL ponte ADORESS FLOAT ADDRESS FLOAT ADORESS | FLOAT [DATA FETCH EXTERNAL) ADDRESS TRANSITIONS PORT OLD DATA i NEW DATA ourTPUT 1 | SAMPLING TIME OF /O PORT PINS DURING INPUT (INCLUDING INTO AND IRT?) Pont INPUT SERIAL (SHIFT CLOCK) Figure 7, instruction Timing January 8, 1992 621PHILIPS INTERNATIONAL SbE D ME 7110826 OO39L55 304 MEPHIN. Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller 80C0851/83C851 with on-chip EEPROM ee, T-49-19-08 Table 3. External Clock Drive XTAL1 Oscillator circuitry: The capacities connected to the crystal should be: C1 = C2 = tof. VARIABLE CLOCK f= 1.2 - 16MHz SYMBOL PARAMETER MIN MAX UNIT tote Oscillator clock period 63 833 ns thigh HIGH time 20 tcLoL ~ tlow ns tlow LOW time 20 totot tHicH ns Rise time - 20 ns 1 Fall time - 20 ns toy Cycle time! 0.75 10 ns NOTE: 1. toy = 12 tote. 24av O45V x Figure 8. External Clock Drive NOTE: AC Inputs during testing are driven at 2.4V for a logic '1' and 0.45V for a logic '0'. Timing measurements are made at 2.0V min for a logle '1' and 0.8V for a logle 0", Figure 9. AC Testing InpuOutput NOTE; VLOAD#0.1 TIMING Vor-0.1V VLOAD > REFERENCE g VLoap-0.1V POINTS VoL+0.1V For timing purposes, a port Ie no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VoH/Vo| level occurs, Igy fio, 2+ 20mA. Figure 10. Float Waveform Figure 11. Igc Test Condition, Active Mode All other pins are disconnected Yeo Nec leo ec Vec ! Voc i Veco Yeo RST Vec Po K Po K RST NI | Ne EK - EK (NC) XTAL2 (NC) XTAL2 CLOCK SIGNAL->] XTAL! CLOCK SIGNAL] XTAL1 Vss Vss Figure 12. lec Test Condition, Idle Mode All other pins are disconnected January 8, 1992 622PHILIPS INTERNATIONAL SLE D MM 7210826 0039296 240 MPHIN Philips Semiconductors Microcontroller Products Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 800851/83C851 \ Oa ' T349~-19-08 Yee tcc Veco \ RST Vcc Po K = EK (Nc) | XTAL2 XTALt F = Figure 13. Clock Signal Waveform for Icg Tests Figure 14. Icc Test Condition, Power Down Mode In Active and Idle Modes All other pins are disconnected. tetcu = tcc. = Sns Veco = 2V to 5.5V January 8, 1992 623