ADC10321
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ADC10321 10-Bit, 20MSPS, 98mW A/D Converter with Internal Sample and Hold
Check for Samples: ADC10321
1FEATURES DESCRIPTION
The ADC10321 is a low power, high performance
2• Internal Sample-and-Hold CMOS analog-to-digital converter that digitizes
• Single +5V Operation signals to 10 bits resolution at sampling rates up to
• Low Power Standby Mode 25Msps while consuming a typical 98mW from a
single 5V supply. Reference force and sense pins
• Ensured No Missing Codes allow the user to connect an external reference buffer
• TTL/CMOS or 3V Logic Input/Output amplifier to ensure optimal accuracy. No missing
Compatible codes is ensured over the full operating temperature
range. The unique two stage architecture achieves
APPLICATIONS 9.2 Effective Bits with a 10MHz input signal and a
20MHz clock frequency. Output formatting is straight
• Digital Video binary coding.
• Communications To ease interfacing to 3V systems, the digital I/O
• Document Scanners power pins of the ADC10321 can be tied to a 3V
• Medical Imaging power source, making the outputs 3V compatible.
• Electro-Optics When not converting, power consumption can be
reduced by pulling the PD (Power Down) pin high,
• Plain Paper Copiers placing the converter into a low power standby state,
• CCD Imaging where it typically consumes less than 4mW. The
ADC10321's speed, resolution and single supply
KEY SPECIFICATIONS operation makes it well suited for a variety of
applications in video, imaging, communications,
• Resolution 10 Bits multimedia and high speed data acquisition. Low
• Conversion Rate 20 Msps power, single supply operation ideally suit the
• ENOB@ 10MHz Input 9.2 Bits (typ) ADC10321 for high speed portable applications, and
its speed and resolution are ideal for charge coupled
• DNL 0.35 LSB (typ) device (CCD) input systems.
• Conversion Latency 2 Clock Cycles The ADC10321 comes in a space saving 32-pin
• PSRR 56 dB TQFP and operates over the industrial (−40°C ≤TA≤
• Power Consumption 98 mW (typ) +85°C) temperature range.
• Low Power Standby Mode <4 mW (typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADC10321
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin Description
No. Symbol Equivalent Circuit
Analog I/O
Analog Input signal to be converted. Conversion range is
30 VIN VREF+S to VREF−S.
Analog input that goes to the high side of the reference
31 VREF+F ladder of the ADC. This voltage should force VREF+S to be in
the range of 2.3V to 4.0V.
Analog output used to sense the voltage near the top of the
32 VREF+SADC reference ladder.
Analog input that goes to the low side of the reference ladder
2 VREF−F of the ADC. This voltage should force VREF−S to be in the
range of 1.3V to 3.0V.
Analog output used to sense the voltage near the bottom of
1 VREF−Sthe ADC reference ladder.
Converter digital clock input. VIN is sampled on the falling
9 CLK edge of CLK input.
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin Description
No. Symbol Equivalent Circuit
Power Down input. When this pin is high, the converter is in
8 PD the Power Down mode and the data output pins are in a high
impedance state.
Output Enable pin. When this pin and the PD pin are low, the
26 OE output data pins are active. When this pin or the PD pin is
high, the output data pins are in a high impedance state.
14 thru
19 Digital Output pins providing the 10 bit conversion results.
and D0 -D9 D0 is the LSB, D9 is the MSB. Valid data is present just after
22 thru the falling edge of the CLK input.
25
Positive analog supply pins. These pins should be connected
to a clean, quiet voltage source of +5V. VAand VDshould
3, 7, 28 VAhave a common supply and be separately bypassed with
10µF to 50µF capacitors in parallel with 0.1µF capacitors.
Positive digital supply pins. These pins should be connected
to a clean, quiet voltage source of +5V. VAand VDshould
5, 10 VDhave a common supply and be separately bypassed with
10µF to 50µF capacitors in parallel with 0.1µF capacitors.
Positive supply pins for the digital output drivers. These pins
12, 21 VDI/O should be connected to a clean, quiet voltage source of +3V
to +5V and be separately bypassed with 10µF capacitors.
The ground return for the analog supply. AGND and DGND
4, 27, AGND should be connected together close to the ADC10321
29 package.
The ground return for the digital supply. AGND and DGND
6, 11 DGND should be connected together close to the ADC10321
pacjage.
13, 20 DGND I/O The ground return of the digital output drivers.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
Positive Supply Voltage (V = VA= VD) 6.5V
Voltage on Any I/O Pin −0.3V to (VAor VD) +0.3V)
Input Current at Any Pin(4) ±25mA
Package Input Current(4) ±50mA
Package Dissipation at TA= 25°C See (5)
ESD Susceptibility(6) Human Body Model 1500V
Machine Model 200V
Soldering Temp., Infrared, 10 sec.(7) 235°C
Storage Temperature −65°C to +150°C
(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supplies ( VIN < AGND or VIN > VAor VD), the current at that pin should be limited
to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 25mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax - TA)/θJA. In the 32-pin TQFP, θJA is 69°C/W, so PDMAX = 1,811 mW at 25°C and 942mW at the maximum operating
ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 110mW
(98mW quiescent power + 2mW reference ladder power +10mW due to 10 TTL load on each digital output). The values for maximum
power dissipation listed above will be reached only when the ADC10321 is operated in a severe fault condition (e.g. when input or
output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should
always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5kΩresistor. Machine model is 220 pF discharged through ZERO Ω.
(7) The 235°C reflow temperature refers to infared reflow. For Vapor Phase Reflow (VPR), the following conditions apply: Maintain the
temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body
must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.
OPERATING RATINGS(1)(2)
Operating Temperature −40°C ≤TA≤+85°C
VA, VDSupply Voltage +4.5V to +5.5V
VDI/O Supply Voltage +2.7V to 5.5V
VIN Voltage Range 1.3V to (VA-1.0V)
VREF + Voltage Range 2.3V to (VA-1.0V)
VREF−Voltage Range 1.3V to 3.0V
PD, CLK, OE Voltage −0.3V to + 5.5V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
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CONVERTER ELECTRICAL CHARACTERISTICS
The following specifications apply for VA= +5.0VDC, VD= 5.0VDC, VDI/O = 5.0VDC, VREF+ = +3.5VDC, VREF−= +1.5VDC, CL=
20pF, fCLK = 20MHz, RS= 25Ω.Boldface limits apply for TA= TMIN to TMAX:all other limits TA= 25°C(1)
Symbol Parameter Conditions Typical(2) Limits(3) Units
Static Converter Characteristics
INL Integral Non-Linearity ±0.45 ±1.0 LSB(max)
DNL Differential-Non Linearity ±0.35 ±0.85 LSB(max)
Resolution with No Missing 10 Bits
Codes
Zero Scale Offset Error −6 mV(max)
Full-Scale Error −6 mV(max)
Dynamic Converter Characteristics
fIN = 1.0MHz 9.5 Bits
ENOB Effective Number of Bits fIN = 4.43MHz 9.5 9.0 Bits(min)
fIN = 10MHz 9.2 Bits
fIN = 1.0MHz 59 dB
Signal-to-Noise Plus Distortion
S/(N+D) fIN = 4.43MHz 59 56 dB(min)
Ratio fIN = 10MHz 57 dB
fIN = 1.0MHz 60 dB
SNR Signal-to-Noise Ratio fIN = 4.43MHz 60 58 dB(min)
fIN = 10MHz 58 dB
fIN = 1.0MHz −71 dB
THD Total Harmonic Distortion fIN = 4.43MHz −70 −59 dB(min)
fIN = 10MHz −66 dB
fIN = 1.0MHz 74 dB
SFDR Spurious Free Dynamic Range fIN = 4.43MHz 72 60 dB
fIN = 10MHz 68 dB
DG Differential Gain Error fIN = 4.43MHz, fCLK = 17.72MHz 0.5 %(max)
DP Differential Phase Error fIN = 4.43MHz, fCLK = 17.72MHz 0.5 deg(max)
Overrange Output Code VIN > VREF+1023
Underrange Output Code VIN < VREF−0
BW Full Power Bandwidth 150 MHz
Change in Full Scale with 4.5V to 5.5V
PSRR Power Supply Rejection Ratio 56 dB
Supply Change
Reference and Analog Input Characteristics(4)
1.3 V(min)
VIN Analog Input Range 4.0 V(max)
CIN Analog VIN Input Capacitance 5 pF
IIN Input Leakage Current 10 µA
850 Ω(min)
RREF Reference Ladder Resistance 1000 1150 Ω(max)
VREF+ Positive Reference Voltage 3.5 4.0 V(max)
VREF−Negative Reference Voltage 1.5 1.3 V(min)
(VREF+) 1.0 V(min)
Total Reference Voltage 2.0
−(VREF −)2.7 V(max)
(1) The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes above VAor below AGND by more than 300 mV. See Figure 1,
Figure 2 and Figure 3.
(2) Typical figures are at TA= TJ= 25°C, and represent most likely parametric norms.
(3) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(4) When the input signal is between VREF+ and (VA+ 300mV), the output code will be 3FFh, or all 1s. When the input signal is between
−300 mV and VREF−, the output code will be 000h, or all 0s.
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DC AND LOGIC ELECTRICAL CHARACTERISTICS
The following specifications apply for VA= +5.0VDC, VD= +5.0VDC, VDI/O = 5.0VDC, VREF+ = +3.5VDC, VREF−= +1.5VDC, CL=
20 pF, fCLK = 20MHz, RS= 25Ω.Boldface limits apply for TA= TMIN to TMAX:all other limits TA= 25°C(1)
Symbol Parameter Conditions Typical(2) Limits(3) Units
CLK, OE, PD, Digital Input Characteristics
VIH Logical "1" Input Voltage VD= 5.5V 2.0 V(min)
VIL Logical "0" Input Voltage VD= 4.5V 1.0 V(max)
IIH Logical "1" Input Current VIH = VD10 µA
IIL Logical "0" Input Current VIL = DGND −10 µA
D00 - D13 Digital Output Characteristics
VDI/O = + 4.5V, IOUT =−0.5mA 4.0 V(min)
VOH Logical "1" Output Voltage VDI/O = + 2.7V, IOUT =−0.5mA 2.4 V(min)
VDI/O = + 4.5V, IOUT =−1.6mA 0.4 V(max)
VOL Logical "0" Output Voltage VDI/O = + 2.7V, IOUT =−1.6mA 0.4 V(max)
VOUT = DGND −10 µA
IOZ TRI-STATE Output Current VOUT = VD10 µA
Output Short Circuit Current VDI/O = 3V ±12 mA
IOS VDI/O = 5V ±25 mA
Power Supply Characteristics
PD = LOW, Ref not included 14.5
IAAnalog Supply Current 16 mA(max)
PD = HIGH, Ref not included 0.5
PD = LOW, Ref not included 5
ID+ IDI/O Digital Supply Current 6mA(max)
PD = HIGH, Ref not included 0.2
PDPower Consumption 98 110 mW (max)
(1) The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes above VAor below AGND by more than 300 mV. See Figure 1,
Figure 2 and Figure 3.
(2) Typical figures are at TA= TJ= 25°C, and represent most likely parametric norms.
(3) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
AC ELECTRICAL CHARACTERISTICS
The following specifications apply for VA= +5.0VDC, VDI/O = 5.0VDC, VREF+ = +3.5VDC, VREF−= +1.5VDC, fCLK = 20MHz, trc = tfc
= 5ns, RS= 25Ω. CL(data bus loading) = 20 pF, Boldface limits apply for TA= TMIN to TMAX:all other limits TA= 25°C(1)
Units
Symbol Parameter Conditions Typical(2) Limits(3) (Limits)
fCLK1 Maximum Clock Frequency 25 20 MHz(min)
fCLK2 Minimum Clock Frequency 1 MHz(max)
tCH Clock High Time 23 ns(min
tCL Clock Low Time 23 ns(min)
45 %(min)
Duty Cycle 50 55 %(max)
Pipeliine Delay (Latency) 2.0 Clock Cycles
trc, tfc Clock Input Rise and Fall Time 5ns(max)
tr, tfOutput Rise and Fall Times 10 ns
tOD Fall of CLK to data valid 20 25 ns(max)
tOH Output Data Hold Time 12 ns
(1) The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes above VAor below AGND by more than 300 mV. See Figure 1,
Figure 2 and Figure 3.
(2) Typical figures are at TA= TJ= 25°C, and represent most likely parametric norms.
(3) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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AC ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for VA= +5.0VDC, VDI/O = 5.0VDC, VREF+ = +3.5VDC, VREF−= +1.5VDC, fCLK = 20MHz, trc = tfc
= 5ns, RS= 25Ω. CL(data bus loading) = 20 pF, Boldface limits apply for TA= TMIN to TMAX:all other limits TA= 25°C(1)
Units
Symbol Parameter Conditions Typical(2) Limits(3) (Limits)
From output High, 2K to 25 ns
Ground
tDIS Rising edge of OE to valid data From output Low, 2K to 18 ns
VDI/O
tEN Falling edge of OE to valid data 1K to VCC 25 ns
tVALID Data valid time 40 ns
tAD Apeture Delay 4 ns
tAJ Aperture Jitter <30 ps
Full Scale Step Response tr= 10ns 1 conversion
VIN step from (VREF+
Overrange Recovery Time 1 conversion
+100mV) to (VREF−)
PD low to 1/2 LSB accurate conversion
tWU 700 ns
(Wake-Up time)
Figure 1. Figure 2. Figure 3.
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TYPICAL PERFORMANCE CHARACTERISTICS
VA= VD= VDI/O = 5V, fCLK = 20MHz, unless otherwise specified.
Typical INL INL vs fCLK
Figure 4. Figure 5.
INL vs VAINL vs Clock Duty Cycle
Figure 6. Figure 7.
Typical DNL DNL vs fCLK
Figure 8. Figure 9.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA= VD= VDI/O = 5V, fCLK = 20MHz, unless otherwise specified.
DNL vs VADNL vs Clock Duty Cycle
Figure 10. Figure 11.
SINAD & ENOB vs Temperature and fIN SINAD & ENOB vs VA
Figure 12. Figure 13.
SINAD & ENOB vs fCLK and fIN IA+ IDvs. Temperature
Figure 14. Figure 15.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA= VD= VDI/O = 5V, fCLK = 20MHz, unless otherwise specified.
Spectral Response at 20 MSPs
Figure 16.
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SPECIFICATION DEFINITIONS
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input
noise.
APERTURE DELAY See Sampling Delay.
DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a given amplitude
small signal, high frequency sine wave input at two different dc input levels.
DIFFERENTIAL PHASE ERROR is the difference in the output phase of a small signal sine wave input at two
different dc input levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio (S/N+D or SINAD). ENOB is defined as (SINAD −1.76) / 6.02.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its 1MHz value for a full scale input. The test is performed with fIN equal to 100 kHz plus
integral multiples of fCLK. The input frequency at which the output is −3 dB relative to the1MHz input signal is the
full power bandwidth.
FULL SCALE (FS) INPUT RANGE of the ADC is the input range of voltages over which the ADC will digitize that
input. For VREF+ = 3.50V and VREF−= 1.50V, FS = (VREF+) −(VREF−) = 2.00V.
FULL SCALE OFFSET ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below
VREF+ and is defined as V1023 −1.5 LSB −VREF+ , where V1023 is the voltage at which the transitions from code
1022 to 1023 occurs.
FULL SCALE STEP RESPONSE is defined as the time required after VIN goes from VREF−to VREF+, or VREF+ to
VREF−, and settles sufficiently for the converter to recover and make a conversion with its rated accuracy.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (1½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
OUTPUT DELAY is the time delay after the fall of the input clock before the data update is present at the output
pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the fall of the input clock.
OVER RANGE RECOVERY TIME is the time required after VIN goes from AGND to VREF+ or VIN goes from VAto
VREF−for the converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output driver stage. Data for any given sample is available by the Pipeline Delay plus the
Output Delay after that sample is taken. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
PSRR (POWER SUPPLY REJECTION RATIO) is the ratio of the change in dc power supply voltage to the
resulting change in Full Scale Error, expressed in dB.
SAMPLING (APERTURE) DELAY or APERTURE TIME is that time required after the fall of the clock input for
the sampling switch to open. The sample is effectively taken this amount of time after the fall of the clock input.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the RMS value of
the input signal to the RMS value of all of the other spectral components below half the clock frequency,
including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB or dBc, between the RMS
values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the
output spectrum that is not present at the input.
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TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic
components, to the rms value of the input signal.
ZERO SCALE OFFSET ERROR is the difference between the ideal input voltage (½ LSB) and the actual input
voltage that just causes a transition from an output code of zero to an output code of one.
Timing Diagram
Figure 17. ADC10321 Timing Diagram
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Figure 18. AC Test Circuit Figure 19. tEN, tDIS Test Circuit
FUNCTIONAL DESCRIPTION
The ADC10321 maintains excellent dynamic performance for input signals up to half the clock frequency. The
use of an internal sample-and-hold amplifier (SHA) enables sustained dynamic performance for signals of input
frequency beyond the clock rate, lowers the converter's input capacitance and reduces the number of external
components required.
The analog signal at VIN that is within the voltage range set by VREF+ S and VREF−S are digitized to ten bits at up
to 25 MSPS. Input voltages below VREF−S will cause the output word to consist of all zeroes. Input voltages
above VREF+ S will cause the output word to consist of all ones. VREF+ S has a range of 2.3 to 4.0 Volts, while
VREF−S has a range of 1.3 to 3.0 Volts. VREF+ S should always be at least 1.0 Volt more positive than VREF−S.
Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital
outputs 2.0 clock cycles plus tOD later. The ADC10321 will convert as long as the clock signal is present at pin 9
and the PD pin is low. The Output Enable pin (OE), when low, enables the output pins. The digital outputs are in
the high impedance state when the OE pin is low or the PD pin is high.
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APPLICATIONS INFORMATION
THE ANALOG INPUT
The analog input of the ADC10321 is a switch (transmission gate) followed by a switched capacitor amplifier. The
capacitance seen at the input changes with the clock level, appearing as about 3pF when the clock is low, and
about 5pF when the clock is high. This small change in capacitance can be reasonably assumed to be a fixed
capacitance. Care should be taken to avoid driving the input beyond the supply rails, even momentarily, as
during power-up.
The LMH6702 has been found to be a good device to drive the ADC10321 because of its low voltage capability,
wide bandwidth, low distortion and minimal Differential Gain and Differential Phase. The LMH6702 performs best
with a feedback resistor of about 100 ohms.
Care should be taken to keep digital noise out of the analog input circuitry to maintain highest noise
performance.
REFERENCE INPUTS
NOTE
Throughout this data sheet reference is made to VREF+ and to VREF−. These refer to the
internal voltage across the reference ladder and are, nominally, VREF+ S and VREF−S,
respectively.
Figure 20 shows a simple reference biasing scheme with minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because the external resistor at pin 2 will have a different
temperature coefficient than the on-chip resistors. Also, the on-chip resistors, while well matched to each other,
will have a large tolerance compared with any external resistors, causing the value of VREF- to be quite variable.
No d.c. current should be allowed to flow through pin 1 or 32 or linearity errors will result near the zero scale and
full scale ends of the signal excursion. The sense pins were designed to be used with high impedance opamp
inputs for high accuracy biasing.
The circuit of Figure 21 is an improvement over the circuit of Figure 20 in that both ends of the reference ladder
are defined with reference voltages. This reduces problems of high reference variability and thermal drift, but
requires two reference sources.
In addition to the usual reference inputs, the ADC10321 has two sense outputs for precision control of the ladder
voltages. These sense outputs (VREF+ S and VREF−S) compensate for errors due to IR drops between the
source of the reference voltages and the ends of the reference ladder itself.
With the addition of two op-amps, the voltages at the top and bottom of the reference ladder can be forced to the
exact value desired, as shown in Figure 22.
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Figure 21. Better low component count reference biasing
The VREF+ F and VREF−F pins should each be bypassed to AGND with 10µF tantalum or electrolytic and 0.1µF
ceramic capacitors. The circuit of Figure 22 may be used if it is desired to obtain precise reference voltages. The
LMC6082 in this circuit was chosen for its low offset voltage, low voltage rail-to-rail capability and low cost.
Since the current flowing through the sense lines (those lines associated with VREF+ S and VREF−S) is
essentially zero, there is negligible voltage drop across any resistance in series with these sense pins and the
voltage at the inverting input of the op-amp accurately represents the voltage at the top (or bottom) of the ladder.
The op-amp drives the force input, forcing the voltage at the ends of the ladder to equal the voltage at the op-
amp's non-inverting input, plus any offset voltage. For this reason, op-amps with low VOS, such as the LMC6081
and LMC6082, should be used for this application.
Voltages at the reference sense pins (VREF+ S and VREF−S) should be within the range specified in the
Operating Ratings table (2.3V to 4.0V for VREF+ and 1.3V to 3.0V for VREF−). Any device used to drive the
reference pins should be able to source sufficient current into the VREF+ F pin and sink sufficient current from the
VREF−F pin when the ladder is at its minimum value of 850 Ohms.
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The reference voltage at the top of the ladder (VREF+) may take on values as low as 1.0V above the voltage at
the bottom of the ladder (VREF−) and as high as (VA- 1.0V) Volts. The voltage at the bottom of the ladder (VREF−)
may take on values as low as 1.3 Volts and as high as 3.0V. However, to minimize noise effects and ensure
accurate conversions, the total reference voltage range (VREF+-VREF−) should be a minimum of 2.0V and a
maximum of 2.7V.
Figure 22. Setting precision reference voltages
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10µF to 50µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 centimeters) of the
A/D power pins, with a 0.1µF ceramic chip capacitor placed as close as possible to each of the converter's power
supply pins. Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source should be used for the analog and digital supplies of the ADC10321, this supply
should not be the supply that is used for other digital circuitry on the board.
As is the case with all high speed converters, the ADC10321 should be assumed to have little high frequency
power supply rejection. A clean analog power source should be used.
No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a
transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits
driving the CLK, PD, OE, analog input and reference pins do not come up any faster than does the voltage at the
ADC10321 power pins.
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THE ADC10321 CLOCK
Although the ADC10321 is tested and its performance is specified with a 20MHz clock, it typically will function
with clock frequencies from 1MHz to 25MHz. Performance is best if the clock rise and fall times are 5ns or less.
If the CLK signal is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the
point where the accuracy of the output data will degrade. This is what limits the minimum sample rate.
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, this device is designed to maintain performance over a range of duty cycles. While it is
specified and performance is specified with a 50% clock duty cycle, performance is typically maintained over a
clock duty cycle range of 45% to 55%.
The clock line should be series terminated at the source end in the characteristic impedance of that line. Use a
series resistor right after the source such that the source impedance plus that series resistor equals the
characteristic impedance of the clock line. This resistor should be as close to the source as possible, but in no
case should it be further away than
where
• tris the rise time of the clock signal
• tPR is the propagation rate down the board. (1)
For a Board of FR-4 material, tPR is typically about 150 ps/inch.
To maintain a consistent impedance along the clock line, use stripline or microstrip techniques (see Application
Note AN-1113 [SNLA011]) and avoid the use of through-holes in the line.
It might also be necessary to terminate the ADC end of the clock line with a series RC to ground such that the
resistor value equals the characteristic impedance of the clock line and the capacitor value is
where
• tPR is again the propagation rate down the clock line
• L is the length of the line in inches
• ZOis the characteristic impedance of the clock line (2)
LAYOUT AND GROUNDING
Proper routing of all signals and proper ground techniques are essential to ensure accurate conversion. Separate
analog and digital ground planes are required to meet data sheet limits. The analog ground plane should be low
impedance and free of noise form other parts of the system.
Each bypass capacitor should be located as close to the appropriate converter pin as possible and connected to
the pin and the appropriate ground plane with short traces. The analog input should be isolated from noisy signal
traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor)
connected between the converter's input and ground should be connected to a very clean point in the analog
ground return.
Figure 23 gives an example of a suitable layout, including power supply routing, ground plane separation, and
bypass capacitor placement. All analog circuitry (input amplifiers, filters, reference components, etc.) should be
placed on or over the analog ground plane. All digital circuitry and I/O lines should be over the digital ground
plane.
Digital and analog signal lines should never run parallel to each other in close proximity with each other. They
should only cross each other when absolutely necessary, and then only at 90° angles. Violating this rule can
result in digital noise getting into the input, which degrades accuracy and dynamic performance (THD, SNR,
SINAD).
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Figure 23. An acceptable layout pattern
DYNAMIC PERFORMANCE
The ADC10321 is ac tested and its dynamic performance is specified. To meet the published specifications, the
clock source driving the CLK input must be free of jitter. For best ac performance, isolating the ADC clock from
any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 24
Meeting dynamic specifications is also dependent upon keeping digital noise out of the input, as mentioned in
THE ANALOG INPUT and LAYOUT AND GROUNDING sections.
Figure 24. Isolating the ADC clock from digital circuitry
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 300mV beyond the supply pins. Exceeding these limits on even a transient basis can cause
faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to
exhibit undershoot that goes more than a volt below ground. A resistor of 50 to 100Ωin series with the offending
digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the ADC10321 (or any device) with a device that is powered
from supplies outside the range of the ADC10321 supply. Such practice may lead to conversion inaccuracies and
even to device damage.
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Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers has to
charge for each conversion, the more instantaneous digital current is required from VDand DGND. These large
charging current spikes can couple into the analog section, degrading dynamic performance. Adequate
bypassing and maintaining separate analog and digital ground planes will reduce this problem on the board.
Buffering the digital data outputs (with an 74F541, for example) may be necessary if the data bus to be driven is
heavily loaded. Dynamic performance can also be improved by adding series resistors of 47Ωat each digital
output.
Driving the VREF+ F pin or the VREF−F pin with devices that can not source or sink the current required
by the ladder. As mentioned in REFERENCE INPUTS, be careful to see that any driving devices can source
sufficient current into the VREF+ F pin and sink sufficient current from the VREF−F pin. If these pins are not driven
with devices than can handle the required current, they will not be held stable and the converter output will
exhibit excessive noise.
Using a clock source with excessive jitter. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate.
Using the same voltage source for VDand other digital logic. As mentioned in POWER SUPPLY
CONSIDERATIONS, VDshould use the same power source used by VA, but should be decoupled from VA.
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REVISION HISTORY
Changes from Revision E (May 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC10321CIVT NRND LQFP NEY 32 250 TBD Call TI Call TI -40 to 85 ADC10321
CIVT
ADC10321CIVT/NOPB ACTIVE LQFP NEY 32 250 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 85 ADC10321
CIVT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
VF0032A
www.ti.com
VBE32A (Rev F)
TYPICAL
NEY0032A
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