CY7C1019D
1-Mbit (128 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05464 Rev. *G Revised May 2, 2011
1-Mbit (128 K × 8) Static RAM
Features
■Pin- and function-compatible with CY7C1019B
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 80 mA @ 10 ns
■Low CMOS standby power
❐ISB2 = 3 mA
■2.0 V Data retention
■Automatic power-down when deselected
■CMOS for optimum speed/power
■Center power/ground pinout
■Easy memory expansion with CE and OE options
■Functionally equivalent to CY7C1019B
■Available in Pb-free 32-pin 400-Mil wide Molded SOJ and
32-pin TSOP II packages
Functional Description [1]
The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected. The eight input and output pins
(IO0 through IO7) are placed in a high-impedance state when:
■Deselected (CE HIGH)
■Outputs are disabled (OE HIGH)
■When the write operation is active (CE LOW, and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is
then written into the location specified on the address pins (A0
through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appears on the IO pins.
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A10
A11
A12
A13
A14
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A15
A16
Logic Block Diagram
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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Document #: 38-05464 Rev. *G Page 2 of 15
Contents
Pin Configuration .............................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
Switching Characteristics ................................................6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................7
Switching Waveforms ...................................................... 7
Read Cycle No. 1 (Address Transition Controlled) .....7
Read Cycle No. 2 (OE Controlled) .............................. 7
Write Cycle No. 1 (CE Controlled) ............................... 8
Write Cycle No. 2 (WE Controlled,
OE HIGH During Write) ...................................................... 8
Write Cycle No. 3 (WE Controlled, OE LOW) ............. 9
Truth Table ........................................................................ 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
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CY7C1019D
Document #: 38-05464 Rev. *G Page 3 of 15
Pin Configuration
Selection Guide
-10 (Industrial) Unit
Maximum Access Time 10 ns
Maximum Operating Current 80 mA
Maximum Standby Current 3 mA
Top View
SOJ/TSOPII
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
IO
0
IO
1
V
CC
A
13
A
16
A
15
OE
IO
7
IO
6
A
12
A
11
A
10
A
9
IO
2
A
0
A
4
A
5
A
6
IO
4
V
CC
IO
5
A
8
IO
3
WE
V
SS
A
14
V
SS
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CY7C1019D
Document #: 38-05464 Rev. *G Page 4 of 15
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Supply Voltage on VCC to Relative GND [2] ..–0.5 V to +6.0 V
DC Voltage Applied to Outputs
in High Z State [2] ................................. –0.5 V to VCC + 0.5 V
DC Input Voltage [2] ............................. –0.5 V to VCC + 0.5 V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40 C to +85 C 5 V 0.5 V 10 ns
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
-10 (Industrial)
Unit
Min Max
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 – V
VOL Output LOW Voltage IOL = 8.0 mA – 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage [2] –0.5 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 A
IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 A
ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz – 80 mA
83 MHz – 72 mA
66 MHz – 58 mA
40 MHz – 37 mA
ISB1 Automatic CE Power-Down
Current—TTL Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL,
f = fmax
–10mA
ISB2 Automatic CE Power-Down
Current—CMOS Inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–3mA
Note
2. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
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Document #: 38-05464 Rev. *G Page 5 of 15
Capacitance [3]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 C, f = 1 MHz, VCC = 5.0 V 6 pF
COUT Output Capacitance 8 pF
Thermal Resistance [3]
Parameter Description Test Conditions 400-Mil
Wide SOJ TSOP II Unit
JA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
56.29 62.22 C/W
JC Thermal Resistance
(Junction to Case)
38.14 21.43 C/W
Figure 1. AC Test Loads and Waveforms [4]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: 3 ns Fall Time: 3 ns
30 pF*
OUTPUT
Z = 50
50
1.5V
(b)
(a)
5 V
OUTPUT
5 pF
(c)
R1 480
R2
255
High Z characteristics:
INCLUDING
JIG AND
SCOPE
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 1 (c).
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Document #: 38-05464 Rev. *G Page 6 of 15
Switching Characteristics
Over the Operating Range[5]
Parameter Description -10 (Industrial) Unit
Min Max
Read Cycle
tpower [6] VCC(typical) to the first access 100 – s
tRC Read Cycle Time 10 – ns
tAA Address to Data Valid – 10 ns
tOHA Data Hold from Address Change 3 – ns
tACE CE LOW to Data Valid – 10 ns
tDOE OE LOW to Data Valid – 5 ns
tLZOE OE LOW to Low Z 0 – ns
tHZOE OE HIGH to High Z [7, 8] –5ns
tLZCE CE LOW to Low Z [8] 3–ns
tHZCE CE HIGH to High Z [7, 8] –5ns
tPU [9] CE LOW to Power-Up 0 – ns
tPD [9] CE HIGH to Power-Down – 10 ns
Write Cycle [10, 11]
tWC Write Cycle Time 10 – ns
tSCE CE LOW to Write End 7 – ns
tAW Address Set-Up to Write End 7 – ns
tHA Address Hold from Write End 0 – ns
tSA Address Set-Up to Write Start 0 – ns
tPWE WE Pulse Width 7 – ns
tSD Data Set-Up to Write End 6 – ns
tHD Data Hold from Write End 0 – ns
tLZWE WE HIGH to Low Z [8] 3–ns
tHZWE WE LOW to High Z [7, 8] –5ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of Figure 1 on page 5. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Max Unit
VDR VCC for Data Retention 2.0 – V
ICCDR Data Retention Current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
–3mA
tCDR [12] Chip Deselect to Data Retention Time 0 – ns
tR [13] Operation Recovery Time tRC –ns
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [14, 15]
Read Cycle No. 2 (OE Controlled) [15, 16]
4.5 V4.5 V
tCDR
VDR > 2 V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
14. Device is continuously selected. OE, CE = VIL.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW..
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Document #: 38-05464 Rev. *G Page 8 of 15
Write Cycle No. 1 (CE Controlled) [17, 18]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
WE
DATA IO
ADDRESS
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
NOTE 19
CE
ADDRESS
WE
DATA IO
OE
Notes
17. Data IO is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. During this period the IOs are in the output state and input signals should not be applied.
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Document #: 38-05464 Rev. *G Page 9 of 15
Write Cycle No. 3 (WE Controlled, OE LOW) [20, 21]
Truth Table
CE OE WE IO0–IO7Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
NOTE 22
CE
ADDRESS
WE
DATA IO
Notes
20. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
22. During this period the IOs are in the output state and input signals should not be applied.
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CY7C1019D
Document #: 38-05464 Rev. *G Page 10 of 15
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1019D-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1019D-10ZSXI 51-85095 32-pin TSOP Type II (Pb-free)
Ordering Code Definitions
Please contact your local Cypress sales representative for availability of these parts.
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Document #: 38-05464 Rev. *G Page 11 of 15
Package Diagrams
Figure 2. 32-pin (400-Mil) Molded SOJ (51-85033)
51-85033 *D
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Document #: 38-05464 Rev. *G Page 12 of 15
Figure 3. 32-pin TSOP Type II (51-85095)
Package Diagrams (continued)
51-85095 *B
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Document #: 38-05464 Rev. *G Page 13 of 15
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE Output Enable
SOJ small outline J-lead
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
µA micro Amperes
µs micro seconds
MHz Mega Hertz
mA milli Amperes
ms milli seconds
mm milli meter
ns nano seconds
ohms
pF pico Farad
VVolts
WWatts
% percent
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Document #: 38-05464 Rev. *G Page 14 of 15
Document History Page
Document Title: CY7C1019D, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05464
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in the Ordering Information
*B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table
Added Data Retention Characteristics table and waveforms
Shaded Ordering Information
*C 307598 See ECN RKF Reduced Speed bins to -10 and -12 ns
*D 520647 See ECN VKN Converted from Preliminary to Final
Removed Commercial Operating range
Removed 12 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2
*E 802877 See ECN VKN Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA
for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
*F 3110052 12/14/2010 AJU Added Ordering Code Definitions.
Updated Package Diagrams.
*G 3245896 05/02/2011 PRAS Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
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Document #: 38-05464 Rev. *G Revised May 2, 2011 Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1019D
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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