Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e * First Actel FPGA Designed Specifically for Space Applications * Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity (LET th > 40, GEO SEU Rate < 10-10 upset/bit-day) * Up to 100 krad (Si) Total Ionizing Dose (TID) Parametric Performance Supported with Lot-Specific Test Data * Single Event Latch-Up Immunity * Pin Compatibility Allows Prototyping with Commercial SX-A and Mission Implementation with Radiation-Tolerant RT54SX-S * Deterministic Power-Up with Support for Hot-Swapping Capabilities * Cold-Sparing Capability * Devices Available from TM1019.5-tested Pedigreed Lots * Slow Slew Rate Option * QML Certified Devices * Secure Programming Technology Prevents Reverse Engineering and Design Theft * Configurable Weak Resistor Pull-up or Pull-down for Tristated Outputs at Power-Up * 100% Circuit Resource Utilization with 100% Pin Locking * Unique In-System Diagnostic and Verification Capability with Silicon Explorer II * Dedicated JTAG Reset (TRST) Pin * Deterministic, User-Controllable Timing * JTAG Boundary Scan Testing In Compliance with IEEE Standard 1149.1 * 0.25m Metal-to-Metal Antifuse Process Generation L e ad i n g E d ge P e r fo r m a nc e * 230 MHz System Performance * 8.7 ns Input Clock to Output Pad * 310 MHz Internal Performance S ta n d ar d F e at u re s * Very Low Power Consumption (Up to 68 mW at Standby) * Configurable I/O Support for 3.3V/5V PCI, LVTTL, TTL, and CMOS * 3.3V and 5V Mixed Voltage Operation with 5V Input Tolerance and 5V Drive Strength S p ec i f i c a ti o n s * 48,000 to 108,000 Available System Gates * Up to 227 User-Programmable I/O Pins (package dependent) R T 5 4 SX - S P r od u c t P r o fi l e Device RT54SX32S RT54SX72S Capacity Typical Gates System Gates 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells SEU Hardened Register Cells (Dedicated Flip-Flops) 2,880 1,800 1,080 6,036 4,024 2,012 Maximum Flip-Flops 1,980 4,024 Maximum User I/Os 227 212 Clocks 3 3 Quadrant Clocks 0 4 Clock-to-Out Delay 8.7 ns 11.0 ns Input Set-Up Time (External) -1.3 ns -3.3 ns Speed Grades Std, -1 Std, -1 208, 256 208, 256 624 Package (by pin count) CQFP CCGA 1 November 2002 (c) 2002 Actel Corporation *See Actel's website for the latest version of the datasheet. This datasheet is web-only. R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s O r d er i n g In f or m a t i o n RT54SX32S - 1 CQ 256 B Application (Temperature Range) B = MIL-STD-883 Class B E = E-Flow (Actel Space Level Flow) Package Lead Count Package Type CQ = Ceramic Quad Flat Pack CG = Ceramic Column Grid Array Speed Grade Blank = Standard Speed 1 = -1 Approximately 15% Faster than Standard Part Number RT54SX32S = 32,000 Typical Gates--RadTolerant RT54SX72S = 72,000 Typical Gates--RadTolerant P ro d u ct P l a n Speed Grade Application Std -1* B E 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Column Grid Array (CCGA) P P RT54SX32S Devices RT54SX72S Devices Contact your Actel sales representative for product availability. Applications: B = MIL-STD-883 Class B = Available * Approximately 15% Faster than Standard E = E-flow (Actel Space Level Flow) P = Planned Ceramic Device Resources User I/Os (including clock buffers) CQFP 208-Pin CQFP 256-Pin CCGA 624-Pin RT54SX32S 173 227 - RT54SX72S 170 212 TBD Device 2 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s Radiation Survivability The RadTolerant SX-S devices have varying total dose radiation survivability. The ability of these devices to survive radiation effects is both device and lot dependent. The user must evaluate and determine the applicability of these devices to their specific design and environmental requirements. Total dose results are summarized in two ways. The first summary is indicated by the maximum total dose level achieved before the device fails to meet an individual performance specification, but remains functional. For Actel FPGAs, the parameter that first exceeds the specification is ICC (standby supply current). The second summary is indicated by the maximum total dose achieved prior to the functional failure of the device. R T 5 4 S X - S - A N e w D e s i gn f or S p a ce A p p l i c a ti o n s The architecture of the RT54SX-S devices is an enhanced version of Actel's SX-A device architecture. For more information about the SX-A device architecture, see the "Background on the Family Architecture" section on page 5. Featuring SEU hardened D flip-flops that offer the benefits of Triple Module Redundancy (TMR), the RT54SX-S family is a unique product offering for space applications. The RT54SX-S devices are manufactured using a 0.25m technology at the Matsushita (MEC) facility in Japan. These devices offer levels of radiation survivability far in excess of typical CMOS devices. S E U H ar d e ne d D F F D e s cr i pt i on Actel provides total dose radiation test data on each lot offered for sale. Reports are available on our website or from Actel's local sales representatives. Listings of available lots and devices can also be provided. In order to meet the stringent SEU requirements of a LET th greater than 40MeV-gm/cm2, the internal design of the R-cell was modified without changing the functionality of the cell. Figure 1 shows basic R-cell functionality. For a radiation performance summary, see Radiation Performance of Actel Products at http://www.actel.com/hirel. This summary also shows single event upset (SEU) and single event latch-up (SEL) testing that has been performed on Actel FPGAs. Figure 2 illustrates a simplified representation of how the D flip-flop in the R-cell is implemented in the SX-A architecture. The flip-flop consists of a master and a slave latch gated by opposite edges of the clock. Each latch is constructed by feeding back the output to the input stage. The potential problem in a space environment is that either of the latches can change state when hit by a particle with enough energy. All radiation performance information is provided for information purposes only and is not guaranteed. Total dose effects are lot-dependent, and Actel does not guarantee that future devices will continue to exhibit similar radiation characteristics. In addition, actual performance can vary widely due to a variety of factors including, but not limited to, characteristics of the orbit, radiation environment, proximity to the satellite exterior, the amount of inherent shielding from other sources within the satellite and actual bare die variations. For these reasons, it is solely the responsibility of the user to determine whether the device will meet the requirements of the specific design. Q M L C e r t i f ic a t i o n Actel has achieved full QML certification demonstrating that quality management procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated circuits. QML certification is a good example of Actel's commitment to supplying the highest quality products for all types of high-reliability, military, and space applications. Many suppliers of microelectronic components have implemented QML as their primary worldwide business system. Appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for high quality, reliable, and cost-effective logistics support throughout QML products' life cycles. S0 Routed Data Input S1 PRE Direct Connect Input D HCLK CLKA, CLKB, Internal Logic Q Y CLR CKS CKP Figure 1 * R-Cell Functional Diagram Q D CLK CLK Figure 2 * SX-A R-Cell Implementation of D Flip-Flop Advanced v1.4 3 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s To achieve the SEU requirements, the D flip-flop in the RT54SX-S R-cell is enhanced (Figure 3). Both the master and slave "latches" are actually implemented with three latches. The feedback path of each of the three latches is voted with the outputs of the other two latches. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. Care was taken in the layout to ensure that a single ion strike could not affect more than one latch. Figure 4 is a simplified schematic of the test circuitry that has been added to test the functionality of all the components of the flip-flop. The inputs to each of the three latches are independently controllable so the voting circuitry in the feedback paths can be exhaustively tested. This testing is performed on an unprogrammed array during wafer sort, final test and post burn-in test. This test circuitry cannot be used to test the flip-flops once the device has been programmed. Q D CLK CLK Voter Gate CLK CLK CLK CLK CLK CLK Figure 3 * RT54SX-S R-Cell Implementation of D Flip-Flop Using Voter Gate Logic Q D Tst1 Voter Gate Tst2 Tst3 CLK Test Circuitry Figure 4 * R-Cell Implementation-- Test Circuitry 4 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s B a c kg r o un d o n th e F a m i l y A r ch i t e ct u r e The RT54SX-S architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of high reliability applications. P r o g r a m m a b l e I n t e r c o nn e ct E le m e nt The RT54SX-S family incorporates up to three layers of metal interconnect (four metal layers in RT54SX72S) and provides efficient use of silicon by locating the routing interconnect resources between the top two metal layers (Figure 5). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the RT54SX-S family abundant routing resources and provides excellent protection against design theft. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses. Additionally, since RT54SX-S is a nonvolatile, single-chip solution, there is no configuration bitstream to intercept. The RT54SX-S interconnect (i.e., the antifuses and metal tracks) also has lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry for the radiation tolerance offered. Routing Tracks Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Via Metal 4 Metal 3 Tungsten Plug Via Metal 2 Metal 1 Tungsten Plug Contact Silicon Substrate Note: RT54SX72S has four layers of metal with the antifuse between Metal 3 and Metal 4. RT4SX32S has three layers of metal with antifuse between Metal 2 and Metal 3. Figure 5 * RT54SX-S Family Interconnect Elements Advanced v1.4 5 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s Logic Module Design The RT54SX-S family architecture is described as a "sea-of-modules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Actel's RT54SX-S family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 1 on page 3). The R-cell registers feature programmable clock polarity, selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the RT54SX-S FPGA. The clock source for the R-cell can be chosen from the hard-wired clock, the routed clocks, or the internal logic. The C-cell implements a range of combinatorial functions up to 5 inputs (Figure 6). Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options (as in previous architectures) to more than 4,000 in the RT54SX-S architecture. An example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions. At the same time, the C-cell structure is extremely synthesis-friendly, simplifying the overall design and reducing synthesis time. D0 D1 Y D2 D3 Sa Sb DB A0 B0 A1 B1 Figure 6 * C-Cell Chip Architecture The RT54SX-S family's chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. M od u le O r g an iz a t io n Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 7 on page 7). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. RT54SX-S devices feature more SuperCluster 1 modules than 6 SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. Routing Resources Clusters and SuperClusters can be connected through the use of two innovative new local routing resources called FastConnect and DirectConnect which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (see Figure 8 on page 7 and Figure 9 on page 8). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1ns. Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s R-Cell S0 C-Cell D0 Routed Data Input S1 D1 PRE Y D2 Direct Connect Input D Q Y D3 Sa Sb HCLK CLR CLKA, CLKB, Internal Logic DB CKS CKP Cluster 1 A0 Cluster 1 Cluster 2 Type 1 SuperCluster B0 A1 B1 Cluster 1 Type 2 SuperCluster Figure 7 * Cluster Organization DirectConnect * No antifuses for smallest routing delay FastConnect * One antifuse Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 1 SuperClusters Figure 8 * DirectConnect and FastConnect for Type 1 SuperClusters Advanced v1.4 7 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s DirectConnect * No antifuses for smallest routing delay FastConnect * One antifuse Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 2 SuperClusters Figure 9 * DirectConnect and FastConnect for Type 2 SuperClusters FastConnect enables horizontal routing between any two logic modules within a given SuperCluster, and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum interconnect propagation delay of 0.4 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays. Clock Resources Actel's high-drive routing structure provides three clock networks (Table 1). The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 8.7 ns clock-to-out (pad-to-pad) performance of the RT54SX-S devices. The hard-wired clock is tuned to provide clock skew of less than 0.3 ns worst case. If not used, this pin must be set as LOW or HIGH on the board. It must not be left floating. Figure 10 shows the clock circuit used for the constant load HCLK. 8 Table 1 * RT54SX-S Clock Resources RT54SX32S RT54SX72S Routed Clocks (CLKA, CLKB) 2 2 Hardwired Clocks (HCLK) 1 1 Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 0 4 Constant Load Clock Network HCLKBUF Figure 10 * RT54SX-S HCLK Clock Pad The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the RT54SX-S device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB pins are not used or sourced from signals, then these pins must be set as LOW or HIGH on the board. They must not be left floating (except in HiRel A54SX72A, where these clocks can be configured as regular I/Os). Figure 11 on page 9 describes the CLKA and CLKB circuit used in RT54SX32S where these clocks can be used as I/Os. Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s Clock Network From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI In addition, the RT54SX72S device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD), which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. If QCLKs are not used as quadrant clocks, they will behave as regular I/Os. The CLKA, CLKB, and QCLK circuits for RT54SX72S are shown in Figure 12. For more information, refer to the "Pin Description" section on page 35. Figure 11 * RT54SX-S Routed Clock Structure (excluding RT54SX72S) OE From Internal Logic Clock Network CLKBUF CLKBUFI CLKINT CLKINTI CLKBIBUF CLKBIBUFI From Internal Logic QCLKBUF QCLKBUFI QCLKINT QCLKINTI QCLKBIBUF QCLKBIBUFI Figure 12 * RT54SX72S Routed Clock and QClock Structure O t h er A r c h i te c t ur a l F e at u re s T e c hn o log y I/O Modules Actel's RT54SX-S family is implemented in high-voltage twin-well CMOS using 0.25m design rules. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals, and has a programmed ("on" state) resistance of 25 with capacitance of 1.0 fF for low signal impedance. Each I/O on a RT54SX-S device can be configured as an input, an output, a tristate output, or a bidirectional pin. Mixed I/O standards are allowed and can be set on an individual basis. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-output-pad timing as fast as 8.7 ns. In most FPGAs, I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in RT54SX-S FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn, enables parallel design of system components and reduces overall design time. All unused I/Os are configured as tristate outputs by Designer software. Each I/O module has an available power-up resistor of approximately 50 k that can configure the I/O to a known state during power up. Just slightly before VCCA reaches 2.5V, the resistors are disabled, so the I/Os will behave normally. For more information about the power-up resistors, please see Actel's application note P e r f o r m an c e The combination of architectural features described above enables RT54SX-S devices to operate with internal clock frequencies up to 310 MHz, enabling very fast execution of even complex logic functions. Thus, the RT54SX-S family is an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an RT54SX-S device with dramatic improvements in cost and time-to-market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance. Advanced v1.4 9 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s SX-A and RT54SX-S Devices in Hot-Swap and Cold Sparing Applications. See Table 2 and Table 3 for more information concerning I/O features. RT54SX-S inputs should be driven by high-speed push-pull devices with a low-resistance pull-up device. If the input voltage is greater than VCCI and a fast push-pull device is NOT used, the high-resistance pull-up of the driver and the internal circuitry of the RT54SX-S I/O may create a voltage divider. This voltage divider could pull the input voltage below spec for some devices connected to the driver. A logic `1' may not be correctly presented in this case. For example, if an open drain driver is used with a pull-up resistor to 5V to provide the logic `1' input, and VCCI is set to 3.3V on the RT54SX-S device, the input signal may be pulled down by the RT54SX-S input. Hot Swapping RT54SX-S I/Os can be configured to be hot swappable in compliance with Compact PCI Specification. However, a 3.3V PCI device is not hot swappable. During power up/down, all I/Os are tristated. VCCA and VCCI do not have to be stable during power up/down. After the RT54SX-S device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip operating conditions are reached. Table 4 summarizes the VCCA voltage at which the I/Os behave according to the user's design for a RT54SX-S device at room temperature for various ramp-up rates. The data reported assumes a linear ramp-up profile to 2.5V. Refer to Actel's application note, Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications for more information on hot swapping. Table 2 * I/O Features Function Description Input Buffer Threshold Selections * 5V: CMOS, PCI,TTL Flexible Output Driver * 3.3V: PCI, LVTTL * 5V: CMOS, PCI,TTL Output Buffer * 3.3V: PCI, LVTTL "Hot-Swap" Capability * I/O on an unpowered device does not sink current (Power supplies are at 0V) * Can be used for "cold sparing" Selectable on an individual I/O basis Individually selectable slew rate, high slew or low slew (The default is high slew rate). The slew is only affected on the falling edge of an output. No slew is changed on the rising edge of the output or any inputs. Individually selectable pull-ups and pull-downs during power up (default is to power up in tristate) Power Up Enables deterministic power up of device VCCA and VCCI can be powered in any order Table 3 * I/O Characteristics for All I/O Configurations TTL, LVTTL 3.3V PCI 5V PCI Hot Swappable Slew Rate Control Yes No Yes Yes. Affects falling edge outputs only Pull up or Pull down No. High slew rate only Pull up or pull down No. High slew rate only Pull up or pull down Power-up Resistor Pull Table 4 * Power-up Time at which I/Os Become Active Ramp Rate 0.25V/s 0.025V/s 5V/ms 2.5V/ms 0.5V/ms 0.25V/ms 0.1V/ms 0.025V/ms Units s s ms ms ms ms ms ms RT54SX32S 10 100 0.46 0.74 2.8 5.2 12.1 47.2 RT54SX72S 10 100 0.41 0.67 2.6 5.0 12.1 47.2 10 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s Power Requirements The RT54SX-S family supports either 3.3V or 5V I/O voltage operation and is designed to tolerate 5V inputs in each case (Table 5). Power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. Power requirements are further reduced due to the small number of antifuses in the path, and because of the low resistance properties of the antifuses. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-powered architecture on the market. Table 5 * Supply Voltages VCCA VCCI 2.5V 3.3V 2.5V 5V *3.3V PCI is not 5V tolerant. RT54SX-S Note: Maximum Input Tolerance Maximum Output Drive 5V* 5V 3.3V 5V B o u n d ar y S c a n T es t i ng ( B S T ) All RT54SX-S devices are IEEE 1149.1 compliant. RT54SX-S devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. The BST function is controlled through the special JTAG pins (TMS, TDI, TCK, TDO, and TRST). The functionality of the JTAG pins is defined by two available modes: Dedicated and Flexible (Table 6). TRST and TMS cannot be employed as user I/Os in either mode. Figure 13 * Device Selection Wizard To enter the Flexible mode, users need to un-check the "Reserve JTAG" box in the "Device Selection Wizard" in Designer. In Flexible mode, TDI, TCK and TDO pins may function as user I/O or BST pins. The functionality is controlled by the BST TAP controller. The TAP controller receives two control inputs, TMS and TCK. Upon power up, the TAP controller enters the Test-Logic-Reset state. In this state, TDI, TCK, and TDO function as user I/O. The TDI, TCK, and TDO are transformed from user I/O into BST pins when a rising edge on TCK is detected while TMS is at logic low. To return to the Test-Logic Reset state, in the absences of TRST assertion, TMS must be high for at least five TCK cycles. An external 10 k pull-up resistor to VCCI should be placed on the TMS pin to pull it HIGH by default. Table 7 describes the different configuration requirements of BST pins and their functionality in different modes. Table 7 * Boundary Scan Pin Configurations and Functionalities Table 6 * Boundary Scan Pin Functionality Program Fuse Blown (Dedicated Test Mode) Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are dedicated BST pins TCK, TDI, TDO are flexible and may be used as I/Os No need for pull-up resistor for TMS Use a pull-up resistor of 10 k on TMS D e d i c a t e d M od e In Dedicated mode, all JTAG pins are reserved for BST; users cannot utilize them as regular I/Os. An internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification. To enter Dedicated mode, users need to reserve the JTAG pins in Actel Designer software. To reserve the JTAG pins, users can check the "Reserve JTAG" box in the "Device Selection Wizard" in Designer (Figure 13). Fl ex ib le M o d e In Flexible mode, TDI, TCK, and TDO may be employed as either user I/O or as JTAG input pins. The internal resistors on the TMS and TDI pins are not present in flexible JTAG mode. Mode Dedicated (JTAG) Flexible (User I/O) Flexible (JTAG) Designer "Reserve JTAG" Selection TAP Controller State Checked Un-Checked Un-Checked Any Test-Logic-Reset Other T R S T P in TRST pin functions as a Dedicated Boundary Scan Reset pin. An internal pull-up resistor is permanently enabled on the TRST pin. Additionally, the TRST pin must be grounded for flight applications. This will prevent Single Event Upsets (SEU) in the TAP controller from inadvertently placing the device into JTAG mode. Probing Capabilities RT54SX-S devices also provide internal probing capability that is accessed with the JTAG pins. The Silicon Explorer Diagnostic Hardware is used to control the TDI, TCK, TMS and TDO pins to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the BST pins are in JTAG mode and the TRST pin is driven HIGH. If the TRST pin is held LOW, the TAP controller will remain in the Test-Logic-Reset state so no probing can be Advanced v1.4 11 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s performed. Silicon Explorer II automatically places the device into JTAG mode, but the user must drive the TRST pin HIGH or allow the internal pull-up resistor to pull TRST HIGH. I/Os to achieve successful layout, then the tool will employ these pins for user I/Os. If you assign user I/Os to the PRA and PRB pins and select the "Reserve Probe" option, Designer Layout will override the "Reserve Probe" option and place your user I/Os on those pins. When selecting the "Reserve Probe" box as shown in Figure 13 on page 11, the user direct the layout tool to reserve the PRA and PRB pins as dedicated outputs for probing. This "reserve" option is merely a guideline. If the Layout tool requires that the PRA and PRB pins to be user To allow probing capabilities, the security fuse must not be programmed. Programming the security fuse will disable the probe circuitry. Table 8 summarizes the possible device configurations for probing. Table 8 * Device Configuration Options for Probe Capability JTAG Mode TRST Security Fuse Programmed PRA, PRB, TDO1 TDI and TCK1 Dedicated LOW No User I/O2 Probing Unavailable I/O2 LOW No Dedicated HIGH No Probe Circuit Outputs Probe Circuit Inputs Flexible HIGH No Probe Circuit Outputs Probe Circuit Inputs - Yes Probe Circuit Secured Probe Circuit Secured - User User I/O2 Flexible Notes: 1. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports during probing. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by the Designer software. Development Tool Support RT54SX-S devices are fully supported by Actel's line of FPGA development tools, including Actel's Designer software and Actel Libero Integrated Design Environment (IDE), the FPGA design tool suite. Designer Software, Actel's suite of FPGA development tools for PCs and Workstations, includes the ACTgen Macro Builder, timing driven place-and-route, timing analysis tools, and fuse file generation. Libero IDE is a design management environment that integrates the needed design tools, streamlines the design flow, manages all design and log files, and passes necessary design data between tools. Libero IDE includes, Synplify, ViewDraw, Actel's Designer Software, ModelSim HDL Simulator, WaveFormer Lite, and Actel's Silicon Explorer II. R T 5 4 S X - S P r o b e C i r c u i t C on t r o l P i n s The RT54SX-S RadTolerant devices contain internal probing circuitry that provides built-in access to every node in a design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy to use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18 channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. 12 The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS, and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 14 on page 13 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification. D e s i g n C o n s i d e r a t i on s Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, critical input signals through these pins are not available. In addition, do not program the Security Fuse. Programming the Security Fuse disables the Probe Circuit. Actel recommends that you use a series 70 termination resistor on every probe connector (TDI, TCK, TMS, TDO, PRA, PRB). The 70 series termination is used to prevent data transmission corruption during probing and reading back the checksum. Advanced v1.4 Additional Channels 16 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s TDI TCK Serial Connection Silicon Explorer II TMS 70 RT54SX-S FPGA 70 70 70 TDO 70 PRA 70 PRB Figure 14 * Probe Setup 2 . 5V / 3 . 3V / 5V O p e ra t i n g C o n di t i o n s R e c om m e nd e d O pe r a t in g C o nd it ion s A b s ol ut e M a xi m um R at i ng s * Symbol Parameter Limits Units Parameter Range* Military Units -55 to +125 C VCCI DC Supply Voltage -0.3 to +6.0 V Temperature VCCA DC Supply Voltage -0.3 to +3.0 V 2.5V Power Supply Tolerance 2.25 to 2.75 V VI Input Voltage -0.5 to + 6.0 V 3.3V Power Supply Tolerance 3.0 to 3.6 V VO Output Voltage -0.5 to +VCCI + 0.5 V 5V Power Supply Tolerance 4.5 to 5.5 V TSTG Storage Temperature -65 to +150 C Note: Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Advanced v1.4 13 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s 3.3V LVTTL and 5V TTL Electrical Specifications Military Symbol VOH VOL Parameter Min. Max. Units VCCI = MIN, VI = VIH or VIL (IOH = -1mA) 0.9 VCCI V VCCI = MIN, VI = VIH or VIL (IOH = -8mA) 2.4 V VCCI = MIN, VI = VIH or VIL (IOL= 1mA) 0.1 VCCI V VCCI = MIN, VI = VIH or VIL (IOL= 12mA) 0.4 V 0.8 V VIL Input Low Voltage VIH Input High Voltage 2.0 IIL/ IIH Input Leakage Current, VIN = VCCI or GND -20 20 A IOZ 3-State Output Leakage Current, VOUT = VCCI or GND -20 20 A tR, tF Input Transition Time 10 ns CIO I/O Capacitance 10 pF Standby Current 25 mA Max. Units ICC IV 1 Curve2 V Can be derived from the IBIS model on the web. Notes: 1. Individual device data is available in the www.actel.com/guru. 2. The IBIS model can be found at www.actel.com/support/support/support_ibis.html. 5V C MO S E le ct r ic al Sp e ci f ic a t io ns Military Symbol Parameter Min. VOH VCCI = MIN, VI = VCCI or GND (IOH = -20A) VOL VCCI = MIN, VI = VCCI or GND (IOL= 20A) VIL Input Low Voltage, VOUT VVOL(max) VIH Input High Voltage, VOUT VVOH(min) IOZ 3-State Output Leakage Current, VOUT = VCCI or GND tR , tF VCCI - 0.1 V 0.1 V 0.3VCC V 0.7VCC 20 A Input Transition Time 10 ns CIO I/O Capacitance 10 pF ICC1 Standby Current 25 mA IV Curve2 Can be derived from the IBIS model on the web. Notes: 1. Individual device data is available in the www.actel.com/guru. 2. The IBIS model can be found at www.actel.com/support/support/support_ibis.html. 14 Advanced v1.4 -20 V R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s 5 V P C I C o m p l i a n ce f o r t h e R T 5 4S X - S F am i l y The RT54SX-S family supports 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. DC Specifications (5V PCI Operation) Symbol Parameter VCCA VCCI VIH Min. Max. Units Supply Voltage for Array 2.3 2.7 V Supply Voltage for I/Os 4.5 5.5 V 2.0 VCCI + 0.5 V -0.5 0.8 V Input High Condition Voltage1 1 VIL Input Low Voltage IIH Input High Leakage Current VIN = 2.7 70 A IIL Input Low Leakage Current VIN = 0.5 -70 A VOH Output High Voltage IOUT = -2 mA VOL Voltage2 Output Low 2.4 V IOUT = 3 mA, 6 mA Capacitance3 CIN Input Pin CCLK CLK Pin Capacitance 5 0.55 V 10 pF 12 pF Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices, which could be up to 16 pF, in order to accommodate PGA packaging. This would mean, in general, that components for expansion boards would need to use alternatives to ceramic PGA packaging (i.e., PQFP, SGA, etc.). Figure 15 shows the 5V PCI V/I curve and the minimum and maximum PCI drive characteristics of the RT54SX-S family. Figure 15 * 5V PCI Curve for RT54SX-S Family 200.0 IOL MAX Spec IOL 150.0 100.0 Current (mA) IOL MIN Spec 50.0 0.0 0 -50.0 0.5 1 1.5 2 2.5 3 3.5 IOH MIN Spec 4 4.5 5 5.5 6 IOH MAX Spec -100.0 -150.0 -200.0 IOH Voltage Out (V) Equation A Equation B IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45) for VCCI > VOUT > 3.1V IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V Advanced v1.4 15 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s A C S p e ci f ic a t io n s ( 5V PC I O pe r a t i o n ) Symbol Parameter Condition Min. 0 < VOUT 1.4 1 Switching Current High 1.4 VOUT < 2.4 IOH(AC) 1, 2 mA (-44 + (VOUT - 1.4)/0.024) mA Equation A on page 15 VOUT = 3.1 3 -142 VOUT 2.2 1 Switching Current Low IOL(AC) ICL slewR slewF 2.2 > VOUT > 0.55 1 VOUT = 0.71 Low Clamp Current -5 < VIN -1 Output Rise Slew Rate Output Fall Slew Rate mA 95 mA (VOUT/0.023) mA Equation B on page 15 0.71 > VOUT > 0 1, 3 (Test Point) Units -44 3.1 < VOUT < VCCI 1, 3 (Test Point) Max. 206 -25 + (VIN + 1)/0.015 mA mA 0.4V to 2.4V load4 1 5 V/ns 2.4V to 0.4V load4 1 5 V/ns Notes: 1. Refer to the V/I curves in Figure 15 on page 15. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specification is not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective curves in Figure 15 on page 15. The equation defined maximum should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both the maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. pin output buffer 16 50 pF Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s 3 . 3V P C I C o m p l i a n ce f o r t h e R T 5 4S X - S F am i l y The RT54SX-S family supports 3.3V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. DC Specifications (3.3V PCI Operation) Symbol Parameter VCCA Min. Max. Units Supply Voltage for Array 2.3 2.7 V VCCI Supply Voltage for I/Os 3.0 3.6 V VIH Input High Voltage 0.5VCCI VCCI + 0.5 V VIL Input Low Voltage -0.5 0.3VCCI V IIPU Condition Input Pull-up Voltage 1 0.7VCCI Current2 IIL/IIH Input Leakage VOH Output High Voltage IOUT = -500 A VOL Output Low Voltage IOUT = 1500 A V 0 < VIN < VCCI 0.9VCCI V 0.1VCCI V 10 pF 12 pF Capacitance3 CIN Input Pin CCLK CLK Pin Capacitance A 10 5 Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input VIN. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10pF (except for CLK) with an exception granted to motherboard-only devices, which could be up to 16 pF, in order to accommodate PGA packaging. This would mean in general that components for expansion boards would need to use alternatives to ceramic PGA packaging. Figure 16 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the RT54SX-S family. 150.0 IOL MAX Spec IOL Current (mA) 100.0 50.0 IOL MIN Spec 0.0 0 -50.0 0.5 1 1.5 2 2.5 3 3.5 4 IOH MIN Spec IOH MAX Spec IOH -100.0 -150.0 Voltage Out (V) Figure 16 * 3.3V PCI Curve for RT54SX-S Family Equation C Equation D IOH = (98.0/VCCI) * (VOUT - VCCI) * (VOUT + 0.4VCCI) for VCCI > VOUT > 0.7 VCCI Advanced v1.4 IOL = (256/VCCI) * VOUT * (VCCI - VOUT) for 0V < VOUT < 0.18 VCCI 17 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s AC Specifications (3.3V PCI Operation) Symbol Parameter Condition Min. 0 < VOUT 0.3VCCI 1 IOH(AC) Switching Current High 0.3VCCI VOUT < 0.9VCCI 1 mA Equation C on page 17 1 0.6VCCI > VOUT > 0.1VCCI 1 VOUT = 0.18VCC 2 ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current VCCI + 4 > VIN VCCI + 1 mA 16VCCI mA (26.7VOUT) mA Equation D on page 17 0.18VCCI > VOUT > 0 1, 2 (Test Point) slewF (-17.1 + (VCCI - VOUT)) -32VCCI VCCI > VOUT 0.6VCCI slewR mA VOUT = 0.7VCC 2 Switching Current Low Units -12VCCI 0.7VCCI < VOUT < VCCI 1, 2 (Test Point) IOL(AC) Max. 38VCCI mA -25 + (VIN + 1)/0.015 mA 25 + (VIN - VCCI - 1)/0.015 mA Output Rise Slew Rate 0.2VCCI to 0.6VCCI load3 1 4 V/ns Output Fall Slew Rate load3 1 4 V/ns 0.6VCCI to 0.2VCCI Notes: 1. Refer to the V/I curves in Figure 16 on page 17. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specification is not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective curves in Figure 16 on page 17. The equation defined maximum should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. pin pin 1/2 in. max. output buffer 10 pF output buffer VCC 1k/25 1k/25 18 1/2 in. max. 10 pF Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s A c te l MI L - S T D - 8 8 3 C l a s s B P r o du c t Fl ow 883--Class B Requirement Step Screen 883 Method 1. Internal Visual 2010, Test Condition B 100% 2. Temperature Cycling 1010, Test Condition C 100% 3. Constant Acceleration 2001, Test Condition D or E, Y1, Orientation Only 100% 4. Particle Impact Noise Detection 2020, Condition A 100% 5. Seal a. Fine b. Gross 1014 6. Visual Inspection 2009 100% 7. Pre-Burn-In Electrical Parameters In accordance with applicable Actel device specification 100% 8. Dynamic Burn-In 1015, Condition D, 160 hours @ 125C or 80 hours @ 150C 100% 9. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification 100% 10. Percent Defective Allowable 5% 11. Final Electrical Test In accordance with applicable Actel device specification, which includes a, b, and c: a. Static Tests (1) 25C (Subgroup 1, Table I) (2) -55C and +125C (Subgroups 2, 3, Table I) b. Functional Tests (1) 25C (Subgroup 7, Table I) (2) -55C and +125C (Subgroups 8A and 8B, Table I) 12. 100% 100% All Lots 100% 5005 5005 100% 5005 5005 c. Switching Tests at 25C (Subgroup 9, Table I) 5005 100% External Visual 2009 Advanced v1.4 100% 19 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s A c te l Ex t e nd e d F l o w 1 Step Screen Method Requirement 1. Destructive In-Line Bond Pull3 2011, Condition D Sample 2. Internal Visual 2010, Condition A 100% 3. Serialization 4. Temperature Cycling 1010, Condition C 100% 5. Constant Acceleration 2001, Condition D or E, Y1 Orientation Only 100% 6. Particle Impact Noise Detection 2020, Condition A 100% 7. Radiographic 2012 (one view only) 100% 8. Pre-Burn-In Test In accordance with applicable Actel device specification 100% 9. Dynamic Burn-In 1015, Condition D, 240 hours @ 125C or 120 hours @150C minimum 100% 10. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification 11. Static Burn-In 12. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification 13. Percent Defective Allowable (PDA) Calculation 5%, 3% Functional Parameters @ 25C 14. Final Electrical Test In accordance with Actel applicable device specification which includes a, b, and c: a. Static Tests (1) 25C (Subgroup 1, Table1) (2) -55C and +125C (Subgroups 2, 3, Table 1) b. Functional Tests (1) 25C (Subgroup 7, Table 15) (2) -55C and +125C (Subgroups 8A and B, Table 1) 15. 100% 1015, Condition C, 72 hours @ 150C or 144 hours @ 125C minimum 100% 100% 100% All Lots 100% 100% 5005 5005 100% 5005 5005 c. Switching Tests at 25C (Subgroup 9, Table 1) 5005 100% Seal 1014 100% 2009 100% a. Fine b. Gross 16. External Visual Notes: 1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel is offering this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004 are shown in notes 2 and 4 below. 2. MIL-STD-883, Method 5004 requires a 100 percent Radiation latch-up testing to Method 1020. Actel will not be performing any radiation testing, and this requirement must be waived in its entirety. 3. Method 5004 requires 100 percent nondestructive bond path to Method 2003. Actel substitutes a destructive bond path to Method 2011 Condition D on a sample basis only. 4. Wafer lot acceptance comply to commercial standards only (requirement per Method 5007 is not performed). 20 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s J un c t i on T e m p e ra t u re ( T J ) The temperature that is selected in Designer Series software is the junction temperature, not ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Equation 1, shown below, can be used to calculate junction temperature. Junction Temperature = T + Ta (1) Where: Ta = Ambient Temperature ja = Junction to ambient of package. ja numbers are located in the Package Thermal Characteristics section below. P a ck a g e T he r m a l C h a r ac t e ri s ti cs The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. ja thermal characteristics are shown with two different air flow rates. The maximum junction temperature is 150C. T = Gradient between junction (silicon) and ambient A sample calculation of the absolute maximum power dissipation allowed for a CQFP 208-pin package at military temperature and still air is as follows: T = ja * P P = Estimating Power Consumption better calculation Max. junction temp. (C) - Max. ambient temp. (C) 150C - 125C Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 1.14W ja (C/W) 22C/W ja ja Pin Count jc Still Air 300 ft/min Units Ceramic Quad Flat Pack (CQFP) 208 6.3 22 14 C/W Ceramic Quad Flat Pack (CQFP) 256 6.2 20 10 C/W Ceramic Quad Flat Pack (CQFP) 208 6.3 22 13 C/W Ceramic Quad Flat Pack (CQFP) with Heat Sink 256 6.2 19 9 C/W Ceramic Column Grid Array (CCGA) 624 TBD TBD TBD TBD Package Type RT54SX32S RT54SX72S For Power Estimator information, please go to http://www.actel.com/products/tools/index.html. Advanced v1.4 21 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s R T 5 4 SX - S T i m i n g M o d el Input Delays I/O Module t INYH = 1.1 ns Internal Delays Combinatorial Cell t IRD1 = 0.8 ns t IRD2 = 1.0 ns t PD = 1.2 ns Predicted Routing Delays I/O Module t RD1 = 0.8 ns t RD4 = 1.5 ns t RD8 = 2.9 ns Routed Clock t RCKH = 4.9 ns Q t RD1 = 0.8 ns t ENZL= 2.5 ns t RCO= 1.0 ns (100% Load) I/O Module t DHL = 2.6 ns Register Cell I/O Module t INYH = 0.5 ns t SUD = 0.4 ns t HD = 0.0 ns Hard-Wired Clock D t HCKH = 3.1 ns t DHL = 3.8 ns I/O Module t DHL = 3.8 ns Register Cell t SUD = 0.7 ns t HD = 0.0 ns Output Delays D Q t RD1 = 0.8 ns t ENZL= 2.5 ns t RCO= 1.0 ns Values shown for RT54SX32S, -1, 5V TTL worst-case military conditions. H a r d- Wi r e d C lo c k R o u t ed C lo ck External Setup External Setup = (tINYH + tIRD2 + tSUD) - tHCKH = 1.1 + 1.0 + 0.7 - 3.1 = -0.3ns Clock-to-Out (Pad-to-Pad) 22 = (tINYH + tIRD2 + tSUD) - tRCKH = 1.1 + 1.0 + 0.7- 4.9= -2.1 ns Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tDHL = tRCKH + tRCO + tRD1 + tDHL = 3.1 + 1.0 + 0.8 + 3.8= 8.7 ns = 4.9+ 1.0 + 0.8 + 3.8 = 10.5 ns Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s Output Buffer Delays E D VCC In 50% Out VOL 50% VOH VCC GND En 1.5V 1.5V PAD To AC test loads (shown below) TRIBUFF 50% VCC Out VCC GND 50% 1.5V tDHL tENZL 90% 1.5V tENZH tENLZ GND 50% VOH 50% Out GND 10% VOL tDLH En tENHZ AC Test Loads Load 3 (Used to measure disable delays) Load 2 (Used to measure enable delays) Load 1 (Used to measure propagation delay) To the output under test VCC 35 pF To the output under test VCC GND R to VCC for tPZL R to GND for tPZH R = 1 k GND R to VCC for tPLZ R to GND for tPHZ R = 1 k To the output under test 5 pF 35 pF In p u t B uf fe r D e l a y s PAD INBUF C-Cell Delays S A B Y Y VCC 3V In Out GND 1.5V 1.5V VCC 50% S, A or B 50% 50% VCC Out GND 50% 0V 50% tPD GND 50% tPD Out 50% tPD Advanced v1.4 GND VCC 50% tPD 23 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s C e l l T i m i n g C ha r a c t e r i s t i c s Fl ip -F lo ps PRE D Q CLK CLR (Positive edge triggered) tHD D tHP tHPWH, tRPWH tSUD CLK tHPWL, tRPWL tRCO Q tCLR tPRESET CLR tWASYN PRESET T i m i n g C h a ra c t er i s ti c s L on g T r a c ks RT54SX-S device timing characteristics are in three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all RT54SX-S devices. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design is complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6 percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays in the data sheet specifications section. C r i t ic al N e t s a nd T yp ic a l N e t s Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. Timing Derating RT54SX-S devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. T em p er a tu r e an d V o l t a ge D er a ti ng F a c to r s (Normalized to Worst-Case Military, T J = 125C, V CCA = 2.3V) Junction Temperature (TJ) 24 VCCA -55 -40 0 25 70 85 125 2.3 0.68 0.69 0.75 0.77 0.86 0.90 1.00 2.5 0.64 0.65 0.70 0.72 0.81 0.84 0.93 2.7 0.60 0.61 0.66 0.68 0.76 0.79 0.88 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s R T 5 4 SX 3 2S T i m i n g C h ar a c te r i s t i c s ( W o r st - C a se M i lit a r y C on d it io n s, V C CA = 2.3 V , V CC I = 3 .0 V , T J = 12 5 C ) `-1' Speed Parameter Description C-Cell Propagation tPD Min. Max. `Std' Speed Min. Max. Units 1.2 1.4 ns Delays1 Internal Array Module Predicted Routing Delays 2 tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.4 0.4 ns tRD1 FO=1 Routing Delay 0.8 0.9 ns tRD2 FO=2 Routing Delay 1.0 1.2 ns tRD3 FO=3 Routing Delay 1.4 1.6 ns tRD4 FO=4 Routing Delay 1.5 1.8 ns tRD8 FO=8 Routing Delay 2.9 3.4 ns tRD12 FO=12 Routing Delay 4.0 4.7 ns tRCO Sequential Clock-to-Q 1.0 1.2 ns tCLR Asynchronous Clear-to-Q 0.9 1.1 ns tPRESET Asynchronous Preset-to-Q 1.0 1.2 ns tSUD Flip-Flop Data Input Set-Up 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.8 2.2 ns R-Cell Timing Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 3.3V PCI 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 3.3V PCI 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 3.3V LVTTL 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 3.3V LVTTL 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 5V PCI 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 5V PCI 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 5V TTL 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 5V TTL 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 5V CMOS 1.4 1.7 ns tINYL Input Data Pad-to-Y LOW 5V CMOS 1.3 1.5 ns Input Module Predicted Routing Delays2 tIRD1 FO=1 Routing Delay 0.8 0.9 ns tIRD2 FO=2 Routing Delay 1.0 1.2 ns tIRD3 FO=3 Routing Delay 1.4 1.6 ns tIRD4 FO=4 Routing Delay 1.5 1.8 ns tIRD8 FO=8 Routing Delay 2.9 3.4 ns tIRD12 FO=12 Routing Delay 4.0 4.7 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Advanced v1.4 25 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s R T 5 4 SX 3 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V C CI = 3. 0V , T J = 1 25 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH Input LOW to HIGH (Pad to R-Cell Input) 3.1 4.0 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 3.1 4.0 ns tHPWH Minimum Pulse Width HIGH 2.1 2.5 ns tHPWL Minimum Pulse Width LOW 2.1 2.5 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.5 4.2 0.6 5.0 ns ns 238 200 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 3.2 3.7 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 3.2 3.7 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 4.0 4.7 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 3.8 4.4 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 4.9 5.8 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 3.8 4.5 ns tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tRCKSW Maximum Skew (Light Load) 1.9 2.0 ns tRCKSW Maximum Skew (50% Load) 1.9 2.0 ns tRCKSW Maximum Skew (100% Load) 1.9 2.0 ns 26 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s R T 5 4 SX 3 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V C CI = 4. 5V , T J = 1 25 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH Input LOW to HIGH (Pad to R-Cell Input) 3.1 3.6 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 3.1 3.6 ns tHPWH Minimum Pulse Width HIGH 2.1 2.5 ns tHPWL Minimum Pulse Width LOW 2.1 2.5 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.5 4.2 0.6 5.0 ns ns 238 200 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 3.1 3.6 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 3.1 3.6 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 3.7 4.6 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 3.8 4.4 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 4.9 5.8 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 3.8 4.5 ns tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tRCKSW Maximum Skew (Light Load) 1.9 2.3 ns tRCKSW Maximum Skew (50% Load) 1.9 2.3 ns tRCKSW Maximum Skew (100% Load) 1.9 2.3 ns Advanced v1.4 27 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s R T 5 4 SX 3 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V C CI = 3. 0V , T J = 1 25 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 3.3V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.8 3.3 ns tDHL Data-to-Pad HIGH to LOW 3.0 3.6 ns tENZL Enable-to-Pad, Z to L 2.1 2.5 ns tENZH Enable-to-Pad, Z to H 2.7 3.9 ns tENLZ Enable-to-Pad, L to Z 2.7 3.9 ns tENHZ Enable-to-Pad, H to Z 2.5 3.0 ns dTLH Delta Delay vs. Load LOW to HIGH 0.03 0.04 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.015 0.015 ns/pF 3.3V LVTTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 3.9 4.6 ns tDHL Data-to-Pad HIGH to LOW 3.8 4.5 ns tDHLS Data-to-Pad HIGH to LOW - low slew 13.7 16.1 ns tENZL Enable-to-Pad, Z to L 2.9 3.4 ns tDENZLS Enable-to-Pad, Z to LOW - low slew 12.7 14.9 ns tENZH Enable-to-Pad, Z to H 3.7 4.4 ns tENLZ Enable-to-Pad, L to Z 3.7 4.4 ns tENHZ Enable-to-Pad, H to Z 3.4 4.0 ns dTLH Delta Delay vs. Load LOW to HIGH 0.033 0.04 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.02 0.02 ns/pF dTHLS Delta Delay vs. Load HIGH to LOW - low slew 0.067 0.073 ns/pF Notes: 1. Delays based on 10pF loading and 25 resistance. 2. Delays based on 35pF loading. 28 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s R T 5 4 SX 3 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V CCI = 4 .5 V , T J = 1 2 5 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 1 5V PCI Output Module Timing tDLH Data-to-Pad LOW to HIGH 3.1 3.7 ns tDHL Data-to-Pad HIGH to LOW 4.2 5.0 ns tENZL Enable-to-Pad, Z to LOW 2.8 3.3 ns tENZH Enable-to-Pad, Z to HIGH 3.2 3.8 ns tENLZ Enable-to-Pad, LOW to Z 4.9 5.8 ns tENHZ Enable-to-Pad, HIGH to Z 4.1 4.9 ns dTLH Delta Delay vs. Load LOW to HIGH 0.02 0.022 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.032 0.04 ns/pF 5V TTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 2.8 3.3 ns tDHL Data-to-Pad HIGH to LOW 3.8 4.5 ns tDHLS Data-to-Pad HIGH to LOW - low slew 10.0 11.8 ns tENZL Enable-to-Pad, Z to LOW 2.5 3.0 ns tDENZLS Enable-to-Pad, Z to LOW - low slew 9.0 10.6 ns tENZH Enable-to-Pad, Z to HIGH 2.8 3.4 ns tENLZ Enable-to-Pad, LOW to Z 4.4 5.3 ns tENHZ Enable-to-Pad, HIGH to Z 3.6 4.4 ns dTLH Delta Delay vs. Load LOW to HIGH 0.017 0.023 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.031 0.037 ns/pF dTHLS Delta Delay vs. Load HIGH to LOW - low slew 0.06 0.07 ns/pF 5V CMOS Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 3.5 4.1 ns tDHL Data-to-Pad HIGH to LOW 3.8 4.5 ns tDHLS Data-to-Pad HIGH to LOW - low slew 10.0 11.8 ns tENZL Enable-to-Pad, Z to LOW 2.3 2.71 ns tDENZLS Enable-to-Pad, Z to LOW - low slew 8.8 10.4 ns tENZH Enable-to-Pad, Z to HIGH 3.0 3.6 ns tENLZ Enable-to-Pad, LOW to Z 4.5 5.3 ns tENHZ Enable-to-Pad, HIGH to Z Notes: 1. Delays based on 50pF loading. 2. Delays based on 35pF loading. 3.5 4.7 ns Advanced v1.4 29 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s R T 5 4 SX 7 2S T i m i n g C h ar a c te r i s t i c s ( W o r st - C a se M i lit a r y C on d it io n s, V C CA = 2 .3 V , V CC I = 3 .0 V , T J = 12 5 C ) `-1' Speed Parameter Description C-Cell Propagation tPD Min. Max. `Std' Speed Min. Max. Units 1.2 1.4 ns Delays1 Internal Array Module Predicted Routing Delays 2 tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.4 0.4 ns tRD1 FO=1 Routing Delay 0.9 1.0 ns tRD2 FO=2 Routing Delay 1.2 1.4 ns tRD3 FO=3 Routing Delay 1.8 2.0 ns tRD4 FO=4 Routing Delay 1.9 2.3 ns tRD8 FO=8 Routing Delay 3.7 4.3 ns tRD12 FO=12 Routing Delay 5.1 6.0 ns tRCO Sequential Clock-to-Q 1.0 1.2 ns tCLR Asynchronous Clear-to-Q 0.9 1.1 ns tPRESET Asynchronous Preset-to-Q 1.0 1.2 ns tSUD Flip-Flop Data Input Set-Up 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.8 2.2 ns R-Cell Timing Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 3.3V PCI 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 3.3V PCI 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 3.3V LVTTL 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 3.3V LVTTL 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 5V PCI 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 5V PCI 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 5V LVTTL 1.1 1.3 ns tINYL Input Data Pad-to-Y LOW 5V LVTTL 1.1 1.3 ns tINYH Input Data Pad-to-Y HIGH 5V CMOS 1.4 1.7 ns tINYL Input Data Pad-to-Y LOW 5V CMOS 1.3 1.5 ns Input Module Predicted Routing Delays2 tIRD1 FO=1 Routing Delay 0.8 0.9 ns tIRD2 FO=2 Routing Delay 1.0 1.2 ns tIRD3 FO=3 Routing Delay 1.4 1.6 ns tIRD4 FO=4 Routing Delay 1.5 1.8 ns tIRD8 FO=8 Routing Delay 2.9 3.4 ns tIRD12 FO=12 Routing Delay 4.0 4.7 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 30 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s R T 5 4 SX 7 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V C CI = 3. 0V , T J = 1 25 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH Input LOW to HIGH (Pad to R-Cell Input) 5.8 1.8 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 5.8 6.8 ns tHPWH Minimum Pulse Width HIGH 3.6 4.3 ns tHPWL Minimum Pulse Width LOW 3.6 4.3 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 1.4 7.2 1.6 8.6 ns ns 139 116 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 5.9 6.8 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 5.9 6.8 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 7.4 8.7 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 7.0 8.2 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 9.1 10.8 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 7.0 8.3 ns tRPWH Min. Pulse Width HIGH 5.7 6.8 ns tRPWL Min. Pulse Width LOW 5.7 6.8 ns tRCKSW Maximum Skew (Light Load) 3.5 3.7 ns tRCKSW Maximum Skew (50% Load) 3.5 3.7 ns tRCKSW Maximum Skew (100% Load) 3.5 3.7 ns Advanced v1.4 31 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s R T 5 4 SX 7 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V C CI = 4. 5V , T J = 1 25 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH Input LOW to HIGH (Pad to R-Cell Input) 5.3 6.1 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 5.3 6.1 ns tHPWH Minimum Pulse Width HIGH 3.6 4.3 ns tHPWL Minimum Pulse Width LOW 3.6 4.3 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 1.4 7.2 1.6 8.6 ns ns 139 116 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 5.7 6.6 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 5.7 6.6 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 6.8 8.4 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 7.0 8.2 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 9.1 10.8 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 7.0 8.3 ns tRPWH Min. Pulse Width HIGH 5.7 6.8 ns tRPWL Min. Pulse Width LOW 5.7 6.8 ns tRCKSW Maximum Skew (Light Load) 3.5 3.7 ns tRCKSW Maximum Skew (50% Load) 3.5 3.7 ns tRCKSW Maximum Skew (100% Load) 3.5 3.7 ns 32 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s R T 5 4 SX 7 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V C CI = 3. 0V , T J = 1 25 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 3.3V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.8 3.3 ns tDHL Data-to-Pad HIGH to LOW 3.0 3.6 ns tDHLS Data-to-Pad HIGH to LOW - low slew 15.0 17.7 ns tENZL Enable-to-Pad, Z to L 2.1 2.5 ns tDENZLS Enable-to-Pad, Z to LOW - low slew 9.3 10.9 ns tENZH Enable-to-Pad, Z to H 2.7 3.9 ns tENLZ Enable-to-Pad, L to Z 2.7 3.9 ns tENHZ Enable-to-Pad, H to Z 2.5 3.0 ns dTLH Delta Delay vs. Load LOW to HIGH 0.03 0.04 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.015 0.015 ns/pF dTHLS Delta Delay vs. Load HIGH to LOW - low slew 0.065 0.075 ns/pF 3.3V LVTTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 3.9 4.6 ns tDHL Data-to-Pad HIGH to LOW 3.8 4.5 ns tDHLS Data-to-Pad HIGH to LOW - low slew 13.7 16.1 ns tENZL Enable-to-Pad, Z to L 2.9 3.4 ns tDENZLS Enable-to-Pad, Z to LOW - low slew 12.7 14.9 ns tENZH Enable-to-Pad, Z to H 3.7 4.4 ns tENLZ Enable-to-Pad, L to Z 3.7 4.4 ns tENHZ Enable-to-Pad, H to Z 3.4 4.0 ns dTLH Delta Delay vs. Load LOW to HIGH 0.033 0.04 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.02 0.02 ns/pF dTHLS Delta Delay vs. Load HIGH to LOW - low slew 0.067 0.073 ns/pF Notes: 1. Delays based on 10pF loading and 25 resistance. 2. Delays based on 35pF loading. Advanced v1.4 33 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s R T 5 4 SX 7 2S T i m i n g C h ar a c te r i s t i c s (continued) ( W o r st - C a se M i lit a r y C on d it io n s V CC A = 2 .3 V , V CCI = 4 .5 V , T J = 1 2 5 C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 1 5V PCI Output Module Timing tDLH Data-to-Pad LOW to HIGH 3.1 3.7 ns tDHL Data-to-Pad HIGH to LOW 4.2 5.0 ns tENZL Enable-to-Pad, Z to LOW 2.8 3.3 ns tENZH Enable-to-Pad, Z to HIGH 3.2 3.8 ns tENLZ Enable-to-Pad, LOW to Z 4.9 5.8 ns tENHZ Enable-to-Pad, HIGH to Z 4.1 4.9 ns dTLH Delta Delay vs. Load LOW to HIGH 0.02 0.022 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.032 0.04 ns/pF 5V TTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 2.8 3.3 ns tDHL Data-to-Pad HIGH to LOW 3.8 4.5 ns tDHLS Data-to-Pad HIGH to LOW - low slew 10.0 11.8 ns tENZL Enable-to-Pad, Z to LOW 2.5 3.0 ns tDENZLS Enable-to-Pad, Z to LOW - low slew 9.0 10.6 ns tENZH Enable-to-Pad, Z to HIGH 2.8 3.4 ns tENLZ Enable-to-Pad, LOW to Z 4.4 5.3 ns tENHZ Enable-to-Pad, HIGH to Z 3.6 4.4 ns dTLH Delta Delay vs. Load LOW to HIGH 0.017 0.023 ns/pF dTHL Delta Delay vs. Load HIGH to LOW 0.031 0.037 ns/pF dTHLS Delta Delay vs. Load HIGH to LOW - low slew 0.06 0.07 ns/pF 5V CMOS Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 3.5 4.1 ns tDHL Data-to-Pad HIGH to LOW 3.8 4.5 ns tDHLS Data-to-Pad HIGH to LOW - low slew 10.0 11.8 ns tENZL Enable-to-Pad, Z to LOW 2.3 2.71 ns tDENZLS Enable-to-Pad, Z to LOW - low slew 8.8 10.4 ns tENZH Enable-to-Pad, Z to HIGH 3.0 3.6 ns tENLZ Enable-to-Pad, LOW to Z 4.5 5.3 ns tENHZ Enable-to-Pad, HIGH to Z Notes: 1. Delays based on 50pF loading. 2. Delays based on 35pF loading. 3.5 4.7 ns 34 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s P i n D e s c r i p ti o n CLKA/B Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5V PCI specifications. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. (For RT54SX72S, these clocks can be configured as user I/O). QCLKA/B/C/D, Quadrant Clock A, B, C, and D I/O These four pins are the quadrant clock inputs and are only for RT54SX72S. They are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5V PCI specifications. Each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the R-cells. If not used as a clock it will behave as a regular I/O. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock This pin is the clock input for sequential modules. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5V PCI specifications. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. I/O Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output levels are compatible with standard TTL, LVTTL, 3.3V/5V PCI or 3.3V/5V CMOS specifications. Unused I/O pins are automatically tristated by the Designer software. NC No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. PRA, I/O * , PRB, I/O * Probe A/B The probe pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. TCK * , I/O Test Clock Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 6 on page 11). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. TDI * , I/O Test Data Input Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 6 on page 11). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. TDO * , I/O Test Data Output Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 6 on page 11). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer II is being used, TDO will act as an output when the "checksum" command is run. It will return to user I/O when "checksum" is complete. TMS * Test Mode Select The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 6 on page 11). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached five TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. For flight requirements, the TRST pin needs to be hard-wired to GND. V CCI Supply Voltage Supply voltage for I/Os. See Table 5 on page 11. V CCA Supply Voltage Supply voltage for Array. See Table 5 on page 11. * 70 series termination should be placed on the board to enable probing capability. Advanced v1.4 35 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s P ac k a g e Pi n A s s i g nm en t s 208-Pin CQFP (Top View) 208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157 1 156 2 155 3 154 4 153 5 152 6 151 7 150 8 149 208-Pin CQFP 44 113 45 112 46 111 47 110 48 109 49 108 50 107 51 106 52 105 53 54 55 56 57 58 59 60 61 36 97 98 99 100 101 102 103 104 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s 20 8 -P in C Q F P Pin Number RT54SX32S Function RT54SX72S Function Pin Number RT54SX32S Function RT54SX72S Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O GND VCCA GND I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKA I/O PRB, I/O GND VCCA GND NC I/O HCLK VCCI QCLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O Note: Pin 65 is a No Connect (NC) on Commercial A54SX32S-PQ208. Advanced v1.4 37 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s 20 8 -P in C Q F P ( c on t in u ed ) Pin Number RT54SX32S Function RT54SX72S Function Pin Number RT54SX32S Function RT54SX72S Function 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD I/O CLKA CLKB NC GND VCCA GND PRA, I/O VCCI I/O I/O QCLKC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O 38 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s P a ck a g e Pi n A s s i g nm en t s (continued) 256-Pin CQFP (Top View) 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 1 192 2 191 3 190 4 189 5 188 6 187 7 186 8 185 256-Pin CQFP 56 137 57 136 58 135 59 134 60 133 61 132 62 131 63 130 64 129 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 Advanced v1.4 39 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s 256-Pin CQFP Pin Number RT54SX32S Function RT54SX72S Function Pin Number RT54SX32S Function RT54SX72S Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST I/O VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKA PRB, I/O GND VCCI GND VCCA I/O HCLK I/O QCLKB I/O I/O I/O I/O I/O I/O 40 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s 256-Pin CQFP (continued) Pin Number RT54SX32S Function RT54SX72S Function Pin Number RT54SX32S Function RT54SX72S Function 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 I/O GND NC GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC GND VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O Advanced v1.4 41 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s 256-Pin CQFP (continued) Pin Number RT54SX32S Function RT54SX72S Function Pin Number RT54SX32S Function RT54SX72S Function 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND NC GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD CLKA CLKB VCCI GND NC GND PRA, I/O I/O I/O VCCA I/O I/O QCLKC I/O 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O 42 Advanced v1.4 R T 5 4S X - S R a d T o le r a n t F PG A s f o r S p a c e A p p l i c a t i o n s P a ck a g e Pi n A s s i g nm en t s CG624 (Bottom View) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Advanced v1.4 43 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s C G 6 2 4- P in 44 C G 6 2 4 - P in C G 6 24 -P in Pin Number RT54SX72S Function Pin Number RT54SX72S Function Pin Number RT54SX72S Function A2 NC B16 I/O D5 PRA A3 NC B17 I/O D6 I/O A4 NC B18 I/O D7 I/O A5 I/O B19 I/O D8 I/O A6 I/O B20 I/O D9 I/O A7 I/O B21 I/O D10 I/O A8 I/O B22 NC D11 I/O A9 I/O B23 VCCI D12 I/O A10 I/O B24 GND D13 I/O A11 I/O B25 NC D14 QCLKD A12 I/O C1 NC D15 I/O A13 NC C2 VCCI D16 I/O A14 I/O C3 GND D17 I/O A15 I/O C4 PRB D18 I/O A16 I/O C5 I/O D19 I/O A17 I/O C6 I/O D20 I/O A18 I/O C7 I/O D21 I/O A19 I/O C8 I/O D22 VCCI A20 I/O C9 I/O D23 GND A21 I/O C10 I/O D24 NC A22 NC C11 QCLKC D25 NC A23 NC C12 I/O E1 I/O A24 NC C13 PRA E2 I/O A25 NC C14 CLKA E3 I/O B1 NC C15 I/O E4 I/O B2 GND C16 I/O E5 TCK B3 GND C17 I/O E6 I/O B4 VCCI C18 I/O E7 I/O B5 NC C19 I/O E8 I/O B6 I/O C20 I/O E9 I/O B7 I/O C21 I/O E10 I/O B8 VCCI C22 I/O E11 I/O B9 NC C23 GND E12 VCCA B10 I/O C24 VCCI E13 NC B11 I/O C25 NC E14 I/O B12 I/O D1 NC E15 I/O B13 I/O D2 NC E16 I/O B14 CLKB D3 TDI E17 I/O B15 I/O D4 GND E18 I/O Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s CG624-Pin CG624-Pin CG624-Pin Pin Number RT54SX72S Function Pin Number RT54SX72S Function Pin Number RT54SX72S Function E19 I/O G8 NC H22 I/O E20 I/O G9 NC H23 I/O E21 I/O G10 NC H24 GND E22 I/O G11 NC H25 I/O E23 I/O G12 NC J1 I/O E24 I/O G13 NC J2 I/O E25 I/O G14 NC J3 I/O F1 I/O G15 NC J4 I/O F2 VCCI G16 NC J5 I/O F3 I/O G17 NC J6 I/O F4 I/O G18 NC J7 NC F5 I/O G19 VCCI J8 NC F6 NC G20 I/O J9 VCCI F7 NC G21 I/O J10 NC F8 I/O G22 I/O J11 NC F9 NC G23 I/O J12 NC F10 NC G24 I/O J13 NC F11 NC G25 I/O J14 NC F12 NC H1 I/O J15 NC F13 I/O H2 I/O J16 NC F14 I/O H3 I/O J17 VCCI F15 NC H4 I/O J18 NC F16 NC H5 I/O J19 NC F17 I/O H6 I/O J20 I/O F18 I/O H7 I/O J21 VCCA F19 I/O H8 VCCI J22 I/O F20 I/O H9 NC J23 I/O F21 I/O H10 NC J24 I/O F22 I/O H11 NC J25 I/O F23 I/O H12 NC K1 I/O F24 I/O H13 NC K2 NC F25 I/O H14 NC K3 I/O G1 I/O H15 NC K4 I/O G2 I/O H16 NC K5 I/O G3 TMS H17 NC K6 NC G4 I/O H18 VCCI K7 NC G5 I/O H19 I/O K8 NC G6 I/O H20 I/O K9 NC G7 VCCI H21 I/O K10 GND Advanced v1.4 45 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s C G 6 2 4- P in 46 C G 6 2 4 - P in C G 6 24 -P in Pin Number RT54SX72S Function Pin Number RT54SX72S Function Pin Number RT54SX72S Function K11 GND L25 I/O N14 GND K12 GND M1 I/O N15 GND K13 GND M2 I/O N16 GND K14 GND M3 I/O N17 NC K15 GND M4 I/O N18 NC K16 GND M5 NC N19 VCCA K17 NC M6 I/O N20 I/O K18 NC M7 NC N21 VCCA K19 NC M8 NC N22 I/O K20 I/O M9 NC N23 I/O K21 I/O M10 GND N24 VCCI K22 I/O M11 GND N25 I/O K23 I/O M12 GND P1 I/O K24 I/O M13 GND P2 I/O K25 I/O M14 GND P3 I/O L1 I/O M15 GND P4 I/O L2 I/O M16 GND P5 I/O L3 I/O M17 NC P6 I/O L4 I/O M18 NC P7 NC L5 I/O M19 NC P8 NC L6 I/O M20 I/O P9 NC L7 NC M21 NC P10 GND L8 NC M22 I/O P11 GND L9 NC M23 I/O P12 GND L10 GND M24 NC P13 GND L11 GND M25 I/O P14 GND L12 GND N1 I/O P15 GND L13 GND N2 I/O P16 GND L14 GND N3 I/O P17 NC L15 GND N4 I/O P18 NC L16 GND N5 VCCA P19 NC L17 NC N6 I/O P20 I/O L18 NC N7 VCCA P21 NC L19 NC N8 NC P22 I/O L20 I/O N9 NC P23 I/O L21 I/O N10 GND P24 I/O L22 I/O N11 GND P25 I/O L23 I/O N12 GND R1 I/O L24 I/O N13 GND R2 I/O Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s CG624-Pin CG624-Pin CG624-Pin Pin Number RT54SX72S Function Pin Number RT54SX72S Function Pin Number RT54SX72S Function R3 I/O T17 NC V6 I/O R4 TRST T18 NC V7 NC R5 I/O T19 NC V8 VCCI R6 NC T20 NC V9 NC R7 NC T21 I/O V10 NC R8 NC T22 I/O V11 NC R9 NC T23 I/O V12 NC R10 GND T24 I/O V13 NC R11 GND T25 I/O V14 NC R12 GND U1 I/O V15 NC R13 GND U2 I/O V16 NC R14 GND U3 I/O V17 NC R15 GND U4 I/O V18 VCCI R16 GND U5 I/O V19 I/O R17 NC U6 I/O V20 I/O R18 NC U7 I/O V21 I/O R19 NC U8 NC V22 VCCA R20 I/O U9 VCCI V23 I/O R21 I/O U10 NC V24 I/O R22 I/O U11 NC V25 I/O R23 I/O U12 NC W1 I/O R24 I/O U13 NC W2 VCCI R25 I/O U14 NC W3 I/O T1 I/O U15 NC W4 I/O T2 I/O U16 NC W5 I/O T3 I/O U17 VCCI W6 I/O T4 I/O U18 NC W7 VCCI T5 I/O U19 NC W8 NC T6 I/O U20 I/O W9 NC T7 I/O U21 I/O W10 NC T8 NC U22 I/O W11 NC T9 NC U23 I/O W12 NC T10 GND U24 I/O W13 NC T11 GND U25 I/O W14 NC T12 GND V1 I/O W15 NC T13 GND V2 I/O W16 NC T14 GND V3 I/O W17 NC T15 GND V4 VCCA W18 I/O T16 GND V5 I/O W19 VCCI Advanced v1.4 47 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s C G 6 2 4- P in 48 C G 6 2 4 - P in C G 6 24 -P in Pin Number RT54SX72S Function Pin Number RT54SX72S Function Pin Number RT54SX72S Function W20 I/O AA9 I/O AB23 I/O W21 I/O AA10 I/O AB24 VCCI W22 I/O AA11 I/O AB25 NC W23 I/O AA12 I/O AC1 NC W24 I/O AA13 VCCA AC2 I/O W25 I/O AA14 NC AC3 GND Y1 I/O AA15 I/O AC4 I/O Y2 I/O AA16 I/O AC5 I/O Y3 I/O AA17 I/O AC6 I/O Y4 I/O AA18 I/O AC7 I/O Y5 I/O AA19 I/O AC8 I/O Y6 I/O AA20 I/O AC9 I/O Y7 I/O AA21 GND AC10 I/O Y8 I/O AA22 I/O AC11 I/O Y9 I/O AA23 I/O AC12 PRB Y10 I/O AA24 I/O AC13 I/O Y11 NC AA25 NC AC14 HCLK Y12 NC AB1 NC AC15 I/O Y13 I/O AB2 VCCI AC16 I/O Y14 NC AB3 I/O AC17 I/O Y15 NC AB4 GND AC18 I/O Y16 I/O AB5 I/O AC19 I/O Y17 I/O AB6 I/O AC20 I/O Y18 I/O AB7 I/O AC21 I/O Y19 I/O AB8 I/O AC22 I/O Y20 I/O AB9 I/O AC23 GND Y21 I/O AB10 I/O AC24 I/O Y22 I/O AB11 I/O AC25 NC Y23 I/O AB12 QCLKA AD1 NC Y24 NC AB13 I/O AD2 GND Y25 I/O AB14 I/O AD3 VCCI AA1 NC AB15 I/O AD4 NC AA2 NC AB16 I/O AD5 I/O AA3 I/O AB17 I/O AD6 I/O AA4 I/O AB18 I/O AD7 I/O AA5 GND AB19 I/O AD8 I/O AA6 I/O AB20 I/O AD9 I/O AA7 I/O AB21 TDO AD10 VCCI AA8 I/O AB22 VCCI AD11 I/O Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s CG624-Pin Pin Number RT54SX72S Function AD12 I/O AD13 I/O AD14 I/O AD15 I/O AD16 NC AD17 I/O AD18 I/O AD19 I/O AD20 I/O AD21 I/O AD22 NC AD23 VCCI AD24 GND AD25 NC AE1 NC AE2 NC AE3 NC AE4 NC AE5 I/O AE6 I/O AE7 I/O AE8 I/O AE9 I/O AE10 I/O AE11 I/O AE12 I/O AE13 I/O AE14 QCLKB AE15 I/O AE16 I/O AE17 I/O AE18 I/O AE19 I/O AE20 I/O AE21 I/O AE22 NC AE23 NC AE24 NC AE25 NC Advanced v1.4 49 R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s L i s t o f C ha n g es The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (Advanced v1.4) Page Advanced v1.3 On the PQ208 package for the RT54SX72S, pin 13, the function is I/O and not VCCI. page 37 The "RT54SX-S Product Profile" table on page 1 table has been updated. page 1 The "Ceramic Device Resources" section on page 2 page 2 The "Clock Resources" section on page 8 has been updated. page 8 Table 1 on page 8 is new. page 8 The "I/O Modules" section on page 9 and have been updated. page 9 Table 2 on page 10 has been updated. page 10 The "Hot Swapping" section on page 10 has been updated. page 10 Table 3 on page 10 is new. page 10 Table 4 on page 10 has been updated. page 10 The "Development Tool Support" section on page 12 has been updated. page 12 The "Design Considerations" section on page 12 has been updated. page 12 The "Pin Description" section on page 35 has been updated. page 35 The CG624 (Bottom View) on page 43 is new. page 43 The "DC Specifications (3.3V PCI Operation)" section on page 17 was updated. page 17 The "Programmable Interconnect Element" section on page 5 has been updated. page 5 The "I/O Modules" section on page 9 and Table 2 page 9 The "Boundary Scan Testing (BST)" section on page 11 has been updated. page 11 The "Dedicated Mode" section on page 11 has been updated. page 11 The "Flexible Mode" section on page 11 has been updated. page 11 Table 7 on page 11 was changed. page 11 The "TRST Pin" section on page 11 has been updated. page 11 The "Probing Capabilities" section on page 11 has been updated. page 11 Table 8 on page 12 is new. page 12 The "Development Tool Support" section on page 12 was changed. page 12 The "Recommended Operating Conditions" section on page 13 has been updated. page 13 The "3.3V LVTTL and 5V TTL Electrical Specifications" table on page 14 was changed. page 14 The "5V CMOS Electrical Specifications" table on page 14 is new. page 14 The "5V PCI Compliance for the RT54SX-S Family" table on page 15 page 15 The "Actel MIL-STD-883 Class B Product Flow" table on page 19 has been updated. page 19 Advanced v1.2.3 Advanced v1.1.2 Advanced v0.3 1 50 The "Actel Extended Flow " table on page 20 has been updated. page 20 The "RT54SX-S Timing Model" table on page 22 and the "Hard-Wired Clock" equation were updated. page 22 The "Pin Description" section on page 35 was updated. page 35 Advanced v1.4 R T 5 4 S X - S R a dT ol e r a nt F P G A s f o r S p a c e A p p l i c a ti o n s Previous version Advanced v0.2 Changes in current version (Advanced v1.4) Page The "Product Plan" table on page 2 has been updated. 2 The "Clock Resources" table on page 8 has been updated. 8 The "Performance" table on page 9, "I/O Modules" table on page 9, "Hot Swapping" table on page 10, "Boundary Scan Testing (BST)" table on page 11, "TRST Pin" table on page 11, "Development Tool Support" table on page 12, and "RT54SX-S Probe Circuit Control Pins" table on page 12 have changed. 9-11 The "Absolute Maximum Ratings*" table on page 13 and "Recommended Operating Conditions" table on page 13 have been updated. 11 The "3.3V and 5.0V Electrical Specifications" section on page 12 and "5V CMOS Electrical 12 Specifications" table on page 14 are new. Advanced v0.1.1 The "RT54SX-S Timing Model" on page 22 was updated. 22 New slew rates were added to the "RT54SX32S Timing Characteristics" on page 28, page 29, and page 34. 29, 30, 35 The TRSTB pin was incorrectly named and changed to TRST. All In the "RT54SX-S Product Profile" table on page 1, the User I/Os have changed. 1 In the "Ceramic Device Resources" table on page 2, the User I/Os have changed. 2 The Clock Networks section has changed to "Clock Resources" table on page 8. 8 The "TRST Pin" table on page 11 has changed. 10 The"Design Considerations" table on page 12 Design Considerations section has changed. 11 In the "2.5V/3.3V/5V Operating Conditions" table on page 13 section, the "Absolute Maximum Ratings*" table on page 13 changed. The IIO row containing the I/O Source Sink Current was deleted. 12 Equation 2 in the "Junction Temperature (TJ)" table on page 21 was corrected. 15 Note that the "Package Characteristics and Mechanical Drawings" section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site. D a ta s he e t C a te g o ri es In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Web-only." The definition of these categories are as follows: P ro d u ct B ri e f The product brief is a modified version of an advanced datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. A d v a n c ed This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. U n m a r ke d ( pr o d uc t i o n) This datasheet version contains information that is considered to be final. Advanced v1.4 51 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Maxfli Court, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81-(0)3-3445-7671 Fax: +81-(0)3-3445-7668 5172151-6/11.02