RT54SX-S RadTolerant FPGAs for Space Applications
12 Advanced v1.4
performed. Silicon Explorer II automatically places the
device into JTAG mode, but the user must drive the TRST
pin HIGH or allow the internal pull-up resistor to pull TRST
HIGH.
When selecting the "Reserve Probe" box as shown in
Figure 13 on page 11, the user direct the layout tool to
reserve the PRA and PRB pins as dedicated outputs for
probing. This "reserve" option is merely a guideline. If the
Layout tool requires that the PRA and PRB pins to be user
I/Os to achieve successful layout, then the tool will employ
these pins for user I/Os. If you assign user I/Os to the PRA
and PRB pins and select the "Reserve Probe" option,
Designer Layout will override the "Reserve Probe" option
and place your user I/Os on those pins.
To allow probing capabilities, the security fuse must not be
programmed. Programming the security fuse will disable the
probe circuitry. Table 8 summarizes the possible device
configurations for probing.
Development Tool Support
RT54SX-S devices are fully supported by Actel’s line of FPGA
development tools, including Actel’s Designer software and
Actel Libero Integrated Design Environment (IDE), the
FPGA design tool suite. Designer Software, Actel’s suite of
FPGA development tools for PCs and Workstations, includes
the ACTgen Macro Builder, timing driven place-and-route,
timing analysis tools, and fuse file generation. Libero IDE is
a design management environment that integrates the
needed design tools, streamlines the design flow, manages
all design and log files, and passes necessary design data
between tools. Libero IDE includes, Synplify, ViewDraw,
Actel’s Designer Software, ModelSim HDL Simulator,
WaveFormer Lite, and Actel’s Silicon Explorer II.
RT54SX-S Probe Circuit Control Pins
The RT54SX-S RadTolerant devices contain internal probing
circuitry that provides built-in access to every node in a
design, enabling 100-percent real-time observation and
analysis of a device's internal logic nodes without design
iteration. The probe circuitry is accessed by Silicon
Explorer II, an easy to use integrated verification and logic
analysis tool that can sample data at 100 MHz (asynchronous)
or 66 MHz (synchronous). Silicon Explorer II attaches to a
PC’s standard COM port, turning the PC into a fully functional
18 channel logic analyzer. Silicon Explorer II allows designers
to complete the design verification process at their desks and
reduces verification time from several hours per cycle to a few
seconds.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 14 on page 13
illustrates the interconnection between Silicon Explorer II
and the FPGA to perform in-circuit verification.
Design Considerations
Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input
or bidirectional ports. Since these pins are active during
probing, critical input signals through these pins are not
available. In addition, do not program the Security Fuse.
Programming the Security Fuse disables the Probe Circuit.
Actel recommends that you use a series 70 Ω termination
resistor on every probe connector (TDI, TCK, TMS, TDO,
PRA, PRB). The 70 Ω series termination is used to prevent
data transmission corruption during probing and reading
back the checksum.
Table 8 • Device Configuration Options for Probe Capability
JTAG Mode TRST
Security Fuse
Programmed PRA, PRB, TDO1TDI and TCK1
Dedicated LOW No User I/O2Probing Unavailable
Flexible LOW No User I/O2User I/O2
Dedicated HIGH No Probe Circuit Outputs Probe Circuit Inputs
Flexible HIGH No Probe Circuit Outputs Probe Circuit Inputs
– – Yes Probe Circuit Secured Probe Circuit Secured
Notes:
1. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports during probing. Since these pins are active during
probing, input signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by the
Designer software.