TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V
Fixed-Output and Adjustable Versions
D
Integrated Precision Supply-Voltage
Supervisor Monitoring Regulator Output
Voltage
D
Active-Low Reset Signal with 200-ms Pulse
Width
D
Very Low Dropout Voltage ...Maximum of
35 mV at IO = 100 mA (TPS7350)
D
Low Quiescent Current – Independent of
Load . . . 340 µA Typ
D
Extremely Low Sleep-State Current,
0.5 µA Max
D
2% Tolerance Over Full Range of Load,
Line, and Temperature for Fixed-Output
Versions§
D
Output Current Range of 0 mA to 500 mA
D
TSSOP Package Option Offers Reduced
Component Height For Critical Applications
description
The TPS73xx devices are members of a family of
micropower low-dropout (LDO) voltage regulators.
They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset
function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
AVAILABLE OPTIONS
OUTPUT VOLTAGE
(V) NEGATIVE-GOING RESET
THRESHOLD VOLTAGE (V) PACKAGED DEVICES
CHIP FORM
TJMIN TYP MAX MIN TYP MAX SMALL
OUTLINE
(D)
PLASTIC DIP
(P) TSSOP
(PW)
CHIP
FORM
(Y)
4.9 5 5.1 4.55 4.65 4.75 TPS7350QD TPS7350QP TPS7350QPW TPS7350Y
4.75 4.85 4.95 4.5 4.6 4.7 TPS7348QD TPS7348QP TPS7348QPW TPS7348Y
40
°
Cto
3.23 3.3 3.37 2.868 2.934 3 TPS7333QD TPS7333QP TPS7333QPW TPS7333Y
40°C
to
125°C2.94 3 3.06 2.58 2.64 2.7 TPS7330QD TPS7330QP TPS7330QPW TPS7330Y
125 C
2.425 2.5 2.575 2.23 2.32 2.39 TPS7325QD TPS7325QP TPS7325QPW TPS7325Y
Adjustable
1.2 V to 9.75 V 1.101 1.123 1.145 TPS7301QD TPS7301QP TPS7301QPW TPS7301Y
The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable
using an external resistor divider (see application information). The chip form is tested at 25°C.
§The TPS7325 has a tolerance of ±3% over the full temperature range.
The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively , offering performance similar to that of the TPS73xx but
without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages
(TSSOP) for applications requiring minimum package size.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
NC
NC
EN
NC
IN
IN
IN
RESET
NC
NC
FB
NC
SENSE
OUT
OUT
NC
NC
PW PACKAGE
(TOP VIEW)
NC – No internal connection
SENSE – Fixed voltage options only
(TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)
FB – Adjustable version only (TPS7301)
1
2
3
4
8
7
6
5
GND
EN
IN
IN
RESET
SENSE/FB
OUT
OUT
D OR P PACKAGE
(TOP VIEW)
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator
to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low . RESET stays low
for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out
begins. At the completion of the 200-ms delay, RESET goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance
is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV
at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1).
Additionally , since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains
constant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500 mA).
These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.
The TPS73xx is offered in 2.5-V, 3-V , 3.3-V, 4.85-V , and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is
available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of
1.2 mm.
Figure 1. Dropout Voltage Versus Output Current
0.25
0.2
0.1
0.05
0
0.15
0 50 100 150 200 250 300
0.3
350 400 450 500
TA = 25°C
TPS7348
TPS7350
Dropout Voltage – V
IO – Output Current – mA
TPS7333
TPS7330
TPS7325
Figure 2. Typical Application Configuration
TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage
options)
Capacitor selection is nontrivial. See application information
section for details.
SENSE
RESET
OUT
OUT
9
8
6
10
IN
IN
IN
EN
GND
321
20
15
14
13
VI
0.1 µF
To System
Reset
CSR = 1
VO
10 µF
+
TPS73xxPW
CO
250 k
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS73xxY chip information
These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted
with conductive epoxy or a gold-silicon preform.
(6)
(4)
(3)
(7)
(2)
(1)
GND
FB
OUT
RESET
IN
EN TPS73xx
80
92
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
SENSE – Fixed voltage options only (TPS7325, TPS7330,
TPS7333, TPS7348, and TPS7350)
FB – Adjustable version only (TPS7301)
BONDING PAD ASSIGNMENTS SENSE
(5)
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to SENSE-pin
connection discussion in the applications
information section of this data sheet.
(3)
(4)
(5)
(6)
(7)
(2)
(1)
functional block diagram
_
+
Vref
OUT
SENSE§/FB
EN
IN
GND
R1
R2
RESET
_
+
TPS7301
TPS7325
TPS7330
TPS7333
TPS7348
TPS7350
DEVICE UNITR1 R2
0
260
358
420
726
756
233
233
233
233
233
k
k
k
k
k
RESISTOR DIVIDER OPTIONS
§For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in applications information section.
Switch positions are shown with EN low (active).
NOTE A. Resistors are nominal values only.
Delayed
Reset
¶¶
MOS transistors
Bilpolar transistors
Diodes
Capacitors
Resistors
COMPONENT COUNT
464
41
4
17
76
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing diagram
Vres is the minimum input voltage for a valid RESET . The symbol Vres is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
VI
VresVres
t
t
t
VO
Threshold
Voltage
RESET
Output 200 ms
Delay 200 ms
Delay
Output
Undefined
Output
Undefined
VIT+
VIT VIT
VIT+
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range§, VI, RESET, SENSE, EN 0.3 V to 11 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Tables 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
§All voltage values are with respect to network terminal ground.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (SEE FIGURE 3)
PACKAGE
T
A
25°CDERATING FACTOR T
A
= 70°C T
A
= 125°C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATING
A
POWER RATING
D725 mW 5.8 mW/°C464 mW 145 mW
P1175 mW 9.4 mW/°C752 mW 235 mW
PW700 mW 5.6 mW/°C448 mW 140 mW
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (SEE FIGURE 4)
PACKAGE
T
C
25°CDERATING FACTOR T
C
= 70°C T
C
= 125°C
PACKAGE
C
POWER RATING ABOVE TC = 25°C
C
POWER RATING
C
POWER RATING
D2188 mW 9.4 mW/°C1765 mW 1248 mW
P2738 mW 21.9 mW/°C1752 mW 548 mW
PW4025 mW 32.2 mW/°C2576 mW 805 mW
Refer to Thermal Information section for detailed power dissipation considerations when using the
TSSOP package.
Figure 3
PW Package
RθJA = 178°C/W
1200
800
400
025 50 75 100
– Maximum Continuous Dissipation – mW
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
125 150
1400
1000
600
200
PD
TA – Free-Air Temperature – °C
D Package
RθJA = 172°C/W
P Package
RθJA = 106°C/W
Figure 4
2400
1600
800
025 50 75 100
– Maximum Continuous Dissipation – mW
3200
4000
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
4800
125 150
4400
3600
2800
2000
1200
400
PD
TC – Case Temperature – °C
D Package
RθJC = 57°C/W
P Package
RθJC = 46°C/W
PW Package
RθJC = 37°C/W
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
TPS7301Q 2.47 10
V
TPS7325Q 3.1 10
V
In
p
ut voltage VI
TPS7330Q 3.5 10 V
Inp
u
t
v
oltage
,
V
I
TPS7333Q 3.77 10
TPS7348Q 5.2 10 V
TPS7350Q 5.33 10
High-level input voltage at EN, VIH 2 V
Low-level input voltage at EN, VIL 0.5 V
Output current range, IO0 500 mA
Operating virtual junction temperature range, TJ–40 125 °C
Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO,
at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads.
To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
VI(min)
+
VO(max)
)
VDO(max load)
Because the TPS7301 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating
VDO from rDS(on) is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for
the recommended input voltage range for the TPS7301.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR = 1 ), SENSE/FB shorted to
OUT (unless otherwise noted)
PARAMETER TEST CONDITIONS§TJMIN TYP MAX UNIT
EN 0.5 V
,
V
I
= V
O
+ 1 V
,
25°C 340 400
µA
u
u
v
EN
0.5
V,
VI
VO
+
1
V,
0 mA IO 500 mA –40°C to 125°C 550 µ
A
p
EN V
27VV10 V
25°C 0.01 0.5
µA
u
u
y
EN
=
V
I,
2
.
7
V
V
I
10
V
–40°C to 125°C 2 µ
A
p
VO=0V
VI=10V
25°C 1.2 2
A
u
u
u
V
O =
0
V
,
V
I =
10
V
–40°C to 125°C 2
A
Pass-element leakage current in standby
EN V
27VV10 V
25°C 0.01 0.5
µA
mode
EN
=
V
I,
2
.
7
V
V
I
10
V
–40°C to 125°C 1 µ
A
Normal operation
V at RESET 10 V
25°C 0.02 0.5
µA
ea
age curren
N
orma
l
opera
ti
on,
V
a
t
RESET
=
10
V
–40°C to 125°C 0.5 µ
A
Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C
Thermal shutdown junction temperature 165 °C
2.5 V VI 6 V
40
°
Cto125
°
C
2
V
og
c
g
s
an
y mo
e
6 V VI 10 V
40°C
to
125°C
2.7
V
27VVI10 V
25°C 0.5
V
og
c
ow
ac
ve mo
e
2
.
7
V
V
I
10
V
–40°C to 125°C 0.5
V
EN hysteresis voltage 25°C 50 mV
0VVI10 V
25°C 0.5 0.001 0.5
µA
npu
curren
0
V
V
I
10
V
–40°C to 125°C 0.5 0.5 µ
A
p
25°C 2.05 2.5
V
u
I
v
–40°C to 125°C 2.5
V
IO(RESET) = 300 µA
25°C 1 1.5
V
n
mum
I
or va
I
O(RESET) = –
300
µ
A
–40°C to 125°C 1.9
V
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to Co.
§Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS7301Q electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 µF (CSR = 1 ), FB
shorted to OUT at device leads (unless otherwise noted)
PARAMETER TEST CONDITIONSTJMIN TYP MAX UNIT
25°C 1.182 V
Reference voltage (measured at FB) 2.5 V VI 10 V,
See Note 1 5 mA IO 500 mA, –40°C to 125°C 1.147 1.217 V
Reference voltage temperature
coefficient –40°C to 125°C 61 75 ppm/°C
VI=24V
50 µAIO150 mA
25°C 0.7 1
V
I =
2
.
4
V
,
50
µ
A
I
O
150
mA
–40°C to 125°C 1
VI=24V
150 mA IO500 mA
25°C 0.83 1.3
Pass-element series resistance
V
I =
2
.
4
V
,
150
mA
I
O
500
mA
–40°C to 125°C 1.3
(See Note 2)
VI=29V
50 µAIO500 mA
25°C 0.52 0.85
V
I =
2
.
9
V
,
50
µ
A
I
O
500
mA
–40°C to 125°C 0.85
VI = 3.9 V, 50 µA IO 500 mA 25°C 0.32
VI = 5.9 V, 50 µA IO 500 mA 25°C 0.23
In
p
ut regulation
V
I
= 2.5 V to 10 V, 50
µ
A I
O
500 mA, 25°C 3 18
mV
Inp
u
t
reg
u
lation
I,
See Note 1
µO,
–40°C to 125°C 25
mV
2.5 V V
I
10 V, I
O
= 5 mA to 500 mA, 25°C 5 14
mV
Out
p
ut regulation
I,
See Note 1
O,
–40°C to 125°C 25
mV
O
u
tp
u
t
reg
u
lation
2.5 V V
I
10 V, I
O
= 50
µ
A to 500 mA, 25°C 7 22
mV
I,
See Note 1
Oµ,
–40°C to 125°C 54
mV
IO=50µA
25°C 48 59
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 44
dB
Ripple
rejection
f
=
120
H
zI
O
= 500 mA, 25°C 45 54
dB
O,
See Note 1 –40°C to 125°C 44
Output noise-spectral density f = 120 Hz 25°C 2 µV/Hz
Co = 4.7 µF 25°C 95
Output noise voltage 10 Hz f 100 kHz Co = 10 µF 25°C 89 µVrms
Co = 100 µF 25°C 74
RESET trip-threshold voltage§VO(FB) decreasing –40°C to 125°C 1.101 1.145 V
RESET hysteresis voltage§Measured at VO(FB) 25°C 12 mV
RESET out
p
ut low voltage§
VI= 2 13 V
IO(RESET) = 400 µA
25°C 0.1 0.4
V
RESET
ou
t
pu
t
l
ow vo
lt
age
§
V
I =
2
.
13
V
,
I
O(RESET) =
400
µ
A
–40°C to 125°C 0.4
V
FB in
p
ut current
25°C–10 0.1 10
nA
FB
inp
u
t
c
u
rrent
–40°C to 125°C–20 20
nA
CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: VDO = IO rDS(on)
rDS(on) is a function of both output current and input voltage. This parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively . For other
programmed values, refer to Figure 33.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS7325Q electrical characteristics at IO = 10 mA, VI = 3.5 V , EN = 0 V, Co = 10 µF (CSR = 1 ), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONSTJMIN TYP MAX UNIT
Out
p
ut voltage
25°C 2.45 2.5 2.55
V
O
u
tp
u
t
v
oltage
3.5 V VI 10 V, 5 mA IO 500 mA –40°C to 125°C 2.425 2.575
V
§
IO=10mA
VI= 2 97 V
25°C 5
§
I
O =
10
mA
,
V
I =
2
.
97
V
–40°C to 125°C 14
Dropout voltage§
IO= 100 mA
VI= 2 97 V
25°C 50 80
mV
D
ropou
t
vo
lt
age
§
I
O =
100
mA
,
V
I =
2
.
97
V
–40°C to 125°C 150
mV
IO= 500 mA
VI= 2 97 V
25°C 270 400
I
O =
500
mA
,
V
I =
2
.
97
V
–40°C to 125°C 600
Pass element series resistance§
(2.97 V – V
O
)/I
O
, V
I
= 2.97 V, 25°C 0.5 0.7
Pass
-
element
series
resistance§
(O)O,
IO = 500 mA
I,
–40°C to 125°C 1.4
In
p
ut regulation
VI=35Vto10V
50 µAIO500 mA
25°C 6 20
mV
Inp
u
t
reg
u
lation
V
I =
3
.
5
V
to
10
V
,
50
µ
A
I
O
500
mA
–40°C to 125°C 25
mV
IO=5mAto500mA
35VVI10 V
25°C 20 32
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
3
.
5
V
V
I
10
V
–40°C to 125°C 50
mV
O
u
tp
u
t
reg
u
lation
IO=50µA to 500 mA
35VVI10 V
25°C 28 60
mV
I
O =
50
µ
A
to
500
mA
,
3
.
5
V
V
I
10
V
–40°C to 125°C 100
mV
IO=50µA
25°C 50 53
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 49
dB
Ripple
rejection
f
=
120
H
z
IO= 500 mA
25°C 49 53
dB
I
O =
500
mA
–40°C to 125°C 32
Output noise-spectral density f = 120 Hz 25°C 2 µV/Hz
Co = 4.7 µF25°C 274
Output noise voltage 10 Hz f 100 kHz Co = 10 µF25°C 228 µVrms
Co = 100 µF25°C 159
RESET trip-threshold voltage VO decreasing –40°C to 125°C 2.23 2.32 2.39 V
RESET out
p
ut low voltage
VI=21V
IO(RESET) =08mA
25°C 0.14 0.4
V
RESET
output
low
voltage
V
I =
2
.
1
V
,
I
O(RESET) = –
0
.
8
mA
–40°C to 125°C 0.4
V
CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from
output voltage.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS7330Q electrical characteristics at IO = 10 mA, VI = 4 V , EN = 0 V, Co = 4.7 µF (CSR = 1 ), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONSTJMIN TYP MAX UNIT
Out
p
ut voltage
25°C 3
V
O
u
tp
u
t
v
oltage
4 V VI 10 V, 5 mA IO 500 mA –40°C to 125°C 2.94 3.06
V
IO=10mA
VI= 2 94 V
25°C 5.2 7
I
O =
10
mA
,
V
I =
2
.
94
V
–40°C to 125°C 10
Dropout voltage
IO= 100 mA
VI= 2 94 V
25°C 52 75
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
2
.
94
V
–40°C to 125°C 100
mV
IO= 500 mA
VI= 2 94 V
25°C 267 450
I
O =
500
mA
,
V
I =
2
.
94
V
–40°C to 125°C 500
Pass element series resistance
(2.94 V – V
O
)/I
O
, V
I
= 2.94 V, 25°C 0.5 0.7
Pass
-
element
series
resistance
(O)O,
IO = 500 mA
I,
–40°C to 125°C 1
In
p
ut regulation
VI=4Vto10V
50 µAIO500 mA
25°C 6 23
mV
Inp
u
t
reg
u
lation
V
I =
4
V
to
10
V
,
50
µ
A
I
O
500
mA
–40°C to 125°C 29
mV
IO=5mAto500mA
4VVI10 V
25°C 20 32
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
4
V
V
I
10
V
–40°C to 125°C 60
mV
O
u
tp
u
t
reg
u
lation
IO=50µA to 500 mA
4VVI10 V
25°C 28 60
mV
I
O =
50
µ
A
to
500
mA
,
4
V
V
I
10
V
–40°C to 125°C 120
mV
IO=50µA
25°C 43 53
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 40
dB
Ripple
rejection
f
=
120
H
z
IO= 500 mA
25°C 39 53
dB
I
O =
500
mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2 µV/Hz
Co = 4.7 µF25°C 274
Output noise voltage 10 Hz f 100 kHz Co = 10 µF25°C 228 µVrms
Co = 100 µF25°C 159
RESET trip-threshold voltage VO decreasing –40°C to 125°C 2.58 2.64 2.7 V
RESET out
p
ut low voltage
VI=26V
IO(RESET) =08mA
25°C 0.14 0.4
V
RESET
output
low
voltage
V
I =
2
.
6
V
,
I
O(RESET) = –
0
.
8
mA
–40°C to 125°C 0.4
V
CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS7333Q electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 µF (CSR = 1 ),
SENSE shorted to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONSTJMIN TYP MAX UNIT
Out
p
ut voltage
25°C 3.3
V
O
u
tp
u
t
v
oltage
4.3 V VI 10 V, 5 mA IO 500 mA –40°C to 125°C 3.23 3.37
V
IO=10mA
VI= 3 23 V
25°C 4.5 7
I
O =
10
mA
,
V
I =
3
.
23
V
–40°C to 125°C 8
Dropout voltage
IO= 100 mA
VI= 3 23 V
25°C 44 60
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
3
.
23
V
–40°C to 125°C 80
mV
IO= 500 mA
VI= 3 23 V
25°C 235 300
I
O =
500
mA
,
V
I =
3
.
23
V
–40°C to 125°C 400
Pass element series resistance
(3.23 V – V
O
)/I
O
, V
I
= 3.23 V, 25°C 0.44 0.6
Pass
-
element
series
resistance
(O)O,
IO = 500 mA
I,
–40°C to 125°C 0.8
In
p
ut regulation
VI=43Vto10V
50 µAIO500 mA
25°C 6 23
mV
Inp
u
t
reg
u
lation
V
I =
4
.
3
V
to
10
V
,
50
µ
A
I
O
500
mA
–40°C to 125°C 29
mV
IO=5mAto500mA 43VVI10 V
25°C 21 38
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
4
.
3
V
V
I
10
V
–40°C to 125°C 75
mV
O
u
tp
u
t
reg
u
lation
IO=50µA to 500 mA 4 3 V VI10 V
25°C 31 60
mV
I
O =
50
µ
A
to
500
mA
,
4
.
3
V
V
I
10
V
–40°C to 125°C 120
mV
IO=50µA
25°C 43 51
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 40
dB
Ripple
rejection
f
=
120
H
z
IO= 500 mA
25°C 39 49
dB
I
O =
500
mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2 µV/Hz
Co = 4.7 µF25°C 274
Output noise voltage 10 Hz f 100 kHz Co = 10 µF25°C 228 µVrms
Co = 100 µF25°C 159
RESET trip-threshold voltage VO decreasing –40°C to 125°C 2.868 V
RESET hysteresis voltage 25°C 18 mV
RESET out
p
ut low voltage
VI=28V
IO(RESET) =1mA
25°C 0.17 0.4
V
RESET
output
low
voltage
V
I =
2
.
8
V
,
I
O(RESET) = –
1
mA
–40°C to 125°C 0.4
V
CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS7348Q electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 µF (CSR = 1 ),
SENSE shorted to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONSTJMIN TYP MAX UNIT
Out
p
ut voltage
25°C 4.85
V
O
u
tp
u
t
v
oltage
5.85 V VI 10 V, 5 mA IO 500 mA –40°C to 125°C 4.75 4.95
V
IO=10mA
VI= 4 75 V
25°C 2.9 6
I
O =
10
mA
,
V
I =
4
.
75
V
–40°C to 125°C 8
Dropout voltage
IO= 100 mA
VI= 4 75 V
25°C 28 37
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
4
.
75
V
–40°C to 125°C 54
mV
IO= 500 mA
VI= 4 75 V
25°C 150 180
I
O =
500
mA
,
V
I =
4
.
75
V
–40°C to 125°C 250
Pass element series resistance
(4.75 V – V
O
)/I
O
, V
I
= 4.75 V, 25°C 0.28 0.37
Pass
-
element
series
resistance
(O)O,
IO = 500 mA
I,
–40°C to 125°C 0.52
In
p
ut regulation
VI=585Vto10V
50 µAIO500 mA
25°C 9 35
mV
Inp
u
t
reg
u
lation
V
I =
5
.
85
V
to
10
V
,
50
µ
A
I
O
500
mA
–40°C to 125°C 37
mV
IO=5mAto500mA 585VVI10 V
25°C 28 42
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
5
.
85
V
V
I
10
V
–40°C to 125°C 80
mV
O
u
tp
u
t
reg
u
lation
IO=50µA to 500 mA 5 85 V VI10 V
25°C 42 65
mV
I
O =
50
µ
A
to
500
mA
,
5
.
85
V
V
I
10
V
–40°C to 125°C 130
mV
IO=50µA
25°C 42 53
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 39
dB
Ripple
rejection
f
=
120
H
z
IO= 500 mA
25°C 39 50
dB
I
O =
500
mA
–40°C to 125°C 35
Output noise-spectral density f = 120 Hz 25°C 2 µV/Hz
Co = 4.7 µF25°C 410
Output noise voltage 10 Hz f 100 kHz Co = 10 µF25°C 328 µVrms
Co = 100 µF25°C 212
RESET trip-threshold voltage VO decreasing –40°C to 125°C 4.5 4.7 V
RESET hysteresis voltage 25°C 26 mV
RESET out
p
ut low voltage
IO(RESET) =12mAV
I= 4 12 V
25°C 0.2 0.4
V
RESET
output
low
voltage
I
O(RESET) = –
1
.
2
mA
,
V
I =
4
.
12
V
–40°C to 125°C 0.4
V
CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS7350Q electrical characteristics at IO = 10 mA, VI = 6 V , EN = 0 V , Co = 4.7 µF (CSR = 1 ), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONSTJMIN TYP MAX UNIT
Out
p
ut voltage
25°C 5
V
O
u
tp
u
t
v
oltage
6 V VI 10 V, 5 mA IO 500 mA –40°C to 125°C 4.9 5.1
V
IO=10mA
VI= 4 88 V
25°C 2.9 6
I
O =
10
mA
,
V
I =
4
.
88
V
–40°C to 125°C 8
Dropout voltage
IO= 100 mA
VI= 4 88 V
25°C 27 35
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
4
.
88
V
–40°C to 125°C 50
mV
IO= 500 mA
VI= 4 88 V
25°C 146 170
I
O =
500
mA
,
V
I =
4
.
88
V
–40°C to 125°C 230
Pass element series resistance
(4.88 V – V
O
)/I
O
, V
I
= 4.88 V, 25°C 0.27 0.35
Pass
-
element
series
resistance
(O)O,
IO = 500 mA
I,
–40°C to 125°C 0.5
In
p
ut regulation
VI=6Vto10V
50 µAIO500 mA
25°C 4 25
mV
Inp
u
t
reg
u
lation
V
I =
6
V
to
10
V
,
50
µ
A
I
O
500
mA
–40°C to 125°C 45
mV
IO=5mAto500mA
6VVI10 V
25°C 30 45
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
6
V
V
I
10
V
–40°C to 125°C 86
mV
O
u
tp
u
t
reg
u
lation
IO=50µA to 500 mA
6VVI10 V
25°C 45 65
mV
I
O =
50
µ
A
to
500
mA
,
6
V
V
I
10
V
–40°C to 125°C 140
mV
IO=50µA
25°C 43 53
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 38
dB
Ripple
rejection
f
=
120
H
z
IO= 500 mA
25°C 41 51
dB
I
O =
500
mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2 µV/Hz
Co = 4.7 µF25°C 430
Output noise voltage 10 Hz f 100 kHz Co = 10 µF25°C 345 µVrms
Co = 100 µF25°C 220
RESET trip-threshold voltage VO decreasing –40°C to 125°C 4.55 4.75 V
RESET hysteresis voltage 25°C 28 mV
RESET out
p
ut low voltage
IO(RESET) =12mA V
I= 4 25 V
25°C 0.15 0.4
V
RESET
output
low
voltage
I
O(RESET) = –
1
.
2
mA
,
V
I =
4
.
25
V
–40°C to 125°C 0.4
V
CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics
PARAMETER TEST CONDITIONS T
J
TPS7301Q, TPS7333Q
TPS7348Q, TPS7350Q UNIT
J
MIN TYP MAX
RESET time out delay
See Figure 5
25°C 140 200 260
ms
RESET
ti
me-ou
t
d
e
l
ay
See
Fig
u
re
5
–40°C to 125°C 100 300
ms
electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR = 1 ), TJ = 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONS
TPS7301Y, TPS7333Y
TPS7348Y, TPS7350Y UNIT
MIN TYP MAX
Ground current (active mode) EN 0.5 V,
0 mA IO 500 mA VI = VO + 1 V, 340 µA
Input current (standby mode) EN = VI,2.7 V VI 10 V 0.01 µA
Output current limit VO = 0 V, VI = 10 V 1.2 A
Pass-element leakage current in standby mode EN = VI,2.7 V VI 10 V 0.01 µA
RESET leakage current Normal operation, V at RESET = 10 V 0.02 µA
Thermal shutdown junction temperature 165 °C
EN logic low (active mode) 2.7 V VI 10 V 0.5 V
EN hysteresis voltage 50 mV
EN input current 0 V VI 10 V 0.001 µA
Minimum VI for active pass element 2.05 V
Minimum VI for valid RESET IO(RESET) = –300 µA 1 V
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS7301Y electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 µF (CSR = 1 ),
TJ = 25°C, FB shorted to OUT at device leads (unless otherwise noted)
PARAMETER TEST CONDITIONSMIN TYP MAX UNIT
Reference voltage (measured at FB) 1.182 V
VI = 2.4 V, 50 µA IO 150 mA 0.7
VI = 2.4 V, 150 mA IO 500 mA 0.83
Pass-element series resistance (See Note 2) VI = 2.9 V, 50 µA IO 500 mA 0.52
VI = 3.9 V, 50 µA IO 500 mA 0.32
VI = 5.9 V, 50 µA IO 500 mA 0.23
Input regulation VI = 2.5 V to 10 V,
See Note 1 50 µA IO 500 mA, 3 mV
Out
p
ut regulation
2.5 V VI 10 V,
See Note 1 IO = 5 mA to 500 mA, 5 mV
O
u
tp
u
t
reg
u
lation
2.5 V VI 10 V,
See Note 1 IO = 50 µA to 500 mA, 7 mV
IO = 50 µA 59
Ripple rejection f = 120 Hz IO = 500 mA,
See Note 1 54 dB
Output noise-spectral density f = 120 Hz 2µV/Hz
Co = 4.7 µF 95
Output noise voltage 10 Hz f 100 kHz Co = 10 µF 89 µVrms
Co = 100 µF 74
RESET hysteresis voltage§Measured at VO(FB) 12 mV
RESET output low voltage§VI = 2.13 V, IO(RESET) = 400 µA 0.1 V
FB input current 0.1 nA
CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: VDO = IO rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively . For other
programmed values, refer to Figure 33.