COP400 | Microcontroller Family COPS Family Users Guide Nationai Semiconductor 9-3 epinyd sjesy Ayjwes SdOOCOPS Family Users Guide COPS Family Users Guide Table of Contents | Section 1.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3.1 3.2 3.3 3.4 3.5 4.1 4.2 43 4.4 4.5 4.6 47 4.8 4.9 4.10 4.11 5.1 5.2 5.3 5.4 5.5 5.6 Description Page Chapter 1. Introduction to COP400 Microcontrollers Summary of COP400 Microcontroller Features. ..........0.... 0s eeeeeaeees 9-7 Chapter 2, COP400 Architecture COP420/COP421 Architecture. ........ 00.0 ccc cece cece eee eee eeanaaes 9-8 COP420/COP421 Functional Description ...........0c ccc cece cece uenes 9-10 Initialization 2.0... ccc cee ne renee tees eneuesueneuauge 9-11 COP420/COP421 Mask Programmable Options ..............ceeeeeeeeee 9-12 COP420L/COP421L Description .......... ccc cece eee eeeeeenees 9-15 COP420L/COP421L Mask-Programmable Options ............2.0000eseee 9-15 COP420C Description ......... 0... ccc cece cence een eeeeeautteneeas 9-17 COP444L Description. ...... 0.0... ccc ccc cece eee renee eentsenaengs 9-18 COP402 and COP402M ROMless Part Description.................20000- 9-18 ~ COP404L ROMless Part Description ................ pene een e ee eeeae 9-18 COP410L/COP411L Architecture ......... 00.0. cece cece eee eee e naa 9-13 COP410L/COP411L Functional Description ............... 000s ceaaee 9-20 COP410L/COP411L Mask-Programmable Options .................00e eee 9-21 Chapter 3. COP400 Instruction Sets COP420-Series/COP444L Instruction Set........ 0... ccc avec cece eee caes 9-23 COP420-Series/COP444L Instruction Set Description ................0005 9-27 COP421-Series Instruction Set Differences............ ccc cece cece eee 9-34 COP410L/COP411L Instruction Set ............ cc cece cece eee eee evene 9-34 COP410L/COP411L Instruction Set Differences ......... 2.0.0.0 cece ees 9-37 Chapter 4. COP400 Programming Techniques Program Memory Allocation ....... 0.0 .cc cece cence eee nuenaenenenaes 9-42 Data Memory Allocation and Manipulation ...............0.--000: bees 9-45 Subroutine Techniques ............ 0c: cee e eee cee eee euaanveneunees 9-46 Utility Routines 2.0... ccc cee cee eee eet eneenneteuagueas 9-47 Timing Considerations ........ 0.0... cc cece cee eee eee e ee eeeneeeans 9-48 BCD Arithmetic Routines .......... 00. ccc cect ersten eeseuenenaes 9-49 Simple Display Loop Routine ............ ccc eee ec eect e eect eeeeeuns 9-51 Interrupt Service Routine... . 0... 0. cece cece eee eaeceertveees 9-53 Timekeeping Routine ..... 2... cece ccc ee enn ee nneeenesneres 9-53 String Search Routine 0.0... 2. ccc cee eens eee t ens ennenes 9-56 Programming Techniques for the COP421-Series, COP410L and 411L....... 9-57 Chapter 5. COP400 I/O Techniques Hardware interfacing Techniques ............ccccucucccccevevcvceueus 9-58 Software VO Techniques .........- 0.0 ccc ccc cece cence eta eaenenevans 9-63 Keyboard/Display Interface. ... 0.0... . cece cece enc cee ucucueuuuunevuas 9-64 SIO (Serial) Input/Output .......... 0.0. ec cen encase nenennenaes A-75 Add-On RAM 20... cece ccc ccc ccenvevececeeeeeeuuennneeeeeeeeeeees }.9-76 INg/INg Inputs 2.0.6... cece cece eee cece cece enc catesuaeneutnnens | .9-77 9-4COPS Family Users Guide List of Figures Figure 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3.1 3.2 41 4.2 43 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 Description COP420/COP421 Block Diagram... 2... ke ees COP420/COP421 Connection Diagrams... 0... 0.0.0. cee COP420/COP421 Pin Descriptions ............ 00.02 eee eee Power-Clear Circuito... . 0c cece ete eter e tnt eee COP420/COP421 Clock Oscillator Configurations .............. 0.00000 COP420/COP421 input/Output Configurations .......... 0... see eee eee COP420L/COP421L Oscillator Configurations .............-. 22.0 eae eee COPAIOLICOP411L Block Diagram ..... 22.0.0... 0002 ee eens COP410L/COP411L Connection Diagrams. ..... 0... 6. cee ees COP410L/COP411L Pin Description .....0... 0... cee ee eee COP410L/COP411L Oscillator Configurations ...... 6... cece ce eee eee INIL Hardware implementation................ beeen et eens Enable Register Features Bits ENg and ENo..........-...2.0.-0--202. COP420 Data Memory Map ..... 066 ee ete eee eee Flowchart for Multiply Routine .......... 0.0... eee eee ee Flowchart for Timekeeping Routine ........... cece eee ee eee COP420 WO LineS ... cc erent ett ene ees COP420 10 Options ............0 002 ec eee e ees COP420 Standard Output Characteristics........... Lecce cence eee eenee COP420 I/O Interconnect Examples .......0..06-. 0c cece eee ete eee COP420 IN Input.Characteristics ............. 0.0002 e eee eee D and G Port Characteristics... 0.2.00... 0. cee eens COP420L I/O Port Characteristics 6.0... 0.0 ccc cee eee COP420 SI,SO, SK CharacteristicS ........ 0... cc cece cee eee eee ees COP420 CKO, CKI, RESET Characteristics ........ 0... cece eee eee COP420 VO Expansion... 0.0.0.0... 2c COP420 LED Display System ......... 00.0... eee eee eee COP420 VF Display System.......0. 0... cee ene eee COP420 MICROBUS Interconnect........ 02.000 ccc ccc eee ence eens COP420 Add-On RAM... . occ ener ee ee enn en en enna Display/Keyboard Interconnect ........... 0.00.2 cee eet teens Fiowchart for Display/Keyboard Debounce Routine..................000. Display Timing Diagram ......... 6... tees Display/Keyboard Interface Source Code ......... 0.0.0... cee cee Key-Decode Routine Assembier Output Listing ......... 0.0... ee eee eee Additional /O Using Sland SO .... 2. 0... cee tenes Multi-COP420 System ........ 200... c eee eee eee e etna Add-On RAM Interconnect... 2.2.0.0... 0. ccc ee eet eens 9-5 epiny ssesy Ajjwe4 SdOdCOPS Family Users Guide COPS Family Users Guide List of Tables | Table Description Page 3.1 COP420/COP421 Instruction Set Table ........... 00. e ee eee eeee 9-24 3.2 COP420/COP421 Instruction Set Symbols............ 00 cece eee neces 9-27 3.3 COP410L/COP411L Instruction Set Table ......... 0.0.00: cece eee eens 9-34 3.4. COP410L/COP411L Instruction Set Symbols ............0 0c cee eee eee 9-37 3.5 Alphabetical Mnemonic Index of COP420/COP421 Instructions............ 9-38 3.6 COP420/COP421 Instructions Listed by Hex Opcodes..................0. 9-39 3.7 Alphabetical Mnemonic Index of COP410L/COP411L Instructions ......... 9-40 3.8 COP410L/COP411L Instructions Listed by Hex Opcodes ......---...00005 9-41 4.1. Page to Hexadecimal Address ........ 0... ccc ccc cence nees 9-42 5.1 COP400-I/O0 Comparison Chart ........ 0.000 cece eee e eee ewe eeneees 9-58 5.2 Seven-Segment Decode Values ........... cc cece ec uc eee e eee ennveeenes 9-68 5.3 JID Pointer Table for Display/Keyboard Routine ..............00e eee ees 9-73 9-6Introduction to the COP400 Microcontrollers This manual provides information on the COP400 series of Nationals single-chip microcontrollers. The material contained in this manual is intended to assist the reader in understanding the internal architecture, instruction set, programming techniques, and hardware and software I/O tech- niques pertaining to the COP400 family of micro- controller devices. The primary focus of this manual is the CoP420 at the time of this printing the most inclusive device, on a hardware and software level, of the COP400 family. Other members of the COP400 family are discussed primarily in terms of the less inclusive features of these other parts (i.e., the COP421, COP410L, COP411L). This approach should not result in a lack of understanding in terms of the operation and programming of these parts since they are subset devices of the COP420, distinguished, for the most part, by deleted hardware and software features. For further information on these other devices and on future COP400 devices the reader should consult the data sheets appropriate to particular COP400 devices. 4.1 Summary of COP400 Microcontroller Features COP400 Microcontrollers are fabricated using CMOS or N-channel, silicon gate MOS technology. They are complete microcomputers containing all system timing, internal logic, ROM, RAM, and 0 necessary to implement dedicated control functions in a variety of applications. Features of the COP400 devices include an instruction set, internal architecture, and 0 scheme designed to facilitate keyboard input, display output, and efficient BCD data manipulation. The various members of the COP400 family allow the user to specify a microcontroller best suited for use in a particular dedicated application. Specifically, COP400 devices offer a choice among single-chip parts with differing amounts of ROM, RAM, W/O capability, and number of instructions. Additionally, many parts have different versions which allow a choice of electrical characteristics while retaining the basic architecture and instruction set of the basic device. (For example, the COP420L and COP420C are available as low- power and CMOS versions, respectively, of the standard COP420 device.) Finally, each part contains a number of clock, O and other options, 9-7 mask-programmed into the part at the same time as the users program; this allows even greater flexibility in matching the COP400 Microcontroller to the users specifications, reducing the need for external interface logic. epindy sJesn Ajwie4 SdOO All COP400 devices feature single-supply operation and fast, standardized, in-house test procedures which verify the internal logic and user program (ROM code) mask-programmed into the device. Several COP400 controllers are available in ROM- less versions for use in prototyping a COP400 system (using the COP400 Development System) or for low-volume applications. Section 1 provides a list of COP400 devices currently available or in design, together with a summary of the basic features of each device. Refer to this manual and data sheets of particular devices for further information on these parts. Future members of the COP400 family will include more powerful hardware and software capabilities, alternative electrical specification devices (low power, CMOS versions) and peripheral devices suitable for use in many applications. The flexible /O configuration of COP400 Microcontrollers allows them to interface with and drive a wide range of devices using minimal external parts. Typical peripheral devices include: 1. Keyboards and displays (direct segment and digit drive possible for several devices). 2. External data memories. 3. Printers. 4. Other COPS devices. 5. A/D and D/A converters. 6. Power control devices (SCRs, TRIACS). 7. Mechanical actuators. 8 . General purpose microprocessors {communication with host GPUs over National's MICROBUS for several COP400 devices). 9. Shift registers. ~ 10, External ROM data storage devices.COPS Family Users Guide COP400 Architecture This chapter provides information on the architecture of the COP400 Microcontrollers. Consistent with the general approach of this manual, the COP420 is primarily discussed with the COP421 treated in terms of differences with respect to the COP420. The COP410L, COP411L and COP444L are similarly treated. The text, therefore, primarily discusses the internal architecture of the COP420, with differences noted for the other devices. Also briefly discussed are different versions of each primary device (e.g., for he COP420, the COP420L and COP420C). As these additional devices, as well as the most inclusive COP400 device, the COP440, become available, further information will be provided in data sheets for each part. ad | | 7d 2.1 COP420/COP421 Architecture Figure 2.1 provides a block diagram of the COP420/COP421. It is intended to acquaint the user with the functions of, and interconnections among, the various logic blocks within the processor. Data paths are illustrated in simplified form to depict how the logic elements communicate with each other in implementing the instruction set of the devices. Note that the IN3-INo general purpose inputs are not available on the COP4?21, nor are the two internal IL latches associated with IN; and INo. TIME-BASE DIVIDER CLOocK GENERATOR COUNTER (DIVIDE BY 1028) PROGRAM MEMORY 1kx8 ROM ADORESS INSTRUCTION DECODE/CONTROL SKIP LOGIC 24 a REGISTER phos a 2g ee DIGIT ADDRESS LE DATAMEMORY _ AEG [gle 64x4 RAM AODA FX o | REGISTER BUFFER 4 L ORIVEAS oe el a S te a tyFigure 2.2 shows the connection diagrams for the 28-pin COP420 and the 24-pin COP421. Figure 2.3 provides a pin description for the COP420/COP421 devices. 9-9 One shouid consult the COP420/COP421 data sheet for maximum ratings, DC and AC electrical characteristics for these devices. Aaah ane Bas SPINS svesyy AWA SdODCOPS Family Users Guide 2.2 COP420/COP421 Functional Description The following text provides a functional description of the logic elements depicted in the COP420/COP421 block diagram. Program Memory Program memory consists of a 1,024-byte ROM. ROM words may be Program instructions, program data or ROM address pointers. Due to the special characteristics associated with the JP and JSRP instructions, ROM must often be conceived of as organized into 16 pages of 64 words (bytes) each. Also, because of the unique operations performed by the LQID and JID instructions, ROM pages must often be thought of as organized into four consecutive blocks of four ROM pages. (For further information on the paging characteristics of these instructions, see Section 4.1.) ROM addressing is accomplished by the 10-bit P register. Its binary value selects one of the 1,024 8-bit words (I7~ Ip} contained in ROM. The value of P is automatically incremented by 1 prior to the execution of the current instruction to point to the next sequential ROM location, untess the current instruction is a transfer of contro! instruction. Jn the latter case, P is loaded with the appropriate non-sequential value to implement the transfer of controi operation performed by the instruction. It should be noted that P will automatically roll-over to point to the next page of program memory. This feature has particular significance for transfer of controt instructions with paging restrictions, i.e., JP, JSRP, JID and LOID. Since P is incremented to roli-over to the next ROM Page prior to executing these instructions, they wilt be treated as residing on the next ROM page if they reside in the last word of a ROM page. Further information is provided in Section 4.1. Three levels of subroutine are implemented by the 10-bit subroutine save registers, SA, SB and SC, providing a iast-in, first-out (LIFO) hardware subroutine stack. ROM instruction words are fetched, decoded and executed by the Instruction Decode, Control and Skip Logic circuitry. Data Memory Data memory consists of a 256-bit RAM, organized as 4 data registers of 16 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1 of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) are usually loaded into or from, or exchanged with, the A register (accumulator), they may also be loaded into or from the Q latches or loaded from the L ports. RAM addressing may also be performed directly by the LOD and XAD instructions based upon the 6-bit contents of the operand field of these instructions. The Bd register also serves as a source register for 4-bit data sent directly to the D outputs. Internal Logic The 4-bit A register (accumulator) is the source and destination register for most 1/0, arithmetic, logic and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L i/O port data and to perform data exchanges with the SIO register. A 4-bit adder performs the arithmetic and logic functions of the COP420, storing results in A. It also outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register, in conjunction with the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SKL or can enable SKL to be a SYNC pulse, providing a clock each instruction cycle time. (See XAS instruction, Table 3.1, and EN register description, below.) Four general-purpose inputs, IN3-INo, are provided for the COP420: INq, IN2 and IN3 may be selected, by a mask-programmable option, as Read Strobe, Chip Select and Write Strobe inputs, respectively, for use in MICROBUS applications. The COP421 does not contain the IN3~-INg inputs and, therefore, must use the 4 bidirectional GIO ports or 8 bidirectional L VO ports as input pins to the device. Use of Nationals MICROBUS is inappropriate with the COP421. The D register provides 4 general purpose outputs and is used as the destination register for the 4-bit contents of Bd. The G register contents are output to 4 general- purpose bidirectional I/O ports. The COP420 Go pin may be mask-programmed as a ready output for MICROBUS applications. The Q register is an internal, latched, 8-bit register, used to hold data loaded to or fram M and A, as well as 8-bit program data from RON. its contents are output to the L I/O ports when the L drivers are enabled under program control (via an LEI instruc- tion). The COP420 may use the MICROBUS option to write L I/O port data into Q upon the occurrence af a WR pulse from the host CPU. The 8 L drivers, when enabled, output the contents of latched Q data to the L 0 ports. Also, the contents of L may be read directly into A and M. As explained above, the COP420 MICROBUS option aliows L I/O port data to be latched into the Qregister. L /O ports can be directly connected to the segments of a multiplexed LED display (using the TRI-STATE LED Direct Drive output configuration option) with Q data being outputted to the Sa-Sg and decimal point segments of the display. The SIO register functions as a 4-bit serial-in/ serial-out shift register or as a binary counter depending on the contents of the EN register. (See EN register description, below.) Its contents can be exchanged with A, allowing it to input or output a continuous serial data stream. SiO may also be used to provide additionai paraliel 1/0 when used as a shift register with its input or output connected to external serial-in/paratlel-out shift registers. The 10-bit time base counter divides the instruction cycle frequency by 1,024, providing a pulse upon overflow. The COP420 SKT instruction tests for the occurrence of this pulse, allowing the programmer to rely on this internal time-base rather than external inputs (e.g., 50/60 Hz signals) to implement real-time routines. The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register (EN3- ENo). 4. The least significant bit of the enable register, ENo, selects the SiO register as either a 4-bit shift register or a 4-bit binary counter. With ENg set, SIO is an asynchronous binary counter, de- crementing its value by on upon each low-going puise (1" to 0") occurring on the SI input (count-down counter). Each pulse must be at least two instruction cycies wide. SK outputs the value of C upon execution of XAS and remains latched until the execution of another XAS instruction. The SO output is equal to the value of EN3. With ENo reset, SIO is a serial shift register shifting ieft each instruction cycle time. The data present at SI goes into the least signifi- cant bit of SIO. SO can be enabled to output the most significant bit of SIO each cycle time. The SK output becomes a logic-controlled clock, providing a SYNC signal each instruction time. It will start outputting a SYNC pulse upon the execution of an XAS instruction with C=1, stopping upon the execution of a subsequent XAS with C =0. _ With EN, set, the COP420 IN, input is enabled as an interrupt input. Immediately following an interrupt, EN, is reset to disabie further interrupts. Note that this interrupt feature associated with IN, is unavailable on the COP421 since it tacks the IN inputs. Bit 1 (EN,) of the Enable Register is, therefore, a dont care bit for the COP421: setting or resetting this bit via an LEI instruction will have no effect on the operation of the COP421. (For further information on the procedure and protocol of this COP420 interrupt feature, see Section 3.2, LEI instruction description.) . With EN, set, the L drivers are enabled to output the data in Q to the L I/O ports. Resetting EN2 disables the L drivers, placing the L 1/0 ports in a high-impedance input state. If the COP420 MICROBUS option is being used, EN2 does not affect the L drivers. apiny ssesn Ajlwed SdOD _ EN, in conjunction with ENo, affects the SO output. With ENo set (binary counter option selected), SO will output the value loaded into EN. With ENo reset (serial shift register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN; with the serial shift register option selected disables SO as the shift register output: data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains reset to 0." Table 2.1 provides a summary of the options and features associated with EN3 and ENo. 2.3 Initialization Upon initialization of the COP420/COP421 as described below, the P register is cleared to 0 (ROM address 0} and the A, B, GC, D, EN, andG registers are cleared. The INg and INg latches are not cleared. The SK output is enabled as a SYNC output, providing a pulse each instruction cycle time. Data memory (RAM) can only be cleared by the users program. The first instruction at address O must be a CLARA. The Reset Logic, internal to the COP420/COP421, will initialize (clear) the device upon power-up if the power supply rise time is less than ims and greater than 1s. If the power supply rise time is greater than 1ms, the user must provide an external RC network and diode to the RESET pin as shown in Figure 2.4 below. The RESET pin is configured as a Schmitt trigger input. If not used, it should be connected to Vcc. Initialization will occur whenever a logic 0 is applied to the RESET input, provided it stays low for at least three instruction cycle times. In order to reset the Time Base Counter, a RESET pulse ten instruction cycle times wide must be applied; note that the counter will overflow and generate an output pulse.COPS Family Users Guide 2.4 COP420/COP421 Mask Programmable Options To allow even greater flexibility in specifying a COP400 device appropriate to the user's application, all COP400 microcontrollers have specific clock configuration, /O and other mask- programmable options associated with them. These options are masked into the part simuitaneously with the masking of the users program in ROM and have been chosen to offer the user a wide range of options which encompasses design options most frequently employed in dedicated, smali system applications. The following text summarizes the COP420/COP421 options according to the various functions foscillator, I/O, ete.) with which they are associated. Clock Oscillator Options There are four basic COP420/COP421 clock oscillator configurations avilable as shown by Figure 2.5 (a-d): a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals the crystal frequency (4MHz maximum) divided by 16 (optional by 8). b. External Oscillator. CKI is configured as a TTL compatible input accepting an external clock signal. The external frequency (4MHz maximum) is divided by 16 (optional by 8) to derive the instruction cycle time. CKO is now available to be used as the RAM power supply (Va) pin, as a general purpose input, or as a synchronizing input. , c. RC Controlled Oscillator. CKI is configured as a single-pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the osciliation frequency divided by 4. CKO is available for non-timing functions as in b above. d. Externally Synchronized Oscillator. Intended for use in multi-COP systems, CKO is programmed to function as an input connected to the SK output of ancther COP420/COP421 with CKI connected as shown. In this configuration, the SK output connected to CKO must provide a SYNC (instruction cycle) signal to CKO, thereby allowing synchronous data transfer between the COPs using only the SI and SO serial /O pins in conjunction with the XAS instruction. Note that On power-up SK is automatically enabled as a SYNC output. (See Initialization, above.) The lower portion of Figure 2.5 provides component values for several instruction cycle times and crystal values associated with the AG controtled and Crystal Oscillator options, respectively. CKO Non-Timing Options In a crystal controlled or multi-COP oscillator system, CKO is used as an output to the crystal network. [In the other two configurations (externa! clock or RC controlled oscillator), CKO may be mask-programmed to perform one of twa available options. Specifically, CKO may be mask- programmed as a general purpose input, read into bit 1 of the accumulator (Az) upon the execution of an INIL instruction. As another option (for bath the COP420 and COP421), CKO can be a RAM power supply pin (Vp), allowing its connection to a standby/backup power supply to maintain the integrity of RAM data with minimum power drain when the main supply is inoperative or shut down to conserve power. Use of this options should include external circuitry to detect loss of Vcc power and force RESET low before Veg drops below spec.CKO apiny sesy Ajlwejy SdOD od : ae -ec * eae (Vg: 08 GENERAL a ok : {p OR GENERAL t EXTERNAL | PURPOSE INPUT OS ae PURPOSE INPUT . Cl CLOGK ee GR SYNC FIND : T PINE -a, Crystal Oscillator . External Oscillater > .e.. RC. Controlled Oscillator BYAE) pt Poot Oe a. [cu CKOE CK! ko] = Sk 0P420/421 Be copaza/421 ue] St $1 |] SO __ d. Externally Synchronized Oscillator: . Crystal Oscillator RC Controlled Oscillator _ - : . ec in ey [ , { | instruction | : Component Values o4 a ' - Srystai On ne : . : Cycle Time i iL. Value Rt R2 Cc. i _R (ka) : ipF) / (us) " 4MH2 1k 4M 27 pF - 1 408 5 20% 3.58MHz tk _ 1M 27 pF | ; 68 220. 5.32 23% 2.09 MHz tk 1M S6pF ft. 82 300 8 229% | | { 22 100 8.6 + 16% i Figure 2.5 COP420/COP421 Oscillator ConfigurationsCOPS Family Users Guide MICROBUS Option The COP420 has an option which aliows it to be used as a peripheral microprocessor device, inputting and outputting data from and to a host microprocessor (uP). IN,, IN, and IN3 general Purpose inputs become MICROBUS compatible read-strobe, chip-select, and write-strobe lines, respectively. IN; becomes RD a logic 0" on this input will cause Q latch data to be enabled to the L ports for input to the uP. INj becomes CS a logic 0 on this line selects the COP420 as the uP peripheral device by enabling the operation of the RD and WR lines and allows for the selection of one of several peripheral components. IN3 becomes WR a logic 0 on this line will write bus data from the L ports to the Q latches for input to the COP420. Gp becomes a ready output, reset by a write pulse from the uP on the WR line, providing the handshaking capability necessary for asynchronous data transfer between the host CPU and the COP420. This option has been designed for compatibility with Nationals MICROBUS a standard interconnect system for 8-bit parallel data transfer between MOS/LS! CPUs and interfacing devices. (See MICROBUS, National Publication.) The functioning and timing relationships between the COP420 signal lines affected by this option are as specified for the MICROBUS intertace. Connection of the COP420 to the MICROBUS is shown in Figure 5.13. a. Standard Output DISABLE . DIBABLE Loy d. Standard L Output DISABLE Meg. g. TRISTATE Push-Pull (L Output} Figure 2.6 Input/Output Configurations ee 6, Open-Drain Output : i - h.input with Load 1/0 Options COP420/421 outputs have the following optional configurations, illustrated in Figure 2.6: a. Standard ~- an enhancement mode device to ground in conjunction with a depletion-mode device to Voc, compatible with TTL and CMOS input requirements. Available on SO, SK, and all D and G outputs. b. Open-Drain ~ an enhancement-mode device to ground only, allowing external pull-up as required by the users application. Available on SO, SK, and all DandG outputs. c. Push-Pull An enhancement-mode device to ground in conjunction with a depletion-mode device paralleled by an enhancement-mode device to Vcc. This configuration has been provided to allow for fast rise and fall times when driving capacitive loads. Available on SO and SK outputs only. d. Standard L ~ same as a., but may be disabled. Available on L outputs only. e. Open Drain L same as b., but may be disabled. Availabie on L outputs only. f. LED Direct Drive an enhancement-mode device to ground and to Vcc, meeting the typical current sourcing requirements of the segments of an LED display. the sourcing device is clamped to limit current flow. These devices may be turned off under program control (See Functional Description, EN Register), placing the outputs in a high-impedance state to provide required LED segment blanking for a multiplexed display. #t = os . oe pag a - ce oe Bods Somes tals oercetion oevice ee a LED (L Output) - Eee See 7_ TRISTATE Push-Pull an enhancement-mode device to ground and Vcc. These outputs are TRI-STATE outputs, allowing for connection of these outputs fo a data bus shared by other bus drivers. COP420/COP421 inputs have the following optional configurations: h. An on-chip depletion load device to Vcc: i. A Hi-Z input which must be driven to a "1" or QO by external components. The above input and output configurations share common enhancement-mode and depletion-mode devices. Specificaily, all configurations use one oF more of six devices (numbered 1-6, respectively). The SO, SK outputs can be configured as shown in a., b., orc. The D and G outputs can be configured as shown in a. or b. Note that when inputting data to the G ports, the G outputs should be set to 't. -The L outputs can be configured as in d., @., f. or g- An important point to remember if using configura- tion d. or f. with the L drivers is that even when the L drivers are disabled, the depletion load device will source a small amount of current; however, when the L lines are used as inputs, the disabled depletion device can not be relied on to source sufficient current to pull an input to logic onan Ail of the L driver options are TRI-STATE -able. Therefore, the L drivers have TRI-STATE-abie Standard and Open-Drain output options as well as the TRI-STATE LED Direct Drive and Push-Pull output options. Since the device to Vcc in the Standard output configuration is a depletion-mode device, it will source up to 0.125mA when this output is turned off in the TRI-STATE mode. This is not a worst case input for a logic 4" level on these inputs and will not be sufficient for an input level without previously enabling Q to L with {Q) = FF 16. Bonding Option The COP421 is a bonding option of the COP420: if the COP420 is bonded as a 24-pin device (without the 4 1N inputs), it becomes the COP421. Note that since it lacks the IN inputs, use of the COP421 bonding option precludes use of the IN input options; the MICROBUS option which would otherwise affect INg-IN1 and Go: use of the IN, hardware interrupt pin and the use of the IL3 and ILp latches associated with the IN3 and INo pins. All other options are available. The COP421 is pin- compatible with the COP410L. 25 COP420LICOP421L Description The COP420L/COP421L are low power versions of the COP420/COP421 containing the same internal logic elements and instruction set as the COP420/COP421, with electrical characteristics which are similar to the COP410L. The major differences between the COP420L/COP421L and COP420/COP421 are the following: Wider operating voltage range of 4.5 to 9.5V optionally available. Operating supply current less than BMA @ Voc = SV. apiny sJesn Aywed SdOd Minimum instruction cycle time of 15ys. Divide-by-32 crystal clock option (2MHz XTAL divided by 32 = 15s instruction cycle time). D and G outputs have direct LED digit drive option (sink 30mA). Other outputs will drive 1 LSTTL or 2 LPTTL loads (Io = 360 yA at 0.4V: lon =40zuA at 2.4V). No MIGROBUS option available. The COP421L is simply a COP420L packaged ina 24-pin dual-in-line package. As a result, the IN inputs are not available on the COP421L, so that the COP421L is pin-compatibie with the COP410L. For further information, see the COP420L/COP421L data sheet. 2.6 COP420L/COP421L Mask Programmable Options Since the COP420L/COP421L are frequently used in battery-operated and/or hand-held consumer-type products, an even greater array of system-cost- reducing options is available. The following text summarizes these options. Clock Oscillator Options There are four basic COP420L/COP421L clock oscillator configurations available as shown in Figure 2.8 (a-d): Crystal/Resonator Controlled Oscillator. CKI and CKO are connected to an external crystal or ceramic resonator. The instruction cycle time equals the crystal/resonator frequency (2.097 MHz maximum) divided by 32 (optional by 16 or 8). _ External Oscillator. CK! is configured as a CMOS compatible input accepting an external clock signal. The external frequency (2 MHz maximum) is divided by 32 (optional by 16, 8 or 4) to derive the instruction cycle time. CKO is now available to be used as the RAM power supply (Va) pin, as a COP420L general purpose input, or as a synchronizing input. a.COPS Family Users Guide COPAZ0L/424L COP420L/421L (Vp OR GENERAL +o pinpose input ee ontrolled Oscillatorc. RC Controlled Oscillator. CK is configured as a single-pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4. CKO is available for non-timing functions as in b above. d. Externally Synchronized Oscillator. Intended for use in multi-COP systems, CKO is programmed to function as an input connected to the SK output of another COP420L/COP421L with CKI connected as shown. In this configuration, the SK output connected to CKO must provide a SYNC (instruction cycle) signal to CKO, thereby allowing synchronous data transfer between the COPs using only the SI and SO serial VO pins in conjunction with the XAS instruction. Note that on power-up SK is automatically enabied as a SYNC output. The lower portion of Figure 2.7 provides component values for several instruction cycle times and crystal values associated with the RC controlled and crystal controlled oscillator options, respectively. CKO Non-Timing Options In a crystal controtled or multi-COP oscillator system, CKO is used as an output to the crystal network. In the other two configurations (external clock or RC controlled oscillator), CKO may be mask-programmed to perform one of two available options. Specifically, CKO may be mask- programmed as a general purpose COP420L input, read into bit 1 of the accumulator (As) upon the execution of an INIL instruction. As another option (for both the COP420L and COP421L}, CKO can be a RAM power supply pin (Vp). allowing its connection to a standby/backup power supply to maintain the integrity of RAM data with minimum power drain when the main supply is inoperative or shut down to conserve power. VO Options While the COP420L/COP421L has capabilities to directly drive LED displays through increased voltage and current specs, the circuit configurations are identical to those of the COP420 in Figure 2.6. Increased current sink and source values are a result of changing device sizes (within the bounds of the same circuit configuration). When emulating the COP420L with the COP402, one might use the typical values of the 402 as worst case COP420L drive parameters. An alternative is the use of the COP404L to emulate the drive of the COP420L. For detailed electrical characteristics, refer to the COP420L/COP421L data sheet. The SO and SK outputs can be configured as shown in Figure 2.6, a, b, or c. The D and G outputs can be configured as shown in a or b. Note that when inputting data to the G ports, the G outputs should be set to 1. The L outputs can be configured as shown ind, e, f, or g- An important point to remember is that aliof the L driver options are TRI-STATE -able. Therefore, the L drivers have TRI-STATE-able Standard and Open- Drain output options as well as the TRISTATE LED Direct Drive and Push-Puil output options. Since the device to Vcc in the Standard output configuration is a depletion-mode device, it will source up to 0.125mA when this output is turned off in the TRISTATE mode,which is insufficient to guarantee a logic 1" input level. Bonding Option The COP421L is a bonding option of the COP420L: if the COP420L is bonded as a 24-pin device (without the 4 1N inputs), it becomes the COP421L. The COP421L is pin-compatible with the COP410L. 2.7 COP420C Description The COP420C is a CMOS version of the COP420. It differs from the COP420 primarily in electrical specifications; however, it also features a dual clock mode option for operation at low speed (typically 244us instruction cycle time) with low power consumption (25yA with Vcc = 2.4V) or high speed (15us instruction cycle time) when necessary to perform internal data computations at a faster rate. The COP420C has the same output drive characteristics as the COP420 (TTLICMOS compatible) and retains the MICROBUS option. The following are the major differences between the COP420C and the COP420.: * Operating voltage of 2.4V to 6.0V. * Low power consumption at 244ys instruction cycle time (inexpensive 32kHz XTAL = 8) = 25pA at Vec =2.4. * Dual clock mode option allowing operation at 16s instruction cycle time (using external RC network) for internal data computation operations. Fast clock mode entered under program control. For further information, see the COP420C data sheet. epiny sesf Ajjwe4 SdOOCOPS Family Users Guide 2.8 COP444L/COP445L Description The COP444L/COP445L are expanded-memory versions of the COP420L containing the same internal logic elements and instruction set as the COP420 and COP420L, but with twice the amounts of ROM and RAM. The major differences between the COP444L/COP445Land the COP420L/COP421L are the following: * Operating supply current less than 11mA at Voc =5V. * 2048 x 8 ROM. 1284 RAM. The COP445L is simply a COP444L in a 24-pin dual- in-line package. As a result, the IN inputs are not available on the COP445L, so that the COP445L is pin-compatible with the GOP421L and COP410L. These devices are emulated using the COP404L. For further information, see the COP444L/445L and/or COP404L data sheets. 2.9 COP402 and COP402M ROM-Less Parts Description The COP402 and COP402M are ROM-less versions of the COP420. They are packaged in 40-pin packages and are available for prototyping a COP420 system using the COP400 Development System (PDS) or, in quantity, for small volume applications using external ROM. The COP402 has been mask programmed with options suitable for use as a general controlier. COP402 inputs have load devices to Veco, the various outputs have the fullest drive capability 9-18 associated with them (L outputs = LED direct drive; G and D outputs = standard: SO, SK outputs = push- pull). The COP402 has been programmed for use with an external crystal network, using CKI and CKO, with an instruction cycle time equal to the crystal frequency divided by 16. The COP402M is the MICROBUS compatible version of the COP402. It features the same options as the COP402 with the single exception that the MICROBUS option has been selected. It is, of course, intended for use in prototyping systems or small volume applications which use the microcontroller as a CPU peripheral component, with communication over Nationals MICROBUS. 2.10 COP404L ROM-Less Part Description The COP404L is a ROM-less version of the COP444L. It is packaged in a 40-pin package and may be used to prototype all low-power COP400 devices (COP411L, COP410L, COP420L, COP421L, COP444L). 2.11 COP410L/COP411L Architecture Figure 2.9 provides a block diagram of the COP410L/COP411L. As with the COP420/COP421 block diagram, it depicts the internal logic and interconnects of the device in simplified form. Note that the COP410L is functionally a subset of the 24-pin COP421L. As with the COP421L, it lacks the COP420L IN inputs and the internal IL latches associated with two of these deleted input pins. These and other architectural differences are discussed in the Functional Description, below. Figure 2.10 shows the Connection Diagrams for the 24-pin COP410L and the 20-pin COP411L. Figure 2.11 provides a pin description for the COP410L/COP411L devices. See data sheet for the electrical specifications of the COP410L/COP411L, showing maximum ratings pius DC and AC characteristics for these devices. The COP401L is available for final program verification for a COP410L/COP411L application.PROGRAM MEMORY 512k x 8 AON ADDRESS INSTRUCTION DECODE/CONTROL SKIP LOGIC DIVIDER DATA MEMORY REG 32% 4 AAM ADDR ACCUMULATOR A Qa REGISTER L ORIVERS CLOEK GENERATOR a REGISTER & BUFFER ee & REGISTER & BUFFER SERIAL WO REGISTER sing $10, $100 apiny sesp Ajwe4 SdOOCOPS Family Users Guide COP410L wen Ao hw 2.12 COP410L/COP411L Functional Description The following text provides a functional description of the differences which exist between the internal architecture of the COP420, covered in detail in Section 2.2, and that of the COP410L and COP411L. Consequently, for information on logic elements not discussed below which appear in Figure 2.9, COP410L/COP411L Block Diagram, refer to Section 2.2. Where appropriate, differences between the COP410L and its smaller version, the COP411L, are noted in the following text. Program Memory Program memory consists of a 12-byte ROM. The same paging characteristics apply to the COP410L/COP411L when allocating program memory instruction code as those which apply to the COP420 (see Section 4.1) except that ROM consists of 8 (0-7) pages of 64 (G-63) words each. ROM addressing is accomplished by a 9-bit P register. The auto increment-before-execution and page-rollover features of the COP420 apply to the COP410L/COP411L. Since the COP410L/COP411L have 2 9-bit subroutine-save registers, SA and SB, subroutine nesting is allowable to two levels (only one level when executing a LQID instruction since this instruction pushes the stack). COPaIIL Data Memory Data memory consists of a 128-bit RAM organized as 4 (0-3) data registers of 8 4-bit digits. Digit addressing is valid only for digits 0, 9-15ina particular register. (The COP4410L/COP411L will, however, treat digit addresses of 1-7 as valid digit values of 9-15, respectively.) As with the COP420, RAM addressing is accomplished by a 6-bit B register whose upper 2 bits (Br) select 1 of 4 data registers and lower 3 bits (Bd) select 1 of 8 4-bit digits. A direct access to data memory, without using the B register, is only permissible with respect to M(3, 15) by using an XAD 3, 15 instruction. All other XAD and all LDD instructions have been deleted from the COP410L/COP411L instruction set. Consequently, ali other RAM locations must be accessed by loading the B register with the address of data memory to be accessed. As with the COP420, Bd also may be used as a Source register to output its 4-bit contents directly to the D outputs via an OBD instruction. 9-20The Q register functions in a similar manner as the COP420 Q register with the following exceptions: 1. Its contents must be read with the INL instruction, since the CQMA instruction has been deleted. . It cannot be loaded with the contents of the L 0 ports since this function is associated with, the deleted MICROBUS option. The COP410L/COP411L does not contain the COP420 internal divide-by-1024 time-base counter, hence, the SKT instruction has been deleted. Real- time program counters must, therefore, rely on an external time-base input (e.g., 50/60 Hz square wave} to derive a program clock for such applications, rather than on the COP410L/COP411L instruction cycle clock itself. Bit 1 of the EN register (EN,) is a dont care bit, as explained above, due to the lack of a COP410L/COP411L IN, input. (The COP420 uses the EN, bit to enable IN, as an interrupt signal.) The CASC, ADT and OGi instructions have been deleted. See Section 3.4 for hints on performing these functions. 2.13 COP410L/COP411L Mask Programmable Options The following text describes the differences which exist between the COP420L mask programmable options and those which are available for the COP410L and COP411L devices. Available clock oscillator configurations are as follows: a. Ceramic Resonator Controlled Oscillator. CHI and CKO are connected to an external ceramic resonator. The instruction cycle time equals the resonator frequency (500kHz maximum) divided by 8. This configuration and its associated options are not available on the 20-pin COP411L since it lacks the CKO pin. . External Oscillator. CK! is configured as a Schmitt trigger input (not TTL compatible), accepting an external clock signal. The external frequency (500kHz maximum) is divided by 8 to derive the instruction cycle time. This option applies to both the COP410L and the COP411L. For the COP416L, moreover, this configuration allows CKO to be used for a RAM power supply (Vp). . RC Controlled Oscillator. CKIl is configured as a single pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillator (RC time-constant) frequency divided by 4. . Externally Synchronized Oscillator. CKO is configured as a synchronizing input from the SK 9-21 output of another COP400 device. CK] is an external oscillator (divide by 8). The lower portion of Figure 2.11 provides component values associated with the RC controlied oscillator option. COP410L CKO Non-Timing Options In the COP410L resonator controlled configuration, CKO is used as an output to the resonator network. In the other two configurations (external clock and RC controlied), CKO may be mask-programmed as a RAM power supply pin (V_), allowing its connection to a standby battery. backup power supply to maintain the integrity of RAM data with minimum power drain when the main supply is inoperative or shut down to conserve power. apiny5 sjesp Ajlwe4s SdOO COP410L/COP411L VO Options COP410L/COP411L inputs and outputs have the same optional configurations as the COP420L/COP421L; see Section 2.7. The input and output configurations share common enhancement-mode and depietion-mode devices. For detailed electrical characteristics on these devices, refer to the COP410L and COP421L data sheets. The SO and SK outputs can be configured as shown in Figure 2.6, a, b, or c. The D and G outputs can be configured as shown in a or b. Note that when inputting data to the G ports, the G outputs should be set to 1. The L outputs can be configured as shown in d, e, f, or g. An important point to remember is that a// of the L driver options are TRI-STATE -able. Therefore, the L drivers have TRI-STATE-able Standard and Open- Drain output options as well as the TRI-STATE LED Direct Drive and Push-Pull output options. Since the device to Vcc in the Standard output configuration is a depletion-mode device, it will source up to 0.125mA when this output is turned off in the TRISTATE mode, which is insufficient to guarantee a logic 1 input level. Bonding Option The COP411L is a bonding option of the COP410L: if the COP410L is bonded as a 20-pin device (without CKO, Ds, D3, and G3), it becomes the COP411L. Use of output options associated with these deleted pins are, of course, preciuded. All other COP410L options are available.COPS Family User's Guide COPa10L 9-22 COPA10L (or COP420L/ 421L/444L/445L)COP400 Instruction Sets 4 This chapter provides information on the instruction sets of the COP400 microcontrollers. As with the architecture of the different devices in the COP400 family, the instruction sets of the various devices allow the user to choose among several devices to provide only as much software capability as is needed for a particular application. Specifically, the instruction sets of the various devices are, generally, subsets of the most inclusive instruction set of the COP440. This chapter will discuss the COP420-series (includes COP421, COP421L, COP421C), COP444L, COP410L, and COP411L, respectively. Users of the COP440 should refer to the COP440 data sheet (when the device becomes available) for information on the additional instructions associated with the COP440 instruction set. This chapter primarily provides information on the machine operations associated with the instruction set of COP400 devices. However, where _appropriate, short examples indicating typical usage of particular instructions are provided. For a detailed treatment on using COP400 instructions to write COP400 assembly janguage programs, see Chapter 4 of this manual. 9-23 3.1 COP420-Series/COP444L Instruction Set Table 3.1 provides the mnemonic, operand, machine code, data flow, skip conditions and description associated with each instruction in the COP420- series/COP444L instruction set. As indicated, an asterisk in the description column signifies a double-byte instruction. Also, notes are provided following this table which describe or refer to additional information relevant to particular instructions. As indicated by Note 3, the INI and INIL instructions are not included in the COP421 instruction set, due to its lack of IN inputs and the IL3 and ILg latches associated with two of the IN inputs (INg and INo, respectively). Note that the COP420-series/COP444L set, as with all COP400 instruction sets, is divided into the following categories: Arithmetic Operations, Input/Output Instructions, Transfer of Control Instructions, Memory Reference Instructions, Register Reference Instructions, and Test Instructions. apiny ses Aywe4y SdOOARITHMETIC INSTRUCTIO ase ADD ADT COPS Family Users Guide CAC CURA comp. XOR TRANSFER OF CON MP PRETSK 9-24_ Table 61 COP420 SeriesiCOPA44L instr ction Set (continued) = _Skip Conditions - escription | Bere = Bd-decrements past 0 - apy ARAM toQ * Copy Q to RAM, A. Load RAM into A, : -Exclusive-OR Br with res oe Load A with. RAM pointed wee to directly bys nd : oe Load a Indirect Wote 9 : . diahin de a Set RAM Bit "Stara Memory. immediate oe and | Increment Bd a Exchange RAM with A, ses Exclusive: OR Br with: t Exchange A with RAM = pointed to directly by: rd : Exchange | RAM with A. : and: Decrement Bad; : ' Exclusive-OR Br with re "Bd increments past 15 Exchange RAM with A - and increment Bd, Exelusive-OR Brwith 7 aping saesn Awe4 SdOd __ REGISTER REFERENCE INSTRUCTIONS oe OF: a . Bd ~ 78 ies 6 Ey a mosteet a | Ee es Be OTTO yp ABR oo : Os: 1000 110010) | | a- ee 33 ae 1o01 4 | ys EN A Br OO AgAg) None None Skip until nota BE che eee td (Note 6) None None , Copy A to 8d Copy Bd to A : Load: a invnediate with: eo Load EN immediate : {Note 7y Exchange A with Br 9-251 ee L Instruction Set (continued) =: Machine | guage. code JOR) Data Flow Skip Conditions === (eseription INSTRUCTIONS | os EES Ge tp Skip if C is True ee, i 's RAM) eho Skip if A Equals RAM Ag Sao = cogs: oie s . Skip if Gis Zero. : : fall 4 bits) " Skip if @ Bltis Zero. COPS eae ee oe feooooory | oo woot ou d000001 yy (Ooo oooy fo ooojoorty | (000110014) o oe EO BeQ ges RAMIBjg = 0 Skip if RAM Bit is Zero RMB) = 0 RAMB)g = 0 _ Atime-base counter ~ S Skip on Timer ~earry has occurred | ns Note a _ Since: fast test. : "+ Input G Ports to A a a nul iL Latehes 1 ce (Note a. re Input L Port to RAMA. Outplit te to G Ports lmmeelate Note t: All su gy symbols indicate bit numbers unless crip pita! C plicitly defined fe.g. Brand Bd ara axplicl iN where U signifies @ least significant (low-order, Hone Tost bith For ample, Aq in deti ned). Bits are numbered les thes f post Significant Getl-most) be oF the Abit HEHE: e two: page baandary f pages 2 or 3 The J ve may. not pie the: fast word of a page, : : Note. EA JSAP transfers | program JSAP May. not jump o the fast word | in page 2 _ Note & LBL is a singi-byte Instruction if'd : aT _ Minus 1, 6.9., to load the tower four bits of 8 wi en she LBL instruction shoule equa By : Note 7 Machine. code for operand fieid: y fo i instruction should equal the binary: abel te be latched into EN, wehete: a 40 ort oi ip each bit o : sponds with the selection ar deselction. of a Particular function: associated with each bit. (See Functional, Description, EN: Register. be : 510 guals the binary. velde of the: its of the: a instructio eee eu wea To oad 0, the lower 9-26table 3.2 provides a list of internal architecture, struction operand and operational symbols used in the COP420-series/COP444L Instruction Set Table. Table 3.5 shows an alphabetical mnemonic index of COP420-series/COP444L instructions, indicating the hexadecimal opcode and description associated with each instruction. Table 3.6 is a list of COP420-series/COP444L instructions arranged in order of their hexadecimal opcodes. The following text gives a description of each COP420-series/COP444L instruction, explaining the machine operations performed by each instruction and, where appropriate, providing short examples iNustrating typical usage of particular instructions. a ee 32 copazo- Series/COP444L- a _ Instruction Set Table Symbols : : Symbol & - Definition: 4 INTERNAL ARCH TECTURE svM BOLS - abit Accumulator Hee: : - BDIDRAM Address Register oe - Upper 2 bits of & (register address) Lower 4bits of B (digit address) 4 Carry Register 9 22 4-bit Data: Output Port pone: t Enable Register 0 : anit: Register to jateh data for G 10 Port Two Toit. Latches associated with. the INg or No ee +0i RC ROM Address s Register program: counter) Spi Register tolateh data for & HO Port AO-bit Subroutine Gave Ragisier A: : = 10-bit Subroutine Save Register B- a Obit Subroutine Save Aagister c a UC AbbiE Shit leg! ster-and Counter a Logie Conirolied Clock Rupe : : : etinition - oo INS RUCTION OPERAND SYMBOLS - : ; a > ABIL Operand Field, 0-45 binary (RAM Digit Sel ect): -. 2bit Operand: Field, o- a binany (RAM Register : Select) - o 40-bit Operand: Field; O- 1023. bay {ROM Aaavess): ye bil Operand Field, 0-16-binary (immediate Data): ; RAMEE Contents of RAM location addressed bys: a mere : _, Contents FROM location addressed by { oo OPERATIONAL 5 SYMBOLS, ee ee oe Minus = : Replaces. . 4s exchanged: Wits cg equal to: | oS Fvecanes: complement of AL ~ Exchisive-OR! Range-of values Sem p 9-27 3.2 COP420-Series/COP444L Instruction Set Description Arithmetic Instructions ASC (Add with carry, Skip on Carry) performs a binary addition of A, C (Carry bit), and M, placing the result in A and C. If a carry occurs, the next program instruction is skipped. ADD (ADD) performs binary addition. The 4-bit addends are A and M. The 4-bit sum is placed in A. ADD does not affect the carry or skip. ADT (ADd Ten to A) adds ten (1010,) to A and, ike ADD, does not affect the carry or skip. It is intended to facilitate Binary Coded Decimal (BCD) arithmetic. For example, the following sequence of instructions will perform a single-digit BCD add of the contents of A and M [the carry is assumed set when entering this routine if addition of the previous least significant digits produced an overflow (A > 9)]: AISC 6 ASC ADT The AISC 6 instruction adds a BCD correction factor (i.e., 6) to the digit in the accumulator. (See AISC instruction.} Since the accumulator contains a BCD digit (< 9) no carry will occur and the next instruction, ASC, will always be executed. The ASC instruction adds the carry and memory digit to A, as explained above. If the result does not produce a carry, signifying that the previous AISC 6 (correction factor) instruction was unnecessary, the ADT instruction is executed, readjusting the accumulator to the proper BCD result. (Remember: ADT neither affects the carry nor skips.) If the ASC result does produce a carry, C is set for propagation to the addition of the next most significant digits and, since no readjustment of the result is necessary, the ADT instruction is skipped. AISC (Add Immediate, Skip on Carry) adds the instruction operand constant y (1-15) to A, skipping the next instruction if a carry out occurs (C is not changed). This instruction finds frequent use in BCD add and subtract routines (see ADT and CASC descriptions) as well as in testing the value of A. (If A is greater than 12, for instance, an AISC 5 will skip the next instruction.) CASC (Complement and Add, Skip on Carry) performs a binary subtraction of A from M by summing the complement of A {A) with C and M, placing the result in A and C. If no carry out occurs, indicating a borrow, C is reset and the next instruction is executed. If a carry occurs, indicating no borrow, C is set and the next instruction is skipped. aping stesp Ajwey SdOOdCOPS Family Users Guide A single BCD digit binary subtraction of A from M may be performed as follows. (The carry bit is assumed set upon initial entry to the routine.) CASG ADT The CASC instruction will set C and skip the ADT instruction if the subtraction does not result ina borrow (A > M). If a borrow occurs, the ADT instruction is executed, readjusting the result to the proper BCD vatiue, leaving C reset for propagation of the borrow in the subtraction of the next most significant BCD digits. CASC is functionally equivalent to a COMP instruction followed by an ASC. CLRA (CLeaR A) clears the accumulator by placing zeros in each of the 4 bits of A. This instruction is often required prior to loading A equal to a desired value with an AISC instruction if the previous contents of A are unknown. For instance, to load A= 11, the following sequence may be used: CLRA AISC 11 The skip features associated with AISC need not be considered in this example. (A carry will never . occur.) COMP (COMPlement A) changes the state of each of 4 bits of A with ones becoming zeros and zeros becoming ones. It has the effect of, and may be used to perform, a binary (ones comptement) subtraction of A from 15 (14112), e.g., complementing A = 6 (01109) will yield 9 (10013). NOP (No OPeration) does not perform any operation. It is useful, however, for simple single instruction time delays or to defeat the skip conditions associated with particular instructions. SC (Set Carry) and AC (Reset Carry) set C and reset C, respectively. SC and RC are most often employed to initialize C prior to entering arithmetic routines. They also allow C to be used as a general-purpose (testable) flag, as long as subsequent instructions do not inadvertently affect the C register. XOR (eXclusive-OR A with M) performs a logical EXCLUSIVE-OR operation of each bit of A with each corresponding bit of M, placing the result in A. This operation can be used to change the state of any bit in M, if the corresponding (equaliy weighted) bit of Ais set. This follows from the EXCLUSIVE-OR truth table where a X +1" =X, and a X+0" =X, assuming the X bits to be one of the 4 bits in M, and the '1 and 0 to be equally weighted bits in A. This instruction, therefore, allows the selective complementing or toggling of one or more bits of M. Example: to change the state of bit 2 of M, set A=0100, perform an XOR, then exchange A into M with an X instruction. Input/Output Instructions ING (INput G ports to A) transfers the 4-bit contents of the IN ports {IN3-!No) to A. INEN (iNput IN inputs to A) transfers the 4-bit contents of the IN ports (IN3-1No) to A. INIL (INput IL latches to A) is a speciai purpose instruction which inputs the two jatches IL3 and ILo (see Figure 3.1 below) and, if the appropriate option is selected, a general-purpose input, CKO, to the accumulator the unused bit/bits of A are reset. Specifically, INIL places IL3 > Ag, CKO > Ap, 0 = Ay, [Lg > Ap. ILg and ILp are the outputs of Jatches associated with the INs and INo inputs. {The general purpose inputs, IN3-INpo, are input to A upon the execution of an ININ instruction. (See ININ Instruction.) The IL3 and IL, latches are set If a jow-going pulse {1 to 0} has occurred on the IN3 and INg inputs, respectively, since the last INIL instruction, provided the input pulse stays low for at least two instruction times. Execution of an INIL inputs IL3 and ILg into A; and Ag respectively, and resets these latches to allow them to respond to subsequent low-gcing pulses on the IN3 and INo lines. These latches are not cleared during a power on reset. If CKO is mask-programmed as a general-purpose input, an INIL will input the state of CKO into Ao. If CKO has not been so programmed, a 1 will be placed in A. A 0 is always piaced in A; upon the execution of an INIL. INIL is useful in recognizing and capturing pulses of short duration or which can't be read conveniently by an ININ instruction. INL (INput L ports to M, A) transfers the 8-bit contents of the bidirectional TRI-STATE 1/O ports to M, A. L7-L4 are placed in M3- Mg (the memory digit pointed to by the B register); L;-Lp are placed in Ag- Ao.OBD (Output Bd to D outputs) transfers the 4-bit contents of Bd (lower 4 bits of the B register) to the D output ports (D3-Dpo). Since, in many applications, the D outputs are connected to a digit decoder, the direct output of Bd allows for a standard interconnect to the binary inputs of the decoder/driver device. OGI (Output to G ports Immediate) transfers the four bits specified in the y operand field of this instruction (Q-15, binary) to G3- Go. OMG (Output M to G ports) transfers the 4-bit contents of M (M3-Mp) to G3- Go. XAS (eXchange A with SiO) exchanges the 4-bit contents of A (A3-Ap) with the 4-bit contents of the SIO register (SIO3-SIOp). SIO will contain serial- inf/serial-out shift register or binary counter data, depending on the value of the EN register. An XAS instruction will also affect the SK output. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the clock. For further information on the EN register and its relationship to the XAS instruction, see LEI Instruction, below. If SIO is selected as a shift register, an XAS instruction must be performed once every 4 instruction cycle times to effect a continuous serial-in or serial-out data stream. Transfer of Control Instructions JID (Jump InDirect) is an indirect addressing instruction, transferring program control to a new ROM location addrssed by the contents of the ROM location pointed to by A and M. Specifically, it loads the lower 8 bits of the ROM address register P with the contents of ROM pointed to by the 10-bit word Pg Pg Ay A2 A, Ag M3 MoM, Mg. The contents of the selected ROM location (!7-I,) are, therefore, loaded into P7-Pg, changing the lower & bits of P to transfer program control to the new ROM location. Pg and Pg remain unchanged throughout the execution of the JID instruction. JID, therefore, may only jump to a ROM location within the current 4-page ROM block (pages 0-3, 4-7, 8-11 oF 12-15). For further information regarding the paging restrictions associated with the JID instruction, see Section 4.1. JiD can be useful in keyboard-decode routines when the values associated with the row and column of a particular key closure are placed in A and M for a jump indirect to the contents of ROM which point to the starting address of the appropriate routine associated with that particular key closure. For an example of use of the JID instruction to access a keyboard-decode ROM pointer table, see Display/Keyboard Program, Section 5.3, #16. 9-29 JMP (JUMP) transfers program control to any word in the ROM as specified by the a field of this instruction. The 10-bit a field is placed in Pg- Pp. JMP is used to transfer program control from one page to another page (if in page 2 or 3, the more efficient single-byte JP instruction may be used) or to transfer control to the /ast word of the current page an invalid transfer for the JP instruction. JP (Jump within Page) transfers program control to the ROM address specified in the operand field of this instruction. The machine code and operand fieid of this instruction have two formats. If program execution is currently within page 2 or 3 (subroutine pages) a 7-bit a field is specified, transferring program control to a word within either of the two subroutine pages. Otherwise, only a 6-bit a fleld is specified, transferring program control to a particular word within the current 64-word ROM page. Specifically, this instruction places ag-ag in Pg-Pp if the program is currently in subroutine page 2 or 3. If in any other page, it places as-ag in Ps- Pp. The restrictions associated with the JP instruction, therefore, are that a 7-bit a field may be used only when in pages 2 or 3. Otherwise, a JP may be used only to jump within the current page by specifying a 6-bit a field in the operand of this instruction. An additional restriction associated with the JP instruction, in either of the above two formats, is that a JP to the last word of any page is invalid, i.e., a may not equal all 1s. A transfer of program control to last word on a page may be effected by using a JMP instruction. (See IMP Instruction, above.) JSRP (Jump to SubRoutine Page} is used to transfer program control from a page other than 2 or 3 to a word within page 2. It accomplishes this by placing a 2 (00102) in Pg-Ps., and the word address specified in the 6-bit a field of the instruction into Ps-Pp. Designed to transfer control to subroutines, it pushes the stack to save the subroutine return address the address of the next program instruction is saved in SA and the other subroutine-save registers are likewise pushed (P+ 1- SA SB - SC). Any previous contents of SC are lost. since SC is the last of the three subroutine-save registers. Subroutine nesting. therefore, is permitted to three levels. SRP is used in conjunction with the RET or RETSK instructions which pop the stack at the end of subroutine to return program control to the main program. As with the JP instruction. JSRP may not transfer program control to the last word of page 2: a may not equal all 1s. A JSR may be used to jump to the last word of a subroutine beginning at the last word of page 2. (See JSR, beiow.) As mentioned above, a further restriction is that a SPINY sJjesp Apwe4y SqdodCOPS Family Users Guide JSRP may not be used when in subroutine pages 2 or 3. To transfer program control to a subroutine in page 2 when in pages 2 or 3, the double-byte JSR should be used, or, if it is not necessary to push the stack, a JP instruction may be used. JSR (Jump to SubRoutine) transfers program contro! to a subroutine located at a particular word address in any ROM page. It modifies the entire P register with the vaiue of the a operand of this instruction, as follows: ag-ag + Pg- Pa. As with the JSRP instruction, JSR pushes the stack (P+1> SA SB SC), saving the next program instruction for a return from the subroutine to the main program via a RET or RETSK instruction. JSR may be used to overcome the restrictions associated with the JSRP instruction: to jump toa subroutine and push the stack when in pages 2 or 3, or to jump to a subroutine located at the last word of page 2. RET (RETurn from subroutine) is used to return program control to the main program following a JSR or JSRP instruction. RET pops the stack (SC > SB > SA = P): the next main program instruction address (P + 1) saved in SA is loaded into P, the contents of SB are loaded into SA and the contents of SC are loaded into SB. (The contents of SC are also retained in SC.) Program control, therefore, is returned to the instruction immediately foilowing the previous subroutine call. RETSK (RETurn from subroutine then SKip), as with the RET instruction above, pops the stack (SC > SB > SA > P), restoring program control to the main program following a subroutine call. it, however, a/ways skips the first instruction encountered when it returns to the main program. This instruction, therefore, provides the programmer with an alternate return from subroutines, either via a RET or RETSK, based upon tests made within the subroutine itself. CAMQ (Copy A, M to Q) transfers the 8-bit contents of A and M to the Q latches. A3- Ao are output to Q7-Q4; M3-Mo are output to Q3- Qpy. Note that CAMGQ is the inverse of CQMA (see CQMA Instruction, below) with respect to the 4 bits of Q with which A and M communicate. Therefore, the input and processing of Q must often be followed by an X (Exchange M with A) instruction before final output to Q in order to maintain the proper bit- weights of the Q data. For example, the following instructions read Q to M, A, set Q, and perform the necessary exchange before execution of the CAMQ instruction: CQMA ,QTOM,A SMB 3 , SET Q; BIT LOCATED IN Mg x , EXCHANGE M WITH A CAMQ ;A,MTOQ 9-30 CQMA (Copy @ to M, A) transfers the 8-bit contents of the Q latches to M and A. Q7-Q, are placed in M3- Mp; Q3- Qo are placed in Ag- Ag. CQMA can be employed after an LQID (Load Q InDirect) instruction to input or alter the value of lookup data. CQMA is also an essential instruction when the COP420 is employed as a MICROBUS peripheral component. In such applications, INg is used by the control microprocessor to write bus data from the L ports to the Q latches. (See Section 2.4, MICROBUS option.) A CQMA will then input this data to M, A as explained above for processing by the COP420 program. Memory Reference Instructions LD (LoaD M into A) loads M (the 4-bit contents of RAM pointed to by the B register: M3- Mo) into Aa-Apo. After M is loaded into A, the 2-bit r operand fieid is EXCLUSIVE-ORed with the contents of Br (upper 2 bits of B RAM register select) to point to a new RAM register for successive memory reference operations. Since the properties of the EXCLUSIVE-OR logic operation are such that a 1 @ X equals the complement of X, use of the r field allows the programmer to switch between any one of the 4 RAM registers by complementing the appropriate bit/bits of the current contents of the Br register. Of course, if r =0, the contents of Br will remain unchanged after the execution of a LD instruction. For example, if the assembly ianguage instruction LD 3 (r =119) is executed with Br = 2 (105) and Bd = 12 (1100,), the contents of RAM register 2, digit 12 will be loaded to A and Br will be changed to (112 + 105 = 015), with B pointing to RAM register 1, digit 12. For assembly language programming use of an EXCLUSIVE-OR r operand field with memory reference instructions which use this field is optional if not specified, an '0 operand is assumed. For further information on allocating RAM map locations for optimum use of the EXCLUSIVE-OR feature associated with this and other memory reference instructions and for sample routines utilizing this feature, refer to Sections 4.2 and 4.4. SMB (Set Memory Bit) and RMB (Reset Memory Bit) set and reset, respectively, a bit in M as specified by the operand field of these instructions. (Remember: M is the 4-bit RAM digit pointed to by the B register.) The operand field is specified according to the bit number (0-3, left-most to right- most bit) of the particular bit to be set or reset, 2.9.,an SMB 3 would set the most significant bit of M. These instructions are useful in operating upon program status flags located in RAM. STII (Store Memory Immediate and Increment Bd) loads the 4-bit contents specified by the yOBD (Output 8d to D outputs) transfers the 4-bit contents of Bd {lower 4 bits of the B register) to the D output ports (D3- Dg). Since, in many applications, the D outputs are connected to a digit decoder, the direct output of Bd allows for a standard interconnect to the binary inputs of the decoder/driver device. OGI (Output to G ports immediate) transfers the four bits specified in the y operand field of this instruction (0-15, binary) to G3-Go. OMG (Output M to G ports) transfers the 4-bit contents of M (M3- Mg} to G3- Go. XAS (eXchange A with SIO) exchanges the 4-bit contents of A (A3- Ag) with the 4-bit contents of the SIO register (SIO4-SIO,). SIO will contain serial- in/serial-out shift register or binary counter data, depending on the value of the EN register. An XAS instruction will also affect the SK output. The XAS instruction copies C into the SKL latch. in the counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the clock. For further information on the EN register and its relationship to the XAS instruction, see LEI Instruction, below. If SIO is selected as a shift register, an XAS instruction must be performed once every 4 instruction cycle times to effect a continuous serial-in or serial-out data stream. Transter of Control Instructions JID (Jump InDirect) is an indirect addressing instruction, transferring program control to a new ROM location addrssed by the contents of the ROM location pointed to by A and M. Specifically, it loads the lower 8 bits of the ROM address register P with the contents of ROM pointed to by the 10-bit word Pg Pg A3 As A,AgMgMoM, Mo. The contents of the selected ROM location (l7-1I9) are, therefore, loaded into P7- Pp, changing the lower 8 bits of P to transfer program control to the new ROM location. Pg and Pg remain unchanged throughout the execution of the JID instruction. JID, therefore, may only jump to a ROM location within the current 4-page ROM block (pages 0-3, 4-7, 8-11 or 12-15). For further information regarding the paging restrictions associated with the JID instruction, see Section 4.1. JID can be useful in keyboard-decode routines when the values associated with the row and column of a particular key closure are placed in A and M for a jump indirect to the contents of ROM which point to the starting address of the appropriate routine associated with that particular key closure. For an example of use of the JID instruction to access a keyboard-decode ROM pointer table, see Display/Keyboard Program, Section 5.3, #16. 9-29 JMP (JUMP) transfers program control to any word in the ROM as specified by the a field of this instruction. The 10-bit a field is placed in Pg~ Pp. JMP is used to transfer program control from one page to another page (if in page 2 or 3, the more efficient single-byte JP instruction may be used) or to transfer control to the /ast word of the current page an invalid transfer for the JP instruction. JP (Jump within Page) transfers program control to the ROM address specified in the operand field of this instruction. The machine code and operand field of this instruction have two formats. |f program execution is currently within page 2 or 3 (subroutine pages) a 7-bit a field is specified, transferring program control to a word within either of the two subroutine pages. Otherwise, only a 6-bit a field is specified, transferring program control to a particular word within the current 64-word ROM page. Specifically, this instruction places ag-ap in Pg- Pp if the program is currently in subroutine page 2 or 3. If in any other page, it places as- ap in Ps5-Pp. The restrictions associated with the JP instruction, therefore, are that a 7-bit a field may be used only when in pages 2 or 3. Otherwise, a JP may be used only to jump within the current page by specifying a 6-bit a field in the operand of this instruction. An additional restriction associated with the JP instruction, in either of the above two formats, is that a JP to the last word of any page is invalid, i.e., a may not equal all ts. A transfer of program control to last word on a page may be effected by using a JMP instruction. (See JMP Instruction, above.) JSRP (Jump to SubRoutine Page) is used to transfer program control from a page other than 2 or 3 to a word within page 2. It accomplishes this by placing a 2 (00102) in Pg-P.s, and the word address specified in the 6-bit a field of the instruction into Ps5-Ppo. Designed to transfer control to subroutines, it pushes the stack to save the subroutine return address the address of the next program instruction is saved in SA and the other subroutine-save registers are likewise pushed (P+1-SA-- SB SC}. Any previous contents of SC are lost, since SC is the last of the three subroutine-save registers. Subroutine nesting. therefore. is permitted to three levels. JSRP is used in conjunction with the RET or RETSK instructions which pop the stack at the end of subroutine to return program control to the main program. As with the JP instruction, JSRP may not transfer program control to the last word of page 2: a may not equal all 1s. A JSR may be used to jump to the last word of a subroutine beginning at the jast word of page 2. (See JSR, below.) As mentioned above, a further restriction is that a apINH sissy Ajlme4y SdOdCOPS Family Users Guide JSRP may not be used when in subroutine pages 2 or 3. To transfer program control to a subroutine in page 2 when in pages 2 or 3, the double-byte JSR should be used, or, if it is not necessary to push the stack, a JP instruction may be used. JSR (Jump to SubRoutine) transfers program control to a subroutine located at a particular word address in any ROM page. It modifies the entire P register with the value of the a operand of this instruction, as follows: ag-ag > Pg- Po. As with the JSRP instruction, JSR pushes the stack (P+1- SA- SB SC), saving the next program instruction for a return from the subroutine to the main program via a RET or RETSK instruction. JSR may be used to overcome the restrictions associated with the JSRP instruction: to jump to a subroutine and push the stack when in pages 2 or 3, or to jump to a subroutine located at the last word of page 2. RET (RETurn from subroutine) is used to return program control to the main program following a JSR or JSRP instruction. RET pops the stack (SC > SB > SA > P): the next main program instruction address (P+ 1) saved in SA is loaded into P, the contents of SB are loaded into SA and the contents of SC are loaded into SB. (The contents of SC are also retained in SC.) Program control, therefore, is returned to the instruction immediately following the previous subroutine call. RETSK (RETurn from subroutine then SKip}, as with the RET instruction above, pops the stack (SC > SB > SA > P), restoring program control to the main program following a subroutine call. It, however, a/ways skips the first instruction encountered when it returns to the main program. This instruction, therefore, provides the programmer with an alternate return from subroutines, either via a RET or RETSK, based upon tests made within the subroutine itself. CAMQ (Copy A, M to Q) transfers the 8-bit contents of A and M to the Q latches. A3- Ag are output to Q7-Qy; M3-Mg are output to Q3-Q,. Note that CAMGQ is the inverse of CQMA (see CQMA Instruction, below) with respect to the 4 bits of Q with which A and M communicate. Therefore, the input and processing of Q must often be followed by an X (Exchange M with 4) instruction before final output to Q in order to maintain the proper bit- weights of the Q data. For example, the following instructions read Q to M, A, set Q, and perform the necessary exchange before execution of the CAMQ instruction: CQMA >QTOM,A SMB 3 , SET Q; BIT LOCATED IN My x , EXCHANGE M WITH A CAMQ ;A,MTOQ 9-30 CQMA (Copy Q to M, A) transfers the 8-bit contents of the Q latches to M and A. Q;-Q, are placed in M3- Mo; Q3- Qo are placed in A3-A 9. CQMA can be employed after an LQID (Load Q InDirect) instruction to input or alter the value of lookup data. COMA is also an essential instruction when the COP420 is employed as a MICROBUS peripheral component. In such applications, INg is used by the control microprocessor to write bus data from the L ports to the Q latches. (See Section 2.4, MICROBUS aption.) A CQMA will then input this data to M, A as explained above for processing by the COP420 program. Memory Reference Instructions LD (LoaD M into A) loads M (the 4-bit contents of RAM pointed to by the B register: M3- Mo) into A3-Ao. After Mis loaded into A, the 2-bit "r operand field is EXCLUSIVE-ORed with the contents of Br (upper 2 bits of B RAM register select) to point to a new RAM register for successive memory reference operations. Since the properties of the EXCLUSIVE-OR logic operation are such that a 1 X equals the complement of X, use of the r field ailows the programmer to switch between any one of the 4 RAM registers by complementing the appropriate bit/bits of the current contents of the Br register. Of course, if r? =Q, the contents of Br will remain unchanged after the execution of a LD instruction. For example, if the assembly language instruction LD 3 (r =115) is executed with Br = 2 (102) and Bd = 12 (11002), the contents of RAM register 2, digit 12 witl be loaded to A and Br will be changed to (115 + 105 = 019), with B pointing to RAM register 1, digit 12. For assembly language programming use of an EXCLUSIVE-OR r operand field with memory reference instructions which use this field is optional if not specified, an 0 operand is assumed. For further information on allocating RAM map locations for optimum use of the EXCLUSIVE-OR feature associated with this and other memory reference instructions and for sample routines utilizing this feature, refer to Sections 4.2 and 4.4. SMB (Set Memory Bit) and RMB (Reset Memory Bit) set and reset, respectively, a bit in M as specified by the operand field of these instructions. (Remember: M is the 4-bit RAM digit pointed to by the B register.) The operand field is specified according to the bit number (0-3, left-most to right- most bit) of the particular bit to be set or reset, e.g., an SMB 3 would set the most significant bit of M. These instructions are useful in operating upon program status flags located in RAM. STII (Store Memory Immediate and Increment Bd) loads the 4-bit contents specified by the yoperand field of the instruction into the RAM memory digit pointed to by the B register, M3- Mg. It is important to note that the value of Bd (RAM digit-select) is incremented (as with the XIS instruction) after the y data is stored in M. LDD (LoaD A with M Directly) loads the 4-bit contents of the RAM memory location pointed to directly by the 'r and d operand fields (register and digit select, respectively) of the instruction, M3-Mo, into Ag- Ag. Note that this instruction and the XAD instruction differ from other memory reference instructions in that the operand of the instruction, not the B register, is used to point to the appropriate RAM digit location to be accessed the B register is unaffected by these instructions. This instruction is useful in accessing RAM counters, status and flag digits, etc., within routines or loops without destroying the previous value of B, allowing the latter to be used for sequential memory access operations and for other reiterative purposes. LQID (Load Q InDirect) is, in effect, a ROM data lookup instruction. !t transfers the 8-bit contents of ROM, l7-l9, pointed to by the 10-bit word PgPgAM to Q7-Qp, respectively. It does this by pushing the stack (P+ 1 SA SB SC) and replacing the least significant 8 bits of P as follows: Ag- Ag > P7-P4; M3-My > P3- Po, leaving the two most significant bits of P unchanged. The ROM data pointed to by the new P address is fetched and loaded into the Q latches, Q7-Qp. Next, the stack is popped (SC ~ SB SA > P), restoring the previous pushed value of P (P+ 1) to continue sequential program execution. Since LQID pushes SB > SC, the previcus contents of SC are lost. Also, when LQID pops the stack, the previously pushed contents of SB are left in SC as well as loaded back into SB. The net result, therefore, of an LQID instruction upon the subroutine-save stack is that the contents of SB are placed in SC (SB > SC). Since it pushes the stack, a LQID should not be executed when three levels of subroutine nesting are currently in effect. (The last return address in SC will be lost.) Since, as with the JID instruction, LQID affects onty the lower 8 bits of P (Pg and Pg are unchanged}, it may only access ROM data located within the current 4-page ROM block (pages 0-3, 4-7, 8-11 or 12-15). For further information on the use of the LQID instruction, see Section 4.1. X (eXchange M with A) exchanges the 4-bit contents of RAM pointed to by the B register, M3-Mg, with Ag- Apo. The r operand field of the instruction is EXCLUSIVE-ORed with the contents of Br after the exchange to provide a new Br RAM register select value as explained in the LD instruction above. XAD (eXchange A with M Directly) exchanges the 4-bit contents of the RAM memory location pointed 9-31 to directly by the r and d operand fields of the instruction, M3- Mp5, with A3- Ag. It has the same characteristics and utility as the LDD instruction above, e.g., the B register is not affected. XDS (eXchange M with A, Decrement Bd and Skip on borrow) performs the same operation as the X instruction above, and also decrements the value of the Bd register (RAM digit-select) after the exchange. Use of an r operand field will, therefore, result in both an altered RAM digit-select value and a new RAM register select value in B. XDS skips the next program instruction when Bd is decremented past 0 (after the contents of RAM digit 0 have been exchanged with A and XDS decrements Bd to 15). Repeated XDSs will watk down through the digits of a RAM register before skipping. XDS together with X instructions can be used to operate upon the corresponding digits of different RAM registers in successive fashion. (See Section 4.2.) Spiny syesn Ajiwe4s SdOOD XIS (eXchange M with A, Increment Bd, and Skip on carry) performs the same operation as the XDS instruction except that it increments Bd after the exchange and skips the next program instruction after Bd increments past 15 (after the contents of RAM digit 15 have been exchanged with A and XIS increments Bd to 0). Consequently, successive X(Ss walk up through the digits of a RAM register before skipping. Register Reference Instructions CAB (Copy A to Bd) transfers the 4-bit contents of A, Ag- Ag, to Bd (the RAM digit-select register). This instruction allows the loading of a new RAM digit- select value via the accumulator, a useful operation in many memory-digit access loops. CBA (Copy Bd to A) transfers the 4-bit contents of Bd (RAM digit select) to A3- Ag. it is the functional corm.plement of the CAB instruction and finds similar use in memory-digit access loops. LBI (Load B immediate) loads the 8 register with the 6-bit value specified by the 'r (2-bit) and d (4-bit) fields of the instruction. lts purpose is to directly load a new RAM register and digit select value into B and, unlike CAB, CBA or XABR, does not require use of the accumulator. A further distinction with respect to CAB and CBA is its ability to alter the Br register (RAM register-select). The LBI instruction is coded or assembled into machine language as e/ther a single- or a double- byte instruction, depending on the value of the d field. If the d field value equals 0 or 9 through 15, the instruction is coded as a single-byte instruction with the lower 6 bits equal to the value of d minus 1. lf the d fleld equals 1 through 8 (1-8), the instruction is coded as a double-byte instruction, with the lower 6 bits of the second byte equal to the value of d. (See LBI Instruction, Table 3.1, and Note 6 of Table 3.1.) ECOPS Family Users Guide To take advantage of the more efficient single-byte LBI format, frequently used program data (counters, flags, etc.) should be placed within RAM digit locations accessible by the LB! single-byte d field (d =0, 9- 15}. (See Section 4.2 for further information.) An important characteristic of the LBI instruction is that it will skip all subsequent LBI instructions until it encounters an instruction which is not an LBI. This feature accommodates it for use in multiple-entry subroutines. (For example, see Adjacent Memory Move Routine, Section 4.4.) LEI (Load EN immediate) loads the enable register with the value contained in the y operand field of this instruction (0-15, binary). Its function is to select or deselect a particular software selectable feature associated with each of the four bits of the enable register (EN3- ENo). These features and the corresponding bit-weights and values associated with each feature are as follows: 1. The least significant bit of the enable register, ENg, selects the SIO register as either a 4-bit shift register or a 4-bit binary counter. With ENg set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going pulse ('1" to O"') occurring on the Sl input. Each pulse must remain at each iogic jevel at least two instruction cycles. SK outputs the value of the C upon the execution of an XAS and remains latched until the execution of another XAS instruction. The SO output is equal to the value of EN3. With ENg reset, SIO is a serial shift register, shifting continuously left each instruction cycle time. The data present at SI goes into the least significant bit of SIO; SO can be enabled to output the most significant bit of SIO each cycle time. SK output becomes a logic-controlled clock, providing a SYNC signal each instruction time. It will start outputting a SYNC pulse upon the execution of an XAS instruction with C = 1, stopping upon the execution of a subsequent XAS with C ="'0. lf ENg is changed from 1" to 0 (0" to 1, the SK output will change from 1 to SYNC (SYNC to 1") without the execution of an XAS instruction. 2. With EN, set, the IN; input is enabied as an interrupt input. Upon the occurrence of a negative pulse on IN,, program control is transferred to the iast word of page 3 (address OF F46). Immediately following an interrupt, EN, is reset to disable further interrupts until later set by an LE} instruction (usually at the end of the interrupt service routine or later within the main program). 9-32 The following features are associated with the IN, interrupt procedure and protocol and must be considered by the programmer when utilizing this software-selectable feature of the COP420- series. (Interrupt is unavailable on the COP421- series since it does not have the IN3-INo inputs.) a. The interrupt, once acknowiedged as explained below, pushes the next sequential program counter address (P+ 1) onto the stack, pushing in turn the contents of the other subroutine-save registers to the next lower level (P+ 1- SA > SB SC). Any previous contents of SC are lost. The program counter is set to address OFF 4, (the last word of page 3) and EN, is reset. . An interrupt will be acknowledged only after the following conditions are met: 1) EN, has been set; 2) A low-going pulse (1 to 0) at least two instruction cycles in width has occurred on the IN, input; 3) A currently executing instruction has been completed; 4) All successive transfer of control instructions and successive LBls have been completed (e.g., if the main program is executing a JP instruction which transfers program contro! to another JP instruction, the interrupt will not be acknowledged until the second JP instruction has been executed). c. Upon acknowledgement of an interrupt, the skip logic status is saved and implemented upon the execution of a subsequent RET instruction. For example, if an interrupt occurs during the execution of ASC (Add with carry, Skip on Carry) instruction which results in a carry, the next instruction (which would normally be skipped) is not skipped; instead, its address is pushed onto the stack, the skip logic status is saved and program control is transferred to the interrupt servicing routine at location OFF 4g. At the end of the interrupt routine, a RET instruction is executed to pop the stack and return program control to the instruction following the original ACS. At this time, the skip logic is enabled and skips this instruction because of the previous ASC carry. Since, as explained above, it is the RET instruction which enables the previously saved status of the skip logic, subroutines should not be nested within the interrupt service routine since their RET instruction wiil enable any previously saved main program skips, interfering with the orderly execution of the interrupt routine. d. The first instruction of the interrupt routine at address OFF,, must be NOP.3. With EN, set, the L drivers are enabled, loading data previously latched into Q to the L I/O ports. Resetting EN, disables the L drivers, placing the L /O ports in a high-impedance state. When the L I/O ports are used as segment drivers to an LED display, the setting and resetting of EN results in the outputting and blanking, respectively, of segment data to the display. When using the MICROBUS option EN does not affect the L drivers. 4, EN, in conjunction with ENo, affects the SO output. With ENo set (binary counter option selected) SO will output the value loaded into EN3. With ENg reset (serial shift register feature selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data (the most significant bit of SIO) each instruction time as explained above. Resetting EN with the serial shift register feature selected disables SO as the shift register output: data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains reset to 0. Figure 3.2 below provides a summary of the features associated with EN3 and EN. Sh [80 [Skater xas. Fp Pst et Shit | inputto, |g | SK= SYNC _ | Register) Shift Register | | if SkL=0, pep ae | SKbS Shit | input lo. seriaroutl | Register| Shift Register. boo eek eae pee |b Negative edge f | SKLE TL ogy | Bina ge egative Edge | Sg SK St OAT Counter | Sensitive Inputto | Op eet 2 Pee Le Binary Coumter |! cee lf SKE =O, : eB ED Ss ores SK=0 =o wSkcei op. Negative Edge. | 2 Ska | Sensitive input tof Poe sKL aa | Lo Binary Counter: cof BK Qn Figure 3.2 Enable Register Features Bits ENs and ENo XABR (eXchange A with Br) exchanges Br (upper 2 bits of B: RAM register-select) with A. Since Br contains only 2 bits, only the lower two bits of A, A,-Apo, are placed in Br. Similarly, the 2 bits of Br are placed in A,-Ag with Os being loaded into the upper 2 bits of A, Ag- A>. XABR is an efficient means of loading the Br register via the accumulator a direct load of the Br register must otherwise be accomplished by an LB! instruction which also affects the Bd portion of the B register. Test Instructions SKC (SKip on Carry) skips the next program instruction if the carry bit is equal to 1. When used in conjunction with the RG and SG , instructions, it allows C to be used as a 1-bit testable flag. SKE (SKip if A Equals M) compares all 4 bits of A with M, skipping the next instruction if the value of Ais equal to the value of M. SKE can be used to compare A with a status or counter digit in M, skipping to an instruction which transfers program control to another routine if equality exists. SKGBZ (Skip if G Bit is Zero) is a double-byte instruction. It tests the state of one of the four G lines (G3- Go) as specified by the n operand of the instruction, skipping the next program instruction if the specified G line is equal to 0. SKGZ (SKip if G is Zero) is a double-byte instruction. It tests the state of all four of the G lines, skipping the next program instruction if G3- Gg are all equal to 0. SKMBZ (SKip on Memory Bit Zero) skips the next program instruction if the RAM memory bit specified by the n field of the instruction (0-3, right-most to left-most M bit) is equal to 0. This instruction, together with the SMB and RMB instructions, allow for the testing and manipulation of single-bit flags contained within RAM digit locations. SKT (SKip on Timer) instruction tests the state of an internal 10-bit time-base counter. This counter divides the instruction cycle clock frequency by 1024 and provides a latched indication of counter overflow. The SKT instruction tests this latch, executing the next program instruction if the latch is not set. If the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associated with this instruction, therefore, allow the controller to generate its own time-base for real-time processing rather than relying on an external input signal. For exampie, using a 2.097 MHz crystal as the time- base to the clock generator, the instruction cycle clock frequency will be 131 KHz (crystal frequency ~ 16) and the binary counter output pulse frequency will be 128Hz. For time-of-day or similar real-time processing, the SKT instruction can call a routine which increments a seconds counter every 128 ticks. 8PINDH sesf Ajjwe4 SdOdCOPS Family Users Guide 3.3 COP421-Series Instruction Set Differences The ININ instruction has been deleted. This is due to the lack of the IN inputs. The INIL instruction has been substantially modified due to the lack of !N inputs and ILaflLy latches. If an {NIL instruction is executed ona COP421-series device, it will input only the state of CKO, providing CKO has been programmed as a general-purpose input (0 > As, Ay, Ag; CKO -> Ad). if CKO has not been programmed as a general- purpose input, the INIL instruction is non-functional on the COP421-series. 3.4 COP410L/COP411L Instruction Set The COP41OL and COP411L instruction sets are subsets of the COP421-series instruction set. Table 3.3 provides the mnemonic, operand, machine code, data flow, skip conditions and description associated with each instruction in the COP410L and COP411L instruction sets. An asterisk in the description column indicates the double-byte instruction. Notes are provided, following this Table 3.3 COP410L/COPAI1L instruction Sot ~~ table, which include additional information relevant to particular instructions. Table 3.4 provides a list of internal architecture, instruction operand and operational symbols used in the COP410L/COP411L Instruction Set Table. Table 3.7 provides an alphabetical mnemonic index of COP410L/COP411L instructions, indicating the hexadecimal opcode and description associated with each instruction. Table 3.8 is a tist of COP410L/COP411L instructions arranged in order of their hexadecimal opcodes. The following text discusses the differences which exist between the GOP410L and COP411L instruction sets and that of the COP420-series. The COP410L is specifically discussed with differences between it and the COP411L noted. All other instructions perform the same machine operations and have the same typical usage as discussed in Section 3.2. For a treatment of the significance of those differences when writing programs for the COP410L and COP411L, see Section 3.5, COP410L/COP411L instruction Set Differences, and Section 4.11, COP410L/COP411L Programming. Jenn ns ah. Machin Co : ee | Mnemonic Operand a ode : ee cena 7 ee : Data Flow. se : ce _ Skip Conditions ARITHMETIGINSTRUCTIONS eee i Sans ASC o1440000 | A+ 6+ RAMB)A jap pot pooy | a + RAM) A claw ao qoooy | ona PNOP ga 8 0 19.910 100) nf None SS uae RO oe oa oor noot 9 ose : x08 : oe : 2 02 : : : a baie ds . arene . : 9-34Table 3.3. COP410LICOP411L Instruction Set (continued) +45 Bd |) RAM) A (Brar= Br RAM(.15) = A SRAMIB) 7 A Bd to Bd Bear Brows RAMB) A Ba +41. Bd. Bren Bro 9-35 ae -Jomp indirect (Note 2): ump > Jumpawithin Page | AUNote Spo Description | aping sJesp Allwe4 SdOD dump to Subroutine F - Se iNote 4y ~. slump to Subroutine _. Return from Subroutine | _ Return from Subroutine then Skip: Copy A, RAM to Qs Ls : None. mo : we None: a None: : None: vNone oy None |: None. _ Bd. decrements past O-. Bd increments past 15. - koad RAM into Ay Exclusive-OR Brwith:r Load O'tndirect (Note: 2} Reset RAM Bit Set RAM -Bit- - Store Memory and Increment Bd Exchange RAM with A, / Exctusive-OR Br with:r Exchange A with RAM = GA5y: Exchange RAM with A . and Decrement Bd; -Exclusive-OR Br with: Exchange RAMiwith A E and increment Bd.. : Exclusive-OR Br with r-