0 Spartan-3AN FPGA Family Data Sheet R DS557 November 19, 2009 0 Product Specification 0 Module 1: Introduction and Ordering Information - DS557-1 (v3.2) November 19, 2009 * * * * * * * * Introduction Features Architectural Overview Configuration Overview In-system Flash Memory Overview General I/O Capabilities Supported Packages and Package Marking Ordering Information * * Module 2: Functional Description Bitstream Sizes Detailed Descriptions by Mode * Self-contained In-System Flash mode * Master Serial Mode using Platform Flash PROM * Master SPI Mode using Commodity Serial Flash * Master BPI Mode using Commodity Parallel Flash * Slave Parallel (SelectMAP) using a Processor * Slave Serial using a Processor * JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNA UG333: Spartan-3AN In-System Flash User Guide UG334: Spartan-3AN Starter Kit User Guide DS557-2 (v3.2) November 19, 2009 Module 3: DC and Switching Characteristics The functionality of the Spartan(R)-3AN FPGA family is described in the following documents: DS557-3 (v3.2) November 19, 2009 * * UG331: Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) * Distributed RAM * SRL16 Shift Registers * Carry and Arithmetic Logic I/O Resources Embedded Multiplier Blocks Programmable Interconnect ISE(R) Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management UG332: Spartan-3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior * * DC Electrical Characteristics Absolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions Switching Characteristics I/O Timing Configurable Logic Block (CLB) Timing Multiplier Timing Block RAM Timing Digital Clock Manager (DCM) Timing Suspend Mode Timing Device DNA Timing Configuration and JTAG Timing Module 4: Pinout Descriptions DS557-4 (v3.2) November 19, 2009 * * * * Pin Descriptions Package Overview Pinout Tables Footprint Diagrams Table 1: Production Status of Spartan-3AN FPGAs Spartan-3AN FPGA XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Status Production Production Production Production Production Additional information on the Spartan-3AN family can be found at http://www.xilinx.com/products/spartan3a/3an.htm. (c) Copyright 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS557 November 19, 2009 Product Specification www.xilinx.com 1 R www.xilinx.com 2 DS557 November 19, 2009 Product Specification < B L B R Spartan-3AN FPGA Family: Introduction and Ordering Information DS557-1 (v3.2) November 19, 2009 Product Specification Introduction The Spartan(R)-3AN FPGA family combines the best attributes of a leading edge, low cost FPGA with nonvolatile technology across a broad range of densities. The family combines all the features of the Spartan-3A FPGA family plus leading technology in-system Flash memory for configuration and nonvolatile data storage. * * * The Spartan-3AN FPGAs are part of the Extended Spartan-3A family, which also includes the Spartan-3A FPGAs and the higher density Spartan-3A DSP FPGAs. The Spartan-3AN FPGA family is excellent for space-constrained applications such as blade servers, medical devices, automotive infotainment, telematics, GPS, and other small consumer products. Combining FPGA and Flash technology minimizes chip count, PCB traces and overall size while increasing system reliability. * The Spartan-3AN FPGA internal configuration interface is completely self-contained, increasing design security. The family maintains full support for external configuration. The Spartan-3AN FPGA is the world's first nonvolatile FPGA with MultiBoot, supporting two or more configuration files in one device, allowing alternative configurations for field upgrades, test modes, or multiple system configurations. * * * * Features * * * * The new standard for low cost nonvolatile FPGA solutions Eliminates traditional nonvolatile FPGA limitations with the advanced 90 nm Spartan-3A device feature set Memory, multipliers, DCMs, SelectIO, hot swap, power management, etc. Integrated robust configuration memory Saves board space Improves ease-of-use Simplifies design Reduces support issues Plentiful amounts of nonvolatile memory available to the user Up to 11+ Mb available MultiBoot support Embedded processing and code shadowing Scratchpad memory * * * * * * * Robust 100K Flash memory program/erase cycles 20 years Flash memory data retention Security features provide bitstream anti-cloning protection Buried configuration interface Unique Device DNA serial number in each device for design Authentication to prevent unauthorized copying Flash memory sector protection and lockdown Configuration watchdog timer automatically recovers from configuration errors Suspend mode reduces system power consumption Retains all design state and FPGA configuration data Fast response time, typically less than 100 s Full hot-swap compliance Multi-voltage, multi-standard SelectIOTM interface pins Up to 502 I/O pins or 227 differential signal pairs LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling Up to 24 mA output drive 3.3V 10% compatibility and hot swap compliance 622+ Mb/s data transfer rate per I/O DDR/DDR2 SDRAM support up to 400 Mb/s LVDS, RSDS, mini-LVDS, PPDS, and HSTL/SSTL differential I/O Abundant, flexible logic resources Densities up to 25,344 logic cells Optional shift register or distributed RAM support Enhanced 18 x 18 multipliers with optional pipeline Hierarchical SelectRAMTM memory architecture Up to 576 Kbits of dedicated block RAM Up to 176 Kbits of efficient distributed RAM Up to eight Digital Clock Managers (DCMs) Eight global clocks and eight additional clocks per each half of device, plus abundant low-skew routing Complete Xilinx(R) ISE(R) and WebPACKTM software development system support MicroBlazeTM and PicoBlazeTM embedded processor cores Fully compliant 32-/64-bit 33 MHz PCITM technology support Low-cost QFP and BGA Pb-free (RoHS) packaging options Pin-compatible with the same packages in the Spartan-3A FPGA family Table 2: Summary of Spartan-3AN FPGA Attributes Device XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN System Gates 50K 200K 400K 700K 1400K Equivalent Logic Cells 1,584 4,032 8,064 13,248 25,344 CLBs 176 448 896 1472 2816 Distributed Slices RAM Bits(1) 704 11K 1792 28K 3,584 56K 5,888 92K 11,264 176K Block RAM Bits(1) 54K 288K 360K 360K 576K Maximum Dedicated Maximum Differential Bitstream In-System Multipliers DCMs User I/O I/O Pairs Size (1) Flash Bits 3 2 108 50 427K 1M 16 4 195 90 1,168K 4M 20 4 311 142 1,842K 4M 20 8 372 165 2,669K 8M 32 8 502 227 4,644K 16M Notes: 1. By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb. (c) Copyright 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS557-1 (v3.2) November 19, 2009 Product Specification www.xilinx.com 3 R Introduction and Ordering Information Architectural Overview The Spartan-3AN FPGA architecture is compatible with that of the Spartan-3A FPGA. The architecture consists of five fundamental programmable functional elements: * Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. * Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. They support a variety of signal standards, including several high-performance differential standards. Double Data-Rate (DDR) registers are included. * Block RAM provides data storage in the form of 18-Kbit dual-port blocks. * Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. * Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XC3S50AN, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XC3S50AN has DCMs only at the top, while the XC3S700AN and XC3S1400AN add two DCMs in the middle of the two columns of block RAM and multipliers. The Spartan-3AN FPGA features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. X-Ref Target - Figure 1 IOBs Multiplier DCM Block RAM CLB IOBs OBs IOBs IOBs CLBs DCM Block RAM / Multiplier DCM IOBs DS557-1_01_122006 Notes: 1. The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column. Figure 1: Spartan-3AN Family Architecture www.xilinx.com 4 DS557-1 (v3.2) November 19, 2009 Product Specification R Introduction and Ordering Information X-Ref Target - Figure 2 Spartan-3AN FPGA Configure from internal Flash memory `0' M2 VCCAUX `1' M1 INIT_B `1' M0 DONE 3.3V Indicates when configuration is finished DS557-1_06_013107 Figure 2: Spartan-3AN FPGA Configuration Interface from Internal SPI Flash Memory Configuration In-System Flash Memory Spartan-3AN FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data is stored on-chip in nonvolatile Flash memory, or externally in a PROM or some other nonvolatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes: Each Spartan-3AN FPGA contains abundant integrated SPI serial Flash memory, shown in Table 3, used primarily to store the FPGA's configuration bitstream. However, the Flash memory array is large enough to store at least two MultiBoot FPGA configuration bitstreams or nonvolatile data required by the FPGA application, such as code-shadowed MicroBlaze processor applications. * Table 3: Spartan-3AN Device In-System Flash Memory Configure from internal SPI Flash memory (Figure 2) Part Number Total Flash Memory (Bits) FPGA Bitstream (Bits) Additional Flash Memory (Bits)(1) Completely self-contained Reduced board space XC3S50AN 1,081,344 437,312 642,048 Easy-to-use configuration interface XC3S200AN 4,325,376 1,196,128 3,127,872 * Master Serial from a Xilinx Platform Flash PROM XC3S400AN 4,325,376 1,886,560 2,437,248 * Serial Peripheral Interface (SPI) from an external industry-standard SPI serial Flash XC3S700AN 8,650,752 2,732,640 5,917,824 * Byte Peripheral Interface (BPI) Up from an industry-standard x8 or x8/x16 parallel NOR Flash XC3S1400AN 17,301,504 4,755,296 12,545,280 1. * Slave Serial, typically downloaded from a processor * Slave Parallel, typically downloaded from a processor * Boundary-Scan (JTAG), typically downloaded from a processor or system tester Aligned to next available page location. After configuration, the FPGA design has full access to the in-system Flash memory via an internal SPI interface; the control logic is implemented with FPGA logic. Additionally, the FPGA application itself can store nonvolatile data or provide live, in-system Flash updates. The MultiBoot feature stores multiple configuration files in the on-chip Flash, providing extended life with field upgrades. MultiBoot also supports multiple system solutions with a single board to minimize inventory and simplify the addition of new features, even in the field. Flexibility is maintained to do additional MultiBoot configurations via the external configuration method. The Spartan-3AN device in-system Flash memory supports leading-edge serial Flash features. The Spartan-3AN device authentication protocol prevents cloning. Design cloning, unauthorized overbuilding, and complete reverse engineering have driven device security requirements to higher and higher levels. Authentication moves the security from bitstream protection to the next generation of design-level security protecting both the design and embedded microcode. The authentication algorithm is entirely user defined, implemented using FPGA logic. Every product, generation, or design can have a different algorithm and functionality to enhance security. DS557-1 (v3.2) November 19, 2009 Product Specification * Small page size (264 or 528 bytes) simplifies nonvolatile data storage * Randomly accessible, byte addressable * Up to 66 MHz serial data transfers * SRAM page buffers Read Flash data while programming another Flash page EEPROM-like byte write functionality Two buffers in most devices, one in XC3S50AN * Page, Block, and Sector Erase * Sector-based data protection and security features www.xilinx.com 5 R Introduction and Ordering Information * Sector Protect: Write- and erase-protect a sector (changeable) Sector Lockdown: Sector data is unchangeable (permanent) I/O Capabilities Separate from FPGA's unique Device DNA identifier The Spartan-3AN FPGA SelectIO interface supports many popular single-ended and differential standards. Table 4 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Some of the user I/Os are unidirectional, input-only pins as indicated in Table 4. 64-byte factory-programmed identifier unique to the in-system Flash memory Spartan-3AN FPGAs support the following single-ended standards: 64-byte one-time programmable, user-programmable field * 3.3V low-voltage TTL (LVTTL) * Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 128-byte Security Register * 100,000 Program/Erase cycles * 20-year data retention * 3.3V PCI at 33 MHz or 66 MHz * Comprehensive programming support * In-system prototype programming via JTAG using Xilinx Platform Cable USB and iMPACT software HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications * Product programming support using BPM Microsystems programmers with appropriate programming adapter SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications Spartan-3AN FPGAs support the following differential standards: Design examples demonstrating in-system programming from a Spartan-3AN FPGA application * LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or 3.3V * Bus LVDS I/O at 2.5V * TMDS I/O at 3.3V * Differential HSTL and SSTL I/O * LVPECL inputs at 2.5V or 3.3V Table 4: Available User I/Os and Differential (Diff) I/O Pairs Package TQ144 TQG144 FT256 FTG256 FG400 FGG400 FG484 FGG484 FG676 FGG676 Body Size (mm)(4) 20 x 20 17 x 17 21 x 21 23 x 23 27 x 27 Device User Diff User Diff User Diff User Diff User Diff XC3S50AN 108 (7) 50 (24) - - - - - - - - XC3S200AN - - 195 (35) 90 (50) - - - - - - XC3S400AN - - - - 311 (63) 142 (78) - - - - XC3S700AN - - - - - - 372 (84) 165 (93) - - XC3S1400AN - - - - - - - - 502 (94) 227 (131) Notes: 1. 2. 3. 4. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. The Diff input-only pin count includes dedicated inputs and differential pins on banks restricted to inputs. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs. See "Pb and Pb-Free Packaging," page 8 for details on Pb and Pb-free packaging options. Each Spartan-3AN FPGA has a pin-compatible Spartan-3A FPGA equivalent, although Spartan-3A FPGAs do not have internal SPI flash and offer more part/package combinations. The footprint for the TQ(G)144 (22 mm x 22 mm) package is larger than the package body. www.xilinx.com 6 DS557-1 (v3.2) November 19, 2009 Product Specification R Introduction and Ordering Information Package Marking The "5C" and "4I" Speed Grade/Temperature Range part combinations may be dual marked as "5C/4I". Devices with the dual mark can be used as either -5C or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. Figure 3 provides a top marking example for Spartan-3AN FPGAs in the quad-flat packages. Figure 4 shows the top marking for Spartan-3AN FPGAs in BGA packages. The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. X-Ref Target - Figure 3 Mask Revision Code Fabrication Code R SPARTAN Device Type Package Speed Grade R Process Technology TM XC3S50AN TQG144 AGQ0725 D1234567A Date Code 4C Lot Code Temperature Range Pin P1 DS557-1_02_080107 Figure 3: Spartan-3AN FPGA QFP Package Marking Example X-Ref Target - Figure 4 Mask Revision Code BGA Ball A1 R SPARTAN Device Type Package R XC3S200ANTM FTG256 AGQ0725 D1234567A 4C Fabrication Code Process Code Date Code Lot Code Speed Grade Temperature Range DS557-1_03_080107 Figure 4: Spartan-3AN FPGA BGA Package Marking Example DS557-1 (v3.2) November 19, 2009 Product Specification www.xilinx.com 7 R Introduction and Ordering Information Pb and Pb-Free Packaging Spartan-3AN FPGAs are available in both leaded (Pb) and Pb-free packaging options (see Table 5). The Pb-free packages are available for all devices and include a `G' character in the ordering code. Leaded (non-Pb-free) packages are available for selected devices. These devices have no `G' in the ordering code and have the same pin-out as Pb-free packages. Table 5: Pb and Pb-Free Package Options Pins 144 256 400 484 676 Type TQFP FTBGA FBGA FBGA FBGA Material Device Pb-Free Speed Range TQG144 XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Pb TQ144 Pb-Free Pb Pb-Free Pb Pb-Free Pb Pb-Free Pb FTG256 FT256 FGG400 FG400 FGG484 FG484 FGG676 FG676 -4 C, I SCD4100(1) -5 C (2) -4 C, I -5 C -4 C, I -5 C (2) -4 C, I -5 C (2) -4 C, I C (2) -5 Notes: 1. 2. To order a Pb package for the XC3S50AN -4 option, append SCD4100 to the part number (XC3S50AN-4TQ144C4100). For Pb packaging for these options, contact your Xilinx sales representative. Ordering Information X-Ref Target - Figure 5 Example: XC3S50AN -4 TQG144 C Device Type Temperature Range: C = Commercial (TJ = 0oC to 85oC) I = Industrial (TJ = -40oC to 100oC) Speed Grade Package Type/Number of Pins DS557-1_05_101109 Figure 5: Device Numbering Format Device Speed Grade Package Type / Number of Pins Temperature Range ( TJ ) C Commercial (0C to 85C) XC3S50AN -4 Standard Performance TQ144/ TQG144 144-pin Thin Quad Flat Pack (TQFP) XC3S200AN -5 High Performance(1) FT256/ FTG256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) I Industrial (-40C to 100C) XC3S400AN FG400/ FGG400 400-ball Fine-Pitch Ball Grid Array (FBGA) XC3S700AN FG484/ FGG484 484-ball Fine-Pitch Ball Grid Array (FBGA) XC3S1400AN FG676/ FGG676 676-ball Fine-Pitch Ball Grid Array (FBGA) Notes: 1. 2. The -5 speed grade is exclusively available in the Commercial temperature range. See Table 4 and Table 5 for available package combinations. www.xilinx.com 8 DS557-1 (v3.2) November 19, 2009 Product Specification R Introduction and Ordering Information Revision History The following table shows the revision history for this document. Date Version Revision 02/26/07 1.0 Initial release. 08/16/07 2.0 Updated for Production release of initial device. 09/12/07 2.0.1 12/12/07 3.0 Updated to Production status with Production release of final family member, XC3S50AN. Noted that non-Pb-free packages may be available for selected devices. 06/02/08 3.1 Minor updates. 11/19/09 3.2 Updated document throughout to reflect availability of Pb package options. Added references to the Extended Spartan-3A family. Removed table note 2 from Table 2. In Table 4, added Pb packages, added table note 4, and updated table note 2. Added Table 5. Noted that only dual-mark devices are guaranteed for both -4I and -5C. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS557-1 (v3.2) November 19, 2009 Product Specification www.xilinx.com 9 R Introduction and Ordering Information www.xilinx.com 10 DS557-1 (v3.2) November 19, 2009 Product Specification R <BL Blue > DS557-2 (v3.2) November 19, 2009 Spartan-3AN FPGA Family: Functional Description Product Specification 0 Spartan-3AN FPGA Design Documentation The functionality of the Spartan(R)-3AN FPGA family is described in the following documents. The topics covered in each guide are listed below: * * * - DS706: Extended Spartan-3A Family Overview www.xilinx.com/support/documentation/ data_sheets/ds706.pdf UG331: Spartan-3 Generation FPGA User Guide http://www.xilinx.com/support/documentation/ user_guides/ug331.pdf Clocking Resources Digital Clock Managers (DCMs) Block RAM ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNA UG333: Spartan-3AN FPGA In-System Flash User Guide http://www.xilinx.com/support/documentation/ user_guides/ug333.pdf For FPGA applications that write to or read from the In-System Flash memory after configuration Configurable Logic Blocks (CLBs) SPI_ACCESS interface - In-System Flash memory architecture Read, program, and erase commands Status registers Sector Protection and Sector Lockdown features Security Register with Unique Identifier Distributed RAM SRL16 Shift Registers Carry and Arithmetic Logic I/O Resources Embedded Multiplier Blocks Programmable Interconnect ISE(R) Design Tools IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management Xilinx Alerts Create a Xilinx MySupport user account and sign up to receive automatic E-mail notification whenever this data sheet or the associated user guides are updated. Sign Up for Alerts on Xilinx MySupport http://www.xilinx.com/support/answers/19380.htm UG332: Spartan-3 Generation Configuration User Guide http://www.xilinx.com/support/documentation/ user_guides/ug332.pdf * Slave Parallel (SelectMAP) using a Processor Slave Serial using a Processor JTAG Mode Spartan-3AN FPGA Starter Kit Configuration Overview For specific hardware examples, please see the Spartan-3AN FPGA Starter Kit board web page, which has links to various design examples and the user guide. - Configuration Pins and Behavior * - Bitstream Sizes Spartan-3AN FPGA Starter Kit Board Page http://www.xilinx.com/s3anstarter * UG334: Spartan-3AN FPGA Starter Kit User Guide http://www.xilinx.com/support/documentation/ boards_and_kits/ug334.pdf Detailed Descriptions by Mode - Master Serial Mode using Xilinx(R) Platform Flash Master SPI Mode using SPI Serial Flash PROM Internal Master SPI Mode Master BPI Mode using Parallel NOR Flash (c) Copyright 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS557-2 (v3.2) November 19, 2009 Product Specification www.xilinx.com 11 R Functional Description Related Product Families The Spartan-3AN FPGA family is generally compatible with the Spartan-3A FPGA family. * DS529: Spartan-3A FPGA Family Data Sheet http://www.xilinx.com/support/documentation/ data_sheets/ds529.pdf Create a Xilinx(R) MySupport user account and sign up to receive automatic E-mail notification whenever this data sheet or the associated user guides are updated. * Sign Up for Alerts on Xilinx MySupport Revision History The following table shows the revision history for this document. Date Version Revision 02/26/07 1.0 Initial release. 08/16/07 2.0 Updated for Production release of initial device. 09/12/07 2.0.1 09/24/07 2.1 Added note that In-System Flash commands were not supported by simulation until ISE 10.1 software. 12/12/07 3.0 Updated to Production status with Production release of final family member, XC3S50AN. Noted that SPI_ACCESS simulation is supported in ISE 10.1 software. Updated links. 06/02/08 3.1 Minor updates. 11/19/09 3.2 In the "Spartan-3AN FPGA Design Documentation" section, added link to DS706, Extended Spartan-3A Family Overview and removed references to older software versions. Minor updates to text. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. www.xilinx.com 12 DS557-2 (v3.2) November 19, 2009 Product Specification R <BL Blue > DS557-3 (v3.2) November 19, 2009 Spartan-3AN FPGA Family: DC and Switching Characteristics Product Specification 0 DC Electrical Characteristics In this section, specifications can be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on characterization. Further changes are not expected. Production: These specifications are approved once the silicon has been characterized over numerous production lots. Parameter values are considered stable with no future changes expected. All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the published parameter values apply to all Spartan(R)-3AN devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades. Absolute Maximum Ratings Stresses beyond those listed under Table 6: Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. Table 6: Absolute Maximum Ratings Symbol Description Conditions Min Max Units VCCINT Internal supply voltage -0.5 1.32 V VCCAUX Auxiliary supply voltage -0.5 3.75 V VCCO Output driver supply voltage -0.5 3.75 V VREF Input reference voltage -0.5 VCCO + 0.5 V -0.95 4.6 V -0.5 4.6 V Human body model - V Charged device model - Machine model - 2000 500 200 VIN Voltage applied to all User I/O pins and Dual-Purpose pins Driver in a high-impedance state Voltage applied to all Dedicated pins Electrostatic Discharge Voltage VESD V V TJ Junction temperature - 125 C TSTG Storage temperature -65 150 C Notes: 1. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages. (c) Copyright 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 13 R DC and Switching Characteristics Power Supply Specifications Table 7: Supply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units VCCINTT Threshold for the VCCINT supply 0.4 1.0 V VCCAUXT Threshold for the VCCAUX supply 1.0 2.0 V VCCO2T Threshold for the VCCO Bank 2 supply 1.0 2.0 V Notes: 1. 2. When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called "Powering Spartan-3 Generation FPGAs" in UG331 for more information). To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Table 8: Supply Voltage Ramp Rate Symbol Description Min Max Units VCCINTR Ramp rate from GND to valid VCCINT supply level 0.2 100 ms VCCAUXR Ramp rate from GND to valid VCCAUX supply level 0.2 100 ms VCCO2R Ramp rate from GND to valid VCCO Bank 2 supply level 0.2 100 ms Notes: 1. 2. When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called "Powering Spartan-3 Generation FPGAs" in UG331 for more information). To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Table 9: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data Symbol Description Units VDRINT VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data 1.0 V VDRAUX VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data 2.0 V www.xilinx.com 14 Min DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics General Recommended Operating Conditions Table 10: General Recommended Operating Conditions Symbol TJ Description Junction temperature Commercial Industrial Min Nominal Max Units 0 - 85 C -40 - 100 C VCCINT Internal supply voltage 1.14 1.20 1.26 V VCCO (1) Output driver supply voltage 1.10 - 3.60 V VCCAUX VIN(2) TIN Auxiliary supply voltage VCCAUX = 3.3V 3.00 3.30 3.60 V Input voltage PCITM IOSTANDARD -0.5 - VCCO+0.5 V All other IOSTANDARDs -0.5 - 4.10 V - - 500 ns Input signal transition time(3) Notes: 1. 2. 3. This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 13 lists the recommended VCCO range specific to each of the single-ended I/O standards, and Table 15 lists that specific to the differential standards. See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins." Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 15 R DC and Switching Characteristics General DC Characteristics for I/O Pins Table 11: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description Test Conditions Min Typ Max Units IL Leakage current at User I/O, Input-only, Dual-Purpose, and Dedicated pins, FPGA powered Driver is in a high-impedance state, VIN = 0V or VCCO max, sample-tested -10 - +10 A IHS Leakage current on pins during hot socketing, FPGA unpowered All pins except INIT_B, PROG_B, DONE, and JTAG pins when PUDC_B = 1. -10 - +10 A INIT_B, PROG_B, DONE, and JTAG pins or other pins when PUDC_B = 0. IRPU(2) RPU(2) Current through pull-up resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins. Dedicated pins are powered by VCCAUX. Equivalent pull-up resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPU per Note 2) IRPD(2) Current through pull-down resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins RPD(2) Equivalent pull-down resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPD per Note 2) IREF VREF current per pin CIN Input capacitance RDT Resistance of optional differential termination circuit within a differential I/O pair. Not available on Input-only pairs. VIN = GND A Add IHS + IRPU VCCO or VCCAUX = 3.0V to 3.6V -151 -315 -710 A VCCO = 2.3V to 2.7V -82 -182 -437 A VCCO = 1.7V to 1.9V -36 -88 -226 A VCCO = 1.4V to 1.6V -22 -56 -148 A VCCO = 1.14V to 1.26V -11 -31 -83 A VCCO = 3.0V to 3.6V 5.1 11.4 23.9 k VCCO = 2.3V to 2.7V 6.2 14.8 33.1 k VCCO = 1.7V to 1.9V 8.4 21.6 52.6 k VCCO = 1.4V to 1.6V 10.8 28.4 74.0 k VCCO = 1.14V to 1.26V 15.3 41.1 119.4 k VIN = VCCO VCCAUX = 3.0V to 3.6V 167 346 659 A VCCAUX = 3.0V to 3.6V VIN = 3.0V to 3.6V 5.5 10.4 20.8 k VIN = 2.3V to 2.7V 4.1 7.8 15.7 k VIN = 1.7V to 1.9V 3.0 5.7 11.1 k VIN = 1.4V to 1.6V 2.7 5.1 9.6 k VIN = 1.14V to 1.26V 2.4 4.5 8.1 k All VCCO levels -10 - +10 A - - - 10 pF VIN = GND VCCO = 3.3V 10% LVDS_33, MINI_LVDS_33, RSDS_33 90 100 115 VCCO = 2.5V 10% LVDS_25, MINI_LVDS_25, RSDS_25 90 110 - Notes: 1. 2. 3. The numbers in this table are based on the conditions set forth in Table 10. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD. VCCAUX must be 3.3V on Spartan-3AN FPGAs. VCCAUX for Spartan-3A FPGAs can be either 3.3V or 2.5V. www.xilinx.com 16 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Quiescent Current Requirements Table 12: Spartan-3AN FPGA Quiescent Supply Current Characteristics Symbol ICCINTQ ICCOQ ICCAUXQ Description Quiescent VCCINT supply current Quiescent VCCO supply current Quiescent VCCAUX supply current Typical(2) Commercial Maximum(2) Industrial Maximum(2) Units XC3S50AN 2 20 30 mA XC3S200AN 7 50 70 mA XC3S400AN 10 85 125 mA XC3S700AN 13 120 185 mA XC3S1400AN 24 220 310 mA XC3S50AN 0.2 2 3 mA XC3S200AN 0.2 2 3 mA XC3S400AN 0.3 3 4 mA XC3S700AN 0.3 3 4 mA XC3S1400AN 0.3 3 4 mA XC3S50AN 3.1 8.1 10.1 mA XC3S200AN 5.1 12.1 15.1 mA XC3S400AN 5.1 18.1 24.1 mA XC3S700AN 6.1 28.1 34.1 mA XC3S1400AN 10.1 50.1 58.1 mA Device Notes: 1. 2. 3. 4. 5. The numbers in this table are based on the conditions set forth in Table 10. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. The internal SPI Flash is deselected (CSB = High); the internal SPI Flash current is consumed on the VCCAUX supply rail. Typical values are characterized using typical devices at room temperature (TJ of 25C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 3.3V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a "blank" configuration data file (that is, a design with no functional elements instantiated). For conditions other than those described above (for example, a design including functional elements), measured quiescent current levels will be different than the values in the table. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3AN FPGA XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design, and b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. For more information on power for the In-System Flash memory, see the Power Management chapter of UG333. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode typically saves 40% total power consumption compared to quiescent current. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 17 R DC and Switching Characteristics Single-Ended I/O Standards Table 13: Recommended Operating Conditions for User I/Os Using Single-Ended Standards IOSTANDARD Attribute VCCO for Drivers(2) VREF Min (V) Nom (V) Max (V) VIL VIH Max (V) Min (V) Min (V) Nom (V) Max (V) LVTTL 3.0 3.3 3.6 0.8 2.0 LVCMOS33(4) 3.0 3.3 3.6 0.8 2.0 LVCMOS25(4,5) 2.3 2.5 2.7 0.7 1.7 LVCMOS18 1.65 1.8 1.95 0.4 0.8 LVCMOS15 1.4 1.5 1.6 0.4 0.8 LVCMOS12 1.1 1.2 1.3 0.4 0.7 PCI33_3 3.0 3.3 3.6 0.3 * VCCO 0.5 * VCCO PCI66_3 3.0 3.3 3.6 0.3 * VCCO 0.5 * VCCO HSTL_I 1.4 1.5 1.6 0.68 0.75 0.9 VREF - 0.1 VREF + 0.1 HSTL_III 1.4 1.5 1.6 - 0.9 - VREF - 0.1 VREF + 0.1 HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 VREF - 0.1 VREF + 0.1 HSTL_II_18 1.7 1.8 1.9 - 0.9 - VREF - 0.1 VREF + 0.1 HSTL_III_18 1.7 1.8 1.9 - 1.1 - VREF - 0.1 VREF + 0.1 SSTL18_I 1.7 1.8 1.9 0.833 0.900 0.969 VREF - 0.125 VREF + 0.125 SSTL18_II 1.7 1.8 1.9 0.833 0.900 0.969 VREF - 0.125 VREF + 0.125 SSTL2_I 2.3 2.5 2.7 1.13 1.25 1.38 VREF - 0.150 VREF + 0.150 SSTL2_II 2.3 2.5 2.7 1.13 1.25 1.38 VREF - 0.150 VREF + 0.150 SSTL3_I 3.0 3.3 3.6 1.3 1.5 1.7 VREF - 0.2 VREF + 0.2 SSTL3_II 3.0 3.3 3.6 1.3 1.5 1.7 VREF - 0.2 VREF + 0.2 VREF is not used for these I/O standards Notes: 1. 2. 3. 4. 5. Descriptions of the symbols used in this table are as follows: VCCO - the supply voltage for output drivers VREF - the reference voltage for setting the input switching threshold VIL - the input voltage that indicates a Low logic level VIH - the input voltage that indicates a High logic level In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs and for PCITM I/O standards. For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 6. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS33 standard. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration. www.xilinx.com 18 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 14: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Table 14: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOL IOH (mA) (mA) IOSTANDARD Attribute LVTTL(3) 2 4 LVCMOS33(3) LVCMOS25(3) LVCMOS18(3) LVCMOS15(3) LVCMOS12(3) 2 4 Test Conditions Logic Level Characteristics VOL Max (V) VOH Min (V) 0.4 2.4 IOSTANDARD Attribute IOL IOH (mA) (mA) Logic Level Characteristics VOL Max (V) VOH Min (V) PCI33_3(5) 1.5 -0.5 10% VCCO 90% VCCO -4 PCI66_3(5) 1.5 -0.5 10% VCCO 90% VCCO 8 -8 0.4 VCCO - 0.4 -2 6 6 -6 HSTL_I(4) 8 8 -8 HSTL_III(4) 24 -8 0.4 VCCO - 0.4 12 12 -12 HSTL_I_18 8 -8 0.4 VCCO - 0.4 16 16 -16 HSTL_II_18(4) 16 -16 0.4 VCCO - 0.4 24 24 -24 HSTL_III_18 24 -8 0.4 VCCO - 0.4 2 2 -2 SSTL18_I 6.7 -6.7 VTT - 0.475 VTT + 0.475 13.4 -13.4 VTT - 0.603 VTT + 0.603 0.4 VCCO - 0.4 4 4 -4 SSTL18_II(4) 6 6 -6 SSTL2_I 8.1 -8.1 VTT - 0.61 VTT + 0.61 16.2 -16.2 VTT - 0.81 VTT + 0.81 8 8 -8 SSTL2_II(4) 12 12 -12 SSTL3_I 8 -8 VTT - 0.6 VTT + 0.6 16 16 -16 SSTL3_II 16 -16 VTT - 0.8 VTT + 0.8 24(4) 24 -24 2 2 -2 4 4 -4 6 6 -6 8 8 -8 12 12 -12 16(4) 16 -16 24(4) 24 -24 2 2 -2 4 4 -4 6 6 -6 8 8 -8 12(4) 12 -12 16(4) 16 -16 2 2 -2 4 4 -4 6 6 -6 8(4) 8 -8 12(4) 12 -12 2 2 -2 4(4) 4 -4 6(4) 6 -6 Notes: 0.4 VCCO - 0.4 1. 2. IOL - the output current condition under which VOL is tested IOH - the output current condition under which VOH is tested VOL - the output voltage that indicates a Low logic level VOH - the output voltage that indicates a High logic level VCCO - the supply voltage for output drivers VTT - the voltage applied to a resistor termination 3. 4. DS557-3 (v3.2) November 19, 2009 Product Specification The numbers in this table are based on the conditions set forth in Table 10 and Table 13. Descriptions of the symbols used in this table are as follows: 0.4 VCCO - 0.4 5. 0.4 VCCO - 0.4 0.4 VCCO - 0.4 For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for the Fast, Slow and QUIETIO slew attributes. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the "Using I/O Resources" chapter in UG331. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see www.xilinx.com/products/ design_resources/conn_central/protocols/pci_pcix.htm. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported. www.xilinx.com 19 R DC and Switching Characteristics Differential I/O Standards Differential Input Pairs X-Ref Target - Figure 6 VINP Internal Logic VINN VINN VID 50% VINP Differential I/O Pair Pins P N VICM GND level VICM = Input common mode voltage = VINP + VINN 2 VID = Differential input voltage = VINP - VINN DS529-3_10_012907 Figure 6: Differential Input Voltages Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards IOSTANDARD Attribute VCCO for Drivers(1) Min (V) Nom (V) Max (V) VID Min (mV) Nom (mV) Max (mV) Min (V) VICM(2) Nom (V) Max (V) 2.35 LVDS_25(3) 2.25 2.5 2.75 100 350 600 0.3 1.25 LVDS_33(3) 3.0 3.3 3.6 100 350 600 0.3 1.25 2.35 BLVDS_25(4) 2.25 2.5 2.75 100 300 - 0.3 1.3 2.35 MINI_LVDS_25(3) 2.25 2.5 2.75 200 - 600 0.3 1.2 1.95 MINI_LVDS_33(3) 3.0 3.3 3.6 200 - 600 0.3 1.2 1.95 LVPECL_25(5) Inputs Only 100 800 1000 0.3 1.2 1.95 LVPECL_33(5) Inputs Only 100 800 1000 0.3 1.2 2.8(6) 1.5 RSDS_25(3) 2.25 2.5 2.75 100 200 - 0.3 1.2 RSDS_33(3) 3.0 3.3 3.6 100 200 - 0.3 1.2 1.5 TMDS_33(3, 4, 7) 3.14 3.3 3.47 150 - 1200 2.7 - 3.23 PPDS_25(3) 2.25 2.5 2.75 100 - 400 0.2 - 2.3 PPDS_33(3) 3.0 3.3 3.6 100 - 400 0.2 - 2.3 DIFF_HSTL_I_18 1.7 1.8 1.9 100 - - 0.8 - 1.1 DIFF_HSTL_II_18(8) 1.7 1.8 1.9 100 - - 0.8 - 1.1 DIFF_HSTL_III_18 1.7 1.8 1.9 100 - - 0.8 - 1.1 DIFF_HSTL_I 1.4 1.5 1.6 100 - - 0.68 DIFF_HSTL_III 1.4 1.5 1.6 100 - - - 0.9 - DIFF_SSTL18_I 1.7 1.8 1.9 100 - - 0.7 - 1.1 DIFF_SSTL18_II(8) 1.7 1.8 1.9 100 - - 0.7 - 1.1 0.9 DIFF_SSTL2_I 2.3 2.5 2.7 100 - - 1.0 - 1.5 DIFF_SSTL2_II(8) 2.3 2.5 2.7 100 - - 1.0 - 1.5 DIFF_SSTL3_I 3.0 3.3 3.6 100 - - 1.1 - 1.9 DIFF_SSTL3_II 3.0 3.3 3.6 100 - - 1.1 - 1.9 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. The VCCO rails supply only differential output drivers, not input circuits. VICM must be less than VCCAUX. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the "Using I/O Resources" chapter in UG331. See "External Termination Requirements for Differential I/O," page 22. LVPECL is supported on inputs only, not outputs. Requires VCCAUX = 3.3V 10%. LVPECL_33 maximum VICM = VCCAUX - (VID / 2) Requires VCCAUX = 3.3V 10% for inputs. (VCCAUX - 300 mV) VICM (VCCAUX - 37 mV) These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the "Using I/O Resources" chapter in UG331. VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in Table 13. Other differential standards do not use VREF. www.xilinx.com 20 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Differential Output Pairs X-Ref Target - Figure 7 VOUTP Internal Logic Differential I/O Pair Pins P N VOUTN VOH VOUTN VOD 50% VOUTP VOL VOCM GND level VOCM = Output common mode voltage = VOUTP + VOUTN 2 VOD = Output differential voltage = VOUTP - VOUTN VOH = Output voltage indicating a High logic level VOL = Output voltage indicating a Low logic levelDS529-3_11_012907 Figure 7: Differential Output Voltages Table 16: DC Characteristics of User I/Os Using Differential Signal Standards VOD IOSTANDARD Attribute LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_HSTL_I DIFF_HSTL_III DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL3_I DIFF_SSTL3_II VOCM Min (mV) 247 247 240 300 300 100 100 400 100 100 - - - Typ (mV) 350 350 350 - - - - - - - - - - Min Max (mV) (V) 454 1.125 454 1.125 460 - 600 1.0 600 1.0 400 1.0 400 1.0 800 VCCO - 0.405 400 0.5 400 0.5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Typ (V) - - 1.30 - - - - - 0.8 0.8 - - - Max (V) 1.375 1.375 - 1.4 1.4 1.4 1.4 VCCO - 0.190 1.4 1.4 - - - - - - - - - - - - - - - - - - - - - - - - - - - VOH VOL Min (V) - - - - - - - - - - VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VTT + 0.475 VTT + 0.475 VTT + 0.61 VTT + 0.81 VTT + 0.6 VTT + 0.8 Max (V) - - - - - - - - - - 0.4 0.4 0.4 0.4 0.4 VTT - 0.475 VTT - 0.475 VTT - 0.61 VTT - 0.81 VTT - 0.6 VTT - 0.8 Notes: 1. The numbers in this table are based on the conditions set forth in Table 10 and Table 15. 2. See "External Termination Requirements for Differential I/O," page 22. 3. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100 across the N and P pins of the differential signal pair. 4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 21 R DC and Switching Characteristics External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards X-Ref Target - Figure 8 Bank 0 and 2 Any Bank Bank 0 Bank 0 Bank 2 VCCO = 3.3V VCCO = 2.5V LVDS_33, MINI_LVDS_33, RSDS_33, PPDS_33 LVDS_25, MINI_LVDS_25, RSDS_25, PPDS_25 Bank 3 Bank 1 1/4th of Bourns Part Number Z0 = 50 CAT16-PT4F4 No VCCO Restrictions LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33, PPDS_25 Bank 2 100 Z0 = 50 DIFF_TERM=No a) Input-only Differential Pairs or Pairs not Using DIFF_TERM=Yes Constraint Z0 = 50 VCCO = 3.3V VCCO = 2.5V LVDS_33, MINI_LVDS_33, RSDS_33, PPDS_33 LVDS_25, MINI_LVDS_25, RSDS_25, PPDS_25 RDT Z0 = 50 VCCO = 3.3V VCCO = 2.5V LVDS_33, MINI_LVDS_33, RSDS_33, PPDS_33 LVDS_25, MINI_LVDS_25, RSDS_25, PPDS_25 DIFF_TERM=Yes b) Differential Pairs Using DIFF_TERM=Yes Constraint DS529-3_09_080307 Figure 8: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards BLVDS_25 I/O Standard X-Ref Target - Figure 9 Any Bank Any Bank Bank 0 Bank 3 Bank 2 VCCO = 2.5V Z0 = 50 165 140 BLVDS_25 1/4th of Bourns Part Number CAT16-PT4F4 Z0 = 50 Bank 1 Bank 1 1/4th of Bourns Part Number CAT16-LV4F12 Bank 3 Bank 0 Bank 2 No VCCO Requirement 100 BLVDS_25 165 DS529-3_07_080307 Figure 9: External Output and Input Termination Resistors for BLVDS_25 I/O Standard TMDS_33 I/O Standard X-Ref Target - Figure 10 Any Bank Bank 0 and 2 Bank 0 3.3V Bank 2 50 Bank 1 Bank 3 Bank 0 50 Bank 2 VCCAUX = 3.3V VCCO = 3.3V TMDS_33 TMDS_33 DVI/HDMI cable DS529-3_08_020107 Figure 10: External Input Resistors Required for TMDS_33 I/O Standard www.xilinx.com 22 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Device DNA Read Endurance Table 17: Device DNA Identifier Memory Characteristics Symbol Description Minimum Units DNA_CYCLES Number of READ operations or JTAG ISC_DNA read operations. Unaffected by HOLD or SHIFT operations 30,000,000 Read cycles Minimum(1) Units Data retention 20 Years Time that the ISF memory is selected and active. SPI_ACCESS design primitive pins CSB = Low, CLK toggling 2 Years 100,000 Cycles 10,000 Cycles 10,000 Cycles 1 Cycle In-System Flash Memory Data Retention, Program/Write Endurance Table 18: In-System Flash (ISF) Memory Characteristics Symbol ISF_RETENTION ISF_ACTIVE ISF_PAGE_CYCLES Description Number of program/erase cycles, per ISF memory page of cumulative random (non-sequential) page erase/program operations ISF_PAGE_REWRITE Number within a sector before pages must be rewritten ISF_SPR_CYCLES Number of program/erase cycles for Sector Protection Register ISF_SEC_CYCLES Number of program cycles for Sector Lockdown Register per sector, user-programmable field in Security Register, and Power-of-2 Page Size Notes: 1. Minimum value at which functionality is still guaranteed. Do not exceed these values. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 23 R DC and Switching Characteristics Switching Characteristics All Spartan-3AN FPGAs ship in two speed grades: -4 and the higher performance -5. Switching characteristics in this document are designated as Preview, Advance, Preliminary, or Production, as shown in Table 19. Each category is defined as follows: are specified using the same numbers for both commercial and industrial grades. Preview: These specifications are based on estimates only and should not be used for timing analysis. * Advance: These specifications are based on simulations only and are typically available soon after establishing FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These specifications are based on complete early silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting preliminary delays is greatly reduced compared to Advance data. Production: These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Software Version Requirements Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status. FPGA designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a production-quality system. Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx(R) ISE(R) software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates. In some cases, a particular family member (and speed grade) is released to Production at a different time than when the speed file is released with the Production label. Any labeling discrepancies are corrected in subsequent speed file releases. See Table 19 for devices that can be considered to have the Production label. All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the published parameter values apply to all Spartan-3AN devices. AC and DC characteristics To create a Xilinx MySupport user account and sign up for automatic E-mail notification whenever this data sheet is updated: Sign Up for Alerts on Xilinx MySupport www.xilinx.com/support/answers/19380.htm Timing parameters and their representative values are selected for inclusion either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3AN speed files (v1.41), part of the Xilinx Development Software, are the original source for many but not all of the values. The speed grade designations for these files are shown in Table 19. For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. Table 19: Spartan-3AN Family v1.41 Speed Grade Designations Device Advance Preliminary Production XC3S50AN -4, -5 XC3S200AN -4, -5 XC3S400AN -4, -5 XC3S700AN -4, -5 XC3S1400AN -4, -5 Table 20 provides the recent history of the Spartan-3AN speed files. Table 20: Spartan-3AN Speed File Version History Version ISE Release Description 1.41 for Spartan-3A family. No ISE 10.1.03 Updated change to data for Spartan-3AN family. 1.40 for Spartan-3A family. No ISE 10.1.02 Updated change to data for Spartan-3AN family. 1.39 ISE 10.1 Updated for Spartan-3A family. No change to data for Spartan-3AN family. 1.38 to Production. No change to ISE 9.2.03i Updated data. 1.37 Updated pin-to-pin setup and hold times, output adjustment, multiplier ISE 9.2.01i TMDS setup/hold times, and block RAM clock width. 1.36 ISE 9.2i Added -5 speed grade, updated to Advance. 1.34 ISE 9.1.03i Updated pin-to-pin timing. 1.32 ISE 9.1.01i Preview speed files for -4 speed grade. www.xilinx.com 24 Preview DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics I/O Timing Pin-to-Pin Clock-to-Output Times Table 21: Pin-to-Pin Clock-to-Output Times for the IOB Output Path Speed Grade Symbol Description Conditions -5 -4 Device Max Max Units XC3S50AN 3.18 3.42 ns XC3S200AN 3.21 3.27 ns XC3S400AN 2.97 3.33 ns XC3S700AN 3.39 3.50 ns XC3S1400AN 3.51 3.99 ns XC3S50AN 4.59 5.02 ns XC3S200AN 4.88 5.24 ns XC3S400AN 4.68 5.12 ns XC3S700AN 4.97 5.34 ns XC3S1400AN 5.06 5.69 ns Clock-to-Output Times TICKOFDCM TICKOF When reading from the Output Flip-Flop (OFF), the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is in use. LVCMOS25(2), 12mA output drive, Fast slew rate, with DCM(3) When reading from OFF, the time LVCMOS25(2), 12mA from the active transition on the output drive, Fast slew Global Clock pin to data appearing rate, without DCM at the Output pin. The DCM is not in use. Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Table 26. If the latter is true, add the appropriate Output adjustment from Table 29. DCM output jitter is included in all measurements. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 25 R DC and Switching Characteristics Pin-to-Pin Setup and Hold Times Table 22: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous) Speed Grade Symbol Description Conditions -5 -4 Device Min Min Units XC3S50AN 2.45 2.68 ns XC3S200AN 2.59 2.84 ns XC3S400AN 2.38 2.68 ns XC3S700AN 2.38 2.57 ns XC3S1400AN 1.91 2.17 ns Setup Times TPSDCM TPSFD When writing to the Input Flip-Flop (IFF), the time from the setup of data at the Input pin to the active transition at a Global Clock pin. The DCM is in use. No Input Delay is programmed. When writing to IFF, the time from the setup of data at the Input pin to an active transition at the Global Clock pin. The DCM is not in use. The Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = 0, with DCM(4) LVCMOS25(2), XC3S50AN 2.55 2.76 ns IFD_DELAY_VALUE = 5, without DCM XC3S200AN 2.32 2.76 ns XC3S400AN 2.21 2.60 ns XC3S700AN 2.28 2.63 ns XC3S1400AN 2.33 2.41 ns Hold Times TPHDCM TPHFD When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is in use. No Input Delay is programmed. LVCMOS25(3), IFD_DELAY_VALUE = 0, with DCM(4) When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is not in use. The Input Delay is programmed. LVCMOS25(3), IFD_DELAY_VALUE = 5, without DCM XC3S50AN -0.36 -0.36 ns XC3S200AN -0.52 -0.52 ns XC3S400AN -0.33 -0.29 ns XC3S700AN -0.17 -0.12 ns XC3S1400AN -0.07 0.00 ns XC3S50AN -0.63 -0.58 ns XC3S200AN -0.56 -0.56 ns XC3S400AN -0.42 -0.42 ns XC3S700AN -0.80 -0.75 ns XC3S1400AN -0.69 -0.69 ns Notes: 1. 2. 3. 4. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 26. If this is true of the data Input, add the appropriate Input adjustment from the same table. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 26. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock's active edge. DCM output jitter is included in all measurements. www.xilinx.com 26 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Input Setup and Hold Times Table 23: Setup and Hold Times for the IOB Input Path Speed Grade Symbol Description Conditions IFD_ DELAY_ VALUE -5 -4 Device Min Min Units XC3S50AN 1.56 1.58 ns XC3S200AN 1.71 1.81 ns XC3S400AN 1.30 1.51 ns XC3S700AN 1.34 1.51 ns XC3S1400AN 1.36 1.74 ns XC3S50AN 2.16 2.18 ns 2 3.10 3.12 ns 3 3.51 3.76 ns 4 4.04 4.32 ns 5 3.88 4.24 ns 6 4.72 5.09 ns 7 5.47 5.94 ns 8 5.97 6.52 ns 2.05 2.20 ns 2 2.72 2.93 ns 3 3.38 3.78 ns 4 3.88 4.37 ns 5 3.69 4.20 ns 6 4.56 5.23 ns 7 5.34 6.11 ns 8 5.85 6.71 ns 1.79 2.02 ns 2 2.43 2.67 ns 3 3.02 3.43 ns 4 3.49 3.96 ns 5 3.41 3.95 ns 6 4.20 4.81 ns 7 4.96 5.66 ns 8 5.44 6.19 ns Setup Times TIOPICK TIOPICKD Time from the setup of data at the LVCMOS25(2) Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed. Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). The Input Delay is programmed. LVCMOS25(2) 0 1 1 1 DS557-3 (v3.2) November 19, 2009 Product Specification XC3S200AN XC3S400AN www.xilinx.com 27 R DC and Switching Characteristics Table 23: Setup and Hold Times for the IOB Input Path (Continued) Speed Grade Symbol TIOPICKD Description Conditions Time from the setup of data at the LVCMOS25(2) Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). The Input Delay is programmed. IFD_ DELAY_ VALUE -5 -4 Min Min Units 1.82 1.95 ns 2 2.62 2.83 ns 3 3.32 3.72 ns 4 3.83 4.31 ns 5 3.69 4.14 ns 6 4.60 5.19 ns 7 5.39 6.10 ns 8 5.92 6.73 ns 1.79 2.17 ns 2 2.55 2.92 ns 3 3.38 3.76 ns 4 3.75 4.32 ns 5 3.81 4.19 ns 6 4.39 5.09 ns 7 5.16 5.98 ns 8 5.69 6.57 ns XC3S50AN -0.66 -0.64 ns XC3S200AN -0.85 -0.65 ns XC3S400AN -0.42 -0.42 ns XC3S700AN -0.81 -0.67 ns XC3S1400AN -0.71 -0.71 ns XC3S50AN -0.88 -0.88 ns 2 -1.33 -1.33 ns 3 -2.05 -2.05 ns 4 -2.43 -2.43 ns 5 -2.34 -2.34 ns 6 -2.81 -2.81 ns 7 -3.03 -3.03 ns 8 -3.83 -3.57 ns -1.51 -1.51 ns 2 -2.09 -2.09 ns 3 -2.40 -2.40 ns 4 -2.68 -2.68 ns 5 -2.56 -2.56 ns 6 -2.99 -2.99 ns 7 -3.29 -3.29 ns 8 -3.61 -3.61 ns 1 1 Device XC3S700AN XC3S1400AN Hold Times TIOICKP TIOICKPD Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. No Input Delay is programmed. Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. The Input Delay is programmed. LVCMOS25(3) LVCMOS25(3) 0 1 1 www.xilinx.com 28 XC3S200AN DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 23: Setup and Hold Times for the IOB Input Path (Continued) Speed Grade Symbol TIOICKPD Description Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. The Input Delay is programmed. Conditions LVCMOS25(3) IFD_ DELAY_ VALUE -5 -4 Min Min Units -1.12 -1.12 ns 2 -1.70 -1.70 ns 3 -2.08 -2.08 ns 4 -2.38 -2.38 ns 5 -2.23 -2.23 ns 6 -2.69 -2.69 ns 7 -3.08 -3.08 ns 8 -3.35 -3.35 ns -1.67 -1.67 ns 2 -2.27 -2.27 ns 3 -2.59 -2.59 ns 4 -2.92 -2.92 ns 5 -2.89 -2.89 ns 6 -3.22 -3.22 ns 7 -3.52 -3.52 ns 8 -3.81 -3.81 ns -1.60 -1.60 ns 2 -2.06 -2.06 ns 3 -2.46 -2.46 ns 4 -2.86 -2.86 ns 5 -2.88 -2.88 ns 6 -3.24 -3.24 ns 7 -3.55 -3.55 ns 8 -3.89 -3.89 ns 1.33 1.61 ns 1 1 1 Device XC3S400AN XC3S700AN XC3S1400AN Set/Reset Pulse Width TRPW_IOB Minimum pulse width to SR control input on IOB - - All Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Table 26. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Table 26. When the hold time is negative, it is possible to change the data before the clock's active edge. Table 24: Sample Window (Source Synchronous) Symbol TSAMP Max Description Setup and hold capture window of an IOB flip-flop. The input capture sample window value is highly specific to a particular application, device, package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the appropriate Xilinx Answer Record for application-specific values. * Answer Record 30879 DS557-3 (v3.2) November 19, 2009 Product Specification Units ps www.xilinx.com 29 R DC and Switching Characteristics Input Propagation Times Table 25: Propagation Times for the IOB Input Path Speed Grade Symbol Description Conditions DELAY_VALUE -5 -4 Max Max Units XC3S50AN 1.04 1.12 ns XC3S200AN 0.87 0.87 ns XC3S400AN 0.65 0.72 ns XC3S700AN 0.92 0.92 ns XC3S1400AN 0.96 1.21 ns Device Propagation Times TIOPI TIOPID The time it takes for data to travel from the Input pin to the I output with no input delay programmed The time it takes for data to travel from the Input pin to the I output with the input delay programmed LVCMOS25(2) IBUF_DELAY_VALUE=0 LVCMOS25(2) 1 1.79 2.07 ns 2 2.13 2.46 ns 3 2.36 2.71 ns 4 2.88 3.21 ns 5 3.11 3.46 ns 6 3.45 3.84 ns 7 3.75 4.19 ns 8 4.00 4.47 ns 9 3.61 4.11 ns 10 3.95 4.50 ns 11 4.18 4.67 ns 12 4.75 5.20 ns 13 4.98 5.44 ns 14 5.31 5.95 ns 15 5.62 6.28 ns 16 5.86 6.57 ns 1 www.xilinx.com 30 XC3S50AN 1.57 1.65 ns 2 XC3S200AN 1.87 1.97 ns 3 2.16 2.33 ns 4 2.68 2.96 ns 5 2.87 3.19 ns 6 3.20 3.60 ns 7 3.57 4.02 ns 8 3.79 4.26 ns 9 3.42 3.86 ns 10 3.79 4.25 ns 11 4.02 4.55 ns 12 4.62 5.24 ns 13 4.86 5.53 ns 14 5.18 5.94 ns DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 25: Propagation Times for the IOB Input Path (Continued) Speed Grade Symbol TIOPID Description The time it takes for data to travel from the Input pin to the I output with the input delay programmed Conditions LVCMOS25(2) -5 -4 Device Max Max Units XC3S200AN 5.43 6.24 ns 5.75 6.59 ns 1.32 1.43 ns 2 1.67 1.83 ns 3 1.90 2.07 ns 4 2.33 2.52 ns 5 2.60 2.91 ns 6 2.94 3.20 ns 7 3.23 3.51 ns 8 3.50 3.85 ns 9 3.18 3.55 ns 10 3.53 3.95 ns 11 3.76 4.20 ns 12 4.26 4.67 ns 13 4.51 4.97 ns 14 4.85 5.32 ns 15 5.14 5.64 ns 16 5.40 5.95 ns 1.84 1.87 ns 2 2.20 2.27 ns 3 2.46 2.60 ns 4 2.93 3.15 ns 5 3.21 3.45 ns 6 3.54 3.80 ns 7 3.86 4.16 ns 8 4.13 4.48 ns 9 3.82 4.19 ns 10 4.17 4.58 ns 11 4.43 4.89 ns 12 4.95 5.49 ns 13 5.22 5.83 ns 14 5.57 6.21 ns 15 5.89 6.55 ns 16 6.16 6.89 ns 1.95 2.18 ns 2 2.29 2.59 ns 3 2.54 2.84 ns 4 2.96 3.30 ns DELAY_VALUE 15 16 1 1 1 DS557-3 (v3.2) November 19, 2009 Product Specification XC3S400AN XC3S700AN XC3S1400AN www.xilinx.com 31 R DC and Switching Characteristics Table 25: Propagation Times for the IOB Input Path (Continued) Speed Grade Symbol TIOPID Description The time it takes for data to travel from the Input pin to the I output with the input delay programmed Conditions LVCMOS25(2) The time it takes for data to travel from the Input pin through the IFF latch to the I output with no input delay programmed LVCMOS25(2) Device Max Max Units 5 XC3S1400AN 3.17 3.52 ns 6 3.52 3.92 ns 7 3.82 4.18 ns 8 4.10 4.57 ns 9 3.84 4.31 ns 10 4.20 4.79 ns 11 4.46 5.06 ns 12 4.87 5.51 ns 13 5.07 5.73 ns 14 5.43 6.08 ns 15 5.73 6.33 ns IFD_DELAY_VALUE=0 www.xilinx.com 32 -4 DELAY_VALUE 16 TIOPLI -5 6.01 6.77 ns XC3S50AN 1.70 1.81 ns XC3S200AN 1.85 2.04 ns XC3S400AN 1.44 1.74 ns XC3S700AN 1.48 1.74 ns XC3S1400AN 1.50 1.97 ns DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 25: Propagation Times for the IOB Input Path (Continued) Speed Grade Symbol Description TIOPLID The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed Conditions LVCMOS25(2 -5 -4 Max Max Units 2.30 2.41 ns 2 3.24 3.35 ns 3 3.65 3.98 ns 4 4.18 4.55 ns 5 4.02 4.47 ns 6 4.86 5.32 ns 7 5.61 6.17 ns 6.11 6.75 ns 2.19 2.43 ns 2 2.86 3.16 ns 3 3.52 4.01 ns 4 4.02 4.60 ns 5 3.83 4.43 ns 6 4.70 5.46 ns 7 5.48 6.33 ns 5.99 6.94 ns 1.93 2.25 ns 2 2.57 2.90 ns 3 3.16 3.66 ns 4 3.63 4.19 ns 5 3.55 4.18 ns 6 4.34 5.03 ns 7 5.09 5.88 ns 5.58 6.42 ns 1.96 2.18 ns 2 2.76 3.06 ns 3 3.45 3.95 ns 4 3.97 4.54 ns 5 3.83 4.37 ns 6 4.74 5.42 ns 7 5.53 6.33 ns 8 6.06 6.96 ns DELAY_VALUE 1 Device XC3S50AN 8 1 XC3S200AN 8 1 XC3S400AN 8 1 DS557-3 (v3.2) November 19, 2009 Product Specification XC3S700AN www.xilinx.com 33 R DC and Switching Characteristics Table 25: Propagation Times for the IOB Input Path (Continued) Speed Grade Symbol Description TIOPLID The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed Conditions LVCMOS25(2 -5 -4 DELAY_VALUE Device Max Max Units 1 XC3S1400AN 1.93 2.40 ns 2 2.69 3.15 ns 3 3.52 3.99 ns 4 3.89 4.55 ns 5 3.95 4.42 ns 6 4.53 5.32 ns 7 5.30 6.21 ns 8 5.83 6.80 ns Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Table 26. www.xilinx.com 34 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Input Timing Adjustments Table 26: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Add the Adjustment Below Speed Grade -5 -4 Units Table 26: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Add the Adjustment Below Speed Grade -5 -4 Units 0.76 0.76 ns Differential Standards Single-Ended Standards LVTTL 0.62 0.62 ns LVDS_25 LVCMOS33 0.54 0.54 ns LVDS_33 0.79 0.79 ns 0.79 0.79 ns LVCMOS25 0 0 ns BLVDS_25 LVCMOS18 0.83 0.83 ns MINI_LVDS_25 0.78 0.78 ns LVCMOS15 0.60 0.60 ns MINI_LVDS_33 0.79 0.79 ns 0.78 0.78 ns LVCMOS12 0.31 0.31 ns LVPECL_25 PCI33_3 0.41 0.41 ns LVPECL_33 0.79 0.79 ns 0.79 0.79 ns PCI66_3 0.41 0.41 ns RSDS_25 HSTL_I 0.72 0.72 ns RSDS_33 0.77 0.77 ns HSTL_III 0.77 0.77 ns TMDS_33 0.79 0.79 ns 0.79 0.79 ns HSTL_I_18 0.69 0.69 ns PPDS_25 HSTL_II_18 0.69 0.69 ns PPDS_33 0.79 0.79 ns 0.74 0.74 ns HSTL_III_18 0.79 0.79 ns DIFF_HSTL_I_18 SSTL18_I 0.71 0.71 ns DIFF_HSTL_II_18 0.72 0.72 ns SSTL18_II 0.71 0.71 ns DIFF_HSTL_III_18 1.05 1.05 ns 0.72 0.72 ns 1.05 1.05 ns SSTL2_I 0.68 0.68 ns DIFF_HSTL_I SSTL2_II 0.68 0.68 ns DIFF_HSTL_III SSTL3_I 0.78 0.78 ns DIFF_SSTL18_I 0.71 0.71 ns ns DIFF_SSTL18_II 0.71 0.71 ns DIFF_SSTL2_I 0.74 0.74 ns DIFF_SSTL2_II 0.75 0.75 ns DIFF_SSTL3_I 1.06 1.06 ns DIFF_SSTL3_II 1.06 1.06 ns SSTL3_II 0.78 0.78 Notes: 1. 2. DS557-3 (v3.2) November 19, 2009 Product Specification The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10, Table 13, and Table 15. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards. www.xilinx.com 35 R DC and Switching Characteristics Output Propagation Times Table 27: Timing for the IOB Output Path Speed Grade Symbol Description -5 -4 Conditions Device Max Max Units LVCMOS25(2), 12 mA output drive, Fast slew rate All 2.87 3.13 ns LVCMOS25(2), 12 mA output drive, Fast slew rate All 2.78 2.91 ns LVCMOS25(2), 12 mA output drive, Fast slew rate All 3.63 3.89 ns 8.62 9.65 ns Clock-to-Output Times TIOCKP When reading from the Output Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the Output pin Propagation Times TIOOP The time it takes for data to travel from the IOB's O input to the Output pin Set/Reset Times TIOSRP TIOGSRQ Time from asserting the OFF's SR input to setting/resetting data at the Output pin Time from asserting the Global Set Reset (GSR) input on the STARTUP_SPARTAN3A primitive to setting/resetting data at the Output pin Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table 29. www.xilinx.com 36 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Three-State Output Propagation Times Table 28: Timing for the IOB Three-State Path Speed Grade Symbol Description Conditions -5 -4 Device Max Max Units Synchronous Output Enable/Disable Times TIOCKHZ Time from the active transition at the OTCLK LVCMOS25, 12 mA input of the Three-state Flip-Flop (TFF) to when output drive, Fast slew the Output pin enters the high-impedance state rate All 0.63 0.76 ns TIOCKON(2) Time from the active transition at TFF's OTCLK input to when the Output pin drives valid data All 2.80 3.06 ns LVCMOS25, 12 mA output drive, Fast slew rate All 9.47 10.36 ns LVCMOS25, 12 mA output drive, Fast slew rate All 1.61 1.86 ns All 3.57 3.82 ns Asynchronous Output Enable/Disable Times TGTS Time from asserting the Global Three State (GTS) input on the STARTUP_SPARTAN3A primitive to when the Output pin enters the high-impedance state Set/Reset Times TIOSRHZ Time from asserting TFF's SR input to when the Output pin enters a high-impedance state TIOSRON(2) Time from asserting TFF's SR input at TFF to when the Output pin drives valid data Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table 29. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 37 R DC and Switching Characteristics Output Timing Adjustments Table 29: Output Timing Adjustments for IOB (Continued) Table 29: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Add the Adjustment Below Speed Grade -5 -4 Units LVCMOS33 Single-Ended Standards LVTTL Slow Fast QuietIO Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Speed Grade -5 -4 Units 2 mA 5.58 5.58 ns 3.17 3.17 ns 2 mA 5.58 5.58 ns 4 mA 4 mA 3.16 3.16 ns 6 mA 3.17 3.17 ns 2.09 2.09 ns 1.24 1.24 ns 6 mA 3.17 3.17 ns 8 mA 8 mA 2.09 2.09 ns 12 mA 12 mA 1.62 1.62 ns 16 mA 1.15 1.15 ns 24 mA 2.55(3) 2.55(3) ns 2 mA 3.02 3.02 ns 16 mA 1.24 1.24 ns 24 mA 2.74(3) 2.74(3) ns 2 mA 3.03 3.03 ns 4 mA 1.71 1.71 ns 1.72 1.72 ns Fast 4 mA 1.71 1.71 ns 6 mA 6 mA 1.71 1.71 ns 8 mA 0.53 0.53 ns 8 mA 0.53 0.53 ns 12 mA 0.59 0.59 ns 16 mA 0.59 0.59 ns 12 mA 0.53 0.53 ns 16 mA 0.59 0.59 ns QuietIO 24 mA 0.51 0.51 ns 2 mA 27.67 27.67 ns 24 mA 0.60 0.60 ns 2 mA 27.67 27.67 ns 4 mA 27.67 27.67 ns 4 mA 27.67 27.67 ns 6 mA 27.67 27.67 ns 16.71 16.71 ns 6 mA 27.67 27.67 ns 8 mA 8 mA 16.71 16.71 ns 12 mA 16.29 16.29 ns 16.18 16.18 ns 12.11 12.11 ns 12 mA 16.67 16.67 ns 16 mA 16 mA 16.22 16.22 ns 24 mA 24 mA 12.11 12.11 ns www.xilinx.com 38 Slow Add the Adjustment Below DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 29: Output Timing Adjustments for IOB (Continued) Add the Adjustment Below Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Speed Grade -5 -4 Units LVCMOS25 2 mA 5.33 5.33 ns 4 mA 2.81 2.81 6 mA 2.82 8 mA 1.14 12 mA 16 mA Slow Fast QuietIO LVCMOS18 Slow Fast QuietIO Table 29: Output Timing Adjustments for IOB (Continued) Add the Adjustment Below Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Speed Grade -5 -4 Units LVCMOS15 2 mA 5.82 5.82 ns ns 4 mA 3.97 3.97 ns 2.82 ns 6 mA 3.21 3.21 ns 1.14 ns 8 mA 2.53 2.53 ns 1.10 1.10 ns 0.83 0.83 ns 24 mA 2.26(3) 2.26(3) 2 mA 4.36 4 mA 1.76 6 mA Slow 12 mA 2.06 2.06 ns 2 mA 5.23 5.23 ns ns 4 mA 3.05 3.05 ns 4.36 ns 6 mA 1.95 1.95 ns 1.76 ns 8 mA 1.60 1.60 ns 1.25 1.25 ns 12 mA 1.30 1.30 ns Fast 8 mA 0.38 0.38 ns 2 mA 34.11 34.11 ns 12 mA 0 0 ns QuietIO 4 mA 25.66 25.66 ns 16 mA 0.01 0.01 ns 6 mA 24.64 24.64 ns 24 mA 0.01 0.01 ns 8 mA 22.06 22.06 ns 2 mA 25.92 25.92 ns 12 mA 20.64 20.64 ns 4 mA 25.92 25.92 ns 2 mA 7.14 7.14 ns 6 mA 25.92 25.92 ns 4 mA 4.87 4.87 ns 8 mA 15.57 15.57 ns 6 mA 5.67 5.67 ns 12 mA 15.59 15.59 ns 2 mA 6.77 6.77 ns 16 mA 14.27 14.27 ns 4 mA 5.02 5.02 ns 24 mA 11.37 11.37 ns 2 mA 4.48 4.48 ns 4 mA 3.69 3.69 ns 6 mA 2.91 2.91 ns 8 mA 1.99 1.99 ns PCI33_3 12 mA 1.57 1.57 ns PCI66_3 16 mA 1.19 1.19 ns 2 mA 3.96 3.96 ns 4 mA 2.57 2.57 ns HSTL_I_18 0.35 0.35 ns 6 mA 1.90 1.90 ns HSTL_II_18 0.30 0.30 ns 8 mA 1.06 1.06 ns HSTL_III_18 0.47 0.47 ns 12 mA 0.83 0.83 ns SSTL18_I 0.40 0.40 ns 16 mA 0.63 0.63 ns SSTL18_II 0.30 0.30 ns 2 mA 24.97 24.97 ns SSTL2_I 0 0 ns 4 mA 24.97 24.97 ns SSTL2_II -0.05 -0.05 ns 6 mA 24.08 24.08 ns SSTL3_I 0 0 ns 8 mA 16.43 16.43 ns SSTL3_II 0.17 0.17 ns 12 mA 14.52 14.52 ns 16 mA 13.41 13.41 ns DS557-3 (v3.2) November 19, 2009 Product Specification LVCMOS12 Slow Fast 6 mA 4.09 4.09 ns 2 mA 50.76 50.76 ns 4 mA 43.17 43.17 ns 6 mA 37.31 37.31 ns 0.34 0.34 ns 0.34 0.34 ns HSTL_I 0.78 0.78 ns HSTL_III 1.16 1.16 ns QuietIO www.xilinx.com 39 R DC and Switching Characteristics Table 29: Output Timing Adjustments for IOB (Continued) Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Add the Adjustment Below Speed Grade -5 -4 Units 1.16 1.16 ns Differential Standards LVDS_25 LVDS_33 0.46 0.46 ns BLVDS_25 0.11 0.11 ns MINI_LVDS_25 0.75 0.75 ns MINI_LVDS_33 0.40 0.40 ns LVPECL_25 Input Only LVPECL_33 RSDS_25 1.42 1.42 ns RSDS_33 0.58 0.58 ns TMDS_33 0.46 0.46 ns PPDS_25 1.07 1.07 ns PPDS_33 0.63 0.63 ns DIFF_HSTL_I_18 0.43 0.43 ns DIFF_HSTL_II_18 0.41 0.41 ns DIFF_HSTL_III_18 0.36 0.36 ns DIFF_HSTL_I 1.01 1.01 ns DIFF_HSTL_III 0.54 0.54 ns DIFF_SSTL18_I 0.49 0.49 ns DIFF_SSTL18_II 0.41 0.41 ns DIFF_SSTL2_I 0.82 0.82 ns DIFF_SSTL2_II 0.09 0.09 ns DIFF_SSTL3_I 1.16 1.16 ns DIFF_SSTL3_II 0.28 0.28 ns Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10, Table 13, and Table 15. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state. Note that 16 mA drive is faster than 24 mA drive for the Slow slew rate. www.xilinx.com 40 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Timing Measurement Methodology connection, and VT is set to zero. The same measurement point (VM) that was used at the Input is also used at the Output. When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 30 lists the conditions to use for each standard. X-Ref Target - Figure 11 VT (VREF) The method for measuring Input timing is as follows: A signal that swings between a Low logic level of VL and a High logic level of VH is applied to the Input under test. Some standards also require the application of a bias voltage to the VREF pins of a given bank to properly set the input-switching threshold. The measurement point of the Input signal (VM) is commonly located halfway between VL and VH. FPGA Output RT (RREF) VM (VMEAS) CL (CREF) DS312-3_04_102406 The Output test setup is shown in Figure 11. A termination voltage VT is applied to the termination resistor RT, the other end of which is connected to the Output. For each standard, RT and VT generally take on the standard values recommended for minimizing signal reflections. If the standard does not ordinarily use terminations (for example, LVCMOS, LVTTL), then RT is set to 1M to indicate an open Notes: 1. The names shown in parentheses are used in the IBIS file. Figure 11: Output Test Setup Table 30: Test Methods for Timing Measurement at I/Os Signal Standard (IOSTANDARD) Inputs Inputs and Outputs Outputs VREF (V) VL (V) VH (V) RT () VT (V) VM (V) LVTTL - 0 3.3 1M 0 1.4 LVCMOS33 - 0 3.3 1M 0 1.65 LVCMOS25 - 0 2.5 1M 0 1.25 LVCMOS18 - 0 1.8 1M 0 0.9 LVCMOS15 - 0 1.5 1M 0 0.75 LVCMOS12 - 0 1.2 1M 0 0.6 - Note 3 Note 3 25 0 0.94 25 3.3 2.03 25 0 0.94 25 3.3 2.03 Single-Ended PCI33_3 Rising Falling PCI66_3 Rising - Note 3 Note 3 Falling HSTL_I 0.75 VREF - 0.5 VREF + 0.5 50 0.75 VREF HSTL_III 0.9 VREF - 0.5 VREF + 0.5 50 1.5 VREF HSTL_I_18 0.9 VREF - 0.5 VREF + 0.5 50 0.9 VREF HSTL_II_18 0.9 VREF - 0.5 VREF + 0.5 25 0.9 VREF HSTL_III_18 1.1 VREF - 0.5 VREF + 0.5 50 1.8 VREF SSTL18_I 0.9 VREF - 0.5 VREF + 0.5 50 0.9 VREF SSTL18_II 0.9 VREF - 0.5 VREF + 0.5 25 0.9 VREF SSTL2_I 1.25 VREF - 0.75 VREF + 0.75 50 1.25 VREF SSTL2_II 1.25 VREF - 0.75 VREF + 0.75 25 1.25 VREF SSTL3_I 1.5 VREF - 0.75 VREF + 0.75 50 1.5 VREF SSTL3_II 1.5 VREF - 0.75 VREF + 0.75 25 1.5 VREF DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 41 R DC and Switching Characteristics Table 30: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) Inputs Inputs and Outputs Outputs VREF (V) VL (V) VH (V) RT () VT (V) VM (V) LVDS_25 - VICM - 0.125 VICM + 0.125 50 1.2 VICM LVDS_33 - VICM - 0.125 VICM + 0.125 50 1.2 VICM BLVDS_25 - VICM - 0.125 VICM + 0.125 1M 0 VICM MINI_LVDS_25 - VICM - 0.125 VICM + 0.125 50 1.2 VICM MINI_LVDS_33 - VICM - 0.125 VICM + 0.125 50 1.2 VICM LVPECL_25 - VICM - 0.3 VICM + 0.3 N/A N/A VICM LVPECL_33 - VICM - 0.3 VICM + 0.3 N/A N/A VICM RSDS_25 - VICM - 0.1 VICM + 0.1 50 1.2 VICM RSDS_33 - VICM - 0.1 VICM + 0.1 50 1.2 VICM TMDS_33 - VICM - 0.1 VICM + 0.1 50 3.3 VICM PPDS_25 - VICM - 0.1 VICM + 0.1 50 0.8 VICM PPDS_33 - VICM - 0.1 VICM + 0.1 50 0.8 VICM DIFF_HSTL_I - VICM - 0.5 VICM + 0.5 50 0.75 VICM DIFF_HSTL_III - VICM - 0.5 VICM + 0.5 50 1.5 VICM DIFF_HSTL_I_18 - VICM - 0.5 VICM + 0.5 50 0.9 VICM DIFF_HSTL_II_18 - VICM - 0.5 VICM + 0.5 50 0.9 VICM DIFF_HSTL_III_18 - VICM - 0.5 VICM + 0.5 50 1.8 VICM DIFF_SSTL18_I - VICM - 0.5 VICM + 0.5 50 0.9 VICM DIFF_SSTL18_II - VICM - 0.5 VICM + 0.5 50 0.9 VICM DIFF_SSTL2_I - VICM - 0.5 VICM + 0.5 50 1.25 VICM DIFF_SSTL2_II - VICM - 0.5 VICM + 0.5 50 1.25 VICM DIFF_SSTL3_I - VICM - 0.5 VICM + 0.5 50 1.5 VICM DIFF_SSTL3_II - VICM - 0.5 VICM + 0.5 50 1.5 VICM Differential Notes: 1. 2. 3. Descriptions of the relevant symbols are as follows: VREF - The reference voltage for setting the input switching threshold VICM - The common mode input voltage VM - Voltage of measurement point on signal transition VL - Low-level test voltage at Input pin VH - High-level test voltage at Input pin RT - Effective termination resistance, which takes on a value of 1 M when no parallel termination is required VT - Termination voltage The load capacitance (CL) at the Output pin is 0 pF for all signal standards. According to the PCI specification. For information on PCI IP solutions, see www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported. The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet. www.xilinx.com 42 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Using IBIS Models to Simulate Load Conditions in Application IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 30 (VT, RT, and VM). Do not confuse VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link: www.xilinx.com/support/download/index.htm Delays for a given application are simulated according to its specific load conditions as follows: 1. Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 11. Use parameter values VT, RT, and VM from Table 30. CREF is zero. 2. Record the time to VM. 3. Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load. 4. Record the time to VMEAS. 5. Compare the results of steps 2 and 4. Add (or subtract) the increase (or decrease) in delay to (or from) the appropriate Output standard adjustment (Table 29) to yield the worst-case delay of the PCB trace. Simultaneously Switching Output Guidelines This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins of a given output signal standard that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce. Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with bonding wires, the package lead frame, DS557-3 (v3.2) November 19, 2009 Product Specification and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality. Table 31 and Table 32 provide the essential SSO guidelines. For each device/package combination, Table 31 provides the number of equivalent VCCO/GND pairs. The equivalent number of pairs is based on characterization and may not match the physical number of pairs. For each output signal standard and drive strength, Table 32 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines in Table 32 are categorized by package style, slew rate, and output drive current. Furthermore, the number of SSOs is specified by I/O bank. Generally, the left and right I/O banks (Banks 1 and 3) support higher output drive current. Multiply the appropriate numbers from Table 31 and Table 32 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter. SSOMAX/IO Bank = Table 31 x Table 32 The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket. The number of SSOs allowed for quad-flat packages (TQ) is lower than for ball grid array packages (FG) due to the larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs. Table 31: Equivalent VCCO/GND Pairs per Bank Package Style Device TQG144 FTG256 FGG400 FGG484 FGG676 XC3S50AN 2 - - - - XC3S200AN - 4 - - - XC3S400AN - - 5 - - XC3S700AN - - - 5 - XC3S1400AN - - - - 9 www.xilinx.com 43 R DC and Switching Characteristics Table 32: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair Table 32: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (Continued) Package Type Package Type FTG256, FGG400, FGG484, FGG676 TQG144 Signal Standard (IOSTANDARD) Top, Bottom Left, Right Top, Bottom Left, Right (Banks 0,2) (Banks 1,3) (Banks 0,2) (Banks 1,3) LVTTL Slow Fast QuietIO Left, Right Top, Bottom Left, Right (Banks 0,2) (Banks 1,3) (Banks 0,2) (Banks 1,3) Slow 2 24 24 76 76 2 20 20 60 60 4 14 14 46 46 4 10 10 41 41 6 11 11 27 27 10 10 20 20 6 10 10 29 29 8 8 6 6 22 22 12 9 9 13 13 16 8 8 10 10 12 6 6 13 13 16 5 5 11 11 Fast 24 - 8 - 9 2 10 10 10 10 24 4 4 9 9 2 10 10 10 10 4 8 8 8 8 5 5 5 5 4 6 6 6 6 6 6 5 5 5 5 8 4 4 4 4 8 3 3 3 3 12 4 4 4 4 16 2 2 2 2 12 3 3 3 3 16 3 3 3 3 QuietIO 24 - 2 - 2 2 36 36 76 76 24 2 2 2 2 2 40 40 80 80 4 32 32 46 46 6 24 24 32 32 4 24 24 48 48 6 20 20 36 36 8 16 16 26 26 16 16 18 18 8 16 16 27 27 12 12 12 12 16 16 16 12 12 14 14 24 - 10 - 10 16 9 9 13 13 24 9 9 12 12 www.xilinx.com 44 Top, Bottom Signal Standard (IOSTANDARD) LVCMOS33 Single-Ended Standards FTG256, FGG400, FGG484, FGG676 TQG144 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 32: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (Continued) Table 32: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (Continued) Package Type FTG256, FGG400, FGG484, FGG676 TQG144 Top, Bottom Left, Right Top, Bottom Left, Right (Banks 0,2) (Banks 1,3) (Banks 0,2) (Banks 1,3) 2 16 16 76 76 4 10 10 46 6 8 8 8 7 7 12 6 16 - Signal Standard (IOSTANDARD) LVCMOS25 Slow Fast QuietIO LVCMOS18 Slow Fast QuietIO Package Type FTG256, FGG400, FGG484, FGG676 TQG144 Top, Bottom Left, Right Top, Bottom Left, Right (Banks 0,2) (Banks 1,3) (Banks 0,2) (Banks 1,3) 2 12 12 55 55 46 4 7 7 31 31 33 33 6 7 7 18 18 24 24 8 - 6 - 15 6 18 18 6 - 11 Signal Standard (IOSTANDARD) LVCMOS15 Slow Fast 12 - 5 - 10 2 10 10 25 25 24 - 5 - 7 4 7 7 10 10 2 12 12 18 18 6 6 6 6 6 4 10 10 14 14 8 - 4 - 4 6 8 8 6 6 12 - 3 - 3 8 6 6 6 6 2 30 30 70 70 12 3 3 3 3 4 21 21 40 40 16 - 3 - 3 6 18 18 31 31 QuietIO 24 - 2 - 2 8 - 12 - 31 2 36 36 76 76 12 - 12 - 20 4 30 30 60 60 2 17 17 40 40 6 24 24 48 48 4 - 13 - 25 8 20 20 36 36 12 12 12 36 36 16 - 12 - 24 - 8 - 2 13 13 64 64 4 8 8 34 6 8 8 22 8 7 7 18 18 12 - 5 - 13 LVCMOS12 Slow 6 - 10 - 18 2 12 9 31 31 36 4 - 9 - 13 8 6 - 9 - 9 2 36 36 55 55 34 4 - 33 - 36 22 6 - 27 - 36 PCI33_3 9 9 16 16 PCI66_3 - 9 - 13 Fast QuietIO 16 - 5 - 10 HSTL_I - 11 - 20 2 13 13 18 18 HSTL_III - 7 - 8 4 8 8 9 9 HSTL_I_18 13 13 17 17 6 7 7 7 7 HSTL_II_18 - 5 - 5 8 4 4 4 4 HSTL_III_18 8 8 10 8 12 - 4 - 4 SSTL18_I 7 13 7 15 16 - 3 - 3 SSTL18_II - 9 - 9 2 30 30 64 64 SSTL2_I 10 10 18 18 4 24 24 64 64 SSTL2_II - 6 - 9 6 20 20 48 48 SSTL3_I 7 8 8 10 8 16 16 36 36 SSTL3_II 5 6 6 7 12 - 12 - 36 16 - 12 - 24 DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 45 R DC and Switching Characteristics Table 32: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (Continued) Package Type FTG256, FGG400, FGG484, FGG676 TQG144 Signal Standard (IOSTANDARD) Top, Bottom Left, Right Top, Bottom Left, Right (Banks 0,2) (Banks 1,3) (Banks 0,2) (Banks 1,3) Differential Standards (Number of I/O Pairs or Channels) LVDS_25 8 - 22 - LVDS_33 8 - 27 - BLVDS_25 1 1 4 4 MINI_LVDS_25 8 - 22 - MINI_LVDS_33 8 - 27 - LVPECL_25 Input Only LVPECL_33 Input Only RSDS_25 8 - 22 - RSDS_33 8 - 27 - TMDS_33 8 - 27 - PPDS_25 8 - 22 - PPDS_33 8 - 27 - DIFF_HSTL_I - 5 - 10 DIFF_HSTL_III - 3 - 4 DIFF_HSTL_I_18 6 6 8 8 DIFF_HSTL_II_18 - 2 - 2 DIFF_HSTL_III_18 4 4 5 4 DIFF_SSTL18_I 3 6 3 7 DIFF_SSTL18_II - 4 - 4 DIFF_SSTL2_I 5 5 9 9 DIFF_SSTL2_II - 3 - 4 DIFF_SSTL3_I 3 4 4 5 DIFF_SSTL3_II 2 3 3 3 Notes: 1. 2. 3. Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only supported in top or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3 Generation FPGA User Guide for additional information. The numbers in this table are recommendations that assume sound board lay out practice. Test limits are the VIL/VIH voltage limits for the respective I/O standard. If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs for information on how to perform weighted average SSO calculations. www.xilinx.com 46 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Configurable Logic Block (CLB) Timing Table 33: CLB (SLICEM) Timing Speed Grade -5 Symbol -4 Description Min Max Min Max Units When reading from the FFX (FFY) Flip-Flop, the time from the active transition at the CLK input to data appearing at the XQ (YQ) output - 0.60 - 0.68 ns TAS Time from the setup of data at the F or G input to the active transition at the CLK input of the CLB 0.18 - 0.36 - ns TDICK Time from the setup of data at the BX or BY input to the active transition at the CLK input of the CLB 1.58 - 1.88 - ns TAH Time from the active transition at the CLK input to the point where data is last held at the F or G input 0 - 0 - ns TCKDI Time from the active transition at the CLK input to the point where data is last held at the BX or BY input 0 - 0 - ns Clock-to-Output Times TCKO Setup Times Hold Times Clock Timing TCH The High pulse width of the CLB's CLK signal 0.63 - 0.75 - ns TCL The Low pulse width of the CLK signal 0.63 - 0.75 - ns FTOG Toggle frequency (for export control) 0 770 0 667 MHz The time it takes for data to travel from the CLB's F (G) input to the X (Y) output - 0.62 - 0.71 ns 1.33 - 1.61 - ns Propagation Times TILO Set/Reset Pulse Width TRPW_CLB The minimum allowable pulse width, High or Low, to the CLB's SR input Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 10. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 47 R DC and Switching Characteristics Table 34: CLB Distributed RAM Switching Characteristics -5 Symbol -4 Description Min Max Min Max Units Time from the active edge at the CLK input to data appearing on the distributed RAM output - 1.69 - 2.01 ns Clock-to-Output Times TSHCKO Setup Times TDS Setup time of data at the BX or BY input before the active transition at the CLK input of the distributed RAM -0.07 - -0.02 - ns TAS Setup time of the F/G address inputs before the active transition at the CLK input of the distributed RAM 0.18 - 0.36 - ns TWS Setup time of the write enable input before the active transition at the CLK input of the distributed RAM 0.30 - 0.59 - ns TDH Hold time of the BX and BY data inputs after the active transition at the CLK input of the distributed RAM 0.13 - 0.13 - ns TAH, TWH Hold time of the F/G address inputs or the write enable input after the active transition at the CLK input of the distributed RAM 0.01 - 0.01 - ns 0.88 - 1.01 - ns Hold Times Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 10. Table 35: CLB Shift Register Switching Characteristics -5 Symbol -4 Description Min Max Min Max Units Time from the active edge at the CLK input to data appearing on the shift register output - 4.11 - 4.82 ns Setup time of data at the BX or BY input before the active transition at the CLK input of the shift register 0.13 - 0.18 - ns Hold time of the BX or BY data input after the active transition at the CLK input of the shift register 0.16 - 0.16 - ns 0.90 - 1.01 - ns Clock-to-Output Times TREG Setup Times TSRLDS Hold Times TSRLDH Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 10. www.xilinx.com 48 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Clock Buffer/Multiplexer Switching Characteristics Table 36: Clock Distribution Switching Characteristics Maximum Speed Grade Description Symbol Minimum -5 -4 Units Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay TGIO - 0.22 0.23 ns Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input TGSI - 0.56 0.63 ns FBUFG 0 350 334 MHz Frequency of signals distributed on global buffers (all sides) Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 10. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 49 R DC and Switching Characteristics 18 x 18 Embedded Multiplier Timing Table 37: 18 x 18 Embedded Multiplier Timing Speed Grade -5 Symbol -4 Description Min Max Min Max Units Combinational multiplier propagation delay from the A and B inputs to the P outputs, assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers unused) - 4.36 - 4.88 ns Combinatorial Delay TMULT Clock-to-Output Times TMSCKP_P Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using the PREG register(2,3) - 0.84 - 1.30 ns TMSCKP_A TMSCKP_B Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using either the AREG or BREG register(2,4) - 4.44 - 4.97 ns TMSDCK_P Data setup time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(3) 3.56 - 3.98 - ns TMSDCK_A Data setup time at the A input before the active transition at the CLK when using the AREG input register(4) 0.00 - 0.00 - ns TMSDCK_B Data setup time at the B input before the active transition at the CLK when using the BREG input register(4) 0.00 - 0.00 - ns TMSCKD_P Data hold time at the A or B input after the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(3) 0.00 - 0.00 - ns TMSCKD_A Data hold time at the A input after the active transition at the CLK when using the AREG input register(4) 0.35 - 0.45 - ns TMSCKD_B Data hold time at the B input after the active transition at the CLK when using the BREG input register(4) 0.35 - 0.45 - ns 0 280 0 250 MHz Setup Times Hold Times Clock Frequency FMULT Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG input registers and the PREG output register(1) Notes: 1. 2. 3. 4. 5. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations. The PREG register is typically used when inferring a single-stage multiplier. Input registers AREG or BREG are typically used when inferring a two-stage multiplier. The numbers in this table are based on the operating conditions set forth in Table 10. www.xilinx.com 50 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Block RAM Timing Table 38: Block RAM Timing Speed Grade -5 Symbol Description -4 Min Max Min Max Units - 2.06 - 2.49 ns TRCCK_ADDR Setup time for the ADDR inputs before the active transition at the CLK input of the block RAM 0.32 - 0.36 - ns TRDCK_DIB Setup time for data at the DIN inputs before the active transition at the CLK input of the block RAM 0.28 - 0.31 - ns TRCCK_ENB Setup time for the EN input before the active transition at the CLK input of the block RAM 0.69 - 0.77 - ns TRCCK_WEB Setup time for the WE input before the active transition at the CLK input of the block RAM 1.12 - 1.26 - ns TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the CLK input 0 - 0 - ns TRCKD_DIB Hold time on the DIN inputs after the active transition at the CLK input 0 - 0 - ns TRCKC_ENB Hold time on the EN input after the active transition at the CLK input 0 - 0 - ns TRCKC_WEB Hold time on the WE input after the active transition at the CLK input 0 - 0 - ns Clock-to-Output Times TRCKO When reading from block RAM, the delay from the active transition at the CLK input to data appearing at the DOUT output Setup Times Hold Times Clock Timing TBPWH High pulse width of the CLK signal 1.56 - 1.79 - ns TBPWL Low pulse width of the CLK signal 1.56 - 1.79 - ns 0 320 0 280 MHz Clock Frequency FBRAM Block RAM clock frequency Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 10. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 51 R DC and Switching Characteristics Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of period jitter, the mean value is the clock period. Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 39 and Table 40) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table 41 through Table 44) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table 39 and Table 40. Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero. Spread Spectrum DCMs accept typical spread spectrum clocks as long as they meet the input requirements. The DLL will track the frequency changes created by the spread spectrum clock to drive the global clocks to the FPGA logic. See XAPP469, Spread-Spectrum Clocking Reception for Displays for details. Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe statistical variation from a mean value. Delay-Locked Loop (DLL) Table 39: Recommended Operating Conditions for the DLL Speed Grade -5 Symbol Description -4 Min Max Min Max Units Frequency of the CLKIN clock input 5(2) 280(3) 5(2) 250(3) MHz CLKIN pulse width as a percentage of the CLKIN period FCLKIN < 150 MHz 40% 60% 40% 60% - FCLKIN > 150 MHz 45% 55% 45% 55% - FCLKIN < 150 MHz - 300 - 300 ps FCLKIN > 150 MHz - 150 - 150 ps Input Frequency Ranges FCLKIN CLKIN_FREQ_DLL Input Pulse Requirements CLKIN_PULSE Input Clock Jitter Tolerance and Delay Path Variation(4) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_DLL_HF Cycle-to-cycle jitter at the CLKIN input CLKIN_PER_JITT_DLL Period jitter at the CLKIN input - 1 - 1 ns CLKFB_DELAY_VAR_EXT Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input - 1 - 1 ns Notes: 1. 2. 3. 4. 5. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 41. The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE, CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM. CLKIN input jitter beyond these limits might cause the DCM to lose lock. The DCM specifications are guaranteed when both adjacent DCMs are locked. www.xilinx.com 52 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 40: Switching Characteristics for the DLL Speed Grade -5 Symbol Description -4 Device Min Max Min Max Units All 5 280 5 250 MHz Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs 5 200 5 200 MHz CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs 10 334 10 334 MHz CLKOUT_FREQ_DV Frequency for the CLKDV output 0.3125 186 0.3125 166 MHz Output Clock Jitter(2,3,4) CLKOUT_PER_JITT_0 Period jitter at the CLK0 output - 100 - 100 ps CLKOUT_PER_JITT_90 Period jitter at the CLK90 output - 150 - 150 ps CLKOUT_PER_JITT_180 Period jitter at the CLK180 output - 150 - 150 ps CLKOUT_PER_JITT_270 Period jitter at the CLK270 output - 150 - 150 ps CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs [0.5% of CLKIN period + 100] - [0.5% of CLKIN period + 100] ps - - 150 - 150 ps [0.5% of CLKIN period + 100] - [0.5% of CLKIN period + 100] ps - [1% of CLKIN period + 350] - [1% of CLKIN period + 350] ps - - 150 - 150 ps - [1% of CLKIN period + 100] ps - [1% of CLKIN period + 100] [1% of CLKIN period + 150] - [1% of CLKIN period + 150] ps - - 5 - 5 ms - 600 - 600 s 15 35 15 35 ps All CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer division CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing non-integer division Duty Cycle(4) CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion All Phase Alignment(4) CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs CLKOUT_PHASE_DLL Phase offset between DLL outputs All CLK0 to CLK2X (not CLK2X180) All others Lock Time LOCK_DLL(3) When using the DLL alone: The 5 MHz < FCLKIN < 15 MHz time from deassertion at the DCM's FCLKIN > 15 MHz Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase All Finest delay resolution, average over all taps All Delay Lines DCM_DELAY_STEP(5) Notes: 1. 2. 3. 4. 5. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 39. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of "[1% of CLKIN period + 150]". Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250 ps. The typical delay step size is 23 ps. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 53 R DC and Switching Characteristics Digital Frequency Synthesizer (DFS) Table 41: Recommended Operating Conditions for the DFS Speed Grade -5 Symbol Input Frequency FCLKIN Description -4 Min Max Min Max Units 0.200 333(4) 0.200 333(4) MHz FCLKFX < 150 MHz - 300 - 300 ps FCLKFX > 150 MHz - 150 - 150 ps - 1 - 1 ns Ranges(2) CLKIN_FREQ_FX Input Clock Jitter Frequency for the CLKIN input Tolerance(3) CLKIN_CYC_JITT_FX_LF CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency CLKIN_PER_JITT_FX Period jitter at the CLKIN input Notes: 1. 2. 3. 4. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 39. CLKIN input jitter beyond these limits may cause the DCM to lose lock. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. Table 42: Switching Characteristics for the DFS Speed Grade -5 Symbol Description -4 Device Min Max Min Max Units Frequency for the CLKFX and CLKFX180 outputs All 5 350 5 320 MHz Period jitter at the CLKFX and CLKFX180 outputs. All Typ Max Typ Max Output Frequency Ranges CLKOUT_FREQ_FX Output Clock Jitter(2,3) CLKOUT_PER_JITT_FX Use the Spartan-3A Jitter Calculator: www.xilinx.com/support/documentation /data_sheets/s3a_jitter_calc.zip ps [1% of CLKFX period + 100] [1% of CLKFX period + 200] [1% of CLKFX period + 100] [1% of CLKFX period + 200] ps All - [1% of CLKFX period + 350] - [1% of CLKFX period + 350] ps CLKIN 20 MHz CLKIN > 20 MHz Duty Cycle(4,5) CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs, including the BUFGMUX and clock tree duty-cycle distortion Phase Alignment(5) CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used All - 200 - 200 ps CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used All - [1% of CLKFX period + 200] - [1% of CLKFX period + 200] ps www.xilinx.com 54 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Table 42: Switching Characteristics for the DFS (Continued) Speed Grade -5 Symbol -4 Description Device Min Max Min Max Units The time from deassertion at the DCM's 5 MHz < FCLKIN Reset input to the rising transition at its < 15 MHz LOCKED output. The DFS asserts LOCKED F when the CLKFX and CLKFX180 signals are CLKIN > 15 MHz valid. If using both the DLL and the DFS, use the longer locking time. All - 5 - 5 ms - 450 - 450 s Lock Time LOCK_FX(2) Notes: 1. 2. 3. 4. 5. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 41. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a maximum CLKFX jitter of "[1% of CLKFX period + 200]". Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 200 ps] = 300 ps. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 55 R DC and Switching Characteristics Phase Shifter (PS) Table 43: Recommended Operating Conditions for the PS in Variable Phase Mode Speed Grade -5 Symbol Description -4 Min Max Min Max Units 1 167 1 167 MHz 40% 60% 40% 60% - Operating Frequency Ranges PSCLK_FREQ (FPSCLK) Frequency for the PSCLK input Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period Table 44: Switching Characteristics for the PS in Variable Phase Mode Symbol Description Phase Shift Amount Units Maximum allowed number of CLKIN < 60 MHz DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN CLKIN 60 MHz clock period in ns. If using CLKIN_DIVIDE_BY_2 = TRUE, double the clock effective clock period. [INTEGER(10 * (TCLKIN - 3 ns))] steps Phase Shifting Range MAX_STEPS(2) [INTEGER(15 * (TCLKIN - 3 ns))] FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting [MAX_STEPS * DCM_DELAY_STEP_MIN] ns FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting [MAX_STEPS * DCM_DELAY_STEP_MAX] ns Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 43. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the bottom of Table 40. www.xilinx.com 56 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Miscellaneous DCM Timing Table 45: Miscellaneous DCM Timing Symbol Description Min Max Units DCM_RST_PW_MIN Minimum duration of a RST pulse width 3 - CLKIN cycles DCM_RST_PW_MAX(2) Maximum duration of a RST pulse width N/A N/A seconds N/A N/A seconds N/A N/A minutes N/A N/A minutes DCM_CONFIG_LAG_TIME(3) Maximum duration from VCCINT applied to FPGA configuration successfully completed (DONE pin goes High) and clocks applied to DCM DLL Notes: 1. 2. 3. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. This specification is equivalent to the VirtexTM-4 DCM_RESET specification. This specification does not apply for Spartan-3AN FPGAs. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3AN FPGAs. DNA Port Timing Table 46: DNA_PORT Interface Timing Symbol Description Min Max Units TDNASSU Setup time on SHIFT before the rising edge of CLK 1.0 - ns TDNASH Hold time on SHIFT after the rising edge of CLK 0.5 - ns TDNADSU Setup time on DIN before the rising edge of CLK 1.0 - ns TDNADH Hold time on DIN after the rising edge of CLK 0.5 - ns TDNARSU Setup time on READ before the rising edge of CLK 5.0 10,000 ns TDNARH Hold time on READ after the rising edge of CLK 0 - ns 0.5 1.5 ns TDNADCKO Clock-to-output delay on DOUT after rising edge of CLK TDNACLKF CLK frequency 0 100 MHz TDNACLKL CLK High time 1.0 ns TDNACLKH CLK Low time 1.0 ns Notes: 1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 s. Internal SPI Access Port Timing Table 47: SPI_ACCESS Interface Timing Speed Grade -5 Symbol Description -4 Min Max Min Max Units TSPICCK_MOSI Setup time on MOSI before the active edge of CLK 4.47 - 5.0 - ns TSPICKC_MOSI Hold time on MOSI after the active edge of CLK 4.03 - 4.5 - ns 50 - 50 - ns TCSB CSB High time TSPICCK_CSB Setup time on CSB before the active edge of CLK 7.15 - 8.0 - ns TSPICCK_CSB Hold time on CSB after the active edge of CLK 7.15 - 8.0 - ns TSPICKO_MISO Clock-to-output delay on MISO after active edge of CLK - 14.3 - 16.0 ns FSPICLK CLK frequency - 50 - 50 MHz FSPICAR1 CLK frequency for Continuous Array Read command - 50 - 50 MHz DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 57 R DC and Switching Characteristics Table 47: SPI_ACCESS Interface Timing (Continued) Speed Grade -5 Symbol Description -4 Min Max Min Max Units FSPICAR1 CLK frequency for Continuous Array Read command, reduced initial latency - 33 - 33 MHz TSPICLKL CLK High time - - ns TSPICLKH CLK Low time 6.8 6.8 ns Notes: 1. For details on using SPI_ACCESS and the In-System Flash memory, see UG333 Spartan-3AN FPGA In-System Flash User Guide. In-System Flash (ISF) Memory Timing Table 48: In-System Flash (ISF) Memory Operations Symbol Description Typical Max Units TXFER Page to Buffer transfer time All - 400 s TCOMP Page to Buffer compare time All - 400 s XC3S50AN XC3S200AN XC3S400AN 2 4 ms XC3S700AN XC3S1400AN 3 6 ms XC3S50AN XC3S200AN XC3S400AN 13 32 ms XC3S700AN XC3S1400AN 15 35 ms XC3S50AN XC3S200AN XC3S400AN XC3S700AN 14 35 ms XC3S1400AN 17 40 ms XC3S50AN 15 35 ms XC3S200AN XC3S400AN 30 75 ms XC3S700AN XC3S1400AN 45 100 ms XC3S50AN 0.8 2.5 s XC3S200AN XC3S400AN XC3S700AN XC3S1400AN 1.6 5 s TPP TPE TPEP TBE TSE Page Programming time Page Erase time Page Erase and Programming time Block Erase time Sector Erase time www.xilinx.com 58 Device DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Suspend Mode Timing X-Ref Target - Figure 12 Entering Suspend Mode Exiting Suspend Mode sw_gwe_cycle sw_gts_cycle SUSPEND Input tSUSPENDHIGH_AWAKE tSUSPENDLOW_AWAKE AWAKE Output tAWAKE_GWE tSUSPEND_GWE Flip-Flops, Block RAM, Distributed RAM Write Protected tAWAKE_GTS tSUSPEND_GTS FPGA Outputs Defined by SUSPEND constraint tSUSPEND_DISABLE FPGA Inputs, Interconnect tSUSPEND_ENABLE Blocked DS610-3_08_061207 Figure 12: Suspend Mode Timing Table 49: Suspend Mode Timing Parameters Symbol Description Min Typ Max Units - 7 - ns +160 +300 +600 ns Entering Suspend Mode TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter (suspend_filter:No) TSUSPENDFILTER Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled (suspend_filter:Yes) TSUSPEND_GWE Rising edge of SUSPEND pin until FPGA output pins drive their defined SUSPEND constraint behavior - 10 - ns TSUSPEND_GTS Rising edge of SUSPEND pin to write-protect lock on all writable clocked elements - <5 - ns TSUSPEND_DISABLE Rising edge of the SUSPEND pin to FPGA input pins and interconnect disabled - 340 - ns Exiting Suspend Mode TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin Does not include DCM lock time - 4 to 108 - s TSUSPEND_ENABLE Falling edge of the SUSPEND pin to FPGA input pins and interconnect re-enabled - 3.7 to 109 - s TAWAKE_GWE1 Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1 - 67 - ns TAWAKE_GWE512 Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512 - 14 - s TAWAKE_GTS1 Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1 - 57 - ns TAWAKE_GTS512 Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512 - 14 - s Notes: 1. 2. These parameters based on characterization. For information on using the Spartan-3AN Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 59 R DC and Switching Characteristics Configuration and JTAG Timing General Configuration Power-On/Reconfigure Timing X-Ref Target - Figure 13 1.2V VCCINT (Supply) 1.0V VCCAUX (Supply) 2.0V VCCO Bank 2 (Supply) 2.0V 3.3V 2.5V or 3.3V TPOR PROG_B (Input) TPROG INIT_B (Open-Drain) TPL TICCK CCLK (Output) DS557-3_01_052908 Notes: 1. 2. 3. When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order if this requirement is met. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2). Figure 13: Waveforms for Power-On and the Beginning of Configuration Table 50: Power-On Timing and the Beginning of Configuration All Speed Grades Symbol Description Device Min Max Units All - 18 ms The width of the low-going pulse on the PROG_B pin All 0.5 - s The time from the rising edge of the PROG_B pin to the rising transition on the INIT_B pin XC3S50AN - 0.5 ms XC3S200AN - 0.5 ms XC3S400AN - 1 ms XC3S700AN - 2 ms TPOR(2) The time from the application of VCCINT, VCCAUX, and VCCO Bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the INIT_B pin TPROG TPL(2) - 2 ms TINIT Minimum Low pulse width on INIT_B output All 250 - ns TICCK(3) The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin All 0.5 4 s XC3S1400AN Notes: 1. 2. 3. 4. The numbers in this table are based on the operating conditions set forth in Table 10. This means power must be applied to all VCCINT, VCCO, and VCCAUX lines. Power-on reset and the clearing of configuration memory occurs during this period. This specification applies only to the Master Serial, SPI, and BPI modes. For details on configuration, see UG332 Spartan-3 Generation Configuration User Guide. www.xilinx.com 60 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Configuration Clock (CCLK) Characteristics Table 51: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol TCCLK1 Description CCLK clock period by ConfigRate setting ConfigRate Setting Temperature Range Minimum 1 (power-on value) Commercial 1,254 TCCLK3 3 TCCLK6 6 (default) TCCLK7 7 TCCLK8 8 TCCLK10 10 TCCLK12 12 TCCLK13 13 TCCLK17 17 TCCLK22 22 TCCLK25 25 TCCLK27 27 TCCLK33 33 TCCLK44 44 TCCLK50 50 TCCLK100 100 Industrial 1,180 Commercial 413 Industrial 390 Commercial 207 Industrial 195 Commercial 178 Industrial 168 Commercial 156 Industrial 147 Commercial 123 Industrial 116 Commercial 103 Industrial 97 Commercial 93 Industrial 88 Commercial 72 Industrial 68 Commercial 54 Industrial 51 Commercial 47 Industrial 45 Commercial 44 Industrial 42 Commercial 36 Industrial 34 Commercial 26 Industrial 25 Commercial 22 Industrial 21 Commercial 11.2 Industrial 10.6 Maximum 2,500 833 417 357 313 250 208 192 147 114 100 93 76 57 50 25 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Set the ConfigRate option value when generating a configuration bitstream. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 61 R DC and Switching Characteristics Table 52: Master Mode CCLK Output Frequency by ConfigRate Option Setting Description ConfigRate Setting Temperature Range Equivalent CCLK clock frequency by ConfigRate setting 1 (power-on value) Commercial Symbol FCCLK1 Minimum 0.400 Industrial Commercial FCCLK3 3 FCCLK6 6 (default) FCCLK7 7 FCCLK8 8 FCCLK10 10 FCCLK12 12 FCCLK13 13 FCCLK17 17 FCCLK22 22 FCCLK25 25 FCCLK27 27 FCCLK33 33 FCCLK44 44 FCCLK50 50 FCCLK100 100 1.20 Industrial Commercial 2.40 Industrial Commercial 2.80 Industrial Commercial 3.20 Industrial Commercial 4.00 Industrial Commercial 4.80 Industrial Commercial 5.20 Industrial Commercial 6.80 Industrial Commercial 8.80 Industrial Commercial 10.00 Industrial Commercial 10.80 Industrial Commercial 13.20 Industrial Commercial 17.60 Industrial Commercial 20.00 Industrial Commercial 40.00 Industrial Maximum Units 0.797 MHz 0.847 MHz 2.42 MHz 2.57 MHz 4.83 MHz 5.13 MHz 5.61 MHz 5.96 MHz 6.41 MHz 6.81 MHz 8.12 MHz 8.63 MHz 9.70 MHz 10.31 MHz 10.69 MHz 11.37 MHz 13.74 MHz 14.61 MHz 18.44 MHz 19.61 MHz 20.90 MHz 22.23 MHz 22.39 MHz 23.81 MHz 27.48 MHz 29.23 MHz 37.60 MHz 40.00 MHz 44.80 MHz 47.66 MHz 88.68 MHz 94.34 MHz Table 53: Master Mode CCLK Output Minimum Low and High Time ConfigRate Setting Symbol TMCCL, TMCCH Description Master Mode CCLK Minimum Low and High Time 100 Units Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns Industrial 1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 Table 54: Slave Mode CCLK Input Low and High Time Symbol TSCCL, TSCCH Description CCLK Low and High time www.xilinx.com 62 Min Max Units 5 ns DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Master Serial and Slave Serial Mode Timing X-Ref Target - Figure 14 PROG_B (Input) INIT_B (Open-Drain) TMCCH TSCCH TMCCL TSCCL CCLK (Input/Output) TDCC DIN (Input) 1/FCCSER TCCD Bit 0 Bit 1 Bit n Bit n+1 TCCO DOUT (Output) Bit n-64 Bit n-63 DS312-3_05_103105 Figure 14: Waveforms for Master Serial and Slave Serial Configuration Table 55: Timing for the Master Serial and Slave Serial Configuration Modes Description Slave/ Master The time from the falling transition on the CCLK pin to data appearing at the DOUT pin Symbol All Speed Grades Min Max Units Both 1.5 10 ns The time from the setup of data at the DIN pin to the rising transition at the CCLK pin Both 7 - ns The time from the rising transition at the CCLK pin to the point when data is last held at the DIN pin Master 0 Slave 1.0 Clock-to-Output Times TCCO Setup Times TDCC Hold Times TCCD - ns Clock Timing TCCH TCCL FCCSER High pulse width at the CCLK input pin Low pulse width at the CCLK input pin Frequency of the clock signal at the CCLK input pin No bitstream compression With bitstream compression Master See Table 53 Slave See Table 54 Master See Table 53 Slave See Table 54 Slave 0 100 MHz 0 100 MHz Notes: 1. 2. The numbers in this table are based on the operating conditions set forth in Table 10. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 63 R DC and Switching Characteristics Slave Parallel Mode Timing X-Ref Target - Figure 15 PROG_B (Input) INIT_B (Open-Drain) TSMCSCC TSMCCCS CSI_B (Input) TSMCCW TSMWCC RDWR_B (Input) TMCCH TSCCH TMCCL TSCCL CCLK (Input) TSMDCC D0 - D7 (Inputs) TSMCCD Byte 0 1/FCCPAR Byte 1 Byte n Byte n+1 DS529-3_02_051607 Notes: 1. 2. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0 - D7 bus. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332 Chapter 7 section "Non-Continuous SelectMAP Data Loading" for more details. Figure 15: Waveforms for Slave Parallel Configuration Table 56: Timing for the Slave Parallel Configuration Mode All Speed Grades Symbol Description Min Max Units TSMDCC The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin 7 - ns TSMCSCC Setup time on the CSI_B pin before the rising transition at the CCLK pin 7 - ns TSMCCW(2) Setup time on the RDWR_B pin before the rising transition at the CCLK pin 15 - ns TSMCCD The time from the rising transition at the CCLK pin to the point when data is last held at the D0-D7 pins 1.0 - ns TSMCCCS The time from the rising transition at the CCLK pin to the point when a logic level is last held at the CSO_B pin 0 - ns TSMWCC The time from the rising transition at the CCLK pin to the point when a logic level is last held at the RDWR_B pin 0 - ns TCCH The High pulse width at the CCLK input pin 5 - ns TCCL The Low pulse width at the CCLK input pin 5 - ns FCCPAR Frequency of the clock signal No bitstream compression at the CCLK input pin With bitstream compression 0 80 MHz 0 80 MHz Setup Times Hold Times Clock Timing Notes: 1. 2. The numbers in this table are based on the operating conditions set forth in Table 10. Some Xilinx documents refer to Parallel modes as "SelectMAP" modes. www.xilinx.com 64 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics External Serial Peripheral Interface (SPI) Configuration Timing X-Ref Target - Figure 16 PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point these pins become user-I/O pins. <0:0:1> (Input) TINITM TMINIT INIT_B New ConfigRate active (Open-Drain) TCCLKn TMCCHn TMCCLn TCCLK1 TMCCL1 TMCCH1 T CCLK1 CCLK TV DIN Data (Input) TCSS Data Data TDCC Data TCCD CSO_B TCCO Command (msb) MOSI Command (msb-1) TDSU T DH Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low. Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B. Shaded values indicate specifications on attached SPI Flash PROM. DS529-3_06_102506 Figure 16: Waveforms for External Serial Peripheral Interface (SPI) Configuration Table 57: Timing for External Serial Peripheral Interface (SPI) Configuration Mode Symbol Description Minimum Maximum Units TCCLK1 Initial CCLK clock period See Table 51 TCCLKn CCLK clock period after FPGA loads ConfigRate bitstream option setting See Table 51 TMINIT Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the rising edge of INIT_B 50 - ns TINITM Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the rising edge of INIT_B 0 - ns TCCO MOSI output valid delay after CCLK falling clock edge See Table 55 TDCC Setup time on the DIN data input before CCLK rising clock edge See Table 55 TCCD Hold time on the DIN data input after CCLK rising clock edge See Table 55 DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 65 R DC and Switching Characteristics Table 58: Configuration Timing Requirements for Attached SPI Serial Flash Symbol Description Requirement Units TCCS SPI serial Flash PROM chip-select time T CCS T MCCL1 - T CCO ns TDSU SPI serial Flash PROM data input setup time T DSU T MCCL1 - T CCO ns TDH SPI serial Flash PROM data input hold time TV SPI serial Flash PROM data clock-to-output time fC or fR Maximum SPI serial Flash PROM clock frequency (also depends on specific read command used) T DH T MCCH1 ns T V T MCCLn - T DCC ns 1 f C --------------------------------T CCLKn ( min ) MHz Notes: 1. 2. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA. Subtract additional printed circuit board routing delay as required by the application. www.xilinx.com 66 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics Byte Peripheral Interface (BPI) Configuration Timing X-Ref Target - Figure 17 PROG_B (Input) PUDC_B (Input) PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. M[2:0] (Input) Mode input pins M[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point the mode pins become user-I/O pins. <0:1:0> TMINIT INIT_B (Open-Drain) TINITM Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low. Pin initially high-impedance (Hi-Z) if PUDC_B input is High. LDC[2:0] HDC CSO_B New ConfigRate active TCCLK1 TCCLK1 T INITADDR TCCLKn CCLK TCCO 000_0000 A[25:0] Address 000_0001 TAVQV D[7:0] (Input) Byte 0 Byte 1 Address Address TCCD TDCC Data Data Data Shaded values indicate specifications on attached parallel NOR Flash PROM. Data DS557-3_16_032009 Figure 17: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration Table 59: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode Symbol Description Minimum Maximum Units TCCLK1 Initial CCLK clock period See Table 51 TCCLKn CCLK clock period after FPGA loads ConfigRate setting See Table 51 TMINIT Setup time on M[2:0] mode pins before the rising edge of INIT_B 50 - ns TINITM Hold time on M[2:0] mode pins after the rising edge of INIT_B 0 - ns TINITADDR Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted and valid 5 5 TCCLK1 cycles TCCO Address A[25:0] outputs valid after CCLK falling edge TDCC Setup time on D[7:0] data inputs before CCLK rising edge TCCD Hold time on D[7:0] data inputs after CCLK rising edge DS557-3 (v3.2) November 19, 2009 Product Specification See Table 55 See TSMDCC in Table 56 0 - ns www.xilinx.com 67 R DC and Switching Characteristics Table 60: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description Requirement Units TCE (tELQV) Parallel NOR Flash PROM chip-select time T CE T INITADDR ns TOE (tGLQV) Parallel NOR Flash PROM output-enable time T OE T INITADDR ns TACC (tAVQV) Parallel NOR Flash PROM read access time T ACC 0.5T CCLKn ( min ) - T CCO - T DCC - PCB ns TBYTE (tFLQV, tFHQV) For x8/x16 PROMs only: BYTE# to output valid time(3) T BYTE T INITADDR ns Notes: 1. 2. 3. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA. Subtract additional printed circuit board routing delay as required by the application. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA's LDC2 pin. The resistor value also depends on whether the FPGA's PUDC_B pin is High or Low. www.xilinx.com 68 DS557-3 (v3.2) November 19, 2009 Product Specification R DC and Switching Characteristics IEEE 1149.1/1553 JTAG Test Access Port Timing X-Ref Target - Figure 18 TCCH TCCL TCK (Input) 1/FTCK TTCKTMS TTMSTCK TMS (Input) TTDITCK TTCKTDI TDI (Input) TTCKTDO TDO (Output) DS557_13_032009 Figure 18: JTAG Waveforms Table 61: Timing for the JTAG Test Access Port All Speed Grades Symbol Description Min Max Units 1.0 11.0 ns All devices and functions except those shown below 7.0 - ns Boundary-Scan commands (INTEST, EXTEST, SAMPLE) on XC3S700AN and XC3S1400AN FPGAs 11.0 7.0 - ns 0 - ns 0 - ns 5 - ns 5 - ns 10 10,000 ns 10 10,000 ns 0 33 MHz Clock-to-Output Times TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin Setup Times TTDITCK The time from the setup of data at the TDI pin to the rising transition at the TCK pin TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin Hold Times TTCKTDI The time from the rising transition at the TCK pin to the point when data is last held at the TDI pin All functions except those shown below Configuration commands (CFG_IN, ISC_PROGRAM) TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the TMS pin 2.0 Clock Timing TCCH The High pulse width at the TCK pin TCCL The Low pulse width at the TCK pin TCCHDNA The High pulse width at the TCK pin All functions except ISC_DNA command During ISC_DNA command TCCLDNA The Low pulse width at the TCK pin FTCK Frequency of the TCK signal All operations on XC3S50AN, XC3S200AN, and XC3S400AN FPGAs and for BYPASS or HIGHZ instructions on all FPGAs All operations on XC3S700AN and XC3S1400AN FPGAs, except for BYPASS or HIGHZ instructions 20 Notes: 1. 2. The numbers in this table are based on the operating conditions set forth in Table 10. For details on JTAG see Chapter 9 "JTAG Configuration Mode and Boundary-Scan" in UG332 Spartan-3 Generation Configuration User Guide. DS557-3 (v3.2) November 19, 2009 Product Specification www.xilinx.com 69 R DC and Switching Characteristics Revision History The following table shows the revision history for this document. Date Version Revision 02/26/07 1.0 Initial release. 08/16/07 2.0 Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38 speed files. DC specifications updated with production values. Other changes throughout. 08/31/07 2.0.1 Updated for Production release of XC3S1400AN. Improved tPEP for XC3S700AN in Table 48. 09/12/07 2.0.2 Updated for Production release of XC3S700AN. 09/24/07 2.1 Updated for Production release of XC3S400AN. Updated Software Version Requirements to note that Production speed files are available as of Service Pack 3. Removed PCIX IOSTANDARD due to limited PCIX interface support. Added note that SPI_ACCESS (In-System Flash) is not currently supported in simulation. 12/12/07 3.0 Updated to Production status with Production release of final family member, XC3S50AN. Noted that SPI_ACCESS simulation is supported in ISE 10.1 software. Removed DNA_RETENTION limit of 10 years in Table 17 since number of Read cycles is the only unique limit. Updated Setup, Hold, and Propagation Times for the IOB Input Path to show values by device in Table 23 and Table 25. Increased SSO recommendation for SSTL18_II in Table 32. Updated Figure 17 and Table 59 to show BPI data synchronous to CCLK rising edge. Updated links. 06/02/08 3.1 Improved VCCAUXT and VCCO2T POR minimum in Table 7 and updated VCCO POR levels in Figure 13. Clarified power sequencing in Note 1 of Table 7, Table 8, and Figure 13. Added VIN to Recommended Operating Conditions in Table 10 and added reference to XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins." Reduced typical ICCINTQ and ICCAUXQ quiescent current values by 12%-58% in Table 12. Noted latest speed file v1.39 in ISE 10.1 software in Table 19. Added reference to Sample Window in Table 24. Changed Internal SPI interface max frequency to 50 MHz and updated other Internal SPI timing parameters to match names and values from speed file in Table 47. Restored Units column to Table 49. Updated CCLK output maximum period in Table 51 to match minimum frequency in Table 52. Added references to User Guides. 11/19/09 3.2 Updated selected I/O standard DC characteristics. Changed typical quiescent current temperature from ambient to junction. Removed references to older software versions. Updated column 3 header of Table 17 and Table 18. Added table note to Table 18. Added TIOPI and TIOPID propagation times in Table 25. Updated TIOCKHZ and TIOCKON synchronous output enable/disable times in Table 28. Removed VREF requirements for differential HSTL and differential SSTL in Table 30. Improved DIFF_SSTL18_II SSO limits in Table 32. Updated table note 3 in Table 39. Removed references to old software versions from Table 47 and Table 48. Added description of spread spectrum in "Spread Spectrum" section. Updated BPI configuration waveforms in Figure 17. Updated TACC equation in Table 60. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. www.xilinx.com 70 DS557-3 (v3.2) November 19, 2009 Product Specification <BL Blue > R DS557-4 (v3.2) November 19, 2009 Spartan-3AN FPGA Family: Pinout Descriptions Product Specification 0 Introduction This section describes how the various pins on a Spartan(R)-3AN FPGA connect within the supported component packages, and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, see the Packaging section of UG331: * UG331: Spartan-3 Generation FPGA User Guide http://www.xilinx.com/support/documentation/ user_guides/ug331.pdf Spartan-3AN FPGAs are available in Pb-free, RoHS packages, indicated by a "G" in the middle of the package code. Leaded (Pb) packages are available for selected devices, with the same pinout and without the `G' in the ordering code (see Table 5, page 8). The Pb-free package code can be selected in the software for the Pb packages since the pinouts are identical. References to the Pb-free package code in this document apply also to the Pb package. Pin Types Most pins on a Spartan-3AN FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different functional types of pins on Spartan-3AN FPGA packages, as outlined in Table 62. In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table. Table 62: Types of Pins on Spartan-3AN FPGAs Type / Color Code Description I/O Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential I/Os. IO_# IO_Lxxy_# Unrestricted, general-purpose input-only pin. This pin does not have an output structure, differential termination resistor, or PCITM clamp diode. IP_# IP_Lxxy_# Dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user I/O after configuration. If the pin is not used during configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation Configuration User Guide for additional information on these signals. M[2:0] PUDC_B CCLK MOSI/CSI_B D[7:1] D0/DIN DOUT CSO_B RDWR_B INIT_B A[25:0] VS[2:0] LDC[2:0] HDC VREF Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF pins in the same bank, provides a reference voltage input for certain I/O standards. If used for a reference voltage within a bank, all VREF pins within the bank must be connected. IP/VREF_# IP_Lxx_#/VREF_# IO/VREF_# IO_Lxx_#/VREF_# CLK Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global IO_Lxx_#/GCLK[15:0], clock inputs that optionally clock the entire device. The exception is the TQ144 package). The IO_Lxx_#/LHCLK[7:0], RHCLK inputs optionally clock the right half of the device. The LHCLK inputs optionally clock the IO_Lxx_#/RHCLK[7:0] left half of the device. See the Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for additional information on these signals. INPUT DUAL CONFIG Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See the UG332: Spartan-3 Generation Configuration User Guide for additional information on the DONE and PROG_B signals. Pin Name(s) in Type DONE, PROG_B (c) Copyright 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 71 R Pinout Descriptions Table 62: Types of Pins on Spartan-3AN FPGAs (Continued) Type / Color Code Description PWR MGMT Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and is powered by VCCAUX. AWAKE is a Dual-Purpose pin. Unless Suspend mode is enabled in the application, AWAKE is available as a user-I/O pin. SUSPEND, AWAKE JTAG Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four dedicated JTAG pins. These pins are powered by VCCAUX. TDI, TMS, TCK, TDO GND Dedicated ground pin. The number of GND pins depends on the package used. All must be connected. GND VCCAUX Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package used. The In-System Flash memory is powered by VCCAUX. All must be connected to +3.3V. VCCAUX VCCINT Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the package used. All must be connected to +1.2V. VCCINT VCCO N.C. Pin Name(s) in Type Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers VCCO_# within the I/O bank and sets the input threshold voltage for some I/O standards. All must be connected. This package pin is not connected in this specific device/package combination. N.C. Notes: 1. # = I/O bank number, an integer between 0 and 3. Package Pins by Type is available, as shown in Table 64. The table shows the maximum number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as general-purpose I/O. AWAKE is counted here as a Dual-Purpose I/O pin. Likewise, the table shows the maximum number of differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by pin type, including the number of unconnected--N.C.--pins on the device. Each package has three separate voltage supply inputs--VCCINT, VCCAUX, and VCCO--and a common ground return, GND. The numbers of pins dedicated to these functions vary by package, as shown in Table 63. Table 63: Power and Ground Supply Pins by Package Package VCCINT VCCAUX VCCO GND TQG144 4 4 8 13 FTG256 6 4 16 28 FGG400 9 8 22 43 FGG484 15 10 24 53 FGG676 23 14 36 77 Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only supported in the top or bottom banks (I/O banks 0 and 2). Inputs are unrestricted. For more details, see the "Using I/O Resources" chapter in UG331. A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/Os depend on the device type and the package in which it Table 64: Maximum User I/O by Package Device Package Maximum User I/Os and Input-Only Maximum InputOnly Maximum Differential Pairs All Possible I/Os by Type I/O INPUT DUAL VREF CLK N.C. XC3S50AN TQG144 108 7 50 42 2 26 8 30 0 XC3S200AN FTG256 195 35 90 69 21 52 21 32 0 XC3S400AN FGG400 311 63 142 155 46 52 26 32 0 XC3S700AN FGG484 372 84 165 194 61 52 33 32 3 XC3S1400AN FGG676 502 94 227 313 67 52 38 32 17 Notes: 1. Some VREFs are on INPUT pins. See pinout tables for details. www.xilinx.com 72 DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Electronic versions of the package pinout tables and footprints are available for download from the Xilinx website: http://www.xilinx.com/support/documentation/data_sheets/ s3a_pin.zip Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the ASCII-text file is easily parsed by most scripting programs. Package Overview Table 65 shows the five low-cost, space-saving production package styles for the Spartan-3AN family. Table 65: Spartan-3AN Family Package Options Maximum I/O Lead Pitch (mm) Body Area (mm) Height (mm) Mass(1) (g) Thin Quad Flat Pack (TQFP) 108 0.5 20 x 20 1.60 1.4 256 Fine-pitch Thin Ball Grid Array (FBGA) 195 1.0 17 x 17 1.55 0.9 FG400/FGG400 400 Fine-pitch Ball Grid Array (FBGA) 311 1.0 21 x 21 2.43 2.2 FG484/FGG484 484 Fine-pitch Ball Grid Array (FBGA) 372 1.0 23 x 23 2.60 2.2 FG676/FGG676 676 Fine-pitch Ball Grid Array (FBGA) 502 1.0 27 x 27 2.60 3.4 Package Leads TQ144/TQG144 144 FT256/FTG256 Type Notes: 1. Package mass is 10%. Each package style is available in an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an extra `G' in the package style name. For example, the standard "CS484" package becomes "CSG484" when ordered as the Pb-free option. Leaded (Pb) packages are available for selected devices, with the same pinout and without the `G' in the ordering code; See Table 5, page 8 for more information. The mechanical dimensions of the Pb and Pb-free packages are similar, as shown in the mechanical drawings provided in Table 66. For additional package information, see UG112: Device Package User Guide. Mechanical Drawings Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in Table 66. Material Declaration Data Sheets (MDDS) are also available on the Xilinx website for each package. Table 66: Xilinx Package Documentation Package TQ144 Drawing Package Drawing TQG144 FT256 Package Drawing Package Drawing FGG676 DS557-4 (v3.2) November 19, 2009 Product Specification PK182_FG400 PK108_FGG400 Package Drawing FGG484 FG676 PK158_FT256 PK115_FTG256 FGG400 FG484 PK169_TQ144 PK126_TQG144 FTG256 FG400 MDDS PK183_FG484 PK110_FGG484 Package Drawing PK155_FG676 PK111_FGG676 www.xilinx.com 73 R Pinout Descriptions Package Thermal Characteristics The power dissipated by an FPGA application has implications on package selection and system design. The power consumed by a Spartan-3AN FPGA is reported using either the XPower Power Estimator or the XPower Analyzer calculator integrated in the Xilinx(R) ISE(R) development software. Table 67 provides the thermal characteristics for the various Spartan-3AN FPGA packages. This information is also available using the Thermal Query tool at: (http://www.xilinx.com/cgi-bin/thermal/thermal.pl). The junction-to-case thermal resistance ( JC) indicates the difference between the temperature measured on the package body (case) and the junction temperature per watt of power consumption. The junction-to-board (JB) value similarly reports the difference between the board and junction temperature. The junction-to-ambient ( JA) value reports the temperature difference between the ambient environment and the junction temperature. The JA value is reported at different air velocities, measured in linear feet per minute (LFM). The "Still Air (0 LFM)" column shows the JA value in a system without a fan. The thermal resistance drops with increasing air flow. Table 67: Spartan-3AN FPGA Package Thermal Characteristics Package Device Junction-to-Case (JC) Junction-toBoard (JB) Junction-to-Ambient (JA) at Different Air Flows Units Still Air (0 LFM) 250 LFM 500 LFM 750 LFM TQG144 XC3S50AN 13.4 32.8 38.9 32.8 32.5 31.7 C/Watt FTG256 XC3S200AN 7.4 23.3 29.0 23.8 23.0 22.3 C/Watt FGG400 XC3S400AN 6.2 12.9 22.5 16.7 15.6 15.0 C/Watt FGG484 XC3S700AN 5.3 11.5 19.4 15.0 13.9 13.4 C/Watt FGG676 XC3S1400AN 4.3 10.9 17.7 13.7 12.6 12.1 C/Watt Notes: 1. Thermal characteristics are similar for leaded (non-Pb-free) packages. www.xilinx.com 74 DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions TQG144: 144-lead Thin Quad Flat Package The XC3S50AN is available in the 144-lead thin quad flat package, TQG144. Table 68: Spartan-3AN TQG144 Pinout (Continued) Pin Type Table 68 lists all the package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. 0 IP_0/VREF_0 P123 VREF 0 VCCO_0 P119 VCCO 0 VCCO_0 P136 VCCO 1 IO_1 P79 I/O The XC3S50AN does not support the address output pins for the Byte-wide Peripheral Interface (BPI) configuration mode. 1 IO_L01N_1/LDC2 P78 DUAL 1 IO_L01P_1/HDC P76 DUAL 1 IO_L02N_1/LDC0 P77 DUAL An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at 1 IO_L02P_1/LDC1 P75 DUAL 1 IO_L03N_1 P84 I/O www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. 1 IO_L03P_1 P82 I/O 1 IO_L04N_1/RHCLK1 P85 RHCLK Pinout Table 1 IO_L04P_1/RHCLK0 P83 RHCLK Table 68: Spartan-3AN TQG144 Pinout 1 IO_L05N_1/TRDY1/RHCLK3 P88 RHCLK Bank Pin Name Bank Pin Name Pin Type 1 IO_L05P_1/RHCLK2 P87 RHCLK 0 IO_0 P142 I/O 1 IO_L06N_1/RHCLK5 P92 RHCLK 0 IO_L01N_0 P111 I/O 1 IO_L06P_1/RHCLK4 P90 RHCLK 0 IO_L01P_0 P110 I/O 1 IO_L07N_1/RHCLK7 P93 RHCLK IO_L07P_1/IRDY1/RHCLK6 P91 RHCLK 0 IO_L02N_0 P113 I/O 1 0 IO_L02P_0/VREF_0 P112 VREF 1 IO_L08N_1 P98 I/O 0 IO_L03N_0 P117 I/O 1 IO_L08P_1 P96 I/O 0 IO_L03P_0 P115 I/O 1 IO_L09N_1 P101 I/O 0 IO_L04N_0 P116 I/O 1 IO_L09P_1 P99 I/O 0 IO_L04P_0 P114 I/O 1 IO_L10N_1 P104 I/O 0 IO_L05N_0 P121 I/O 1 IO_L10P_1 P102 I/O IO_L11N_1 P105 I/O 0 IO_L05P_0 P120 I/O 1 0 IO_L06N_0/GCLK5 P126 GCLK 1 IO_L11P_1 P103 I/O 0 IO_L06P_0/GCLK4 P124 GCLK 1 IP_1/VREF_1 P80 VREF 0 IO_L07N_0/GCLK7 P127 GCLK 1 IP_1/VREF_1 P97 VREF 0 IO_L07P_0/GCLK6 P125 GCLK 1 VCCO_1 P86 VCCO 0 IO_L08N_0/GCLK9 P131 GCLK 1 VCCO_1 P95 VCCO 0 IO_L08P_0/GCLK8 P129 GCLK 2 IO_2/MOSI/CSI_B P62 DUAL 0 IO_L09N_0/GCLK11 P132 GCLK 2 IO_L01N_2/M0 P38 DUAL 0 IO_L09P_0/GCLK10 P130 GCLK 2 IO_L01P_2/M1 P37 DUAL IO_L02N_2/CSO_B P41 DUAL 0 IO_L10N_0 P135 I/O 2 0 IO_L10P_0 P134 I/O 2 IO_L02P_2/M2 P39 DUAL 0 IO_L11N_0 P139 I/O 2 IO_L03N_2/VS1 P44 DUAL 0 IO_L11P_0 P138 I/O 2 IO_L03P_2/RDWR_B P42 DUAL 0 IO_L12N_0/PUDC_B P143 DUAL 2 IO_L04N_2/VS0 P45 DUAL 0 IO_L12P_0/VREF_0 P141 VREF 2 IO_L04P_2/VS2 P43 DUAL 0 IP_0 P140 INPUT 2 IO_L05N_2/D7 P48 DUAL DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 75 R Pinout Descriptions Table 68: Spartan-3AN TQG144 Pinout (Continued) Bank Pin Name Table 68: Spartan-3AN TQG144 Pinout (Continued) Pin Type Bank Pin Type 2 IO_L05P_2 P46 I/O 3 IO_L10P_3 P27 I/O 2 IO_L06N_2/D6 P49 DUAL 3 IO_L11N_3 P30 I/O 2 IO_L06P_2 P47 I/O 3 IO_L11P_3 P28 I/O 2 IO_L07N_2/D4 P51 DUAL 3 IO_L12N_3 P32 I/O 2 IO_L07P_2/D5 P50 DUAL 3 IO_L12P_3 P31 I/O 2 IO_L08N_2/GCLK15 P55 GCLK 3 IP_L13N_3/VREF_3 P35 VREF 2 IO_L08P_2/GCLK14 P54 GCLK 3 IP_L13P_3 P33 INPUT 2 IO_L09N_2/GCLK1 P59 GCLK 3 VCCO_3 P14 VCCO 2 IO_L09P_2/GCLK0 P57 GCLK 3 VCCO_3 P23 VCCO 2 IO_L10N_2/GCLK3 P60 GCLK GND GND P9 GND 2 IO_L10P_2/GCLK2 P58 GCLK GND GND P17 GND 2 IO_L11N_2/DOUT P64 DUAL GND GND P26 GND 2 IO_L11P_2/AWAKE P63 PWR MGMT GND GND P34 GND GND GND P56 GND GND GND P65 GND GND GND P81 GND GND GND P89 GND GND GND P100 GND GND GND P106 GND GND GND P118 GND GND GND P128 GND GND GND P137 GND 2 IO_L12N_2/D3 P68 DUAL 2 IO_L12P_2/INIT_B P67 DUAL 2 IO_L13N_2/D0/DIN/MISO P71 DUAL 2 IO_L13P_2/D2 P69 DUAL 2 IO_L14N_2/CCLK P72 DUAL 2 IO_L14P_2/D1 P70 DUAL 2 IP_2/VREF_2 P53 VREF 2 VCCO_2 P40 VCCO 2 VCCO_2 P61 VCCO 3 IO_L01N_3 P6 I/O VCCAUX SUSPEND P74 PWR MGMT 3 IO_L01P_3 P4 I/O VCCAUX DONE P73 CONFIG 3 IO_L02N_3 P5 I/O VCCAUX PROG_B P144 CONFIG 3 IO_L02P_3 P3 I/O VCCAUX TCK P109 JTAG 3 IO_L03N_3 P8 I/O VCCAUX TDI P2 JTAG 3 IO_L03P_3 P7 I/O VCCAUX TDO P107 JTAG 3 IO_L04N_3/VREF_3 P11 VREF VCCAUX TMS P1 JTAG 3 IO_L04P_3 P10 I/O VCCAUX VCCAUX P36 VCCAUX 3 IO_L05N_3/LHCLK1 P13 LHCLK VCCAUX VCCAUX P66 VCCAUX 3 IO_L05P_3/LHCLK0 P12 LHCLK VCCAUX VCCAUX P108 VCCAUX 3 IO_L06N_3/IRDY2/LHCLK3 P16 LHCLK VCCAUX VCCAUX P133 VCCAUX 3 IO_L06P_3/LHCLK2 P15 LHCLK VCCINT VCCINT P22 VCCINT 3 IO_L07N_3/LHCLK5 P20 LHCLK VCCINT VCCINT P52 VCCINT 3 IO_L07P_3/LHCLK4 P18 LHCLK VCCINT VCCINT P94 VCCINT 3 IO_L08N_3/LHCLK7 P21 LHCLK VCCINT VCCINT P122 VCCINT 3 IO_L08P_3/TRDY2/LHCLK6 P19 LHCLK 3 IO_L09N_3 P25 I/O 3 IO_L09P_3 P24 I/O 3 IO_L10N_3 P29 I/O www.xilinx.com 76 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions User I/Os by Bank Table 69 indicates how the 108 available user-I/O pins are distributed between the four I/O banks on the TQG144 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 69: User I/Os Per Bank for the XC3S50AN in the TQG144 Package Package Edge I/O Bank Maximum I/O Top 0 Right 1 Bottom 2 Left 3 TOTAL All Possible I/O Pins by Type I/O INPUT DUAL VREF CLK 27 14 1 1 3 8 25 11 0 4 2 8 30 2 0 21 1 6 26 15 1 0 2 8 108 42 2 26 8 30 Footprint Migration Differences The XC3S50AN FPGA is the only Spartan-3AN device offered in the TQG144 package. The XC3S50AN FPGA is pin compatible with the Spartan-3A XC3S50A FPGA in the TQ(G)144 package, although the Spartan-3A FPGA requires an external configuration source. DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 77 R Pinout Descriptions TQG144 Footprint Note pin 1 indicator in top-left corner and logo orientation. 116 IO_L04N_0 115 IO_L03P_0 114 IO_L04P_0 113 IO_L02N_0 112 IO_L02P_0/VREF_0 111 IO_L01N_0 110 IO_L01P_0 109 TCK 134 IO_L10P_0 133 VCCAUX 132 IO_L09N_0/GCLK11 131 IO_L08N_0/GCLK9 130 IO_L09P_0/GCLK10 129 IO_L08P_0/GCLK8 128 GND 127 IO_L07N_0/GCLK7 126 IO_L06N_0/GCLK5 125 IO_L07P_0/GCLK6 124 IO_L06P_0/GCLK4 123 IP_0/VREF_0 122 VCCINT 121 IO_L05N_0 120 IO_L05P_0 119 VCCO_0 118 GND 117 IO_L03N_0 X Bank 1 IP_L13N_3/VREF_3 35 VCCAUX 36 GND IO_L11N_1 IO_L10N_1 IO_L11P_1 IO_L10P_1 IO_L09N_1 GND IO_L09P_1 IO_L08N_1 IP_1/VREF_1 IO_L08P_1 VCCO_1 VCCINT IO_L07N_1/RHCLK7 IO_L06N_1/RHCLK5 IO_L07P_1/RHCLK6 IO_L06P_1/RHCLK4 GND IO_L05N_1/RHCLK3 IO_L05P_1/RHCLK2 VCCO_1 IO_L04N_1/RHCLK1 IO_L03N_1 IO_L04P_1/RHCLK0 IO_L03P_1 GND IP_1/VREF_1 IO_1 IO_L01N_1/LDC2 IO_L02N_1/LDC0 IO_L01P_1/HDC IO_L02P_1/LDC1 IO_L14N_2/CCLK IO_L13P_2/D2 IO_L14P_2/D1 IO_L13N_2/D0/DIN/MISO 65 66 67 68 69 70 71 72 GND VCCAUX IO_L12P_2/INIT_B IO_L12N_2/D3 46 47 48 49 50 51 52 53 IO_L05P_2 IO_L06P_2 IO_L05N_2/D7 IO_L06N_2/D6 IO_L07P_2/D5 IO_L07N_2/D4 VCCINT IP_2/VREF_2 IO_L08P_2/GCLK14 IO_L08N_2/GCLK15 GND IO_L09P_2/GCLK0 IO_L10P_2/GCLK2 IO_L03P_2/RDWR_B 42 IO_L04P_2/VS2 43 IO_L03N_2/VS1 44 IO_L04N_2/VS0 45 IO_L01P_2/M1 37 IO_L01N_2/M0 38 IO_L02P_2/M2 39 VCCO_2 40 IO_L02N_2/CSO_B 41 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 SUSPEND 73 DONE Bank 2 IO_L11P_2/AWAKE IO_L11N_2/DOUT 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 IO_L09N_2/GCLK1 IO_L10N_2/GCLK3 VCCO_2 IO_2/MOSI/CSI_B IO_L02P_3 IO_L01P_3 IO_L02N_3 IO_L01N_3 IO_L03P_3 IO_L03N_3 GND IO_L04P_3 IO_L04N_3/VREF_3 IO_L05P_3/LHCLK0 IO_L05N_3/LHCLK1 VCCO_3 IO_L06P_3/LHCLK2 IO_L06N_3/LHCLK3 GND IO_L07P_3/LHCLK4 IO_L08P_3/LHCLK6 IO_L07N_3/LHCLK5 IO_L08N_3/LHCLK7 VCCINT VCCO_3 IO_L09P_3 IO_L09N_3 GND IO_L10P_3 IO_L11P_3 IO_L10N_3 IO_L11N_3 IO_L12P_3 IO_L12N_3 IP_L13P_3 GND 108 VCCAUX 107 TDO Bank 0 54 55 56 57 58 59 60 61 62 63 64 1 2 Bank 3 TMS TDI 139 IO_L11N_0 138 IO_L11P_0 137 GND 136 VCCO_0 135 IO_L10N_0 144 PROG_B 143 IO_L12N_0/PUDC_B 142 IO_0 141 IO_L12P_0/VREF_0 140 IP_0 X-Ref Target - Figure 19 DS529-4_10_031207 Figure 19: XC3S50AN FPGA in TQG144 Package Footprint (top view) I/O: Unrestricted, general-purpose user I/O 25 DUAL: Configuration pins, then possible user I/O 8 VREF: User I/O or input voltage reference for bank 2 INPUT: Unrestricted, general-purpose input pin 30 CLK: User I/O, input, or global buffer input 8 VCCO: Output voltage supply for bank 2 CONFIG: Dedicated configuration pins JTAG: Dedicated JTAG port pins 4 VCCINT: Internal core supply voltage (+1.2V) 0 N.C.: Not connected GND: Ground 4 VCCAUX: Auxiliary supply voltage 2 SUSPEND: Dedicated SUSPEND and dual-purpose AWAKE Power Management pins 42 4 13 www.xilinx.com 78 DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions FTG256: 256-ball Fine-pitch, Thin Ball Grid Array The 256-ball fine-pitch, thin ball grid array package, FTG256, supports the XC3S200AN FPGAs. Table 70: Spartan-3AN FTG256 Pinout (Continued) Table 70 lists all the package pins. They are sorted by bank number and then by pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. Bank Pin Name FT256 Ball Type 0 IO_L15P_0 A6 I/O 0 IO_L16N_0 C6 I/O 0 IO_L16P_0 D7 I/O 0 IO_L17N_0 C5 I/O Figure 20 shows the footprint for the XC3S200AN. 0 IO_L17P_0 A5 I/O An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at 0 IO_L18N_0 B4 I/O 0 IO_L18P_0 A4 I/O 0 IO_L19N_0 B3 I/O 0 IO_L19P_0 A3 I/O Pinout Table 0 IO_L20N_0/PUDC_B D5 DUAL 0 IO_L20P_0/VREF_0 C4 VREF Table 70: Spartan-3AN FTG256 Pinout 0 IP_0 D6 INPUT 0 IP_0 D12 INPUT 0 IP_0 E6 INPUT 0 IP_0 F7 INPUT 0 IP_0 F9 INPUT 0 IP_0 F10 INPUT 0 IP_0/VREF_0 E9 VREF 0 VCCO_0 B5 VCCO 0 VCCO_0 B9 VCCO 0 VCCO_0 B13 VCCO 0 VCCO_0 E8 VCCO 1 IO_L01N_1/LDC2 N14 DUAL 1 IO_L01P_1/HDC N13 DUAL 1 IO_L02N_1/LDC0 P15 DUAL 1 IO_L02P_1/LDC1 R15 DUAL 1 IO_L03N_1/A1 N16 DUAL 1 IO_L03P_1/A0 P16 DUAL 1 IO_L05N_1/VREF_1 M14 VREF 1 IO_L05P_1 M13 I/O 1 IO_L06N_1/A3 K13 DUAL www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. Bank Pin Name FT256 Ball Type 0 IO_L01N_0 C13 I/O 0 IO_L01P_0 D13 I/O 0 IO_L02N_0 B14 I/O 0 IO_L02P_0/VREF_0 B15 VREF 0 IO_L03N_0 D11 I/O 0 IO_L03P_0 C12 I/O 0 IO_L04N_0 A13 I/O 0 IO_L04P_0 A14 I/O 0 IO_L05N_0 A12 I/O 0 IO_L05P_0 B12 I/O 0 IO_L06N_0/VREF_0 E10 VREF 0 IO_L06P_0 D10 I/O 0 IO_L07N_0 A11 I/O 0 IO_L07P_0 C11 I/O 0 IO_L08N_0 A10 I/O 0 IO_L08P_0 B10 I/O 0 IO_L09N_0/GCLK5 D9 GCLK 0 IO_L09P_0/GCLK4 C10 GCLK 0 IO_L10N_0/GCLK7 A9 GCLK 0 IO_L10P_0/GCLK6 C9 GCLK 0 IO_L11N_0/GCLK9 D8 GCLK 0 IO_L11P_0/GCLK8 C8 GCLK 0 IO_L12N_0/GCLK11 B8 GCLK 0 IO_L12P_0/GCLK10 A8 GCLK 0 IO_L13N_0 C7 I/O 0 IO_L13P_0 A7 I/O 0 IO_L14N_0/VREF_0 E7 VREF 0 IO_L14P_0 F8 I/O 0 IO_L15N_0 B6 I/O DS557-4 (v3.2) November 19, 2009 Product Specification 1 IO_L06P_1/A2 L13 DUAL 1 IO_L07N_1/A5 M16 DUAL 1 IO_L07P_1/A4 M15 DUAL 1 IO_L08N_1/A7 L16 DUAL 1 IO_L08P_1/A6 L14 DUAL 1 IO_L10N_1/A9 J13 DUAL 1 IO_L10P_1/A8 J12 DUAL 1 IO_L11N_1/RHCLK1 K14 RHCLK 1 IO_L11P_1/RHCLK0 K15 RHCLK 1 IO_L12N_1/TRDY1/RHCLK3 J16 RHCLK 1 IO_L12P_1/RHCLK2 K16 RHCLK 1 IO_L14N_1/RHCLK5 H14 RHCLK www.xilinx.com 79 R Pinout Descriptions Table 70: Spartan-3AN FTG256 Pinout (Continued) Bank Pin Name Table 70: Spartan-3AN FTG256 Pinout (Continued) FT256 Ball Type Bank FT256 Ball Type 1 IO_L14P_1/RHCLK4 J14 RHCLK 2 IO_L06P_2/D7 T5 DUAL 1 IO_L15N_1/RHCLK7 H16 RHCLK 2 IO_L07N_2 P6 I/O 1 IO_L15P_1/IRDY1/RHCLK6 H15 RHCLK 2 IO_L07P_2 N7 I/O 1 IO_L16N_1/A11 F16 DUAL 2 IO_L08N_2/D4 N8 DUAL 1 IO_L16P_1/A10 G16 DUAL 2 IO_L08P_2/D5 P7 DUAL 1 IO_L17N_1/A13 G14 DUAL 2 IO_L09N_2/GCLK13 T7 GCLK 1 IO_L17P_1/A12 H13 DUAL 2 IO_L09P_2/GCLK12 R7 GCLK 1 IO_L18N_1/A15 F15 DUAL 2 IO_L10N_2/GCLK15 T8 GCLK 1 IO_L18P_1/A14 E16 DUAL 2 IO_L10P_2/GCLK14 P8 GCLK 1 IO_L19N_1/A17 F14 DUAL 2 IO_L11N_2/GCLK1 P9 GCLK 1 IO_L19P_1/A16 G13 DUAL 2 IO_L11P_2/GCLK0 N9 GCLK 1 IO_L20N_1/A19 F13 DUAL 2 IO_L12N_2/GCLK3 T9 GCLK 1 IO_L20P_1/A18 E14 DUAL 2 IO_L12P_2/GCLK2 R9 GCLK 1 IO_L22N_1/A21 D15 DUAL 2 IO_L13N_2 M10 I/O 1 IO_L22P_1/A20 D16 DUAL 2 IO_L13P_2 N10 I/O 1 IO_L23N_1/A23 D14 DUAL 2 IO_L14N_2/MOSI/CSI_B P10 DUAL 1 IO_L23P_1/A22 E13 DUAL 2 IO_L14P_2 T10 I/O 1 IO_L24N_1/A25 C15 DUAL 2 IO_L15N_2/DOUT R11 DUAL 1 IO_L24P_1/A24 C16 DUAL 2 T11 1 IP_L04N_1/VREF_1 K12 VREF IO_L15P_2/ AWAKE PWR MGMT 1 IP_L04P_1 K11 INPUT 2 IO_L16N_2 N11 I/O 1 IP_L09N_1 J11 INPUT 2 IO_L16P_2 P11 I/O 2 IO_L17N_2/D3 P12 DUAL 2 IO_L17P_2/INIT_B T12 DUAL 2 IO_L18N_2/D1 R13 DUAL 2 IO_L18P_2/D2 T13 DUAL 2 IO_L19N_2 P13 I/O 2 IO_L19P_2 N12 I/O 2 IO_L20N_2/CCLK R14 DUAL 2 IO_L20P_2/D0/DIN/MISO T14 DUAL 2 IP_2 L7 INPUT 2 IP_2 L8 INPUT 2 IP_2/VREF_2 L9 VREF 2 IP_2/VREF_2 L10 VREF 2 IP_2/VREF_2 M7 VREF 2 IP_2/VREF_2 M8 VREF 2 IP_2/VREF_2 M11 VREF 1 IP_L09P_1/VREF_1 J10 VREF 1 IP_L13N_1 H11 INPUT 1 IP_L13P_1 H10 INPUT 1 IP_L21N_1 G11 INPUT 1 IP_L21P_1/VREF_1 G12 VREF 1 IP_L25N_1 F11 INPUT 1 IP_L25P_1/VREF_1 F12 VREF 1 VCCO_1 E15 VCCO 1 VCCO_1 H12 VCCO 1 VCCO_1 J15 VCCO 1 VCCO_1 2 2 N15 VCCO IO_L01N_2/M0 P4 DUAL IO_L01P_2/M1 N4 DUAL 2 IO_L02N_2/CSO_B T2 DUAL 2 IO_L02P_2/M2 R2 DUAL 2 IO_L03N_2/VS2 T3 DUAL 2 IO_L03P_2/RDWR_B R3 DUAL 2 IO_L04N_2/VS0 P5 DUAL 2 IO_L04P_2/VS1 N6 DUAL 2 IO_L05N_2 R5 I/O 2 IO_L05P_2 T4 I/O 2 IO_L06N_2/D6 T6 DUAL 2 IP_2/VREF_2 N5 VREF 2 VCCO_2 M9 VCCO 2 VCCO_2 R4 VCCO 2 VCCO_2 R8 VCCO 2 VCCO_2 R12 VCCO 3 IO_L01N_3 C1 I/O 3 IO_L01P_3 C2 I/O www.xilinx.com 80 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 70: Spartan-3AN FTG256 Pinout (Continued) Bank Pin Name FT256 Ball Table 70: Spartan-3AN FTG256 Pinout (Continued) Type Bank Pin Name FT256 Ball Type 3 IO_L02N_3 D3 I/O 3 IP_L21N_3 K6 INPUT 3 IO_L02P_3 D4 I/O 3 IP_L21P_3 K5 INPUT 3 IO_L03N_3 E1 I/O 3 IP_L25N_3/VREF_3 L6 VREF 3 IO_L03P_3 D1 I/O 3 IP_L25P_3 L5 INPUT 3 IO_L05N_3 E2 I/O 3 VCCO_3 D2 VCCO 3 IO_L05P_3 E3 I/O 3 VCCO_3 H2 VCCO 3 IO_L07N_3 G4 I/O 3 VCCO_3 J5 VCCO 3 IO_L07P_3 F3 I/O 3 VCCO_3 M2 VCCO 3 IO_L08N_3/VREF_3 G1 VREF GND GND A1 GND 3 IO_L08P_3 F1 I/O GND GND A16 GND 3 IO_L09N_3 H4 I/O GND GND B7 GND 3 IO_L09P_3 G3 I/O GND GND B11 GND 3 IO_L10N_3 H5 I/O GND GND C3 GND 3 IO_L10P_3 H6 I/O GND GND C14 GND 3 IO_L11N_3/LHCLK1 H1 LHCLK GND GND E5 GND 3 IO_L11P_3/LHCLK0 G2 LHCLK GND GND E12 GND 3 IO_L12N_3/IRDY2/LHCLK3 J3 LHCLK GND GND F2 GND 3 IO_L12P_3/LHCLK2 H3 LHCLK GND GND F6 GND 3 IO_L14N_3/LHCLK5 J1 LHCLK GND GND G8 GND 3 IO_L14P_3/LHCLK4 J2 LHCLK GND GND G10 GND 3 IO_L15N_3/LHCLK7 K1 LHCLK GND GND G15 GND 3 IO_L15P_3/TRDY2/LHCLK6 K3 LHCLK GND GND H9 GND 3 IO_L16N_3 L2 I/O GND GND J8 GND 3 IO_L16P_3/VREF_3 L1 VREF GND GND K2 GND 3 IO_L17N_3 J6 I/O GND GND K7 GND 3 IO_L17P_3 J4 I/O GND GND K9 GND 3 IO_L18N_3 L3 I/O GND GND L11 GND 3 IO_L18P_3 K4 I/O GND GND L15 GND 3 IO_L19N_3 L4 I/O GND GND M5 GND 3 IO_L19P_3 M3 I/O GND GND M12 GND 3 IO_L20N_3 N1 I/O GND GND P3 GND 3 IO_L20P_3 M1 I/O GND GND P14 GND 3 IO_L22N_3 P1 I/O GND GND R6 GND 3 IO_L22P_3 N2 I/O GND GND R10 GND 3 IO_L23N_3 P2 I/O GND GND T1 GND 3 IO_L23P_3 R1 I/O GND GND T16 GND 3 IO_L24N_3 M4 I/O VCCAUX SUSPEND R16 3 IO_L24P_3 N3 I/O PWR MGMT 3 IP_L04N_3/VREF_3 F4 VREF VCCAUX DONE T15 CONFIG 3 IP_L04P_3 E4 INPUT VCCAUX PROG_B A2 CONFIG 3 IP_L06N_3/VREF_3 G5 VREF VCCAUX TCK A15 JTAG VCCAUX TDI B1 JTAG VCCAUX TDO B16 JTAG VCCAUX TMS B2 JTAG 3 IP_L06P_3 G6 INPUT 3 IP_L13N_3 J7 INPUT 3 IP_L13P_3 DS557-4 (v3.2) November 19, 2009 Product Specification H7 INPUT www.xilinx.com 81 R Pinout Descriptions Table 70: Spartan-3AN FTG256 Pinout (Continued) FT256 Ball Type VCCAUX VCCAUX E11 VCCAUX VCCAUX VCCAUX F5 VCCAUX VCCAUX VCCAUX L12 VCCAUX VCCAUX VCCAUX M6 VCCAUX VCCINT VCCINT G7 VCCINT VCCINT VCCINT G9 VCCINT VCCINT VCCINT H8 VCCINT VCCINT VCCINT J9 VCCINT VCCINT VCCINT K8 VCCINT VCCINT VCCINT K10 VCCINT Bank Pin Name User I/Os by Bank Table 71 indicates how the available user-I/O pins are distributed between the four I/O banks on the FTG256 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 71: User I/Os Per Bank on XC3S200AN in the FTG256 Package Package Edge I/O Bank Maximum I/O Top 0 Right All Possible I/O Pins by Type I/O INPUT DUAL VREF CLK 47 27 6 1 5 8 1 50 1 6 30 5 8 Bottom 2 48 11 2 21 6 8 Left 3 50 30 7 0 5 8 195 69 21 52 21 32 TOTAL Footprint Migration Differences The XC3S200AN FPGA is the only Spartan-3AN device offered in the FTG256 package. The XC3S200AN FPGA is pin compatible with the Spartan-3A XC3S200A FPGA in the FT(G)256 package, although the Spartan-3A FPGA requires an external configuration source. www.xilinx.com 82 DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions FTG256 Footprint (XC3S200AN) X-Ref Target - Figure 20 E F I/O I/O L01N_3 L01P_3 I/O L03P_3 I/O I/O I/O I/O L18P_0 L17P_0 L15P_0 L13P_0 VCCO_3 I/O I/O L18N_0 GND L20P_0 VREF_0 I/O I/O I/O L02N_3 L02P_3 I/O I/O I/O INPUT L03N_3 L05N_3 L05P_3 L04P_3 I/O L08P_3 GND I/O I/O G L08N_3 VREF_3 L11P_3 LHCLK0 H L11N_3 LHCLK1 I/O I/O J L14N_3 LHCLK5 L14P_3 LHCLK4 L15N_3 LHCLK7 L L16P_3 VREF_3 Bank 3 I/O M N P R T I/O L20P_3 I/O L13N_0 INPUT GND INPUT L14N_0 VREF_0 VCCAUX GND INPUT L16P_0 L10N_0 GCLK7 INPUT L06N_3 VREF_3 INPUT I/O I/O I/O INPUT L09N_3 L10N_3 L10P_3 L13P_3 I/O INPUT L17N_3 L13N_3 L06P_3 I/O L17P_3 VCCO_3 I/O I/O I/O L05N_0 L04N_0 L04P_0 I/O L08P_0 I/O L09P_0 GCLK4 I/O L09N_0 GCLK5 VCCO_0 INPUT I/O L01N_0 VCCINT GND VCCINT GND VCCAUX INPUT L25N_1 INPUT L21N_1 INPUT INPUT L13P_1 L13N_1 INPUT VCCINT L09P_1 INPUT VREF_1 L09N_1 I/O GND L15P_3 TRDY2 LHCLK6 I/O INPUT INPUT L18P_3 L21P_3 L21N_3 I/O I/O INPUT L18N_3 L19N_3 L25P_3 L25N_3 VREF_3 GND VCCAUX I/O I/O L19P_3 L24N_3 I/O I/O I/O L24P_3 I/O I/O L22N_3 L23N_3 INPUT VREF_2 I/O I/O L01N_2 M0 L04N_2 VS0 L03P_2 VCCO_2 RDWR_B L05N_2 GND I/O L02P_2 M2 L01P_2 M1 I/O I/O I/O L02N_2 CSO_B L03N_2 VS2 I/O L05P_2 I/O VCCINT INPUT INPUT INPUT I/O L16N_3 VCCO_3 GND I/O L04P_2 VS1 I/O L07N_2 INPUT INPUT VREF_2 VREF_2 I/O L07P_2 GND INPUT INPUT VREF_2 I/O I/O L08N_2 D4 L11P_2 GCLK0 I/O I/O I/O L08P_2 D5 L10P_2 GCLK14 L11N_2 GCLK1 VCCO_2 L12P_2 GCLK2 I/O GND VCCINT VREF_2 VCCO_2 I/O I/O I/O I/O I/O L06P_2 D7 L06N_2 D6 L09N_2 GCLK13 L10N_2 GCLK15 L12N_2 GCLK3 GND I/O L02P_0 VREF_0 TDO I/O I/O L24N_1 A25 L24P_1 A24 I/O I/O I/O L23N_1 A23 L22N_1 A21 L22P_1 A20 VCCO_1 L18P_1 A14 I/O I/O L23P_1 A22 L20P_1 A18 I/O INPUT I/O I/O I/O I/O L25P_1 VREF_1 L20N_1 A19 L19N_1 A17 L18N_1 A15 L16N_1 A11 GND L16P_1 A10 INPUT I/O I/O L21P_1 VREF_1 L19P_1 A16 L17N_1 A13 I/O I/O VCCO_1 L17P_1 A12 L14N_1 RHCLK5 I/O I/O I/O L10P_1 A8 L10N_1 A9 L14P_1 RHCLK4 I/O I/O L15P_1 IRDY1 RHCLK6 I/O L15N_1 RHCLK7 I/O VCCO_1 L12N_1 TRDY1 RHCLK3 I/O I/O I/O I/O L11N_1 RHCLK1 L11P_1 RHCLK0 L12P_1 RHCLK2 I/O I/O GND VCCAUX L06P_1 A2 L08P_1 A6 GND L08N_1 A7 GND I/O I/O I/O L13P_2 L16N_2 L19P_2 I/O I/O L16P_2 I/O L17N_2 D3 I/O I/O GND L06N_1 A3 INPUT L14P_2 TCK INPUT VREF_2 GND GND 16 L04N_1 VREF_1 I/O L14N_2 MOSI CSI_B I/O L01P_0 I/O L02N_0 15 L04P_1 INPUT L13N_2 I/O L09P_2 GCLK12 INPUT I/O GND GND I/O L03P_0 I/O INPUT VCCO_0 I/O L03N_0 INPUT VCCINT I/O L05P_0 L07P_0 I/O L06N_0 VREF_0 I/O GND L06P_0 VREF_0 L14P_0 14 I/O I/O I/O 13 L07N_0 L10P_0 GCLK6 L11N_0 GCLK9 12 I/O I/O I/O L12N_3 IRDY2 LHCLK3 VCCO_0 11 L08N_0 L11P_0 GCLK8 I/O I/O L12P_3 LHCLK2 L12P_0 GCLK10 L12N_0 GCLK11 I/O L20N_0 PUDC_B L07N_3 L22P_3 GND I/O L16N_0 I/O I/O I/O I/O L17N_0 I/O I/O I/O GND L09P_3 L20N_3 L23P_3 L04N_3 VREF_3 I/O I/O K I/O L15N_0 INPUT I/O L07P_3 I/O VCCO_3 VCCO_0 10 I/O L15N_2 DOUT VCCO_2 I/O L05P_1 I/O I/O I/O I/O L05N_1 VREF_1 L07P_1 A4 L07N_1 A5 L03N_1 A1 I/O I/O L01P_1 HDC L01N_1 LDC2 VCCO_1 I/O I/O GND L02N_1 LDC0 L03P_1 A0 I/O L19N_2 I/O I/O I/O I/O L18N_2 D1 L20N_2 CCLK L02P_1 LDC1 I/O I/O I/O L15P_2 AWAKE L17P_2 INIT_B L18P_2 D2 Bank 1 D I/O L19N_0 Bank 0 8 9 7 D C TMS 6 EN TDI 5 L19P_0 G B O GND PR A 4 SP 3 SU 2 _B 1 I/O L20P_2 D0 DIN/MISO Bank 2 DONE GND DS529-4_06_101106 Figure 20: XC3S200AN FPGA in FTG256 Package Footprint (top view) 69 I/O: Unrestricted, general-purpose user I/O 51 DUAL: Configuration pins, then possible user I/O 21 VREF: User I/O or input voltage reference for bank 21 INPUT: Unrestricted, general-purpose input pin 32 CLK: User I/O, input, or global buffer input 16 VCCO: Output voltage supply for bank JTAG: Dedicated JTAG port pins 6 VCCINT: Internal core supply voltage (+1.2V) GND: Ground 4 VCCAUX: Auxiliary supply voltage 2 CONFIG: Dedicated configuration pins 4 0 N.C.: Not connected 28 DS557-4 (v3.2) November 19, 2009 Product Specification 2 SUSPEND: Dedicated SUSPEND and dual-purpose AWAKE Power Management pins www.xilinx.com 83 R Pinout Descriptions FGG400: 400-ball Fine-pitch Ball Grid Array The 400-ball fine-pitch ball grid array, FGG400, supports the XC3S400AN FPGA as shown in Table 72 and Figure 21. Table 72 lists all the FGG400 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. Pinout Table Table 72: Spartan-3AN FGG400 Pinout Bank Pin Name Table 72: Spartan-3AN FGG400 Pinout (Continued) Bank FG400 Ball Type 0 IO_L14P_0 B11 I/O 0 IO_L15N_0/GCLK5 E11 GCLK 0 IO_L15P_0/GCLK4 D11 GCLK 0 IO_L16N_0/GCLK7 C10 GCLK 0 IO_L16P_0/GCLK6 A10 GCLK 0 IO_L17N_0/GCLK9 E10 GCLK 0 IO_L17P_0/GCLK8 D10 GCLK 0 IO_L18N_0/GCLK11 A8 GCLK 0 IO_L18P_0/GCLK10 A9 GCLK 0 IO_L19N_0 C9 I/O FG400 Ball Type 0 IO_L19P_0 B9 I/O 0 IO_L01N_0 A18 I/O 0 IO_L20N_0 C8 I/O 0 IO_L01P_0 B18 I/O 0 IO_L20P_0 B8 I/O 0 IO_L02N_0 C17 I/O 0 IO_L21N_0 D8 I/O 0 IO_L02P_0/VREF_0 D17 VREF 0 IO_L21P_0 C7 I/O 0 IO_L03N_0 E15 I/O 0 IO_L22N_0/VREF_0 F9 VREF 0 IO_L03P_0 D16 I/O 0 IO_L22P_0 E9 I/O 0 IO_L04N_0 A17 I/O 0 IO_L23N_0 F8 I/O 0 IO_L04P_0/VREF_0 B17 VREF 0 IO_L23P_0 E8 I/O 0 IO_L05N_0 A16 I/O 0 IO_L24N_0 A7 I/O 0 IO_L05P_0 C16 I/O 0 IO_L24P_0 B7 I/O 0 IO_L06N_0 C15 I/O 0 IO_L25N_0 C6 I/O 0 IO_L06P_0 D15 I/O 0 IO_L25P_0 A6 I/O 0 IO_L07N_0 A14 I/O 0 IO_L26N_0 B5 I/O 0 IO_L07P_0 C14 I/O 0 IO_L26P_0 A5 I/O 0 IO_L08N_0 A15 I/O 0 IO_L27N_0 F7 I/O 0 IO_L08P_0 B15 I/O 0 IO_L27P_0 E7 I/O 0 IO_L09N_0 F13 I/O 0 IO_L28N_0 D6 I/O 0 IO_L09P_0 E13 I/O 0 IO_L28P_0 C5 I/O 0 IO_L10N_0/VREF_0 C13 VREF 0 IO_L29N_0 C4 I/O 0 IO_L10P_0 D14 I/O 0 IO_L29P_0 A4 I/O 0 IO_L11N_0 C12 I/O 0 IO_L30N_0 B3 I/O 0 IO_L11P_0 B13 I/O 0 IO_L30P_0 A3 I/O 0 IO_L12N_0 F12 I/O 0 IO_L31N_0 F6 I/O 0 IO_L12P_0 D12 I/O 0 IO_L31P_0 E6 I/O 0 IO_L13N_0 A12 I/O 0 IO_L32N_0/PUDC_B B2 DUAL 0 IO_L13P_0 B12 I/O 0 IO_L32P_0/VREF_0 A2 VREF 0 IO_L14N_0 C11 I/O 0 IP_0 E14 INPUT www.xilinx.com 84 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 72: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name Table 72: Spartan-3AN FGG400 Pinout (Continued) FG400 Ball Type Bank Pin Name FG400 Ball Type 0 IP_0 F11 INPUT 1 IO_L14N_1/A7 M18 DUAL 0 IP_0 F14 INPUT 1 IO_L14P_1/A6 M17 DUAL 0 IP_0 G8 INPUT 1 IO_L16N_1/A9 L16 DUAL 0 IP_0 G9 INPUT 1 IO_L16P_1/A8 L15 DUAL 0 IP_0 G10 INPUT 1 IO_L17N_1/RHCLK1 M20 RHCLK 0 IP_0 G12 INPUT 1 IO_L17P_1/RHCLK0 M19 RHCLK 0 IP_0 G13 INPUT 1 IO_L18N_1/TRDY1/RHCLK3 L18 RHCLK 0 IP_0 H9 INPUT 1 IO_L18P_1/RHCLK2 L19 RHCLK 0 IP_0 H10 INPUT 1 IO_L20N_1/RHCLK5 L17 RHCLK 0 IP_0 H11 INPUT 1 IO_L20P_1/RHCLK4 K18 RHCLK 0 IP_0 H12 INPUT 1 IO_L21N_1/RHCLK7 J20 RHCLK 0 IP_0/VREF_0 G11 VREF 1 IO_L21P_1/IRDY1/RHCLK6 K20 RHCLK 0 VCCO_0 B4 VCCO 1 IO_L22N_1/A11 J18 DUAL 0 VCCO_0 B10 VCCO 1 IO_L22P_1/A10 J19 DUAL 0 VCCO_0 B16 VCCO 1 IO_L24N_1 K16 I/O 0 VCCO_0 D7 VCCO 1 IO_L24P_1 J17 I/O 0 VCCO_0 D13 VCCO 1 IO_L25N_1/A13 H18 DUAL 0 VCCO_0 F10 VCCO 1 IO_L25P_1/A12 H19 DUAL 1 IO_L01N_1/LDC2 V20 DUAL 1 IO_L26N_1/A15 G20 DUAL 1 IO_L01P_1/HDC W20 DUAL 1 IO_L26P_1/A14 H20 DUAL 1 IO_L02N_1/LDC0 U18 DUAL 1 IO_L28N_1 H17 I/O 1 IO_L02P_1/LDC1 V19 DUAL 1 IO_L28P_1 G18 I/O 1 IO_L03N_1/A1 R16 DUAL 1 IO_L29N_1/A17 F19 DUAL 1 IO_L03P_1/A0 T17 DUAL 1 IO_L29P_1/A16 F20 DUAL 1 IO_L05N_1 T20 I/O 1 IO_L30N_1/A19 F18 DUAL 1 IO_L05P_1 T18 I/O 1 IO_L30P_1/A18 G17 DUAL 1 IO_L06N_1 U20 I/O 1 IO_L32N_1 E19 I/O 1 IO_L06P_1 U19 I/O 1 IO_L32P_1 E20 I/O 1 IO_L07N_1 P17 I/O 1 IO_L33N_1 F17 I/O 1 IO_L07P_1 P16 I/O 1 IO_L33P_1 E18 I/O 1 IO_L08N_1 R17 I/O 1 IO_L34N_1 D18 I/O 1 IO_L08P_1 R18 I/O 1 IO_L34P_1 D20 I/O 1 IO_L09N_1 R20 I/O 1 IO_L36N_1/A21 F16 DUAL 1 IO_L09P_1 R19 I/O 1 IO_L36P_1/A20 G16 DUAL 1 IO_L10N_1/VREF_1 P20 VREF 1 IO_L37N_1/A23 C19 DUAL 1 IO_L10P_1 P18 I/O 1 IO_L37P_1/A22 C20 DUAL 1 IO_L12N_1/A3 N17 DUAL 1 IO_L38N_1/A25 B19 DUAL 1 IO_L12P_1/A2 N15 DUAL 1 IO_L38P_1/A24 B20 DUAL 1 IO_L13N_1/A5 N19 DUAL 1 IP_1/VREF_1 N14 VREF 1 IO_L13P_1/A4 N18 DUAL 1 IP_L04N_1/VREF_1 P15 VREF DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 85 R Pinout Descriptions Table 72: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name Table 72: Spartan-3AN FGG400 Pinout (Continued) FG400 Ball Type Bank FG400 Ball Type 1 IP_L04P_1 P14 INPUT 2 IO_L10N_2 Y7 I/O 1 IP_L11N_1/VREF_1 M15 VREF 2 IO_L10P_2 Y6 I/O 1 IP_L11P_1 M16 INPUT 2 IO_L11N_2 U9 I/O 1 IP_L15N_1 M13 INPUT 2 IO_L11P_2 T9 I/O 1 IP_L15P_1/VREF_1 M14 VREF 2 IO_L12N_2/D6 W8 DUAL 1 IP_L19N_1 L13 INPUT 2 IO_L12P_2/D7 V7 DUAL 1 IP_L19P_1 L14 INPUT 2 IO_L13N_2 V9 I/O 1 IP_L23N_1 K14 INPUT 2 IO_L13P_2 V8 I/O 1 IP_L23P_1/VREF_1 K15 VREF 2 IO_L14N_2/D4 T10 DUAL 1 IP_L27N_1 J15 INPUT 2 IO_L14P_2/D5 U10 DUAL 1 IP_L27P_1 J16 INPUT 2 IO_L15N_2/GCLK13 Y9 GCLK 1 IP_L31N_1 J13 INPUT 2 IO_L15P_2/GCLK12 W9 GCLK 1 IP_L31P_1/VREF_1 J14 VREF 2 IO_L16N_2/GCLK15 W10 GCLK 1 IP_L35N_1 H14 INPUT 2 IO_L16P_2/GCLK14 V10 GCLK 1 IP_L35P_1 H15 INPUT 2 IO_L17N_2/GCLK1 V11 GCLK 1 IP_L39N_1 G14 INPUT 2 IO_L17P_2/GCLK0 Y11 GCLK 1 IP_L39P_1/VREF_1 G15 VREF 2 IO_L18N_2/GCLK3 V12 GCLK 1 VCCO_1 D19 VCCO 2 IO_L18P_2/GCLK2 U11 GCLK 1 VCCO_1 H16 VCCO 2 IO_L19N_2 R12 I/O 1 VCCO_1 K19 VCCO 2 IO_L19P_2 T12 I/O 1 VCCO_1 N16 VCCO 2 IO_L20N_2/MOSI/CSI_B W12 DUAL 1 VCCO_1 T19 VCCO 2 IO_L20P_2 Y12 I/O 2 IO_L01N_2/M0 V4 DUAL 2 IO_L21N_2 W13 I/O 2 IO_L01P_2/M1 U4 DUAL 2 IO_L21P_2 Y13 I/O 2 IO_L02N_2/CSO_B Y2 DUAL 2 IO_L22N_2/DOUT V13 DUAL 2 IO_L02P_2/M2 W3 DUAL 2 IO_L22P_2/AWAKE U13 2 IO_L03N_2 W4 I/O PWR MGMT 2 IO_L03P_2 Y3 I/O 2 IO_L23N_2 R13 I/O 2 IO_L04N_2 R7 I/O 2 IO_L23P_2 T13 I/O 2 IO_L04P_2 T6 I/O 2 IO_L24N_2/D3 W14 DUAL 2 IO_L05N_2 U5 I/O 2 IO_L24P_2/INIT_B Y14 DUAL 2 IO_L05P_2 V5 I/O 2 IO_L25N_2 T14 I/O 2 IO_L06N_2 U6 I/O 2 IO_L25P_2 V14 I/O 2 IO_L06P_2 T7 I/O 2 IO_L26N_2/D1 V15 DUAL 2 IO_L07N_2/VS2 U7 DUAL 2 IO_L26P_2/D2 Y15 DUAL 2 IO_L07P_2/RDWR_B T8 DUAL 2 IO_L27N_2 T15 I/O 2 IO_L08N_2 Y5 I/O 2 IO_L27P_2 U15 I/O 2 IO_L08P_2 Y4 I/O 2 IO_L28N_2 W16 I/O 2 IO_L09N_2/VS0 W6 DUAL 2 IO_L28P_2 Y16 I/O 2 IO_L09P_2/VS1 V6 DUAL 2 IO_L29N_2 U16 I/O www.xilinx.com 86 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 72: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name Table 72: Spartan-3AN FGG400 Pinout (Continued) FG400 Ball Type Bank Pin Name FG400 Ball Type 2 IO_L29P_2 V16 I/O 3 IO_L09P_3 F3 I/O 2 IO_L30N_2 Y18 I/O 3 IO_L10N_3 F2 I/O 2 IO_L30P_2 Y17 I/O 3 IO_L10P_3 E3 I/O 2 IO_L31N_2 U17 I/O 3 IO_L12N_3 H2 I/O 2 IO_L31P_2 V17 I/O 3 IO_L12P_3 G3 I/O 2 IO_L32N_2/CCLK Y19 DUAL 3 IO_L13N_3/VREF_3 G1 VREF 2 IO_L32P_2/D0/DIN/MISO W18 DUAL 3 IO_L13P_3 F1 I/O 2 IP_2 P9 INPUT 3 IO_L14N_3 H3 I/O 2 IP_2 P12 INPUT 3 IO_L14P_3 J4 I/O 2 IP_2 P13 INPUT 3 IO_L16N_3 J2 I/O 2 IP_2 R8 INPUT 3 IO_L16P_3 J3 I/O 2 IP_2 R10 INPUT 3 IO_L17N_3/LHCLK1 K2 LHCLK 2 IP_2 T11 INPUT 3 IO_L17P_3/LHCLK0 J1 LHCLK 2 IP_2/VREF_2 N9 VREF 3 IO_L18N_3/IRDY2/LHCLK3 L3 LHCLK 2 IP_2/VREF_2 N12 VREF 3 IO_L18P_3/LHCLK2 K3 LHCLK 2 IP_2/VREF_2 P8 VREF 3 IO_L20N_3/LHCLK5 L5 LHCLK 2 IP_2/VREF_2 P10 VREF 3 IO_L20P_3/LHCLK4 K4 LHCLK 2 IP_2/VREF_2 P11 VREF 3 IO_L21N_3/LHCLK7 M1 LHCLK 2 IP_2/VREF_2 R14 VREF 3 IO_L21P_3/TRDY2/LHCLK6 L1 LHCLK 2 VCCO_2 R11 VCCO 3 IO_L22N_3 M3 I/O 2 VCCO_2 U8 VCCO 3 IO_L22P_3/VREF_3 M2 VREF 2 VCCO_2 U14 VCCO 3 IO_L24N_3 M5 I/O 2 VCCO_2 W5 VCCO 3 IO_L24P_3 M4 I/O 2 VCCO_2 W11 VCCO 3 IO_L25N_3 N2 I/O 2 VCCO_2 W17 VCCO 3 IO_L25P_3 N1 I/O 3 IO_L01N_3 D3 I/O 3 IO_L26N_3 N4 I/O 3 IO_L01P_3 D4 I/O 3 IO_L26P_3 N3 I/O 3 IO_L02N_3 C2 I/O 3 IO_L28N_3 R1 I/O 3 IO_L02P_3 B1 I/O 3 IO_L28P_3 P1 I/O 3 IO_L03N_3 D2 I/O 3 IO_L29N_3 P4 I/O 3 IO_L03P_3 C1 I/O 3 IO_L29P_3 P3 I/O 3 IO_L05N_3 E1 I/O 3 IO_L30N_3 R3 I/O 3 IO_L05P_3 D1 I/O 3 IO_L30P_3 R2 I/O 3 IO_L06N_3 G5 I/O 3 IO_L32N_3 T2 I/O 3 IO_L06P_3 F4 I/O 3 IO_L32P_3/VREF_3 T1 VREF 3 IO_L07N_3 J5 I/O 3 IO_L33N_3 R4 I/O 3 IO_L07P_3 J6 I/O 3 IO_L33P_3 T3 I/O 3 IO_L08N_3 H4 I/O 3 IO_L34N_3 U3 I/O 3 IO_L08P_3 H6 I/O 3 IO_L34P_3 U1 I/O 3 IO_L09N_3 G4 I/O 3 IO_L36N_3 T4 I/O DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 87 R Pinout Descriptions Table 72: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name Table 72: Spartan-3AN FGG400 Pinout (Continued) FG400 Ball Type Bank FG400 Ball Type 3 IO_L36P_3 R5 I/O GND GND G2 GND 3 IO_L37N_3 V2 I/O GND GND G19 GND 3 IO_L37P_3 V1 I/O GND GND H8 GND 3 IO_L38N_3 W2 I/O GND GND H13 GND 3 IO_L38P_3 W1 I/O GND GND J9 GND 3 IP_3 H7 INPUT GND GND J11 GND 3 IP_L04N_3/VREF_3 G6 VREF GND GND K1 GND 3 IP_L04P_3 G7 INPUT GND GND K10 GND 3 IP_L11N_3/VREF_3 J7 VREF GND GND K12 GND 3 IP_L11P_3 J8 INPUT GND GND K17 GND 3 IP_L15N_3 K7 INPUT GND GND L4 GND 3 IP_L15P_3 K8 INPUT GND GND L9 GND 3 IP_L19N_3 K5 INPUT GND GND L11 GND 3 IP_L19P_3 K6 INPUT GND GND L20 GND 3 IP_L23N_3 L6 INPUT GND GND M10 GND 3 IP_L23P_3 L7 INPUT GND GND M12 GND 3 IP_L27N_3 M7 INPUT GND GND N8 GND 3 IP_L27P_3 M8 INPUT GND GND N11 GND 3 IP_L31N_3 N7 INPUT GND GND N13 GND 3 IP_L31P_3 M6 INPUT GND GND P2 GND 3 IP_L35N_3 N6 INPUT GND GND P19 GND 3 IP_L35P_3 P5 INPUT GND GND R6 GND 3 IP_L39N_3/VREF_3 P7 VREF GND GND R9 GND 3 IP_L39P_3 P6 INPUT GND GND T16 GND 3 VCCO_3 E2 VCCO GND GND U12 GND 3 VCCO_3 H5 VCCO GND GND V3 GND 3 VCCO_3 L2 VCCO GND GND V18 GND 3 VCCO_3 N5 VCCO GND GND W7 GND 3 VCCO_3 U2 VCCO GND GND W15 GND GND GND A1 GND GND GND Y1 GND GND GND A11 GND GND GND Y10 GND GND GND A20 GND GND GND Y20 GND GND GND B6 GND VCCAUX SUSPEND R15 GND GND B14 GND PWR MGMT GND GND C3 GND VCCAUX DONE W19 CONFIG GND GND C18 GND VCCAUX PROG_B D5 CONFIG GND GND D9 GND VCCAUX TCK A19 JTAG GND GND E5 GND VCCAUX TDI F5 JTAG GND GND E12 GND VCCAUX TDO E17 JTAG GND GND F15 GND VCCAUX TMS E4 JTAG www.xilinx.com 88 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 72: Spartan-3AN FGG400 Pinout (Continued) FG400 Ball Type VCCAUX VCCAUX A13 VCCAUX VCCAUX VCCAUX E16 VCCAUX VCCAUX VCCAUX H1 VCCAUX VCCAUX VCCAUX K13 VCCAUX VCCAUX VCCAUX L8 VCCAUX VCCAUX VCCAUX N20 VCCAUX VCCAUX VCCAUX T5 VCCAUX VCCAUX VCCAUX Y8 VCCAUX VCCINT VCCINT J10 VCCINT VCCINT VCCINT J12 VCCINT VCCINT VCCINT K9 VCCINT VCCINT VCCINT K11 VCCINT VCCINT VCCINT L10 VCCINT VCCINT VCCINT L12 VCCINT VCCINT VCCINT M9 VCCINT VCCINT VCCINT M11 VCCINT VCCINT VCCINT N10 VCCINT Bank Pin Name User I/Os by Bank Table 73 indicates how the 311 available user-I/O pins are distributed between the four I/O banks on the FGG400 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 73: User I/Os Per Bank for the XC3S400AN in the FGG400 Package Package Edge I/O Bank Maximum I/O Top 0 Right All Possible I/O Pins by Type I/O INPUT DUAL VREF CLK 77 50 12 1 6 8 1 79 21 12 30 8 8 Bottom 2 76 35 6 21 6 8 Left 3 79 49 16 0 6 8 311 155 46 52 26 32 TOTAL Footprint Migration Differences The XC3S400AN is the only Spartan-3AN FPGA offered in the FGG400 package. The XC3S400AN FPGA is pin compatible with the Spartan-3A XC3S400A FPGA in the FG(G)400 package, although the Spartan-3A FPGA requires an external configuration source. DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 89 R Pinout Descriptions FG400 Footprint X-Ref Target - Figure 21 Bank 0 1 Left Half of FG400 Package (top view) 155 2 3 I/O A B I/O: Unrestricted, general-purpose user I/O C GND I/O L02P_3 L32P_0 VREF_0 I/O I/O I/O L03P_3 L02N_3 5 6 7 I/O I/O I/O I/O I/O L30P_0 L29P_0 L26P_0 L25P_0 L24N_0 I/O L32N_0 PUDC_B 4 L30N_0 GND VCCO_0 I/O L26N_0 GND 8 9 10 I/O I/O I/O L18N_0 GCLK11 L18P_0 GCLK10 L16P_0 GCLK6 I/O I/O I/O L24P_0 L20P_0 L19P_0 I/O I/O I/O I/O I/O I/O L29N_0 L28P_0 L25N_0 L21P_0 L20N_0 L19N_0 I/O I/O I/O I/O L05P_3 L03N_3 L01N_3 L01P_3 PR O G D _B INPUT: Unrestricted, 46 general-purpose input pin I/O L28N_0 VCCO_0 I/O L21N_0 E VREF: User I/O or input F 26 voltage reference for bank I/O L05N_3 I/O VCCO_3 L10P_3 I/O I/O I/O I/O L13P_3 L10N_3 L09P_3 L06P_3 I/O 2 4 2 L13N_3 VREF_3 H VCCAUX J L17P_3 LHCLK0 K GND L L21P_3 TRDY2 LHCLK6 I/O I/O M L21N_3 LHCLK7 L22P_3 VREF_3 I/O JTAG: Dedicated JTAG port pins SUSPEND: Dedicated SUSPEND and dual-purpose AWAKE Power Management pins GND: Ground 43 22 G CONFIG: Dedicated configuration pins VCCO: Output voltage supply for bank Bank 3 32 CLK: User I/O, input, or clock buffer input GND P I/O I/O L09N_3 L06N_3 I/O I/O I/O L14N_3 L08N_3 VCCO_3 I/O I/O I/O I/O L31P_0 L27P_0 L23P_0 L22P_0 I/O L23N_0 L22N_0 VREF_0 VCCO_0 INPUT INPUT INPUT GND INPUT INPUT GND VCCINT VCCINT GND GND VCCINT VCCINT GND INPUT L04N_3 VREF_3 I/O L08P_3 R VCCAUX: Auxiliary supply 8 voltage U I/O L07P_3 L11N_3 VREF_3 INPUT INPUT INPUT INPUT L19N_3 L19P_3 L15N_3 L15P_3 INPUT INPUT VCCAUX I/O I/O L20P_3 LHCLK4 I/O VCCO_3 L18N_3 IRDY2 LHCLK3 I/O GND L23N_3 I/O I/O INPUT INPUT INPUT L24N_3 L31P_3 L27N_3 L27P_3 INPUT INPUT L35N_3 L31N_3 I/O VCCO_3 I/O I/O INPUT INPUT L29P_3 L29N_3 L35P_3 L39P_3 I/O I/O I/O I/O I/O L28N_3 L30P_3 L30N_3 L33N_3 L36P_3 V W I/O I/O I/O L32N_3 L33P_3 L36N_3 VCCO_3 I/O I/O L37P_3 L37N_3 I/O I/O L38P_3 L38N_3 GND L02N_2 CSO_B I/O Y L23P_3 L24P_3 L26N_3 I/O L11P_3 I/O I/O GND L20N_3 LHCLK5 INPUT L22N_3 L26P_3 L34P_3 INPUT I/O L07N_3 I/O L32P_3 VREF_3 INPUT I/O L25N_3 I/O T L04P_3 L14P_3 VCCINT: Internal core 9 supply voltage (+1.2V) INPUT I/O L18P_3 LHCLK2 I/O L34N_3 I/O L01P_2 M1 I/O GND I/O L02P_2 M2 L01N_2 M0 I/O L03N_2 VCCAUX GND L39N_3 VREF_3 I/O L04N_2 I/O I/O L06P_2 I/O I/O L06N_2 I/O INPUT L04P_2 L05N_2 L05P_2 I/O I/O L09P_2 VS1 L12P_2 D7 L09N_2 VS0 GND I/O I/O I/O I/O I/O L03P_2 L08P_2 L08N_2 L10P_2 L10N_2 Bank 2 GND INPUT VREF_2 INPUT I/O L07P_2 RDWR_B I/O L07N_2 VS2 I/O VCCO_2 I/O I/O L27N_0 L16P_3 I/O I/O L17N_0 GCLK9 I/O I/O L17N_3 LHCLK1 L17P_0 GCLK8 L31N_0 L16N_3 I/O I/O TDI I/O L25P_3 L28P_3 GND L12P_3 L12N_3 I/O N TMS I/O L16N_0 GCLK7 I/O GND DUAL: Configuration pins, 51 then possible user I/O VCCO_0 VCCO_2 INPUT VREF_2 INPUT GND I/O L11P_2 I/O L11N_2 I/O I/O L13P_2 L13N_2 VCCINT INPUT VREF_2 INPUT I/O L14N_2 D4 I/O L14P_2 D5 I/O L16P_2 GCLK14 I/O I/O I/O L12N_2 D6 L15P_2 GCLK12 L16N_2 GCLK15 VCCAUX L15N_2 GCLK13 I/O GND DS529-4_03_101106 Figure 21: FG400 Package Footprint (top view) www.xilinx.com 90 DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Bank 0 GND 12 I/O L13N_0 13 VCCAUX I/O I/O I/O L14P_0 L13P_0 L11P_0 I/O I/O L14N_0 L11N_0 I/O L15P_0 GCLK4 I/O L12P_0 I/O L15N_0 GCLK5 GND I/O L10N_0 VREF_0 VCCO_0 I/O L09P_0 I/O I/O L12N_0 L09N_0 INPUT INPUT INPUT INPUT GND GND VCCINT VCCINT GND GND VCCINT VCCINT GND INPUT INPUT VREF_0 GND INPUT INPUT L31N_1 VCCAUX 15 16 17 18 I/O I/O I/O I/O I/O L07N_0 L08N_0 L05N_0 L04N_0 L01N_0 VCCO_0 L04P_0 VREF_0 GND I/O I/O I/O I/O L06N_0 L05P_0 L02N_0 I/O I/O L06P_0 L03P_0 L02P_0 VREF_0 VCCAUX TDO INPUT INPUT I/O L03N_0 I/O INPUT GND INPUT I/O I/O L39P_1 VREF_1 L36P_1 A20 L30P_1 A18 INPUT INPUT L35N_1 L35P_1 INPUT L31P_1 VREF_1 INPUT L23N_1 INPUT INPUT I/O L27N_1 L27P_1 L24P_1 INPUT L23P_1 VREF_1 I/O L19P_1 L20N_1 RHCLK5 INPUT INPUT L15P_1 VREF_1 L11N_1 VREF_1 INPUT VREF_1 INPUT L04P_1 INPUT L04N_1 VREF_1 I/O I/O I/O I/O L19P_2 L23P_2 L25N_2 L27N_2 GND L22P_2 AWAKE I/O I/O L22N_2 DOUT I/O VCCO_2 I/O L17P_2 GCLK0 L20N_2 MOSI CSI_B I/O L21N_2 I/O I/O L20P_2 L21P_2 VCCO_2 I/O L25P_2 L11P_1 VCCO_1 I/O L26P_2 D2 Bank 2 DS557-4 (v3.2) November 19, 2009 Product Specification I/O I/O I/O L30N_1 A19 L29N_1 A17 L29P_1 A16 GND L26N_1 A15 I/O L28P_1 I/O I/O I/O L25P_1 A12 L26P_1 A14 I/O I/O I/O L22N_1 A11 L22P_1 A10 L21N_1 RHCLK7 I/O L18N_1 TRDY1 RHCLK3 D E F I/O L25N_1 A13 L20P_1 RHCLK4 C G H J I/O VCCO_1 L21P_1 IRDY1 RHCLK6 K GND L I/O L18P_1 RHCLK2 I/O I/O L17N_1 RHCLK1 M N I/O I/O I/O L12N_1 A3 L13P_1 A4 L13N_1 A5 VCCAUX GND L10N_1 VREF_1 I/O I/O I/O I/O I/O I/O L08N_1 L08P_1 L09P_1 L09N_1 I/O L03P_1 A0 I/O I/O I/O B L17P_1 RHCLK0 L31N_2 L24P_2 INIT_B I/O L34P_1 L32P_1 L10P_1 I/O I/O L29P_2 L31P_2 L28N_2 VCCO_1 I/O I/O I/O I/O L37P_1 A22 I/O L05P_1 I/O L02N_1 LDC0 GND VCCO_1 L32P_2 D0 DIN/MISO I/O I/O I/O L28P_2 L30P_2 L30N_2 I/O L05N_1 I/O I/O L06P_1 L06N_1 P R T U I/O I/O L02P_1 LDC1 L01N_1 LDC2 DONE L01P_1 HDC W GND Y I/O VCCO_2 Right Half of FGG400 Package (top view) A I/O I/O GND I/O L37N_1 A23 L32N_1 L07N_1 GND I/O L38P_1 A24 I/O I/O I/O I/O L38N_1 A25 L33P_1 L07P_1 L03N_1 A1 GND L14N_1 A7 L29N_2 I/O I/O L34N_1 TCK I/O I/O L26N_2 D1 GND 20 L14P_1 A6 L27P_2 I/O L24N_2 D3 INPUT I/O L12P_1 A2 N INPUT VREF_2 I/O L24N_1 I/O L01P_0 19 I/O GND I/O I/O L18N_2 GCLK3 I/O L16N_1 A9 L23N_2 I/O I/O L28N_1 I/O I/O L17N_2 GCLK1 VCCO_1 L16P_1 A8 L19N_2 I/O L18P_2 GCLK2 I/O L33N_1 INPUT SU SP E VCCO_2 L36N_1 A21 L39N_1 INPUT L19N_1 GND I/O I/O L10P_0 INPUT L15N_1 I/O L07P_0 INPUT INPUT I/O L08P_0 D VREF_2 INPUT VREF_2 INPUT 14 Bank 1 11 V I/O I/O L32N_2 CCLK DS529-4_04_101106 www.xilinx.com 91 R Pinout Descriptions FGG484: 484-ball Fine-pitch Ball Grid Array The 484-ball fine-pitch ball grid array, FGG484, supports the XC3S700AN FPGA, as described in Table 74. Table 74 lists all the FGG484 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. Pinout Table Table 74: Spartan-3AN FGG484 Pinout Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Name IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0/VREF_0 IO_L03N_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L05N_0 IO_L05P_0 IO_L06N_0 IO_L06P_0/VREF_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0 IO_L10N_0 IO_L10P_0 IO_L11N_0 IO_L11P_0 IO_L12N_0/VREF_0 IO_L12P_0 IO_L13N_0 IO_L13P_0 IO_L14N_0 IO_L14P_0 IO_L15N_0 IO_L15P_0 IO_L16N_0 IO_L16P_0 IO_L17N_0/GCLK5 FG484 Ball D18 E17 C19 D19 A20 B20 F15 E15 A18 C18 A19 B19 C17 D17 C16 D16 E14 C14 A17 B17 C15 D15 A15 A16 A14 B15 E13 F13 C13 D13 A13 B13 E12 Type I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 www.xilinx.com 92 Pin Name IO_L17P_0/GCLK4 IO_L18N_0/GCLK7 IO_L18P_0/GCLK6 IO_L19N_0/GCLK9 IO_L19P_0/GCLK8 IO_L20N_0/GCLK11 IO_L20P_0/GCLK10 IO_L21N_0 IO_L21P_0 IO_L22N_0 IO_L22P_0 IO_L23N_0 IO_L23P_0 IO_L24N_0/VREF_0 IO_L24P_0 IO_L25N_0 IO_L25P_0 IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0 IO_L28N_0 IO_L28P_0 IO_L29N_0 IO_L29P_0 IO_L30N_0 IO_L30P_0 IO_L31N_0 IO_L31P_0 IO_L32N_0 IO_L32P_0 IO_L33N_0 IO_L33P_0 IO_L34N_0 IO_L34P_0 IO_L35N_0 IO_L35P_0 IO_L36N_0/PUDC_B IO_L36P_0/VREF_0 IP_0 IP_0 IP_0 IP_0 IP_0 IP_0 IP_0 FG484 Ball C12 A11 A12 C11 B11 E11 D11 C10 A10 A8 A9 E10 D10 C9 B9 C8 B8 A6 A7 C7 D7 A5 B6 D6 C6 D8 E9 B4 A4 D5 C5 B3 A3 F8 E7 E6 F7 A2 B2 E16 E8 F10 F12 F16 G10 G11 Type GCLK GCLK GCLK GCLK GCLK GCLK GCLK I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DUAL VREF INPUT INPUT INPUT INPUT INPUT INPUT INPUT DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Name IP_0 IP_0 IP_0 IP_0 IP_0 IP_0 IP_0 IP_0 IP_0 IP_0 IP_0/VREF_0 IP_0/VREF_0 IP_0/VREF_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO_L01N_1/LDC2 IO_L01P_1/HDC IO_L02N_1/LDC0 IO_L02P_1/LDC1 IO_L03N_1/A1 IO_L03P_1/A0 IO_L05N_1 IO_L05P_1 IO_L06N_1 IO_L06P_1 IO_L07N_1 IO_L07P_1 IO_L09N_1 IO_L09P_1 IO_L10N_1 IO_L10P_1 IO_L11N_1 IO_L11P_1 IO_L13N_1 IO_L13P_1 IO_L14N_1 IO_L14P_1 IO_L15N_1/VREF_1 IO_L15P_1 IO_L17N_1/A3 IO_L17P_1/A2 IO_L18N_1/A5 IO_L18P_1/A4 IO_L19N_1/A7 DS557-4 (v3.2) November 19, 2009 Product Specification FG484 Ball G12 G13 G14 G15 G16 G7 G9 H10 H13 H14 G8 H12 H9 B10 B14 B18 B5 F14 F9 Y21 AA22 W20 W19 T18 T17 W21 Y22 V20 V19 V22 W22 U21 U22 U19 U20 T22 T20 T19 R20 R22 R21 P22 P20 P18 R19 N21 N22 N19 Type INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT VREF VREF VREF VCCO VCCO VCCO VCCO VCCO VCCO DUAL DUAL DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O DUAL DUAL DUAL DUAL DUAL Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Name IO_L19P_1/A6 IO_L20N_1/A9 IO_L20P_1/A8 IO_L21N_1/RHCLK1 IO_L21P_1/RHCLK0 IO_L22N_1/TRDY1/RHCLK3 IO_L22P_1/RHCLK2 IO_L24N_1/RHCLK5 IO_L24P_1/RHCLK4 IO_L25N_1/RHCLK7 IO_L25P_1/IRDY1/RHCLK6 IO_L26N_1/A11 IO_L26P_1/A10 IO_L28N_1 IO_L28P_1 IO_L29N_1/A13 IO_L29P_1/A12 IO_L30N_1/A15 IO_L30P_1/A14 IO_L32N_1 IO_L32P_1 IO_L33N_1/A17 IO_L33P_1/A16 IO_L34N_1/A19 IO_L34P_1/A18 IO_L36N_1 IO_L36P_1 IO_L37N_1 IO_L37P_1 IO_L38N_1 IO_L38P_1 IO_L40N_1 IO_L40P_1 IO_L41N_1 IO_L41P_1 IO_L42N_1 IO_L42P_1 IO_L44N_1/A21 IO_L44P_1/A20 IO_L45N_1/A23 IO_L45P_1/A22 IO_L46N_1/A25 IO_L46P_1/A24 IP_L04N_1/VREF_1 IP_L04P_1 IP_L08N_1 IP_L08P_1 IP_L12N_1/VREF_1 FG484 Ball N20 N17 N18 L22 M22 L20 L21 M20 M18 K19 K20 J22 K22 L19 L18 J20 J21 G22 H22 K18 K17 H20 H21 F21 F22 G20 G19 H19 J18 F20 E20 F18 F19 D22 E22 D20 D21 C21 C22 B21 B22 G17 G18 R16 R15 P16 P15 R18 Type DUAL DUAL DUAL RHCLK RHCLK RHCLK RHCLK RHCLK RHCLK RHCLK RHCLK DUAL DUAL I/O I/O DUAL DUAL DUAL DUAL I/O I/O DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DUAL DUAL DUAL DUAL DUAL DUAL VREF INPUT INPUT INPUT VREF www.xilinx.com 93 R Pinout Descriptions Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Name IP_L12P_1 IP_L16N_1/VREF_1 IP_L16P_1 IP_L23N_1 IP_L23P_1 IP_L27N_1 IP_L27P_1/VREF_1 IP_L31N_1 IP_L31P_1 IP_L35N_1 IP_L35P_1/VREF_1 IP_L39N_1 IP_L39P_1 IP_L43N_1/VREF_1 IP_L43P_1 IP_L47N_1 IP_L47P_1/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO_L01N_2/M0 IO_L01P_2/M1 IO_L02N_2/CSO_B IO_L02P_2/M2 IO_L03N_2 IO_L03P_2 IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L07N_2 IO_L07P_2 IO_L08N_2 IO_L08P_2 IO_L09N_2/VS2 IO_L09P_2/RDWR_B IO_L10N_2 IO_L10P_2 IO_L11N_2/VS0 IO_L11P_2/VS1 IO_L12N_2 IO_L12P_2 IO_L13N_2 FG484 Ball R17 N16 N15 M16 M17 L16 M15 K16 L15 K15 K14 H18 H17 J15 J16 H15 H16 E21 J17 K21 P17 P21 V21 W5 V6 Y4 W4 AA3 AB2 AA4 AB3 Y5 W6 AB5 AB4 Y6 W7 AB6 AA6 W9 V9 AB7 Y7 Y8 W8 AB8 AA8 Y10 Type INPUT VREF INPUT INPUT INPUT INPUT VREF INPUT INPUT INPUT VREF INPUT INPUT VREF INPUT INPUT VREF VCCO VCCO VCCO VCCO VCCO VCCO DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DUAL DUAL I/O I/O DUAL DUAL I/O I/O I/O Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Type I/O DUAL DUAL I/O I/O DUAL DUAL GCLK GCLK GCLK GCLK GCLK GCLK GCLK GCLK I/O I/O DUAL I/O I/O I/O AA15 DUAL PWR MGMT I/O I/O DUAL DUAL I/O I/O DUAL DUAL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DUAL 2 2 IO_L24P_2/AWAKE AB15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L25N_2 IO_L25P_2 IO_L26N_2/D3 IO_L26P_2/INIT_B IO_L27N_2 IO_L27P_2 IO_L28N_2/D1 IO_L28P_2/D2 IO_L29N_2 IO_L29P_2 IO_L30N_2 IO_L30P_2 IO_L31N_2 IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L34N_2 IO_L34P_2 IO_L35N_2 IO_L35P_2 IO_L36N_2/CCLK Y15 W15 U13 V13 Y16 AB16 Y17 AA17 AB18 AB17 V15 V14 V16 W16 AA19 AB19 V17 W18 W17 Y18 AA21 AB21 AA20 www.xilinx.com 94 FG484 Ball V10 AB9 Y9 AB10 AA10 AB11 Y11 V11 U11 Y12 W12 AB12 AA12 U12 V12 Y13 AB13 AB14 AA14 Y14 W13 Pin Name IO_L13P_2 IO_L14N_2/D6 IO_L14P_2/D7 IO_L15N_2 IO_L15P_2 IO_L16N_2/D4 IO_L16P_2/D5 IO_L17N_2/GCLK13 IO_L17P_2/GCLK12 IO_L18N_2/GCLK15 IO_L18P_2/GCLK14 IO_L19N_2/GCLK1 IO_L19P_2/GCLK0 IO_L20N_2/GCLK3 IO_L20P_2/GCLK2 IO_L21N_2 IO_L21P_2 IO_L22N_2/MOSI/CSI_B IO_L22P_2 IO_L23N_2 IO_L23P_2 IO_L24N_2/ DOUT DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Name IO_L36P_2/D0/DIN/MISO IP_2 IP_2 IP_2 IP_2 IP_2 IP_2 IP_2 IP_2 IP_2 N.C. N.C. IP_2 IP_2 IP_2/VREF_2 IP_2/VREF_2 IP_2/VREF_2 IP_2/VREF_2 IP_2/VREF_2 IP_2/VREF_2 IP_2/VREF_2 IP_2/VREF_2 N.C. IP_2/VREF_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO_L01N_3 IO_L01P_3 IO_L02N_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L05N_3 IO_L05P_3 IO_L06N_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 DS557-4 (v3.2) November 19, 2009 Product Specification FG484 Ball AB20 P12 R10 R11 R9 T13 T14 T9 U10 U15 U16 U7 U8 V7 R12 R13 R14 T10 T11 T15 T16 T7 T8 V8 AA13 AA18 AA5 AA9 U14 U9 D2 C1 C2 B1 E4 D3 G5 G6 E1 D1 E3 F4 G4 F3 H6 H5 J5 K6 Type DUAL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT N.C. N.C. INPUT INPUT VREF VREF VREF VREF VREF VREF VREF VREF N.C. VREF VCCO VCCO VCCO VCCO VCCO VCCO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Name IO_L12N_3 IO_L12P_3 IO_L13N_3 IO_L13P_3 IO_L14N_3 IO_L14P_3 IO_L16N_3 IO_L16P_3 IO_L17N_3/VREF_3 IO_L17P_3 IO_L18N_3 IO_L18P_3 IO_L20N_3 IO_L20P_3 IO_L21N_3/LHCLK1 IO_L21P_3/LHCLK0 IO_L22N_3/IRDY2/LHCLK3 IO_L22P_3/LHCLK2 IO_L24N_3/LHCLK5 IO_L24P_3/LHCLK4 IO_L25N_3/LHCLK7 IO_L25P_3/TRDY2/LHCLK6 IO_L26N_3 IO_L26P_3/VREF_3 IO_L28N_3 IO_L28P_3 IO_L29N_3 IO_L29P_3 IO_L30N_3 IO_L30P_3 IO_L32N_3 IO_L32P_3 IO_L33N_3 IO_L33P_3 IO_L34N_3 IO_L34P_3 IO_L36N_3 IO_L36P_3/VREF_3 IO_L37N_3 IO_L37P_3 IO_L38N_3 IO_L38P_3 IO_L40N_3 IO_L40P_3 IO_L41N_3 IO_L41P_3 IO_L42N_3 IO_L42P_3 FG484 Ball F1 F2 G1 G3 H3 H4 H1 H2 J1 J3 K4 K5 K2 K3 L3 L5 L1 K1 M2 M1 M4 M3 N3 N1 P2 P1 P5 P3 N4 M5 R2 R1 R4 R3 T4 R5 T3 T1 U2 U1 V3 V1 U5 T5 U4 U3 W2 W1 Type I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O www.xilinx.com 95 R Pinout Descriptions Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Name IO_L43N_3 IO_L43P_3 IO_L44N_3 IO_L44P_3 IO_L45N_3 IO_L45P_3 IP_3/VREF_3 IP_3/VREF_3 IP_L04N_3/VREF_3 IP_L04P_3 IP_L11N_3 IP_L11P_3 IP_L15N_3/VREF_3 IP_L15P_3 IP_L19N_3 IP_L19P_3 IP_L23N_3 IP_L23P_3 IP_L27N_3 IP_L27P_3 IP_L31N_3 IP_L31P_3 IP_L35N_3 IP_L35P_3 IP_L39N_3 IP_L39P_3 IP_L46N_3/VREF_3 IP_L46P_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND FG484 Ball W3 V4 Y2 Y1 AA2 AA1 J8 R6 H7 H8 K8 J7 L8 K7 M8 L7 M6 M7 N9 N8 N5 N6 P8 N7 R8 P7 T6 R7 E2 J2 J6 N2 P6 V2 A1 A22 AA11 AA16 AA7 AB1 AB22 B12 B16 B7 C20 C3 D14 D9 Type I/O I/O I/O I/O I/O I/O VREF VREF VREF INPUT INPUT INPUT VREF INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT VREF INPUT VCCO VCCO VCCO VCCO VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FG484 Ball F11 F17 F6 G2 G21 J11 J13 J14 J19 J4 J9 K10 K12 L11 L13 L17 L2 L6 L9 M10 M12 M14 M21 N11 N13 P10 P14 P19 P4 P9 T12 T2 T21 U17 U6 W10 W14 Y20 Y3 VCCAUX SUSPEND U18 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX Y19 C4 A21 F5 E19 D4 D12 www.xilinx.com 96 Pin Name DONE PROG_B TCK TDI TDO TMS VCCAUX Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PWR MGMT CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 74: Spartan-3AN FGG484 Pinout (Continued) Bank VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT FG484 Ball E18 E5 H11 L4 M19 P11 V18 V5 W11 J10 J12 K11 K13 K9 L10 L12 L14 M11 M13 M9 N10 N12 N14 P13 Pin Name VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Type VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT User I/Os by Bank Table 75 indicates how the user-I/O pins are distributed between the four I/O banks on the FGG484 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 75: User I/Os Per Bank for the XC3S700AN in the FGG484 Package Package Edge All Possible I/O Pins by Type I/O Bank Maximum I/O I/O INPUT DUAL VREF CLK Top 0 92 58 17 1 8 8 Right 1 94 33 15 30 8 8 Bottom 2 92 43 11 21 9 8 Left 3 94 61 17 0 8 8 372 195 60 52 33 32 TOTAL Footprint Migration Differences The XC3S700AN is the only Spartan-3AN FPGA offered in the FGG484 package. The XC3S700AN FPGA is pin compatible with the Spartan-3A XC3S700A FPGA in the FG(G)484 package, although the Spartan-3A FPGA requires an external configuration source. DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 97 R Pinout Descriptions X-Ref Target - Figure 22 Bank 0 A B I/O: Unrestricted, 195 general-purpose user I/O 60 INPUT: Unrestricted, general-purpose input pin 51 DUAL: Configuration pins, then possible user I/O C D E F 33 32 VREF: User I/O or input voltage reference for bank G CLK: User I/O, input, or clock buffer input H GND I/O L02P_3 L36N_0 PUDC_B I/O L36P_0 VREF_0 I/O I/O L01P_3 L02N_3 4 I/O I/O L22P_0 L21P_0 I/O I/O L33N_0 L31N_0 GND TMS I/O I/O L07N_3 L03N_3 I/O I/O I/O L08P_3 L07P_3 VCCO_0 I/O L28P_0 I/O I/O I/O L27N_0 L25N_0 I/O I/O I/O I/O L32N_0 L29N_0 L27P_0 L30N_0 VCCAUX TDI I/O I/O L35N_0 L34P_0 GND I/O I/O I/O I/O L08N_3 L05N_3 L05P_3 I/O I/O I/O I/O I/O L16P_3 L14N_3 L14P_3 L09P_3 L09N_3 K L22P_3 LHCLK2 CONFIG: Dedicated configuration pins L L22N_3 IRDY2 LHCLK3 I/O I/O M L24P_3 LHCLK4 L24N_3 LHCLK5 N L26P_3 VREF_3 I/O I/O GND I/O L24P_0 L29P_0 L13P_3 L17P_3 I/O L25P_0 I/O I/O VCCO_3 GND L32P_0 L16N_3 SUSPEND: Dedicated SUSPEND and dual-purpose AWAKE Power Management pins JTAG: Dedicated JTAG port pins I/O L22N_0 L12P_3 L17N_3 VREF_3 I/O L10N_3 VCCO_3 INPUT I/O I/O L35P_0 L34N_0 INPUT INPUT L04N_3 VREF_3 INPUT VREF_0 INPUT L11P_3 VREF_3 I/O I/O I/O I/O INPUT INPUT L18N_3 L18P_3 L10P_3 L15P_3 L11N_3 GND L21N_3 LHCLK1 VCCAUX L21P_3 LHCLK0 GND I/O VCCO_3 I/O I/O INPUT I/O VCCO_0 I/O L21N_0 I/O L23P_0 L19P_0 GCLK8 I/O L19N_0 GCLK9 I/O L20P_0 GCLK10 I/O I/O L23N_0 L20N_0 GCLK11 VCCO_0 INPUT GND INPUT INPUT INPUT INPUT VCCAUX GND VCCINT GND VCCINT GND VCCINT GND VCCINT GND VCCINT GND VCCINT VCCINT GND GND GND VCCAUX INPUT INPUT INPUT INPUT L19P_3 L15N_3 VREF_3 L25N_3 LHCLK7 I/O INPUT INPUT INPUT L30P_3 L23N_3 L23P_3 L19N_3 I/O I/O INPUT INPUT INPUT INPUT INPUT L26N_3 L30N_3 L31N_3 L31P_3 L35P_3 L27P_3 L27N_3 INPUT INPUT L39P_3 L35N_3 L25P_3 TRDY2 LHCLK6 I/O L18N_0 GCLK7 I/O INPUT INPUT 11 L30P_0 VREF_0 L20P_3 I/O GND L04P_3 I/O I/O I/O L24N_0 VREF_0 INPUT L20N_3 I/O Bank 3 2 I/O L26P_0 I/O I/O 2 I/O L26N_0 L12N_3 J 10 I/O I/O GND 9 L28N_0 L03P_3 I/O 8 I/O I/O L13N_3 7 L31P_0 L01N_3 VCCO_3 6 I/O I/O I/O 5 L33P_0 L06P_3 L06N_3 4 _B I/O 3 G Left Half of FG484 Package (top view) 2 O 1 PR FG484 Footprint GND: Ground 53 24 P VCCO: Output voltage supply for bank R I/O I/O I/O L28P_3 L28N_3 L29P_3 VCCINT: Internal core 15 supply voltage (+1.2V) U 10 VCCAUX: Auxiliary supply voltage (+3.3V) N.C.: Not connected V W 3 Y A A A B I/O L29N_3 VCCO_3 I/O I/O I/O I/O I/O INPUT INPUT INPUT L32P_3 L32N_3 L33P_3 L33N_3 L34P_3 VREF_3 L46P_3 L39N_3 I/O T GND L36P_3 VREF_3 GND I/O I/O I/O L36N_3 L34N_3 L40P_3 I/O I/O I/O I/O I/O L37P_3 L37N_3 L41P_3 L41N_3 L40N_3 I/O L38P_3 VCCO_3 I/O I/O L38N_3 L43P_3 I/O I/O I/O L42P_3 L42N_3 L43N_3 I/O I/O L44P_3 L44N_3 I/O I/O L01N_2 M0 L02N_2 CSO_B I/O I/O I/O I/O L45P_3 L45N_3 L03N_2 L04N_2 GND INPUT L46N_3 VREF_3 VREF_2 GND N.C. L01P_2 M1 INPUT I/O I/O L05P_2 L07P_2 I/O I/O I/O L05N_2 L07N_2 L10P_2 VCCO_2 N.C. INPUT INPUT VCCO_2 INPUT INPUT VREF_2 VREF_2 INPUT L17P_2 GCLK12 I/O I/O VCCAUX L02P_2 M2 I/O GND INPUT I/O L08P_2 GND INPUT VREF_2 I/O I/O L11P_2 VS1 L09N_2 VS2 I/O I/O L11N_2 VS0 L14P_2 D7 I/O L12P_2 I/O I/O I/O I/O I/O I/O I/O L03P_2 L04P_2 L06P_2 L06N_2 L08N_2 L10N_2 L12N_2 Bank 2 I/O L09P_2 RDWR_B VCCO_2 I/O L14N_2 D6 I/O I/O L13P_2 L17N_2 GCLK13 GND VCCAUX I/O L13N_2 I/O L15P_2 I/O L15N_2 I/O L16P_2 D5 GND I/O L16N_2 D4 DS557-4_01_032709 Figure 22: FG484 Package Footprint (top view) www.xilinx.com 98 DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Bank 0 I/O L18P_0 GCLK6 GND I/O L17P_0 GCLK4 VCCAUX I/O L17N_0 GCLK5 INPUT INPUT INPUT VREF_0 13 14 I/O I/O L16N_0 L13N_0 I/O L16P_0 VCCO_0 15 I/O L12N_0 VREF_0 I/O L13P_0 GND 17 18 19 20 I/O I/O I/O I/O I/O L12P_0 L10N_0 L05N_0 L06N_0 L03N_0 VCCO_0 L06P_0 VREF_0 I/O GND L10P_0 I/O I/O I/O I/O I/O I/O I/O I/O L15N_0 L09P_0 L11N_0 L08N_0 L07N_0 L05P_0 L02N_0 I/O L15P_0 GND I/O I/O I/O L08P_0 L07P_0 L01N_0 L02P_0 VREF_0 VCCAUX TDO I/O I/O I/O L14N_0 L09N_0 L04P_0 I/O L14P_0 VCCO_0 INPUT INPUT INPUT INPUT GND GND INPUT VCCINT L35P_1 VREF_1 I/O I/O L11P_0 I/O L04N_0 INPUT INPUT L47N_1 INPUT VCCINT 16 L43N_1 VREF_1 I/O INPUT L01P_0 I/O INPUT INPUT I/O L39P_1 L39N_1 L37N_1 INPUT L43P_1 VCCO_1 I/O L37P_1 I/O L38P_1 I/O L36N_1 I/O INPUT I/O I/O L35N_1 L31N_1 L32P_1 L32N_1 L25N_1 RHCLK7 GND VCCINT INPUT INPUT I/O I/O L31P_1 L27N_1 L28P_1 L28N_1 GND VCCINT GND VCCINT GND VCCINT INPUT GND I/O I/O I/O L33P_1 A16 L30P_1 A14 I/O I/O I/O L29N_1 A13 L29P_1 A12 L26N_1 A11 VCCO_1 L26P_1 A10 I/O L25P_1 IRDY1 RHCLK6 I/O I/O L18N_1 A5 L18P_1 A4 INPUT INPUT L08P_1 L08N_1 VCCO_1 L17N_1 A3 VCCO_1 L15N_1 VREF_1 I/O L18N_2 GCLK15 I/O I/O L19N_2 GCLK1 L04N_1 VREF_1 I/O L12N_1 VREF_1 L17P_1 A2 I/O I/O L03P_1 A0 L03N_1 A1 INPUT N.C. GND D E F G H J K L M N I/O I/O L15P_1 I/O I/O I/O L13P_1 L14P_1 L14N_1 I/O I/O L13N_1 L11P_1 GND I/O L11N_1 P R T SU VCCO_2 EN D INPUT I/O I/O I/O I/O L30P_2 L30N_2 L31N_2 L33N_2 GND I/O I/O I/O I/O L31P_2 L34N_2 L33P_2 I/O I/O L25N_2 L27N_2 I/O L22P_2 I/O L22N_2 MOSI CSI_B VCCAUX L25P_2 I/O I/O INPUT VREF_2 L23N_2 L21P_2 L12P_1 INPUT I/O VCCO_2 INPUT VREF_2 L21N_2 I/O L19P_2 GCLK0 INPUT GND C I/O I/O INPUT L23P_2 L21P_1 RHCLK0 L19P_1 A6 INPUT I/O GND I/O I/O GND L18P_2 GCLK14 I/O L21N_1 RHCLK1 L19N_1 A7 L04P_1 I/O I/O L22P_1 RHCLK2 I/O INPUT L26P_2 INIT_B L22N_1 TRDY1 RHCLK3 L24P_1 VCCAUX L24N_1 RHCLK4 RHCLK5 I/O B I/O L20P_1 A8 INPUT I/O L30N_1 A15 I/O VREF_2 L20P_2 GCLK2 GND L20N_1 A9 INPUT I/O I/O I/O L34P_1 A18 L16N_1 VREF_1 VREF_2 L26N_2 D3 L23P_1 I/O L34N_1 A19 INPUT INPUT I/O INPUT L23N_1 I/O L41P_1 L16P_1 INPUT VREF_2 L20N_2 GCLK3 INPUT SP INPUT VCCINT L27P_1 VREF_1 GND VCCO_1 L33N_1 A17 I/O VCCINT I/O L44P_1 A20 Right Half of FGG484 Package (top view) A I/O I/O INPUT I/O L44N_1 A21 I/O L36P_1 GND I/O L45P_1 A22 L41N_1 I/O L46P_1 A24 I/O L45N_1 A23 I/O L38N_1 I/O GND L42P_1 I/O L46N_1 A25 TCK I/O L40P_1 INPUT 22 L42N_1 I/O GND L47P_1 VREF_1 GND L40N_1 INPUT INPUT I/O L03P_0 21 Bank 1 12 I/O L24N_2 DOUT I/O L24P_2 AWAKE I/O L28N_2 D1 I/O L34P_2 I/O GND L28P_2 D2 VCCO_2 I/O I/O I/O I/O L10N_1 L10P_1 L09N_1 L09P_1 I/O I/O L06P_1 L06N_1 I/O I/O L02P_1 LDC1 L02N_1 LDC0 DONE GND VCCO_1 I/O I/O L05N_1 L07P_1 I/O I/O L32N_2 I/O L36N_2 CCLK I/O L07N_1 L01N_1 LDC2 I/O L35N_2 I/O L05P_1 I/O L01P_1 HDC I/O I/O I/O I/O I/O L27P_2 L29P_2 L29N_2 L32P_2 Bank 2 DS557-4 (v3.2) November 19, 2009 Product Specification L36P_2 D0 DIN/MISO I/O L35P_2 GND U V W Y A A A B DS557-4_02_032709 www.xilinx.com 99 R Pinout Descriptions FGG676: 676-ball Fine-pitch Ball Grid Array The 676-ball fine-pitch ball grid array, FGG676, supports the XC3S1400AN FPGA. Table 76 lists all the FGG676 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. Pinout Table Table 76: Spartan-3AN FGG676 Pinout Bank 0 Pin Name IO_L01N_0 Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank FG676 Ball Type 0 IO_L18N_0 A18 I/O 0 IO_L18P_0 B18 I/O 0 IO_L19N_0 B17 I/O 0 IO_L19P_0 C17 I/O 0 IO_L20N_0/VREF_0 E15 VREF 0 IO_L20P_0 F15 I/O 0 IO_L21N_0 C16 I/O 0 IO_L21P_0 D17 I/O 0 IO_L22N_0 C15 I/O 0 IO_L22P_0 D16 I/O 0 IO_L23N_0 A15 I/O IO_L23P_0 B15 I/O FG676 Ball Type 0 F20 I/O 0 IO_L24N_0 F14 I/O IO_L24P_0 E14 I/O 0 IO_L01P_0 G20 I/O 0 0 IO_L02N_0 F19 I/O 0 IO_L25N_0/GCLK5 J14 GCLK 0 IO_L02P_0/VREF_0 G19 VREF 0 IO_L25P_0/GCLK4 K14 GCLK IO_L26N_0/GCLK7 A14 GCLK GCLK 0 IO_L05N_0 C22 I/O 0 0 IO_L05P_0 D22 I/O 0 IO_L26P_0/GCLK6 B14 0 IO_L06N_0 C23 I/O 0 IO_L27N_0/GCLK9 G13 GCLK IO_L27P_0/GCLK8 F13 GCLK 0 IO_L06P_0 D23 I/O 0 0 IO_L07N_0 A22 I/O 0 IO_L28N_0/GCLK11 C13 GCLK IO_L28P_0/GCLK10 B13 GCLK B12 I/O 0 IO_L07P_0 B23 I/O 0 0 IO_L08N_0 G17 I/O 0 IO_L29N_0 0 IO_L08P_0 H17 I/O 0 IO_L29P_0 A12 I/O IO_L30N_0 C12 I/O D13 I/O 0 IO_L09N_0 B21 I/O 0 0 IO_L09P_0 C21 I/O 0 IO_L30P_0 0 IO_L10N_0 D21 I/O 0 IO_L31N_0 F12 I/O IO_L31P_0 E12 I/O VREF 0 IO_L10P_0 E21 I/O 0 0 IO_L11N_0 C20 I/O 0 IO_L32N_0/VREF_0 D11 0 IO_L11P_0 D20 I/O 0 IO_L32P_0 C11 I/O IO_L33N_0 B10 I/O 0 IO_L12N_0 K16 I/O 0 0 IO_L12P_0 J16 I/O 0 IO_L33P_0 A10 I/O IO_L34N_0 D10 I/O C10 I/O 0 IO_L13N_0 E17 I/O 0 0 IO_L13P_0 F17 I/O 0 IO_L34P_0 0 IO_L14N_0 A20 I/O 0 IO_L35N_0 H12 I/O IO_L35P_0 G12 I/O 0 IO_L14P_0/VREF_0 B20 VREF 0 0 IO_L15N_0 A19 I/O 0 IO_L36N_0 B9 I/O IO_L36P_0 A9 I/O I/O 0 IO_L15P_0 B19 I/O 0 0 IO_L16N_0 H15 I/O 0 IO_L37N_0 D9 0 IO_L16P_0 G15 I/O 0 IO_L37P_0 E10 I/O IO_L38N_0 B8 I/O 0 IO_L17N_0 C18 I/O 0 0 IO_L17P_0 D18 I/O 0 IO_L38P_0 A8 I/O 0 IO_L39N_0 K12 I/O www.xilinx.com 100 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name FG676 Ball Table 76: Spartan-3AN FGG676 Pinout (Continued) Type Bank Pin Name FG676 Ball Type 0 IO_L39P_0 J12 I/O 0 IP_0/VREF_0 D14 VREF 0 IO_L40N_0 D8 I/O 0 IP_0/VREF_0 G11 VREF 0 IO_L40P_0 C8 I/O 0 IP_0/VREF_0 J17 VREF 0 IO_L41N_0 C6 I/O 0 N.C. A24 N.C. 0 IO_L41P_0 B6 I/O 0 N.C. B24 N.C. 0 IO_L42N_0 C7 I/O 0 N.C. D5 N.C. 0 IO_L42P_0 B7 I/O 0 N.C. E9 N.C. 0 IO_L43N_0 K11 I/O 0 N.C. F18 N.C. 0 IO_L43P_0 J11 I/O 0 N.C. E6 N.C. 0 IO_L44N_0 D6 I/O 0 N.C. F9 N.C. 0 IO_L44P_0 C5 I/O 0 N.C. G18 N.C. 0 IO_L45N_0 B4 I/O 0 VCCO_0 B5 VCCO 0 IO_L45P_0 A4 I/O 0 VCCO_0 B11 VCCO 0 IO_L46N_0 H10 I/O 0 VCCO_0 B16 VCCO 0 IO_L46P_0 G10 I/O 0 VCCO_0 B22 VCCO 0 IO_L47N_0 H9 I/O 0 VCCO_0 E8 VCCO 0 IO_L47P_0 G9 I/O 0 VCCO_0 E13 VCCO 0 IO_L48N_0 E7 I/O 0 VCCO_0 E19 VCCO 0 IO_L48P_0 F7 I/O 0 VCCO_0 H11 VCCO 0 IO_L51N_0 B3 I/O 0 VCCO_0 H16 VCCO 0 IO_L51P_0 A3 I/O 1 IO_L01N_1/LDC2 Y21 DUAL 0 IO_L52N_0/PUDC_B G8 DUAL 1 IO_L01P_1/HDC Y20 DUAL 0 IO_L52P_0/VREF_0 F8 VREF 1 IO_L02N_1/LDC0 AD25 DUAL 0 IP_0 A5 INPUT 1 IO_L02P_1/LDC1 AE26 DUAL 0 IP_0 A7 INPUT 1 IO_L03N_1/A1 AC24 DUAL 0 IP_0 A13 INPUT 1 IO_L03P_1/A0 AC23 DUAL 0 IP_0 A17 INPUT 1 IO_L04N_1 W21 I/O 0 IP_0 A23 INPUT 1 IO_L04P_1 W20 I/O 0 IP_0 C4 INPUT 1 IO_L05N_1 AC25 I/O 0 IP_0 D12 INPUT 1 IO_L05P_1 AD26 I/O 0 IP_0 D15 INPUT 1 IO_L06N_1 AB26 I/O 0 IP_0 D19 INPUT 1 IO_L06P_1 AC26 I/O 0 IP_0 E11 INPUT 1 IO_L07N_1/VREF_1 AB24 VREF 0 IP_0 E18 INPUT 1 IO_L07P_1 AB23 I/O 0 IP_0 E20 INPUT 1 IO_L08N_1 V19 I/O 0 IP_0 F10 INPUT 1 IO_L08P_1 V18 I/O 0 IP_0 G14 INPUT 1 IO_L09N_1 AA23 I/O 0 IP_0 G16 INPUT 1 IO_L09P_1 AA22 I/O 0 IP_0 H13 INPUT 1 IO_L10N_1 U20 I/O 0 IP_0 H18 INPUT 1 IO_L10P_1 V21 I/O 0 IP_0 J10 INPUT 1 IO_L11N_1 AA25 I/O 0 IP_0 J13 INPUT 1 IO_L11P_1 AA24 I/O 0 IP_0 J15 INPUT 1 IO_L12N_1 U18 I/O 0 IP_0/VREF_0 D7 VREF 1 IO_L12P_1 U19 I/O DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 101 R Pinout Descriptions Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name FG676 Ball Table 76: Spartan-3AN FGG676 Pinout (Continued) Type Bank FG676 Ball Type 1 IO_L13N_1 Y23 I/O 1 IO_L42N_1/A17 M20 DUAL 1 IO_L13P_1 Y22 I/O 1 IO_L42P_1/A16 N20 DUAL 1 IO_L14N_1 T20 I/O 1 IO_L43N_1/A19 J25 DUAL 1 IO_L14P_1 U21 I/O 1 IO_L43P_1/A18 J26 DUAL 1 IO_L15N_1 Y25 I/O 1 IO_L45N_1 M22 I/O 1 IO_L15P_1 Y24 I/O 1 IO_L45P_1 M21 I/O 1 IO_L17N_1 T17 I/O 1 IO_L46N_1 K22 I/O 1 IO_L17P_1 T18 I/O 1 IO_L46P_1 K23 I/O 1 IO_L18N_1 V22 I/O 1 IO_L47N_1 M18 I/O 1 IO_L18P_1 W23 I/O 1 IO_L47P_1 M19 I/O 1 IO_L19N_1 V25 I/O 1 IO_L49N_1 J22 I/O 1 IO_L19P_1 V24 I/O 1 IO_L49P_1 J23 I/O 1 IO_L21N_1 U22 I/O 1 IO_L50N_1 K21 I/O 1 IO_L21P_1 V23 I/O 1 IO_L50P_1 L22 I/O 1 IO_L22N_1 R20 I/O 1 IO_L51N_1 G24 I/O 1 IO_L22P_1 R19 I/O 1 IO_L51P_1 G23 I/O 1 IO_L23N_1/VREF_1 U24 VREF 1 IO_L53N_1 K20 I/O 1 IO_L23P_1 U23 I/O 1 IO_L53P_1 L20 I/O 1 IO_L25N_1/A3 R22 DUAL 1 IO_L54N_1 F24 I/O 1 IO_L25P_1/A2 R21 DUAL 1 IO_L54P_1 F25 I/O 1 IO_L26N_1/A5 T24 DUAL 1 IO_L55N_1 L17 I/O 1 IO_L26P_1/A4 T23 DUAL 1 IO_L55P_1 L18 I/O 1 IO_L27N_1/A7 R17 DUAL 1 IO_L56N_1 F23 I/O 1 IO_L27P_1/A6 R18 DUAL 1 IO_L56P_1 E24 I/O 1 IO_L29N_1/A9 R26 DUAL 1 IO_L57N_1 K18 I/O 1 IO_L29P_1/A8 R25 DUAL 1 IO_L57P_1 K19 I/O 1 IO_L30N_1/RHCLK1 P20 RHCLK 1 IO_L58N_1 G22 I/O 1 IO_L30P_1/RHCLK0 P21 RHCLK 1 IO_L58P_1/VREF_1 F22 VREF 1 IO_L31N_1/TRDY1/RHCLK3 P25 RHCLK 1 IO_L59N_1 J20 I/O 1 IO_L31P_1/RHCLK2 P26 RHCLK 1 IO_L59P_1 J19 I/O 1 IO_L33N_1/RHCLK5 N24 RHCLK 1 IO_L60N_1 D26 I/O 1 IO_L33P_1/RHCLK4 P23 RHCLK 1 IO_L60P_1 E26 I/O 1 IO_L34N_1/RHCLK7 N19 RHCLK 1 IO_L61N_1 D24 I/O 1 IO_L34P_1/IRDY1/RHCLK6 P18 RHCLK 1 IO_L61P_1 D25 I/O 1 IO_L35N_1/A11 M25 DUAL 1 IO_L62N_1/A21 H21 DUAL 1 IO_L35P_1/A10 M26 DUAL 1 IO_L62P_1/A20 J21 DUAL 1 IO_L37N_1 N21 I/O 1 IO_L63N_1/A23 C25 DUAL 1 IO_L37P_1 P22 I/O 1 IO_L63P_1/A22 C26 DUAL 1 IO_L38N_1/A13 M23 DUAL 1 IO_L64N_1/A25 G21 DUAL 1 IO_L38P_1/A12 L24 DUAL 1 IO_L64P_1/A24 H20 DUAL 1 IO_L39N_1/A15 N17 DUAL 1 IP_L16N_1 Y26 INPUT 1 IO_L39P_1/A14 N18 DUAL 1 IP_L16P_1 W25 INPUT 1 IO_L41N_1 K26 I/O 1 IP_L20N_1/VREF_1 V26 VREF 1 IO_L41P_1 K25 I/O 1 IP_L20P_1 W26 INPUT www.xilinx.com 102 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name FG676 Ball Table 76: Spartan-3AN FGG676 Pinout (Continued) Type Bank Pin Name FG676 Ball Type 1 IP_L24N_1/VREF_1 U26 VREF 2 IO_L11P_2 AD7 I/O 1 IP_L24P_1 U25 INPUT 2 IO_L12N_2 AA10 I/O 1 IP_L28N_1 R24 INPUT 2 IO_L12P_2 Y10 I/O 1 IP_L28P_1/VREF_1 R23 VREF 2 IO_L13N_2 U11 I/O 1 IP_L32N_1 N25 INPUT 2 IO_L13P_2 V11 I/O 1 IP_L32P_1 N26 INPUT 2 IO_L14N_2 AB7 I/O 1 IP_L36N_1 N23 INPUT 2 IO_L14P_2 AC8 I/O 1 IP_L36P_1/VREF_1 M24 VREF 2 IO_L15N_2 AC9 I/O 1 IP_L40N_1 L23 INPUT 2 IO_L15P_2 AB9 I/O 1 IP_L40P_1 K24 INPUT 2 IO_L16N_2 W12 I/O 1 IP_L44N_1 H25 INPUT 2 IO_L16P_2 V12 I/O 1 IP_L44P_1/VREF_1 H26 VREF 2 IO_L17N_2/VS2 AA12 DUAL 1 IP_L48N_1 H24 INPUT 2 IO_L17P_2/RDWR_B Y12 DUAL 1 IP_L48P_1 H23 INPUT 2 IO_L18N_2 AF8 I/O 1 IP_L52N_1/VREF_1 G25 VREF 2 IO_L18P_2 AE8 I/O 1 IP_L52P_1 G26 INPUT 2 IO_L19N_2/VS0 AF9 DUAL 1 IP_L65N_1 B25 INPUT 2 IO_L19P_2/VS1 AE9 DUAL 1 IP_L65P_1/VREF_1 B26 VREF 2 IO_L20N_2 W13 I/O 1 VCCO_1 AB25 VCCO 2 IO_L20P_2 V13 I/O 1 VCCO_1 E25 VCCO 2 IO_L21N_2 AC12 I/O 1 VCCO_1 H22 VCCO 2 IO_L21P_2 AB12 I/O 1 VCCO_1 L19 VCCO 2 IO_L22N_2/D6 AF10 DUAL 1 VCCO_1 L25 VCCO 2 IO_L22P_2/D7 AE10 DUAL 1 VCCO_1 N22 VCCO 2 IO_L23N_2 AC11 I/O 1 VCCO_1 T19 VCCO 2 IO_L23P_2 AD11 I/O 1 VCCO_1 T25 VCCO 2 IO_L24N_2/D4 AE12 DUAL 1 VCCO_1 W22 VCCO 2 IO_L24P_2/D5 AF12 DUAL 2 IO_L01N_2/M0 AD4 DUAL 2 IO_L25N_2/GCLK13 Y13 GCLK 2 IO_L01P_2/M1 AC4 DUAL 2 IO_L25P_2/GCLK12 AA13 GCLK 2 IO_L02N_2/CSO_B AA7 DUAL 2 IO_L26N_2/GCLK15 AE13 GCLK 2 IO_L02P_2/M2 Y7 DUAL 2 IO_L26P_2/GCLK14 AF13 GCLK 2 IO_L05N_2 Y9 I/O 2 IO_L27N_2/GCLK1 AA14 GCLK 2 IO_L05P_2 W9 I/O 2 IO_L27P_2/GCLK0 Y14 GCLK 2 IO_L06N_2 AF3 I/O 2 IO_L28N_2/GCLK3 AE14 GCLK 2 IO_L06P_2 AE3 I/O 2 IO_L28P_2/GCLK2 AF14 GCLK 2 IO_L07N_2 AF4 I/O 2 IO_L29N_2 AC14 I/O 2 IO_L07P_2 AE4 I/O 2 IO_L29P_2 AD14 I/O 2 IO_L08N_2 AD6 I/O 2 IO_L30N_2/MOSI/CSI_B AB15 DUAL 2 IO_L08P_2 AC6 I/O 2 IO_L30P_2 AC15 I/O 2 IO_L09N_2 W10 I/O 2 IO_L31N_2 W15 I/O 2 IO_L09P_2 V10 I/O 2 IO_L31P_2 V14 I/O 2 IO_L10N_2 AE6 I/O 2 IO_L32N_2/DOUT AE15 DUAL 2 IO_L10P_2 AF5 I/O 2 IO_L32P_2/AWAKE AD15 2 IO_L11N_2 AE7 I/O PWR MGMT DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 103 R Pinout Descriptions Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name Table 76: Spartan-3AN FGG676 Pinout (Continued) FG676 Ball Type Bank FG676 Ball Type 2 IO_L33N_2 AD17 I/O 2 IP_2 AD9 INPUT 2 IO_L33P_2 AE17 I/O 2 IP_2 AD10 INPUT 2 IO_L34N_2/D3 Y15 DUAL 2 IP_2 AD16 INPUT 2 IO_L34P_2/INIT_B AA15 DUAL 2 IP_2 AF2 INPUT 2 IO_L35N_2 U15 I/O 2 IP_2 AF7 INPUT 2 IO_L35P_2 V15 I/O 2 IP_2 Y11 INPUT 2 IO_L36N_2/D1 AE18 DUAL 2 IP_2/VREF_2 AA9 VREF 2 IO_L36P_2/D2 AF18 DUAL 2 IP_2/VREF_2 AA20 VREF 2 IO_L37N_2 AE19 I/O 2 IP_2/VREF_2 AB6 VREF 2 IO_L37P_2 AF19 I/O 2 IP_2/VREF_2 AB10 VREF 2 IO_L38N_2 AB16 I/O 2 IP_2/VREF_2 AC10 VREF 2 IO_L38P_2 AC16 I/O 2 IP_2/VREF_2 AD12 VREF 2 IO_L39N_2 AE20 I/O 2 IP_2/VREF_2 AF15 VREF 2 IO_L39P_2 AF20 I/O 2 IP_2/VREF_2 AF17 VREF 2 IO_L40N_2 AC19 I/O 2 IP_2/VREF_2 AF22 VREF 2 IO_L40P_2 AD19 I/O 2 IP_2/VREF_2 Y16 VREF 2 IO_L41N_2 AC20 I/O 2 N.C. AA8 N.C. 2 IO_L41P_2 AD20 I/O 2 N.C. AC5 N.C. 2 IO_L42N_2 U16 I/O 2 N.C. AC22 N.C. 2 IO_L42P_2 V16 I/O 2 N.C. AD5 N.C. 2 IO_L43N_2 Y17 I/O 2 N.C. Y18 N.C. 2 IO_L43P_2 AA17 I/O 2 N.C. Y19 N.C. 2 IO_L44N_2 AD21 I/O 2 N.C. AD23 N.C. 2 IO_L44P_2 AE21 I/O 2 N.C. W18 N.C. 2 IO_L45N_2 AC21 I/O 2 N.C. Y8 N.C. 2 IO_L45P_2 AD22 I/O 2 VCCO_2 AB8 VCCO 2 IO_L46N_2 V17 I/O 2 VCCO_2 AB14 VCCO 2 IO_L46P_2 W17 I/O 2 VCCO_2 AB19 VCCO 2 IO_L47N_2 AA18 I/O 2 VCCO_2 AE5 VCCO 2 IO_L47P_2 AB18 I/O 2 VCCO_2 AE11 VCCO 2 IO_L48N_2 AE23 I/O 2 VCCO_2 AE16 VCCO 2 IO_L48P_2 AF23 I/O 2 VCCO_2 AE22 VCCO 2 IO_L51N_2 AE25 I/O 2 VCCO_2 W11 VCCO 2 IO_L51P_2 AF25 I/O 2 VCCO_2 W16 VCCO 2 IO_L52N_2/CCLK AE24 DUAL 3 IO_L01N_3 J9 I/O 2 IO_L52P_2/D0/DIN/MISO AF24 DUAL 3 IO_L01P_3 J8 I/O 2 IP_2 AA19 INPUT 3 IO_L02N_3 B1 I/O 2 IP_2 AB13 INPUT 3 IO_L02P_3 B2 I/O 2 IP_2 AB17 INPUT 3 IO_L03N_3 H7 I/O 2 IP_2 AB20 INPUT 3 IO_L03P_3 G6 I/O 2 IP_2 AC7 INPUT 3 IO_L05N_3 K8 I/O 2 IP_2 AC13 INPUT 3 IO_L05P_3 K9 I/O 2 IP_2 AC17 INPUT 3 IO_L06N_3 E4 I/O 2 IP_2 AC18 INPUT 3 IO_L06P_3 D3 I/O www.xilinx.com 104 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name FG676 Ball Table 76: Spartan-3AN FGG676 Pinout (Continued) Type Bank Pin Name FG676 Ball Type 3 IO_L07N_3 F4 I/O 3 IO_L34N_3/LHCLK5 P3 LHCLK 3 IO_L07P_3 E3 I/O 3 IO_L34P_3/LHCLK4 P4 LHCLK 3 IO_L09N_3 G4 I/O 3 IO_L35N_3/LHCLK7 P10 LHCLK 3 IO_L09P_3 F5 I/O 3 IO_L35P_3/TRDY2/LHCLK6 N9 LHCLK 3 IO_L10N_3 H6 I/O 3 IO_L36N_3 R2 I/O 3 IO_L10P_3 J7 I/O 3 IO_L36P_3/VREF_3 R1 VREF 3 IO_L11N_3 F2 I/O 3 IO_L37N_3 R4 I/O 3 IO_L11P_3 E1 I/O 3 IO_L37P_3 R3 I/O 3 IO_L13N_3 J6 I/O 3 IO_L38N_3 T4 I/O 3 IO_L13P_3 K7 I/O 3 IO_L38P_3 T3 I/O 3 IO_L14N_3 F3 I/O 3 IO_L39N_3 P6 I/O 3 IO_L14P_3 G3 I/O 3 IO_L39P_3 P7 I/O 3 IO_L15N_3 L9 I/O 3 IO_L40N_3 R6 I/O 3 IO_L15P_3 L10 I/O 3 IO_L40P_3 R5 I/O 3 IO_L17N_3 H1 I/O 3 IO_L41N_3 P9 I/O 3 IO_L17P_3 H2 I/O 3 IO_L41P_3 P8 I/O 3 IO_L18N_3 L7 I/O 3 IO_L42N_3 U4 I/O 3 IO_L18P_3 K6 I/O 3 IO_L42P_3 T5 I/O 3 IO_L19N_3 J4 I/O 3 IO_L43N_3 R9 I/O 3 IO_L19P_3 J5 I/O 3 IO_L43P_3/VREF_3 R10 VREF 3 IO_L21N_3 M9 I/O 3 IO_L44N_3 U2 I/O 3 IO_L21P_3 M10 I/O 3 IO_L44P_3 U1 I/O 3 IO_L22N_3 K4 I/O 3 IO_L45N_3 R7 I/O 3 IO_L22P_3 K5 I/O 3 IO_L45P_3 R8 I/O 3 IO_L23N_3 K2 I/O 3 IO_L47N_3 V2 I/O 3 IO_L23P_3 K3 I/O 3 IO_L47P_3 V1 I/O 3 IO_L25N_3 L3 I/O 3 IO_L48N_3 T9 I/O 3 IO_L25P_3 L4 I/O 3 IO_L48P_3 T10 I/O 3 IO_L26N_3 M7 I/O 3 IO_L49N_3 V5 I/O 3 IO_L26P_3 M8 I/O 3 IO_L49P_3 U5 I/O 3 IO_L27N_3 M3 I/O 3 IO_L51N_3 U6 I/O 3 IO_L27P_3 M4 I/O 3 IO_L51P_3 T7 I/O 3 IO_L28N_3 M6 I/O 3 IO_L52N_3 W4 I/O 3 IO_L28P_3 M5 I/O 3 IO_L52P_3 W3 I/O 3 IO_L29N_3/VREF_3 M1 VREF 3 IO_L53N_3 Y2 I/O 3 IO_L29P_3 M2 I/O 3 IO_L53P_3 Y1 I/O 3 IO_L30N_3 N4 I/O 3 IO_L55N_3 AA3 I/O 3 IO_L30P_3 N5 I/O 3 IO_L55P_3 AA2 I/O 3 IO_L31N_3 N2 I/O 3 IO_L56N_3 U8 I/O 3 IO_L31P_3 N1 I/O 3 IO_L56P_3 U7 I/O 3 IO_L32N_3/LHCLK1 N7 LHCLK 3 IO_L57N_3 Y6 I/O 3 IO_L32P_3/LHCLK0 N6 LHCLK 3 IO_L57P_3 Y5 I/O 3 IO_L33N_3/IRDY2/LHCLK3 P2 LHCLK 3 IO_L59N_3 V6 I/O 3 IO_L33P_3/LHCLK2 P1 LHCLK 3 IO_L59P_3 V7 I/O DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 105 R Pinout Descriptions Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name FG676 Ball Table 76: Spartan-3AN FGG676 Pinout (Continued) Type Bank FG676 Ball Type 3 IO_L60N_3 AC1 I/O GND GND A6 GND 3 IO_L60P_3 AB1 I/O GND GND A11 GND 3 IO_L61N_3 V8 I/O GND GND A16 GND 3 IO_L61P_3 U9 I/O GND GND A21 GND 3 IO_L63N_3 W6 I/O GND GND A26 GND 3 IO_L63P_3 W7 I/O GND GND AA1 GND 3 IO_L64N_3 AC3 I/O GND GND AA6 GND 3 IO_L64P_3 AC2 I/O GND GND AA11 GND 3 IO_L65N_3 AD2 I/O GND GND AA16 GND 3 IO_L65P_3 AD1 I/O GND GND AA21 GND 3 IP_L04N_3/VREF_3 C1 VREF GND GND AA26 GND 3 IP_L04P_3 C2 INPUT GND GND AD3 GND 3 IP_L08N_3 D1 INPUT GND GND AD8 GND 3 IP_L08P_3 D2 INPUT GND GND AD13 GND 3 IP_L12N_3/VREF_3 H4 VREF GND GND AD18 GND 3 IP_L12P_3 G5 INPUT GND GND AD24 GND 3 IP_L16N_3 G1 INPUT GND GND AF1 GND 3 IP_L16P_3 G2 INPUT GND GND AF6 GND 3 IP_L20N_3/VREF_3 J2 VREF GND GND AF11 GND 3 IP_L20P_3 J3 INPUT GND GND AF16 GND 3 IP_L24N_3 K1 INPUT GND GND AF21 GND 3 IP_L24P_3 J1 INPUT GND GND AF26 GND 3 IP_L46N_3 V4 INPUT GND GND C3 GND 3 IP_L46P_3 U3 INPUT GND GND C9 GND 3 IP_L50N_3/VREF_3 W2 VREF GND GND C14 GND 3 IP_L50P_3 W1 INPUT GND GND C19 GND 3 IP_L54N_3 Y4 INPUT GND GND C24 GND 3 IP_L54P_3 Y3 INPUT GND GND F1 GND 3 IP_L58N_3/VREF_3 AA5 VREF GND GND F6 GND 3 IP_L58P_3 AA4 INPUT GND GND F11 GND 3 IP_L62N_3 AB4 INPUT GND GND F16 GND 3 IP_L62P_3 AB3 INPUT GND GND F21 GND 3 IP_L66N_3/VREF_3 AE2 VREF GND GND F26 GND 3 IP_L66P_3 AE1 INPUT GND GND H3 GND 3 VCCO_3 AB2 VCCO GND GND H8 GND 3 VCCO_3 E2 VCCO GND GND H14 GND 3 VCCO_3 H5 VCCO GND GND H19 GND 3 VCCO_3 L2 VCCO GND GND J24 GND 3 VCCO_3 L8 VCCO GND GND K10 GND 3 VCCO_3 P5 VCCO GND GND K17 GND 3 VCCO_3 T2 VCCO GND GND L1 GND 3 VCCO_3 T8 VCCO GND GND L6 GND 3 VCCO_3 W5 VCCO GND GND L11 GND GND A1 GND GND GND L13 GND GND www.xilinx.com 106 Pin Name DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name FG676 Ball Type Table 76: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name FG676 Ball Type GND GND L15 GND VCCAUX VCCAUX E16 VCCAUX GND GND L21 GND VCCAUX VCCAUX E22 VCCAUX GND GND L26 GND VCCAUX VCCAUX J18 VCCAUX GND GND M12 GND VCCAUX VCCAUX K13 VCCAUX GND GND M14 GND VCCAUX VCCAUX L5 VCCAUX GND GND M16 GND VCCAUX VCCAUX N10 VCCAUX GND GND N3 GND VCCAUX VCCAUX P17 VCCAUX GND GND N8 GND VCCAUX VCCAUX T22 VCCAUX GND GND N11 GND VCCAUX VCCAUX U14 VCCAUX GND GND N15 GND VCCAUX VCCAUX V9 VCCAUX GND GND P12 GND VCCINT VCCINT K15 VCCINT GND GND P16 GND VCCINT VCCINT L12 VCCINT GND GND P19 GND VCCINT VCCINT L14 VCCINT GND GND P24 GND VCCINT VCCINT L16 VCCINT GND GND R11 GND VCCINT VCCINT M11 VCCINT GND GND R13 GND VCCINT VCCINT M13 VCCINT GND GND R15 GND VCCINT VCCINT M15 VCCINT GND GND T1 GND VCCINT VCCINT M17 VCCINT GND GND T6 GND VCCINT VCCINT N12 VCCINT GND GND T12 GND VCCINT VCCINT N13 VCCINT GND GND T14 GND VCCINT VCCINT N14 VCCINT GND GND T16 GND VCCINT VCCINT N16 VCCINT GND GND T21 GND VCCINT VCCINT P11 VCCINT GND GND T26 GND VCCINT VCCINT P13 VCCINT GND GND U10 GND VCCINT VCCINT P14 VCCINT GND GND U13 GND VCCINT VCCINT P15 VCCINT GND GND U17 GND VCCINT VCCINT R12 VCCINT GND GND V3 GND VCCINT VCCINT R14 VCCINT GND GND W8 GND VCCINT VCCINT R16 VCCINT GND GND W14 GND VCCINT VCCINT T11 VCCINT GND GND W19 GND VCCINT VCCINT T13 VCCINT GND GND W24 GND VCCINT VCCINT T15 VCCINT V20 PWR MGMT VCCINT VCCINT U12 VCCINT VCCAUX SUSPEND VCCAUX DONE AB21 CONFIG VCCAUX PROG_B A2 CONFIG VCCAUX TCK A25 JTAG VCCAUX TDI G7 JTAG VCCAUX TDO E23 JTAG VCCAUX TMS D4 JTAG VCCAUX VCCAUX AB5 VCCAUX VCCAUX VCCAUX AB11 VCCAUX VCCAUX VCCAUX AB22 VCCAUX VCCAUX VCCAUX E5 VCCAUX DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 107 R Pinout Descriptions User I/Os by Bank Table 77 indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FGG676 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 77: User I/Os Per Bank for the XC3S1400AN in the FGG676 Package Package Edge All Possible I/O Pins by Type I/O Bank Maximum I/O I/O INPUT DUAL VREF CLK Top 0 120 82 20 1 9 8 Right 1 130 67 15 30 10 8 Bottom 2 120 67 14 21 10 8 Left 3 132 97 18 0 9 8 502 313 67 52 38 32 TOTAL Footprint Migration Differences The XC3S1400AN is the only Spartan-3AN FPGA offered in the FGG676 package. The XC3S1400AN FPGA is pin compatible with the Spartan-3A XC3S1400A FPGA in the FG(G)676 package, although the Spartan-3A FPGA requires an external configuration source. www.xilinx.com 108 DS557-4 (v3.2) November 19, 2009 Product Specification R FG676 Footprint Pinout Descriptions X-Ref Target - Figure 23 Bank 0 1 B C D 3 4 I/O I/O L51P_0 L45P_0 I/O I/O I/O I/O L02N_3 L02P_3 L51N_0 L45N_0 GND INPUT INPUT I/O: Unrestricted, 313 general-purpose user I/O O GND PR A G _B Left Half of FG676 Package (top view) 2 L04N_3 VREF_3 INPUT L04P_3 INPUT INPUT I/O L08N_3 L08P_3 L06P_3 TMS 5 6 7 INPUT GND INPUT VCCO_0 8 10 I/O I/O I/O L38P_0 L36P_0 L33P_0 I/O I/O I/O I/O I/O L41P_0 L42P_0 L38N_0 L36N_0 L33N_0 I/O I/O I/O I/O L44P_0 L41N_0 L42N_0 L40P_0 N.C. 9 GND E DUAL: Configuration pins, 51 then possible user I/O 2 SUSPEND: Dedicated SUSPEND and dual-purpose AWAKE Power Management pins CLK: User I/O, input, or 32 clock buffer input 4 JTAG: Dedicated JTAG port pins GND: Ground 77 Bank 3 CONFIG: Dedicated configuration pins VCCINT: Internal core 23 supply voltage (+1.2V) VCCAUX: Auxiliary supply N.C.: Not connected VCCAUX I/O I/O L30N_0 INPUT I/O I/O I/O VREF_0 L40N_0 L37N_0 L34N_0 VCCO_0 N.C. I/O I/O I/O I/O L14N_3 L07N_3 L09P_3 I/O I/O INPUT I/O L14P_3 L09N_3 L12P_3 L03P_3 INPUT L16N_3 L16P_3 GND L12N_3 VREF_3 I/O I/O L17N_3 L17P_3 INPUT INPUT VCCO_3 GND I/O L48N_0 I/O L48P_0 I/O TDI I/O I/O L10N_3 L03N_3 L52N_0 PUDC_B GND N.C. INPUT I/O VREF_0 L35P_0 I/O I/O L47N_0 L46N_0 K INPUT I/O I/O I/O I/O I/O I/O I/O I/O L24N_3 L23N_3 L23P_3 L22N_3 L22P_3 L18P_3 L13P_3 L05N_3 L05P_3 L GND VCCO_3 VCCAUX GND M L29N_3 VREF_3 N I/O I/O I/O I/O I/O L19P_3 L13N_3 L10P_3 L01P_3 L01N_3 I/O I/O L18N_3 VCCO_3 I/O I/O L15N_3 L15P_3 I/O I/O I/O I/O I/O I/O I/O I/O L27N_3 L27P_3 L28P_3 L28N_3 L26N_3 L26P_3 L21N_3 L21P_3 GND L35P_3 TRDY2 LHCLK6 I/O L31N_3 I/O L33N_3 IRDY2 LHCLK3 GND I/O I/O L30N_3 L30P_3 I/O I/O L34N_3 LHCLK5 L34P_3 LHCLK4 I/O I/O L32P_3 LHCLK0 L32N_3 LHCLK1 I/O I/O I/O I/O L39N_3 L39P_3 L41P_3 L41N_3 L33P_3 LHCLK2 R L36P_3 VREF_3 I/O I/O I/O I/O I/O I/O I/O I/O L36N_3 L37P_3 L37N_3 L40P_3 L40N_3 L45N_3 L45P_3 L43N_3 T GND VCCO_3 W A A I/O I/O I/O L38P_3 L38N_3 L42P_3 I/O L51P_3 VCCO_3 I/O I/O I/O I/O I/O I/O L46P_3 L42N_3 L49P_3 L51N_3 L56P_3 L56N_3 L61P_3 I/O INPUT INPUT GND INPUT I/O I/O I/O I/O L46N_3 L49N_3 L59N_3 L59P_3 L61N_3 L50N_3 VREF_3 I/O I/O L52P_3 L52N_3 I/O I/O INPUT INPUT I/O I/O L53P_3 L53N_3 L54P_3 L54N_3 L57P_3 L57N_3 I/O I/O INPUT L55P_3 L55N_3 L58P_3 INPUT INPUT L62P_3 L62N_3 L50P_3 GND A C I/O I/O I/O L60N_3 L64P_3 L64N_3 A D I/O I/O L65P_3 L65N_3 I/O VCCO_3 17 INPUT INPUT L66P_3 L66N_3 VREF_3 GND INPUT VCCO_3 VCCAUX N.C. I/O GND L01N_2 M0 I/O I/O L06P_2 L07P_2 I/O L63P_3 INPUT L58N_3 VREF_3 I/O L01P_2 M1 I/O L63N_3 N.C. VCCO_2 I/O I/O I/O L06N_2 L07N_2 L10P_2 GND I/O L02P_2 M2 N.C. I/O GND L02N_2 CSO_B INPUT I/O VREF_2 L14N_2 I/O L08P_2 INPUT I/O I/O L08N_2 L11P_2 I/O L39P_0 I/O L28P_0 GCLK10 I/O L28N_0 GCLK11 I/O L30P_0 VCCO_0 I/O L27P_0 GCLK8 I/O L27N_0 GCLK9 INPUT INPUT I/O I/O L43N_0 L39N_0 GND VCCINT GND VCCINT GND VCCINT VCCAUX N.C. VCCO_2 VCCAUX GND VCCINT VCCINT GND VCCINT GND VCCINT GND VCCINT GND VCCINT VCCINT GND I/O L43P_3 VREF_3 I/O INPUT L47N_3 I/O INPUT I/O L48P_3 I/O I/O I/O L35N_0 L43P_0 L35N_3 VCCINT LHCLK7 I/O L44N_3 L47P_3 VCCAUX L48N_3 I/O L60P_3 A F GND L44P_3 A B A E VCCO_3 VCCO_0 13 I/O P V GND I/O I/O I/O INPUT L29P_3 L31P_3 I/O I/O L19N_3 L25P_3 I/O L31N_0 I/O L20P_3 I/O GND L46P_0 INPUT L25N_3 INPUT I/O L31P_0 I/O INPUT L20N_3 VREF_3 INPUT INPUT L47P_0 J L24P_3 I/O L37P_0 I/O L32N_0 VREF_0 I/O L52P_0 VREF_0 I/O L29N_0 L32P_0 I/O N.C. VCCO_0 I/O L29P_0 I/O L44N_0 L11N_3 INPUT Y 14 voltage I/O L06N_3 G U VCCO: Output voltage 36 supply for bank I/O L07P_3 GND I/O 2 VCCO_3 F H VREF: User I/O or input 38 voltage reference for bank I/O L11P_3 GND 12 L34P_0 INPUT: Unrestricted, 67 general-purpose input pin 11 GND I/O L13N_2 I/O I/O I/O I/O L09P_2 L13P_2 L16P_2 L20P_2 I/O I/O L05P_2 L09N_2 I/O I/O L05N_2 L12P_2 INPUT I/O VREF_2 L12N_2 I/O INPUT L15P_2 VREF_2 VCCO_2 I/O I/O L16N_2 L20N_2 I/O I/O INPUT L17P_2 RDWR_B L25N_2 GCLK13 I/O I/O GND L17N_2 VS2 L25P_2 GCLK12 VCCAUX I/O L21P_2 I/O I/O INPUT I/O I/O L14P_2 L15N_2 VREF_2 L23N_2 L21N_2 GND INPUT INPUT I/O I/O I/O L10N_2 L11N_2 L18P_2 GND INPUT I/O L18N_2 Bank 2 I/O I/O L19P_2 VS1 L22P_2 D7 I/O I/O L19N_2 VS0 L22N_2 D6 INPUT INPUT I/O INPUT L23P_2 VREF_2 I/O I/O VCCO_2 L24N_2 D4 L26N_2 GCLK15 I/O I/O GND L24P_2 D5 L26P_2 GCLK14 GND DS557-4_07_032309 Figure 23: FG676 Package Footprint (top view) DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 109 R Pinout Descriptions Bank 0 I/O L26N_0 GCLK7 I/O L26P_0 GCLK6 GND INPUT VREF_0 I/O L24P_0 15 I/O L23N_0 I/O L23P_0 INPUT VCCO_0 I/O I/O L14N_0 I/O I/O I/O L19N_0 L18P_0 L15P_0 I/O I/O L17N_0 I/O I/O I/O L22P_0 L21P_0 L17P_0 I/O I/O I/O L16P_0 I/O L16N_0 I/O INPUT I/O VCCAUX GND INPUT VCCO_0 I/O L13N_0 I/O L13P_0 I/O L08N_0 I/O L08P_0 I/O INPUT L12P_0 VREF_0 I/O L25P_0 GCLK4 VCCINT VCCINT GND VCCINT GND VCCINT GND VCCINT GND L12N_0 GND INPUT N.C. VCCO_0 VCCINT GND GND I/O VCCINT L27N_1 A7 GND GND I/O I/O L35N_2 L42N_2 INPUT N.C. TCK GND I/O N.C. L07P_0 I/O I/O I/O L05N_0 L06N_0 GND INPUT L65N_1 I/O I/O L63N_1 A23 L63P_1 A22 I/O I/O I/O I/O I/O I/O I/O L11P_0 L10N_0 L05P_0 L06P_0 L61N_1 L61P_1 L60N_1 VCCAUX TDO INPUT I/O L10P_0 I/O GND I/O I/O L01P_0 L64N_1 A25 I/O I/O L64P_1 A24 L62N_1 A21 I/O I/O I/O L59P_1 L59N_1 L62P_1 A20 L58P_1 VREF_1 I/O L56P_1 VCCO_1 I/O I/O I/O L56N_1 L54N_1 L54P_1 INPUT L52N_1 VREF_1 INPUT INPUT INPUT L48P_1 L48N_1 L44N_1 I/O I/O GND L43N_1 A19 L43P_1 A18 I/O I/O I/O I/O I/O INPUT I/O I/O L50N_1 L46N_1 L46P_1 L40P_1 L41P_1 L41N_1 I/O INPUT L50P_1 L40N_1 VCCO_1 GND I/O I/O L47N_1 L47P_1 I/O L53P_1 I/O L42N_1 A17 GND I/O I/O L45P_1 L45N_1 I/O I/O I/O L39P_1 A14 L34N_1 RHCLK7 L42P_1 A16 I/O I/O GND L30N_1 RHCLK1 L30P_1 RHCLK0 L34P_1 IRDY1 RHCLK6 I/O L27P_1 A6 I/O I/O L17P_1 I/O I/O L22P_1 L22N_1 VCCO_1 I/O L14N_1 I/O L37N_1 VCCO_1 I/O L37P_1 I/O INPUT I/O I/O L36P_1 VREF_1 L35N_1 A11 L35P_1 A10 INPUT INPUT L32N_1 L32P_1 I/O INPUT L33N_1 RHCLK5 L36N_1 I/O I/O L33P_1 RHCLK4 GND I/O I/O INPUT L25P_1 A2 L25N_1 A3 L28P_1 VREF_1 I/O I/O GND VCCAUX L26P_1 A4 L26N_1 A5 I/O I/O I/O I/O I/O I/O L12P_1 L10N_1 L14P_1 L21N_1 L23P_1 I/O I/O I/O L46N_2 L08P_1 L08N_1 N.C. GND N.C. N.C. I/O I/O L27P_2 GCLK0 L34N_2 D3 I/O I/O L27N_2 GCLK1 L34P_2 INIT_B I/O VCCO_2 L30N_2 MOSI CSI_B VCCO_2 INPUT I/O VREF_2 L43N_2 GND I/O L38N_2 I/O I/O I/O L29N_2 L30P_2 L38P_2 I/O L29P_2 I/O L32P_2 AWAKE I/O I/O L28N_2 GCLK3 L32N_2 DOUT I/O L28P_2 GCLK2 INPUT VREF_2 I/O L46P_2 INPUT VCCO_2 GND I/O I/O L43P_2 L47N_2 INPUT INPUT I/O L33N_2 I/O L33P_2 INPUT VREF_2 I/O L47P_2 INPUT GND I/O L36N_2 D1 I/O L36P_2 D2 INPUT VCCO_2 EN I/O L42P_2 SU SP I/O INPUT L28N_1 I/O L23N_1 VREF_1 L31N_1 TRDY1 RHCLK3 VCCO_1 GND T INPUT L24P_1 I/O L19N_1 L20N_1 VREF_1 INPUT INPUT L16P_1 L20P_1 I/O I/O L01N_1 LDC2 INPUT INPUT GND DONE I/O I/O I/O L40N_2 L41N_2 L45N_2 I/O I/O I/O I/O INPUT L13P_1 L13N_1 L15P_1 L15N_1 L16N_1 I/O I/O I/O I/O L09P_1 L09N_1 L11P_1 L11N_1 VCCAUX N.C. I/O I/O I/O I/O L40P_2 L41P_2 L44N_2 L45P_2 I/O I/O I/O L37N_2 L39N_2 L44P_2 I/O I/O L37P_2 L39P_2 Bank 2 GND GND VCCO_2 I/O L07P_1 I/O L07N_1 VREF_1 I/O I/O L03P_1 A0 L03N_1 A1 N.C. GND VCCO_1 I/O INPUT I/O VREF_2 L48P_2 I/O L52N_2 CCLK I/O L52P_2 D0 DIN/MISO I/O L06N_1 I/O I/O L06P_1 I/O L48N_2 GND L05N_1 L02N_1 LDC0 I/O L51N_2 I/O L51P_2 I/O L05P_1 I/O L02P_1 LDC1 GND V W Y A A A B A C A D A E A F DS557-4_08_032709 www.xilinx.com 110 U INPUT I/O L01P_1 HDC VREF_2 INPUT L24N_1 VREF_1 L19P_1 I/O P R I/O L18P_1 N I/O L21P_1 VCCO_1 M L29N_1 A9 I/O I/O L I/O L18N_1 L04N_1 K L29P_1 A8 I/O I/O J I/O L31P_1 RHCLK2 L10P_1 L04P_1 H I/O L38P_1 A12 L38N_1 A13 L12N_1 L35P_2 I/O INPUT L44P_1 VREF_1 L53N_1 I/O L31N_2 L52P_1 I/O VCCO_1 E G I/O L51N_1 L49P_1 D INPUT I/O L51P_1 I/O C F I/O L49N_1 B GND L57P_1 L31P_2 GND I/O L60P_1 L58N_1 VCCO_1 Right Half of FGG676 Package (top view) A INPUT L65P_1 VREF_1 I/O L17N_1 GND 26 D VCCAUX VCCINT 25 L57N_1 I/O VCCAUX VCCO_0 24 L09P_0 I/O I/O VCCINT VCCINT I/O L09N_0 I/O L07N_0 23 I/O L01N_0 GND GND 22 L11N_0 I/O INPUT VCCAUX I/O L14P_0 VREF_0 L02N_0 I/O L55P_1 A15 INPUT L02P_0 VREF_0 I/O I/O VCCINT L39N_1 GND N.C. L55N_1 VCCINT 21 L15N_0 L19P_0 L20N_0 VREF_0 20 I/O I/O INPUT 19 L18N_0 L21N_0 L20P_0 L25N_0 GCLK5 GND 18 I/O I/O GND 17 L22N_0 L24N_0 INPUT 16 Bank 1 14 DS557-4 (v3.2) November 19, 2009 Product Specification R Pinout Descriptions Revision History The following table shows the revision history for this document. Date Version Revision 02/26/07 1.0 Initial release. 08/16/07 2.0 Updated for Production release of initial device. Noted that family is available in Pb-free packages only. 09/12/07 2.0.1 09/24/07 2.1 Update thermal characteristics in Table 67. 12/12/07 3.0 Updated to Production status with Production release of final family member, XC3S50AN. Noted that non-Pb-free packages may be available for selected devices. Updated thermal characteristics in Table 67. Updated links. 06/02/08 3.1 Add "Package Overview" section. Removed VREF and INPUT designations and diamond symbols on unconnected N.C. pins for XC3S700AN FG484 in Table 74 and Figure 21 and for XC3S1400AN FGG676 in Table 76 and Figure 22. 11/19/09 3.2 Renamed package `Footprint Area' to `Body Area' throughout document. Noted in "Introduction" that references to Pb-free package code also apply to the Pb package. Added Pb packages to Table 65 and Table 66. Changed Body Area of TQ144/TQG144 packages in Table 65. Corrected bank designation for SUSPEND to VCCAUX. Noted that non-Pb-free (Pb) packages are available for selected devices. Updated Table 75 and Figure 21 for I/O vs. Input pin counts. Minor updates to text. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS557-4 (v3.2) November 19, 2009 Product Specification www.xilinx.com 111 R Pinout Descriptions www.xilinx.com 112 DS557-4 (v3.2) November 19, 2009 Product Specification