NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on 64Mx8 DDR2 SDRAM Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx8 DDR2 SDRAM devices. * Performance: * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 14/10/2 Addressing * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 84-ball FBGA Package * RoHS Compliance PC2-3200 PC2-4200 PC2-5300 Speed Sort DIMM Latency fCK Clock Frequency tCK Clock Cycle fDQ DQ Burst Frequency 5A 37B Unit 3C 3 4 5 200 266 333 5 3.75 3 ns 400 533 667 MHz MHz * Intended for 200 MHz, 266MHz, and 333MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8V 0.1V * SDRAMs have 4 internal banks for concurrent operation * Module has one physical bank * Differential clock inputs * Data is read or written on both clock edges Description NT1GT64U8HA0BN is unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 128Mx64 high-speed memory array. Modules use sixteen 64Mx8 84-ball FBGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. The DIMM is intended for use in applications operating up to 200 MHz (266MHz, 333MHz) clock speeds and achieves high-speed data transfer rates of up to 400 MHz (533MHz, 667MHz). Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number Speed NT1GT64U8HA0BN -5A DDR2-400 PC2-3200 200MHz (5ns @ CL = 3) NT1GT64U8HA0BN -37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) NT1GT64U8HA0BN -3C DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) REV 1.1 11/2005 Organization Power Leads Note 128Mx64 1.8V Gold Green 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Pin Description CK0, Differential Clock Inputs CKE0, CKE1 DQ0-DQ63 Clock Enable Row Address Strobe Bidirectional data strobes - Column Address Strobe Differential data strobes DM0-DM7 Write Enable , Data input/output DQS0-DQS7 Chip Selects Input Data Masks VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs A0-A12 Row Address Inputs A0-A9 Column Address Inputs VSS Column Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output ODT0, ODT1 Active termination control lines SA0, SA1 A10/AP NC VDDSPD Serial EEPROM positive power supply Ground Serial Presence Detect Address Inputs No Connect Pinout Pin Front 1 VREF 2 VSS 51 3 VSS 4 DQ4 53 5 DQ0 6 DQ5 7 DQ1 8 VSS 9 VSS 10 DM0 11 Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 57 DQ19 58 DQ23 107 BA0 108 157 DQ48 158 DQ52 59 VSS 60 VSS 109 110 159 DQ49 160 DQ53 12 VSS 61 DQ24 62 DQ28 111 112 VDD 161 VSS 162 VSS 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 114 ODT0 163 NC 164 CK1 15 VSS 16 DQ7 65 VSS 66 VSS 115 116 (A13) 165 VSS 166 17 DQ2 18 VSS 67 DM3 68 117 VDD 118 VDD 167 168 VSS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 ODT1 120 NC 169 DQS6 170 DM6 21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS 30 CK0 79 CKE0 80 CKE1 129 130 DM4 179 DQ56 180 DQ60 29 VDD 31 DQS1 32 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 (A15) 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 (BA2) 86 (A14) 135 DQ34 136 DQ39 185 DM7 186 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 49 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.1 11/2005 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Input/Output Functional Description Symbol Type Polarity Function - (SSTL) Cross Point The system clock inputs. All the DDR2 SDRAM address and control inputs are sampled on the cross point of the rising edge of CK and falling edge of CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, to be executed by the SDRAM. CK0 - CK2, , , VREF Supply , , define the operation Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A13 defines the row address when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 - A13 defines the column address when sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS7 - (SSTL) DM0 - DM7 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x64 DIMM configurations. Power and ground for the DDR2 SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pull-up. VDDSPD REV 1.1 11/2005 Supply Serial EEPROM positive power supply. 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Functional Block Diagram (1GB, 2Ranks, 64Mx8 DDR2 SDRAMs) DQS0 DQS4 DM0 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS D0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D8 DQS1 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS D12 DM5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS D1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D9 DQS2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D5 DQS D13 DQS6 DM6 DM2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS D2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D10 DQS3 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQS D14 DQS7 DM3 DM7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA1 A0-A13 Notes : DQS D3 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D11 BA0-BA1 : SDRAMs D0-D17 A0-A13 : SDRAMs D0-D17 : SDRAMs D0-D17 : SDRAMs D0-D17 : SDRAMs D0-D17 CKE : SDRAMs D0-D8 CKE : SDRAMs D9-D17 ODT : SDRAMs D0-D8 ODT : SDRAMs D9-D17 CKE0 CKE1 ODT0 ODT1 11/2005 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DM1 REV 1.1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 1. 2. 3. 4. 5. DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D7 VDDSPD VDDQ VDD VREF VSS VDDID DQ-to-I/O wiring may be changed within a byte. DQ/DQS/DM/CKE/CS relationships are maintained as shown. DQ/DQS/ resistors are 22 Ohms +/- 5% BAx, Ax, , , resistors are 5.1 Ohms +/- 5% Address and control resistors are 22 Ohms +/- 5% DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D15 Serial PD D0-D8 D0-D8 D0-D8 D0-D8 Strap : see Note 4 Serial PD SCL WP A0 SA0 A1 A2 SA1 SA2 SDA 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (Part 1 of 2) SPD Entry Value Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Serial PD Data Entry (Hexadecimal) DDR2400 DDR2533 DDR2667 DDR2400 DDR2533 DDR2667 -5A -37B -3C -5A -37B -3C 128 80 256 08 DDR2-SDRAM 08 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks 2 rank, Height = 30mm 61 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 18 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time from Clock at CL=4 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) 33 Address and Command Hold Time After Clock (tIH) 34 Data Input Setup Time Before Clock (tDS) 0.10 ns 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge delay (tRTP) 39 Reserved 0.6ns 05 3.75ns 3ns 50 3D 30 0.5ns 0.45ns 60 50 45 Non-Parity 00 SR/1x(7.8us) 82 X8 08 NA 00 Undefined 00 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) REV 1.1 11/2005 5ns <4.10mm 01 Regular SODIMM (67.6mm) 04 Normal DIMM 00 Support weak driver 01 03 5ns 3.75ns 3.75ns 50 3D 3D 0.6ns 0.5ns 0.5ns 60 50 50 5ns 50 512MB 0.35ns 0.25 ns 80 35 25 20 0.475 ns 0.375 ns 0.325ns 47 37 27 0.15 ns 0.05ns 15 10 10 0.175ns 27 22 0.2ns 17 15ns 10ns 7.5 ns Note 3C 7.5ns 28 1E 7.5ns 1E Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 60ns 3C 1E 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (Part 2 of 2) SPD Entry Value Byte Description Serial PD Data Entry (Hexadecimal) DDR2- DDR2- DDR2- DDR2- DDR2- DDR2- Note 400 533 667 400 533 667 -5A -37B -3C -5A -37B Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.35ns 0.30ns 0.25ns 23 1E 18 45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.40ns 0.35ns 2D 28 22 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 16C 18C 20C 43 4B 53 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 37C 47C 58C 25 2E 3A 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 27C 33C 39C 1B 21 27 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 30C 37C 44C 1E 25 2C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 23C 26C 38C 2E 34 4C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 30C 35C 37C 1E 23 25 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 35C 37C 40C 23 25 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 1.2 12 63 Checksum for Byte 0-62 Checksum Data 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 72 105ns -3C 42 8ns Module Manufacturing Location 92-255 Reserved NT1GT64U8HA0BN-5A NT1GT64U8HA0BN-37B NT1GT64U8HA0BN-3C REV 1.1 11/2005 80 N/A 1C 73-91 Module Part Number Note: 1. 69 00 3C 51 122C/W 7A 39C 23C 52 27 28C 17 53 1C FA Manufacturing code -- Module Part Number in ASCII -- Undefined -- FC 1 4E5431475436345538484130424E2D35412020 4E5431475436345538484130424E2D33374220 4E5431475436345538484130424E2D33432020 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Absolute Maximum Ratings Symbol VIN, VOUT VDD Rating Units Voltage on I/O pins relative to Vss Parameter -0.5 to +2.3 V Voltage on VDD pins relative to Vss -1.0 to +2.3 V Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V VDDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V TSTG Storage Temperature (Plastic) -55 to +100 C VDDQ Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tREFI = 3.9 s tCASE > 85C DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 0 0 V 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 VSS, VSSQ VREF Supply Voltage, I/O Supply Voltage Input Reference Voltage VTT Termination Voltage Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Input AC/DC logic level Symbol VIH (AC) Parameter Input High (Logic1) Voltage Min Max Units Notes VREF + 0.250 - V 1 1 VIL (AC) Input Low (Logic0) Voltage - VREF - 0.250 V VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 On Die Termination (ODT) Current Symbol IODTO IODTT Parameter Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING REV 1.1 11/2005 Min Max Units EMRS(1) State 5 7.5 mA/DQ A6=0, A2=1 2.5 3.75 mA/DQ A6=1, A2=0 10 15 mA/DQ A6=0, A2=1 5 7.5 mA/DQ A6=1, A2=0 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol Parameter/Condition PC2-3200 PC2-4200 PC2-5300 (5A) (37B) (3C) Unit Notes IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 776 800 1000 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 816 880 1120 mA 1 IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 80 80 80 mA 1 IDD2Q Precharge Quiet Stand by Current 400 640 640 mA 1 Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); IDD2N address and control inputs changing once per clock cycle 512 480 800 mA 1 IDD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 208 256 304 mA 1 IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 80 80 96 mA 1 IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 280 336 400 mA 1 Operating Current: one bank; Burst = 4; reads; continuous burst; address IDD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 896 960 1440 mA 1 Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 856 1000 1520 mA 1 1296 1520 1680 mA 1 80 80 80 mA 1 1456 1520 1760 mA 1 IDD5 Auto-Refresh Current: tRC = tRFC (MIN) IDD6 Self-Refresh Current: CKE 0.2V IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. Note: 1. Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.1 11/2005 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol -37B -3C Max. Min. Max. Min. -0.6 +0.6 -0.5 +0.5 -0.45 +0.45 DQS output access time from CK/ -0.5 +0.5 -0.45 +0.45 -0.4 +0.4 ns tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL - tCH or tCL - tCH or tCL - tCK tDQSCK DQ output access time from CK/ Max. Unit Min. tAC tCK Clock Cycle Time 5 8 3.75 8 3 8 ns DQ and DM input hold time 275 - 225 - 175 - ps tDS DQ and DM input setup time 150 - 100 - 100 - ps tIPW Input pulse width 0.6 - 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - 0.35 - tCK - tAC max - tAC max - tAC max ns tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max tAC min tAC max tAC min tAC max ns DQS-DQ skew (DQS & associated DQ signals) - 0.35 - 0.30 - 0.24 ns tQHS Data hold Skew Factor - 0.45 - 0.4 - 0.34 ns tQH Data output hold time from DQS tHP tQHS - tHP tQHS - tHP tQHS - ns Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - 2 - tCK tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK tWPRE Write preamble 0.35 - 0.35 - 0.35 - tCK tDQSQ tDQSS tDQSL,(H) tIH Address and control input hold time 475 - 375 - 275 - ps tIS Address and control input setup time 0.35 - 0.25 - 0.2 - ns tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK - tIS + tCK + tIH - tIS + tCK + tIH - ns tIS + tCK + tIH tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRFC Refresh to active/Refresh command time 105 105 105 ns Average Periodic Refresh Interval (85C < TCASE 95C) 3.9 3.9 3.9 s Average Periodic Refresh Interval (0C TCASE 85C) 7.8 7.8 7.8 s tREFI tRRD REV 1.1 Active bank A to Active bank B command 7.5 - 7.5 - 7.5 - Notes ns tDH tDIPW 11/2005 -5A Parameter ns 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol tCCD -5A Parameter Min. to -37B Max. Min. 2 tWR Write recovery time WR Write recovery time with Auto-Precharge 15 -3C Max. 2 - 15 Min. Max. 2 - 15 Unit tCK - ns tWR/tCK tWR/tCK tWR/tCK WR +tRP - WR +tRP - WR +tRP ns - tCK 10 - 7.5 - 7.5 - ns tDAL Auto precharge write recovery + precharge time tWTR Internal write to read command delay tRTP Internal read to precharge command delay 7.5 7.5 7.5 ns tXSNR Exit self refresh to a Non-read command tRFC +10 tRFC +10 tRFC +10 ns tXSRD Exit self refresh to a Read command 200 200 200 tCK Exit precharge power down to any Non- read command 2 - 2 - 2 - tCK tXARD Exit active power down to read command 2 - 2 - 2 - tCK tXARDS Exit active power down to read command 6-AL - 6-AL - 7-AL - tCK tXP Notes tCKE CKE minimum pulse width 3 - 3 - 3 - tCK tOIT OCD drive mode output delay 0 12 0 12 0 12 ns 2 2 2 2 2 2 tCK tAC tAC tAC tAC ODT tAOND tAON tAONPD tAOFD ODT turn-on delay ODT turn-on tAC(min) tAC(max) ns 2tCK + 2tCK + 2tCK + tAC(min) t t tAC(max) AC(min) tAC(max) AC(min) tAC(max) +2 +2 +2 +1 +1 +1 ns (min) ODT turn-on (Power down mode) ODT turn-off delay 2.5 (max) +1 (min) 2.5 2.5 (max) +1 2.5 +0.7 2.5 2.5 tCK ODT turn-off tAC(min) tAC(max) tAC(max) tAC(max) t t +0.6 AC(min) +0.6 AC(min) +0.6 ns tAOFPD ODT turn-off (Power down mode) 2.5tCK 2.5tCK 2.5tCK + + + tAC(min) tAC(min) tAC(min) t t t +2 +2 +2 AC(max) AC(max) AC(max) +1 +1 +1 ns tANPD ODT to power down entry latency tAXPD ODT power down exit latency tAOF 3 3 3 tCK 8 8 8 tCK Speed Grade Definition tRAS Row Active Time 40 70000 45 70000 45 70000 ns tRCD RAS to CAS delay 15 - 15 - 15 - ns tRC Row Cycle Time 55 - 60 - 60 - ns tRP Row Precharge Time 15 - 15 - 15 - ns REV 1.1 11/2005 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Package Dimensions (1GB, 2Ranks, 64Mx8 DDR2 SDRAMs) FRONT 67.60 30.00 20.00 6.00 4.00 63.60 (2X) 1.80 1 2.15 39 41 11.40 199 Detail A Detail B 4.20 47.40 2.70 2.45 BACK SIDE 3.80 MAX 1.00+/- 0.10 Detail B 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail A Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.1 11/2005 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64U8HA0BN (Green) 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Revision Log Rev Date 0.1 08/2004 Preliminary. Modification 0.2 03/2005 Add IDD data. 0.3 04/2005 Add AC timing spec. 0.4 06/2005 Add Part Number in SPD. 1.0 07/2005 Official Release. 1.1 11/2005 Update SPD code. Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c)2003 REV 1.1 11/2005 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.