MR25H40PU - Everspin Technologies, Inc.

MR25H40

4Mb Serial SPI MRAM

FEATURES

• No write delays

• Unlimited write endurance

• Data retention greater than 20 years

• Automatic data protection on power loss

• Fast, simple SPI interface with up to 40 MHz clock rate

• 3.0 to 3.6 Volt power supply range

• Low current sleep mode

• Industrial temperatures

• Small footprint 8-pin DFN RoHS-compliant package

• Easily mounted 8-pin DIP RoHS-compliant package

• Direct replacement for serial EEPROM, Flash, FeRAM

INTRODUCTION

The MR25H40 is a 4,194,304-bit magnetoresistive random access

memory (MRAM) device organized as 524,288 words of 8 bits. The

MR25H40 oers serial EEPROM and serial Flash compatible read/write

timing with no write delays and unlimited read/write endurance.

Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between

writes. The MR25H40 is the ideal memory solution for applications that must store and retrieve data and

programs quickly using a small number of I/O pins.

The MR25H40 is available in a small footprint 5 mm x 6 mm 8-pin DFN package and a 300 mil 8-pin DIP

package that is compatible with serial EEPROM, Flash, and FeRAM products.

The MR25H40 provides highly reliable data storage over a wide range of temperatures. The product is of-

fered with industrial temperature (-40° to +85 °C) options.

Document Number: MR25H40 Rev. 2, 1/2011

RoHS

CONTENTS

1. DEVICE PIN ASSIGNMENT......................................................................... 2

2. SPI COMMUNICATIONS PROTOCOL...................................................... 4

3. ELECTRICAL SPECIFICATIONS................................................................. 10

4. TIMING SPECIFICATIONS.......................................................................... 12

5. ORDERING INFORMATION....................................................................... 16

6. MECHANICAL DRAWING.......................................................................... 17

7. REVISION HISTORY...................................................................................... 19

How to Reach Us.......................................................................................... 19

Overview

The MR25H40 is a serial MRAM with memory array logically organized as 512Kx8 using the four pin inter-

face of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral inter-

face (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash

components allowing MRAM to replace these components in the same socket and interoperate on a shared

SPI bus. Serial MRAM oers superior write speed, unlimited endurance, low standby & operating power, and

more reliable data retention compared to available serial memory alternatives.

512Kb x 8

MRAM ARRAY

Instruction Decode

Clock Generator

Control Logic

Write Protect

HOLD

SCK

Instruction Register

Address Register

Counter

Data I/O Register

Nonvolatile Status

19 8

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

MR25H40

Document Number: MR25H40 Rev. 2, 1/2011

System Conguration

Single or multiple devices can be connected to the bus as show in Figure 1.2. Pins SCK, SO and SI are com-

mon among devices. Each device requires CS and HOLD pins to be driven seperately.

MOSI

MISO

MOSI = Master Out Slave In

MISO = Master In Slave Out

SCK

SCKSISO SCKSISO

HOLD

HOLD HOLDCS CS

SPI

Micro Controller EVERSPIN SPI MRAM 1 EVERSPIN SPI MRAM 2

Figure 1.2 System Conguration

Signal Name Pin I/O Function Description

CS 1 Input Chip Select An active low chip select for the serial MRAM. When chip select is high, the

memory is powered down to minimize standby power, inputs are ignored

and the serial output pin is Hi-Z. Multiple serial memories can share a com-

mon set of data pins by using a unique chip select for each memory.

SO 2 Output Serial Output The data output pin is driven during a read operation and remains Hi-Z at

all other times. SO is Hi-Z when HOLD is low. Data transitions on the data

output occur on the falling edge of SCK.

WP 3 Input Write Protect A low on the write protect input prevents write operations to the Status

VSS 4 Supply Ground Power supply ground pin.

SI 5 Input Serial Input All data is input to the device through this pin. This pin is sampled on the

rising edge of SCK and ignored at other times. SI can be tied to SO to create

a single bidirectional data bus if desired.

SCK 6 Input Serial Clock Synchronizes the operation of the MRAM. The clock can operate up to 40

MHz to shift commands, address, and data into the memory. Inputs are

captured on the rising edge of clock. Data outputs from the MRAM occur

on the falling edge of clock. The serial MRAM supports both SPI Mode 0

(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is

normally low. In Mode 3, the clock is normally high. Memory operation is

static so the clock can be stopped at any time.

HOLD 7 Input Hold A low on the Hold pin interrupts a memory operation for another task.

When HOLD is low, the current operation is suspended. The device will

ignore transitions on the CS and SCK when HOLD is low. All transitions of

HOLD must occur while CS is low.

VDD 8 Supply Power Supply Power supply voltage from +3.0 to +3.6 volts.

DEVICE PIN ASSIGNMENT MR25H40

Document Number: MR25H40 Rev. 2, 1/2011

HOLD

SCK

DD CS

HOLD

SCK

8-Pin DFN 8-Pin DIP

Figure 1.2 Pin Diagrams (Top View)

2. SPI COMMUNICATIONS PROTOCOL

MR25H40

Instruction Description Binary Code Hex Code Address Bytes Data Bytes

WREN Write Enable 0000 0110 06h 0 0

WRDI Write Disable 0000 0100 04h 0 0

RDSR Read Status Register 0000 0101 05h 0 1

WRSR Write Status Register 0000 0001 01h 0 1

READ Read Data Bytes 0000 0011 03h 3 1 to ∞

WRITE Write Data Bytes 0000 0010 02h 3 1 to ∞

SLEEP Enter Sleep Mode 1011 1001 B9h 0 0

WAKE Exit Sleep Mode 1010 1011 ABh 0 0

Table 2.1 Command Codes

4Document Number: MR25H40 Rev. 2, 1/2011

Status Register

The status register consists of the 8 bits listed in table 2.2. As seen in table 2.3, the Status Register Write

Disable bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide

hardware memory block protection. Bits BP0 and BP1 dene the memory block arrays that are protected

as described in table 2.4. The fast writing speed of MR25H40 does not require write status bits. The state of

bits 6,5,4, and 0 can be user modied and do not aect memory operation. All bits in the status register

are pre-set from the factory in the “0” state.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SRWD Don’t Care Don’t Care Don’t Care BP1 BP0 WEL Don’t Care

Table 2.2 Status Register Bit Assignments

MR25H40 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For

both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling

edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The

memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS

falls.

All memory transactions start when CS is brought low to the memory. The rst byte is a command code. De-

pending upon the command, subsequent bytes of address are input. Data is either input or output. There

is only one command performed per CS active period. CS must go inactive before another command can

be accepted. To ensure proper part operation according to specications, it is necessary to terminate each

access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or

aborted accesses.

SPI COMMUNICATIONS PROTOCOL MR25H40

5Document Number: MR25H40 Rev. 2, 1/2011

WEL SRWD WP Protected Blocks Unprotected Blocks Status

0 X X Protected Protected Protected

1 0 X Protected Writable Writable

1 1 Low Protected Writable Protected

1 1 High Protected Writable Writable

Table 2.3 Memory Protection Modes

Status Register Memory Contents

BP1 BP0 Protected Area Unprotected Area

0 0 None All Memory

0 1 Upper Quarter Lower Three-Quarters

1 0 Upper Half Lower Half

1 1 All None

Table 2.4 Block Memory Write Protection

Read Status Register (RDSR)

The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can

be read at any time to check the status of write enable latch bit, status register write protect bit, and block

write protect bits. For MR25H40, the write in progress bit (bit 0) is not written by the memory because

there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and

then driving CS high.

Figure 2.1 RDSR

SCK

Status Register Out

High Impedance High Z

Mode 3

Mode 0

10 2 3 4 5 6 7 0 1 2 3 4 5 6 7

00000101

MSB

76543210

Block Protection

The memory enters hardware block protection when the WP input is low and the Status Register Write Dis-

able (SRWD) bit is set to 0. The memory leaves hardware block protection only when the WP pin goes high.

While WP is low, the write protection blocks for the memory are determined by the status register bits BP0

and BP1 and cannot be modied without taking the WP signal high again.

If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection

mode. This means that block write protection is controlled solely by the status register BP0 and BP1 block

write protect bits and this information can be modied using the WRSR command.

SCK

Instruction (04h)

High Impedance

Mode 3

Mode 0

Mode 3

Mode 0

10 234567

00000100

6Document Number: MR25H40 Rev. 2, 1/2011

SPI COMMUNICATIONS PROTOCOL MR25H40

Write Status Register (WRSR)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. The

WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a

WREN command while pin WP and bit SRWD correspond to values that make the status register writable

as seen in table 2.3. Status Register bits are non-volatile with the exception of the WEL which is reset to 0

upon power cycling.

The WRSR command is entered by driving CS low, sending the command code and status register write

data byte, and then driving CS high.

Write Enable (WREN)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The

Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN

command is entered by driving CS low, sending the command code, and then driving CS high.

SCK

Instruction (06h)

High Impedance

Mode 3

Mode 0

Mode 3

Mode 0

10 234567

00000110

Write Disable (WRDI)

The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 7).

This prevents writes to status register or memory. The WRDI command is entered by driving CS low, send-

ing the command code, and then driving CS high.

The Write Enable Latch (WEL) is reset on power-up or when the WRDI command is completed.

Figure 2.3 WRDI

Figure 2.2 WREN

7Document Number: MR25H40 Rev. 2, 1/2011

SPI COMMUNICATIONS PROTOCOL MR25H40

Figure 2.4 WRSR

SCK

Status Register In

High Impedance

Mode 3

Mode 0

Instruction (01h)

0000000176543210

MSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Read Data Bytes (READ)

The Read Data Bytes (READ) command allows data bytes to be read starting at an address specied by the

24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are read out sequen-

tially from memory until the read operation is terminated by bringing CS high The entire memory can be

read in a single command. The address counter will roll over to 0000h when the address reaches the top of

memory.

The READ command is entered by driving CS low and sending the command code. The memory drives the

read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-

nated by bringing CS high.

Figure 2.5 READ

SCK

24-Bit Address

High Impedance

Instruction (03h)

Data Out 1 Data Out 2

0 0 0 0 0 0 1 1 212223 3

765432107

210

MSB

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SPI COMMUNICATIONS PROTOCOL MR25H40

8Document Number: MR25H40 Rev. 2, 1/2011

Write Data Bytes (WRITE)

The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specied by

the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are written sequen-

tially in memory until the write operation is terminated by bringing CS high. The entire memory can be

written in a single command. The address counter will roll over to 0000h when the address reaches the top

of memory.

Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock

speed without write delays or data polling. Back to back WRITE commands to any random location in mem-

ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or

block organized memory so it is ideal for both program and data storage.

The WRITE command is entered by driving CS low, sending the command code, and then sequential write

data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS

high.

Figure 2.6 WRITE

SCK

24-Bit Address

High Impedance

Instruction (02h)

00000010232221 321076543210

MSB MSB

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SCK

Data Byte 3

High Impedance

Data Byte NData Byte 2

34 210 76543210

MSB

76543210765

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3

Mode 0

SPI COMMUNICATIONS PROTOCOL MR25H40

9Document Number: MR25H40 Rev. 2, 1/2011

Enter Sleep Mode (SLEEP)

The Enter Sleep Mode (SLEEP) command turns o all MRAM power regulators in order to reduce the overall

chip standby power to 15 μA typical. The SLEEP command is entered by driving CS low, sending the com-

mand code, and then driving CS high. The standby current is achieved after time, tDP

. If power is removed

when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid

command following SLEEP mode entry is a WAKE command.

Exit Sleep Mode (WAKE)

The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.

The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.

The memory returns to standby mode after tRDP

. The CS pin must remain high until the tRDP period is over.

WAKE must be executed after sleep mode entry and prior to any other command.

Figure 2.7 SLEEP

Figure 2.8 WAKE

SCK

Standby CurrentActive Current

Mode 3

Mode 0

Sleep Mode Current

Instruction (B9h)

10111001

01234567

SCK

Sleep Mode Current

Mode 3

Mode 0

Standby Current

Instruction (ABh)

10101011

01234567

RDP

3. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or

electric elds; however, it is advised that normal precautions be taken to avoid application of any voltage

greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic elds. Precautions should be taken to avoid

application of any magnetic eld more intense than the eld intensity specied in the maximum ratings.

Parameter Symbol Value Unit

Supply voltage2VDD -0.5 to 4.0 V

Voltage on any pin2VIN -0.5 to VDD + 0.5 V

Output current per pin IOUT ±20 mA

Package power dissipation PD0.600 W

Temperature under bias

MR25H40C (Industrial) TBIAS -45 to 95 °C

Storage Temperature Tstg -55 to 150 °C

Lead temperature during solder (3 minute max) TLead 260 °C

Maximum magnetic eld during write Hmax_write 12,000 A/m

Maximum magnetic eld during read or standby Hmax_read 12,000 A/m

1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-

tion should be restricted to recommended operating conditions. Exposure to excessive voltages or

magnetic elds could aect device reliability.

2 All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more

than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited

to less than 20mA.

3 Power dissipation capability depends on package characteristics and use environment.

Table 3.1 Absolute Maximum Ratings1

MR25H40

Document Number: MR25H40 Rev. 2, 1/2011

Parameter Symbol Min Typical Max Unit

Power supply voltage VDD 3.0 3.6 V

Input high voltage VIH 2.2 - VDD + 0.3 V

Input low voltage VIL -0.5 - 0.8 V

Temperature under bias

MR25H40C (Industrial) TA-40 - 85 °C

Table 3.2 Operating Conditions

MR25H40

ELECTRICAL SPECIFICATIONS

Parameter Symbol Min Typical Max Unit

Input leakage current ILI - - ±1 μA

Output leakage current ILO - - ±1 μA

Output low voltage

(IOL = +4 mA)

(IOL = +100 μA)

VOL - - 0.4

VDD + 0.2

Output high voltage

(IOH = -4 mA)

(IOH = -100 μA)

VOH 2.4

VDD - 0.2

--V

Table 3.3 DC Characteristics

Table 3.4 Power Supply Characteristics

Parameter Symbol Typical Max Unit

Active Read Current (@ 1 MHz) IDDR 5.0 TBD mA

Active Read Current (@ 40 MHz) IDDR 12 TBD mA

Active Write Current (@ 1 MHz) IDDW 9.0 TBD mA

Active Write Current (@ 40 MHz) IDDW 28 TBD mA

AC Standby Current (CS High) ISB1 250 TBD μA

CMOS Standby Current (CS High) ISB2 90 TBD μA

Standby Sleep Mode Current (CS High) IZZ 15 TBD μA

MR25H40

4. TIMING SPECIFICATIONS

Table 4.1 Capacitance1

Parameter Symbol Typical Max Unit

Control input capacitance CIn - 6 pF

Input/Output capacitance CI/O - 8 pF

1 ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.

Table 4.2 AC Measurement Conditions

Figure 4.1 Output Load for Impedance Parameter Measurements

Figure 4.2 Output Load for all Other Parameter Measurements

Parameter Value Unit

Logic input timing measurement reference level 1.5 V

Logic output timing measurement reference level 1.5 V

Logic input pulse levels 0 or 3.0 V

Input rise/fall time 2 ns

Output load for low and high impedance parameters See Figure 4.1

Output load for all other timing parameters See Figure 4.2

Output

L= 1.5 V

RL= 50 Ω

ZD= 50 Ω

Output

435 Ω

590 Ω

30 pF

3.3 V

MR25H40

TIMING SPECIFICATIONS

Power-Up Timing

The MR25H40 is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time

from the time when VDD (min) is reached until the rst CS low to allow internal voltage references to become

stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up

sequence.

Parameter Symbol Min Typical Max Unit

Write Inhibit Voltage VWI 2.2 - TBD V

Startup Time tPU 400 - - μs

Table 4.3 Power-Up

VDD

(max)

VDD(min)

tPU

Time

Normal Operation

Chip Selection not allowed

Reset state

of the

device

Figure 4.3 Power-Up Timing

MR25H40

TIMING SPECIFICATIONS

Parameter Symbol Min Typical Max Unit

SCK Clock Frequency fSCK 0 - 40 MHz

Input Rise Time tRI - - 50 ns

Input Fall Time tRF - - 50 ns

SCK High Time tWH 11 - - ns

SCK Low Time tWL 11 - - ns

Synchronous Data Timing (See gure 4.4)

CS High Time tCS 40 - - ns

CS Setup Time tCSS 10 - - ns

CS Hold Time tCSH 10 - - ns

Data In Setup Time tSU 5 - - ns

Data In Hold Time tH 5 - - ns

Output Valid2tV 0 - 9 ns

Output Hold Time tHO 0 - - ns

HOLD Timing (See gure 4.5)

HOLD Setup Time tHD 10 - - ns

HOLD Hold Time tCD 10 - - ns

HOLD to Output Low Impedance tLZ - - 20 ns

HOLD to Output High Impedance tHZ - - 20 ns

Other Timing Specications

WP Setup To CS tWPS 5 - - ns

WP Hold From CS tWPH 5 - - ns

Sleep Mode Entry Time tDP 3 - - μs

Sleep Mode Exit Time tRDP 400 - - μs

Output Disable Time tDIS 12 - - ns

1 Operating Temperature Range, VDD=3.0 to 3.6 V, CL= 30 pF

2 Automotive tV is TBD.

Table 4.4 AC Timing Parameters1

Synchronous Data Timing

MR25H40

TIMING SPECIFICATIONS

Figure 4.5 HOLD Timing

SCK

HOLD

Figure 4.4 Synchronous Data Timing

SCK

High Impedance

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

CSS

tWL

CSH

tDIS

Document Number: MR25H40 Rev. 2, 1/201116

MR25H40

5. ORDERING INFORMATION

Figure 5.1 Part Numbering System

Part Number Description Temperature

MR25H40CDC 3 V 4Mb Serial MRAM 8-DFN Industrial

MR25H40CDCR 3 V 4Mb Serial MRAM 8-DFN Tape and Reel Industrial

MR25H40PU 3 V 4Mb Serial MRAM 8-DIP Tube Commercial

Table 5.1 Available Parts

Part markings do not indicate tray or tape and reel.

Package Options

DC 8 Pin DFN on Tray

DCR 8 Pin DFN on Tape and Reel

PU 8 Pin PDIP in Tube

Temperature Range

CIndustrial (-40 to +85 °C ambient)

Memory Density

40 4 Mb

Interface

25H High Speed Serial SPI Family

Product Type

MR Magnetoresistive RAM

MR 25H 40 C DC

NOTE:

1. Angles in degrees.

2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08 mm.

3. Warpage shall not exceed 0.10 mm.

4. Refer to JEDEC MO-229

6. MECHANICAL DRAWINGS

Document Number: MR25H40 Rev. 3, 3/201117

DAP Size

4.4 x 4.4

Detail A

Pin 1 Index

Figure 6.1 DFN Package

MR25H40

Exposed metal Pad. Do not

connect anything except VSS

Unit A B C D E F G H I J K L M N O

mm - Max

- Min

5.10

4.90

6.10

5.9

1.00

0.90

1.27

BSC

0.45

0.35

0.05

0.35

Ref.

0.70

0.50

4.20

4.00

4.20

4.00

0.261

0.195 C0.35 R0.20 0.211

0.195

0.05

MR25H40

Figure 6.2 DIP Package

PIN INDEX

Unit A B C D E F G H I J

mm - Max

- Min

10.16

9.14

6.60

6.10

3.56

3.05

1.02

0.38

3.56

3.04

0.53

0.38

2.79

2.29

8.26

7.62

9.40

8.13

0.30

0.20

inch - Max

- Min

0.40

0.36

0.26

0.24

0.14

0.12

0.04

0.02

0.14

0.12

0.02

0.01

0.11

0.09

0.33

0.30

0.37

0.32

0.008

0.012

Reference JEDEC MO-001

MR25H40

Document Number: MR25H40 Rev. 2, 1/201119

Revision Date Description of Change

0 Jan 15, 2010 Product Concept Release

0 .1 Feb. 23, 2010 Fixed typos in text.

1 May 5, 2010 Removed commercial specications. All parts meet industrial specications.

2 Jan 11, 2011 Preliminary Product Release. Updated description of status register non-volatility, WAKE

command, Table 3.4.

7. REVISION HISTORY

Information in this document is provided solely to enable system and software implementers to use

Everspin Technologies products. There are no express or implied licenses granted hereunder to design or

fabricate any integrated circuit or circuits based on the information in this document. Everspin Technolo-

gies reserves the right to make changes without further notice to any products herein. Everspin makes no

warranty, representation or guarantee regarding the suitability of its products for any particular purpose,

nor does Everspin Technologies assume any liability arising out of the application or use of any product or

circuit, and specically disclaims any and all liability, including without limitation consequential or inci-

dental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/

or specications can and do vary in dierent applications and actual performance may vary over time. All

operating parameters including “Typicals” must be validated for each customer application by customer’s

technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights

of others. Everspin Technologies products are not designed, intended, or authorized for use as compo-

nents in systems intended for surgical implant into the body, or other applications intended to support

or sustain life, or for any other application in which the failure of the Everspin Technologies product

could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin

Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and

hold Everspin Technologies and its ocers, employees, subsidiaries, aliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or

indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,

even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture

of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other

product or service names are the property of their respective owners.

How to Reach Us:

Home Page:

www.everspin.com

E-Mail:

support@everspin.com

orders@everspin.com

sales@everspin.com

USA/Canada/South and Central America

Everspin Technologies

1300 N. Alma School Road, CH-409

Chandler, Arizona 85224

+1-877-347-MRAM (6726)

+1-480-347-1111

Europe, Middle East and Africa

support.europe@everspin.com

Japan

support.japan@everspin.com

Asia Pacic

support.asia@everspin.com

Document Control Number:

EST00429_M25H40 Revision 2.5 5/2011

File Name:

EST_MR25H40_prod.pdf

Preliminary - This is a product in development that has xed target specications that are subject to change pending characterization results.