Hitachi 16-Bit Single-Chip Microcomputer
H8S/2194 Series, H8S/2194C Series,
H8S/2194 F-ZTAT™, H8S/2194C F-ZTAT™
H8S/2194, HD6432194, HD64F2194,
H8S/2193, HD6432193
H8S/2192, HD6432192
H8S/2191, HD6432191
H8S/2194C, HD6432194C, HD64F2194C,
H8S/2194B, HD6432194B
H8S/2194A, HD6432194A
Hardwa re Manu al
ADE-602-160A
Rev. 2. 0
11/10/00
Hitachi, Ltd.
Cautions
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However, contact Hitachi’s sa les office before using the product in an application that
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Rev. 2.0, 11/00, page I of V
M ain Revi sion s and Ad ditions in this Edition
Page Ite m Revisions (See Manual for Details)
All pages of
this manual Amendment s due t o introduction of the H8S/ 2194C
series
5 1.1 Overview Table 1. 1 Features
Memory and Product lineup amended
14 1.4 Differ ences between
H8S/2194C Series and
H8S/2194 Series
Added
All pages of
section 2 Notes on TAS inst ruction added
31 2.6.1 Overview Table 2.1 Instruction Classification
Notes 3 added
65, 66 3.4 Address Map in Each
Operating Mode Address maps f or the H8S/2194C series added
68 4.1 Overview Table 4.1 Internal Chip Status in Each Mode
Timer L, PSU, 12- bit PWM added
Sleep and Watch modes of I/O amended
79 4.4.1 Sleep Mode Descript ion amended
Other supporting m odules (excluding the servo
circuit and 12-bit PWM) do not st op.
80 4.5.1 Module Stop Mode Table 4. 4 MSTP Bits and Corresponding On-Chip
Supporting Module s
Module corresponding t o t he MSTP1 bit amended
119 6.4.5 Interrup t Respons e
Times Table 6.8 Interrupt Response Times
Note 2 amended
121 6.5.4 When NMI is Disabled Added
126 Figure 7.3 Flash Memory Mode Transit ions
Amended
127
7.2.3 Flash Memory
Operating Modes Fig ure 7.4 Boot M ode
Amended
131 7.3.1 Flash M emory Control
Register 1 (FLMCR1) Descript ion amended
FLM CR1 is initialize d by a reset, in power- d o wn
state (excluding the medium -spee d mode , modul e
stop mode, and sleep m ode), or when a low level is
input to t he FWE pin.
Rev. 2.0, 11/00, page II of V
Page Ite m Revisions (See Manual for Details)
134 7.3.2 Flash M emory Control
Register 2 (FLMCR2) Descript ion amended
The ESU and PSU bits ar e cleared to 0 in power-
down state (excluding the medi um -speed mode ,
module stop mode, and sleep mode), hardware
protect mode, and software protect mode.
Descript ion amended
EBR1 and EBR2 are each initialized t o H’00 by a
reset, in power- down stat e (excluding the medium -
speed mode, module sto p mode , and sleep mode),
when a low level is input to the FWE pin, or when a
high level is input to the FWE pin and the SWE bit in
FLM CR1 is not set.
136 7.3.3 Erase Block Registers 1
and 2 (EBR1, EBR2)
Table 7. 4 Flash Mem ory Erase Blocks
EB3 address am ended
138 7.4 On-Board Progra m ming
Modes Table 7.5 Sett ing On-Board Programm ing Modes
MD0 pin level in use pr ogram mode am ended
140 Figure 7.8 Boot Mode Execution Procedure
Flow amended
141 Table 7.6 System Clock Frequencies f or which
Automatic Adjustment of This LSI Bit Rate is
Possible
2400-bps transfer bit rate deleted
142
7.4.1 Boot Mode
Figure 7.10 RAM Areas in Boot Mode
Programming control pr ogram ar ea amended
145 7.5.1 Program Mode Descript ion amended
(For det ails, see the flowchart in f igur e 7. 12.)
146 7.5.2 Program - Verify Mode Descript ion amended
(For det ails, see the flowchart in f igur e 7. 12.)
7.5.3 Erase Mode Descript ion amended
(For det ails, see the flowchart in f igur e 7. 13.)
148
7.5.4 Erase-Verif y Mode Descript ion amended
(For det ails, see the flowchart in f igur e 7. 13.)
150 7.6.1 Hardwar e Protect ion Table 7. 7 Hardware Pr otection
Reset/standby protection descript ion amended
152 7.6.3 Error Protection FLER bit setting condition (3) amended
Figure 7.14 Flash Memory State Transitions
amended
153 7.7 Interrupt Handling when
Programming/Erasing Flash
Memory
Note 1 amended
154 7.8.2 Socket Adapters and
Me mo ry Map Table 7. 9 Socket Adapter Product Codes
amended
Rev. 2.0, 11/00, page III of V
Page Ite m Revisions (See Manual for Details)
166 7.8.9 Program mer Mode
Tran s it io n Time Figur e 7.2 3 Os c illa tion Stabiliza tion Time, Bo ot
Program Transfer Time, and Power Supply Fall
Sequence
Vcc timing amended
169 7.10 Note on Switching fr om
F-ZTAT Version t o Mask ROM
Version
Added
Section 8 ROM (H8S/2194C
Series) Added
221 9.1 Overview Descr iption amended due to intr oduction of the
H8S/2194C series
304 14.1.2 Block Diagram Figure 14.1 Block Diagram of the Tim er J
φ/1024 clock source (for H8S/2194C series) added
308 14.2.1 Timer M ode Regist er J
(TMJ) Bits 3 and 2
Descript ion amended
311, 312 14.2.2 Time r J Control
Register (TM JC) Bit 0 description amended
336 16.2.1 Timer R Mode
Register 1 (TMRM1) Bit 0 description amended
416 20.2.1 12-Bit PWM Control
Registers (CPWCR, DPWCR) Initialization description amended
419 20.2.2 12-Bit PWM Data
Registers (CPWDR, DPWDR) Initialization description amended
420 20.2.3 Module stop Contr ol
Register (MSTPCR) Added
443 23.1.2 Block Diagram Figure 23.1 Block Diagram of SCI1
Register names am ended
454 23.2.7 Serial Status Regist er
(SSR1) Bit 7:
Clearing conditions amended
520 25.1.4 Register Configur ation Table 25. 2 Register Conf igurat ion
Note 2 de scription amended
522 25.2.1 I2C Bus Data Register
(ICDR) Descript ion amended
531,
534 to 536 25.2.5 I2C Bus Control
Register (ICCR) Bit 7 description amended
Bit 1 description amended
541 25.2.6 I2C Bus Status
Register (ICSR) Bit 4 descr iption amended
544 25.2.7 Serial/Tim er Cont rol
Register (STCR) Bit 5 description amended
Rev. 2.0, 11/00, page IV of V
Page Item Revisions (See Manual for Details)
547 to 549 25.3.2 Master Transmit
Operation
550 to 552 25.3.3 Master Receive
Operation
556 25.3.5 Slave Transmit
Operation
Description amended
561 Figure 25.14 Flowchart for Master Transmit Mode
(Example) amende d
562
25.3.8 Sample Flowcharts
Figure 25.15 Flowchart for Master Receive Mode
(Example) amende d
565, 566 25.3.9 Initialization of Internal
State Added
570 to 572 25.4 Usage Notes Description (7) to (9) added
604 27.3.7 RTS Instruction Figure 27.15 RTS Instruction
Description amended
Stack storing
613 28.1.2 Block Diagram Figure 28.1 Block Diagram of Servo Circuits
Amended
624 28.2.5 Register Descriptions (5) CTL Gain Control Register (CTLGR)
Bits 3 to 0: CTL Amplifier Gain Setting Bits
(CTLGR3 to 0) values of CTL output gain amended
627 28.3.2 Block Diagram Figure 28.6 REF30 Signal Generator
amended
634 28.3.4 Register Descriptions (5) Reference Period Mode Register 2 (RFM2)
Bit 7: TBC Selection Bit
Description amended
663, 664 28.4.5 Register Descriptions (4) FIFO Output Pattern Register 1 (FPDRA)
(5) FIFO Output Pattern Register 2 (FPDRB)
Descriptions of bits in these registers added
667, 668 28.4.5 Register Descriptions (9) DFG Reference Register 2 (DFCRB)
Descriptions of bits 4 to 0 added
(11) DFG Reference Count Register (DFCTR)
Initial value of bit 4 to 0 amended and descriptions
added
669, 670 28.4.6 Description of
Operation Completely Amended
688 28.6.4 Register Descriptions (5) Drum Speed Error Detection Control Register
(DFVCR)
Descriptions of bits 1 and 0 amended
Rev. 2.0, 11/00, page V of V
Page Ite m Revisions (See Manual for Details)
708 28.8.4 Register Descript ions (5) Capst an Speed Error Detection Control Regist er
(CFVCR)
Descript ions of bits 1 and 0 am ended
745 28.12.5 Additional V Pulse
Signal Figure 28. 46 Additional V Pulse Negat ive Polarity
is Spec ified
Value of POL amended
761 28.13.5 Register Descriptions (8) Duty I/O Register (DI/O)
Descript ions of ASM Mark Detect Mode amended
769 28.13.8 Duty Discriminator Values of duty amended
780 28.14.2 CTL Frequency
Divider Figur e 28.63 CTL Frequency Divider amended
817 28.17 Module Stop Contr ol
Register (MSTPCR) Added
819 to 860 29 Electrical Characteristics Descript ion amended due t o introduct ion of the
H8S/2194C series
861 to 909 Appendix A Instr uction Set Not es on TAS instruction added
917 to 1017 B.2 Function List Following list of registers amended
H’D097: RFM2
H’D0A4: CTLGR
H’D13A: TMJ
H’D13B: TMJC
H’D148: SMR1
H’D14C: SR1
H’D158: ICCR
H’D159: ICSR
H’FFF8: FLMCR1
H’FFF9: FLMCR2
H’FFFA: EBR1
H’FFFB: EBR2
1019 to 1031 C.1 Pin Circuit Diagrams Table C.1 Pin Circuit Diagrams
Com p lete ly am en ded
Figure E. 3 Sample Ext ernal Circuit for Ser vo
Section
Amended
1035 E.3 Sample External Circuits
Figure E. 4 Example of External Circuit f or Sync
Signal Det ection Circuit Section
Amended
1036 Appendix F List of Product
Codes Figure F. 1 Product Codes List of H8S/2194 ser ies
and H8S/2194C series
Rev. 2.0, 11/00, page i of xviii
Contents
Section 1 Overview........................................................................................ 1
1.1 Overview.....................................................................................................................1
1.2 Internal Block Diagram................................................................................................ 6
1.3 Pin Arrangement and Functions .................................................................................... 7
1.3.1 Pin Arrangement ............................................................................................. 7
1.3.2 Pin Functions................................................................................................... 8
1.4 Differences between H8S/2194C Series a nd H8S/2194 Se ries....................................... 14
Section 2 CPU ............................................................................................... 15
2.1 Overview.....................................................................................................................15
2.1.1 Features........................................................................................................... 15
2.1.2 Differences bet ween H8S/2600 CPU a nd H8S/2000 CPU................................. 16
2.1.3 Differences from H8/300 CPU......................................................................... 16
2.1.4 Differences from H8/300H CPU...................................................................... 17
2.2 CPU Operating Modes................................................................................................. 18
2.3 Address Space.............................................................................................................. 23
2.4 Register Configuration................................................................................................. 24
2.4.1 Overview......................................................................................................... 24
2.4.2 General Registers ............................................................................................ 25
2.4.3 Control Registe rs............................................................................................. 26
2.4.4 Initial Register Values ..................................................................................... 27
2.5 Data Formats ............................................................................................................... 28
2.5.1 General Register Data Formats ........................................................................ 28
2.5.2 Memory Data Formats..................................................................................... 30
2.6 Instruction Set..............................................................................................................31
2.6.1 Overview......................................................................................................... 31
2.6.2 Instructions and Addressing Modes .................................................................. 32
2.6.3 Table of Instructions Classified by Function..................................................... 33
2.6.4 Basic Instruction Formats ................................................................................ 43
2.6.5 Notes on Use of Bit-Manipulation Instructions................................................. 44
2.7 Addressing Mod es and Effec tiv e Address Calcu lation .................................................. 45
2.7.1 Addressing Mode ............................................................................................ 45
2.7.2 Effective Address Calculation .......................................................................... 48
2.8 Processing States.......................................................................................................... 52
2.8.1 Overview......................................................................................................... 52
2.8.2 Reset State....................................................................................................... 53
2.8.3 Exception-Ha ndling State ................................................................................ 54
2.8.4 Progra m Exe cut ion State.................................................................................. 55
2.8.5 Power-Down State........................................................................................... 56
Rev. 2.0, 11/00, page ii of xviii
2.9 Bas ic Ti min g............................................................................................................... 57
2.9.1 Overview ........................................................................................................ 57
2.9.2 On-Chip Memory (ROM, RAM)...................................................................... 57
2.9.3 On-Chip Supporting Module Ac cess Ti ming.................................................... 58
2.10 Usage Note..................................................................................................................58
Section 3 MCU Operating Modes.................................................................. 59
3.1 Overview.....................................................................................................................59
3.1.1 Operating Mode Selection ............................................................................... 59
3.1.2 Regi ster Configuration..................................................................................... 59
3.2 Register Descriptions................................................................................................... 60
3.2.1 Mode Control Register (MD CR)...................................................................... 60
3.2.2 System Control Register (SYSCR)................................................................... 60
3.3 Operating Mode Descriptions....................................................................................... 62
3.3.1 Mo d e 1............................................................................................................ 62
3.4 Address Map................................................................................................................ 63
Section 4 Power-Down State ......................................................................... 67
4.1 Overview.....................................................................................................................67
4.1.1 Regi ster Configuration..................................................................................... 71
4.2 Register Descriptions................................................................................................... 72
4.2.1 Standby Cont rol Register (SBYCR)................................................................. 72
4.2.2 Low-Power Control Register (LPWRCR) ........................................................ 74
4.2.3 Timer Register A (TMA)................................................................................. 76
4.2.4 Module Stop Control Register (MSTPCR)....................................................... 77
4.3 Medium-Speed Mode ................................................................................................... 78
4.4 Sleep Mode .................................................................................................................. 79
4.4.1 Sleep Mode..................................................................................................... 79
4.4.2 Clearing Sleep Mode....................................................................................... 79
4.5 Module Stop Mode ...................................................................................................... 80
4.5.1 Module Stop Mode.......................................................................................... 80
4.6 Standby Mode .............................................................................................................. 81
4.6.1 Standby Mode ................................................................................................. 81
4.6.2 Clearing Standby Mode................................................................................... 81
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode ........................ 81
4.7 Watch Mode................................................................................................................ 83
4.7.1 Watch Mode.................................................................................................... 83
4.7.2 Clearing Wa tch Mode...................................................................................... 83
4.8 Subsleep Mode ............................................................................................................ 84
4.8.1 Subsleep Mode................................................................................................ 84
4.8.2 Clearing Subsleep Mode.................................................................................. 84
4.9 Subactive Mode........................................................................................................... 85
4.9.1 Subactive Mode ............................................................................................... 85
Rev. 2.0, 11/00, page iii of xviii
4.9.2 Clearing Subactive Mode................................................................................. 85
4.10 D ir ect Trans ition.......................................................................................................... 86
4.10.1 Overview of Direct Transition ......................................................................... 86
Section 5 Exception Handling........................................................................ 87
5.1 Overview.....................................................................................................................87
5.1.1 Exception Handling Types and Priority............................................................ 87
5.1.2 Exception Handling Operation......................................................................... 88
5.1.3 Exception Sources and Vector Table................................................................ 88
5.2 Reset ........................................................................................................................... 90
5.2.1 Overview......................................................................................................... 90
5.2.2 Reset Sequence................................................................................................ 90
5.2.3 Interrupts after Reset ....................................................................................... 91
5.3 Interrupts..................................................................................................................... 92
5.4 Trap Instruction ........................................................................................................... 93
5.5 Stack Status after Exception Handling.......................................................................... 94
5.6 Notes on Use of the Stack ............................................................................................ 95
Section 6 Interrupt Controller ......................................................................... 97
6.1 Overview.....................................................................................................................97
6.1.1 Features........................................................................................................... 97
6.1.2 Block Diagram................................................................................................ 98
6.1.3 Pin Configuration............................................................................................ 99
6.1.4 Regi ster Configuration..................................................................................... 99
6.2 Register Descriptions................................................................................................... 100
6.2.1 System Control Register (SYSCR) ................................................................... 100
6.2.2 Inte rrupt Control Regi sters A to D (ICRA to ICRD)......................................... 101
6.2.3 IRQ Enable Register (IENR)............................................................................ 102
6.2.4 IRQ Edge Select Registers (IEGR)................................................................... 103
6.2.5 IRQ Status Register (IRQR) ............................................................................. 104
6.2.6 Port Mode Register (PMR1) ............................................................................ 105
6.3 Interrupt Sources.......................................................................................................... 106
6.3.1 External Interrup ts........................................................................................... 106
6.3.2 Inte rnal Inte rrupts............................................................................................ 108
6.3.3 Interrupt Exception Vector Table..................................................................... 108
6.4 Interrupt Operation....................................................................................................... 111
6.4.1 Interrupt Control Modes and Interrupt Operation.............................................. 111
6.4.2 Interrupt Control Mode 0................................................................................. 113
6.4.3 Interrupt Control Mode 1................................................................................. 115
6.4.4 Interrupt Exception Handling Sequence ........................................................... 118
6.4.5 Inte rrupt Response Times ................................................................................ 119
6.5 Usage Notes................................................................................................................. 120
6.5.1 Contention between Int errupt Generation and Disabling................................... 120
Rev. 2.0, 11/00, page iv of xviii
6.5.2 Instructions that Disa ble Interrupts................................................................... 121
6. 5.3 Inte r rupt s durin g Exec uti o n of EEPMOV Instr uction........................................ 121
6.5.4 When NMI is Disabled.................................................................................... 121
Section 7 ROM (H8S/2194 Series) ................................................................ 123
7.1 Overview..................................................................................................................... 123
7.1.1 Block Diagram................................................................................................ 123
7.2 Overview of Flash Memory.......................................................................................... 124
7.2.1 Features........................................................................................................... 124
7.2.2 Block Diagram................................................................................................ 125
7.2.3 Flash Memory Opera ting Modes...................................................................... 126
7.2.4 Pin Configuration............................................................................................ 130
7.2.5 Regi ster Configuration..................................................................................... 130
7.3 Flash Memory Register De scriptions............................................................................ 131
7.3.1 Flash Memory Control Register 1 (FLMCR1).................................................. 131
7.3.2 Flash Memory Control Register 2 (FLMCR2).................................................. 134
7.3.3 Era se Bl ock Re gisters 1 and 2 (EBR1, EBR2).................................................. 136
7.3.4 Serial/Timer Control Register (STCR)............................................................. 137
7.4 On-Board Programming Modes.................................................................................... 138
7.4.1 Boot Mode...................................................................................................... 139
7.4.2 User Progra m Mode ........................................................................................ 144
7.5 Programming/Erasing Fla sh Memory ........................................................................... 145
7.5.1 Program Mode................................................................................................. 145
7.5.2 Program-Verify Mode ..................................................................................... 146
7.5.3 Erase Mode..................................................................................................... 148
7.5.4 Erase-Verify Mode.......................................................................................... 148
7.6 Flash Memory Protection............................................................................................. 150
7.6.1 Hardware Protection........................................................................................ 150
7.6.2 Software Protection......................................................................................... 151
7.6.3 Error Prote ction............................................................................................... 152
7.7 Interrupt Handling when Programming/E rasing Fla sh Memory..................................... 153
7.8 Flash Memory Programmer Mode................................................................................ 154
7.8.1 Programmer Mode Sett ing............................................................................... 154
7.8.2 Socket Adapters and Memory Map.................................................................. 154
7.8.3 Programmer Mode Operation........................................................................... 155
7.8.4 Memory Read Mode........................................................................................ 157
7.8.5 Auto-Program Mode........................................................................................ 160
7.8.6 Auto-Erase Mode ............................................................................................ 162
7.8.7 Status Read Mode ............................................................................................ 163
7.8.8 Status Polling.................................................................................................. 165
7.8.9 Programmer Mode Tra nsition Time................................................................. 166
7.8.10 Notes On Memory Programming..................................................................... 166
7.9 Flash Memory Programming and Erasi ng Preca utions .................................................. 167
Rev. 2.0, 11/00, page v of xviii
7.10 Note on Switching from F-ZTAT Version to Mask ROM Version................................. 169
Section 8 ROM (H8S/2194C Series)..............................................................171
8.1 Overview..................................................................................................................... 171
8.1.1 Block Diagram................................................................................................ 171
8.2 Overview of Flash Memory .......................................................................................... 172
8.2.1 Features........................................................................................................... 172
8.2.2 Block Diagram................................................................................................ 173
8.2.3 Flash Memory Opera ting Modes...................................................................... 174
8.2.4 Pin Configuration............................................................................................ 178
8.2.5 Regi ster Configuration..................................................................................... 178
8.3 Flash Memory Register De scriptions............................................................................ 179
8.3.1 Flash Memory Control Register 1 (FLMCR1).................................................. 179
8.3.2 Flash Memory Control Register 2 (FLMCR2).................................................. 182
8.3.3 Erase Block Registers 1 (EBR1) ...................................................................... 185
8.3.4 Erase Block Registers 2 (EBR2) ...................................................................... 185
8.3.5 Serial/Timer Control Register (STCR) ............................................................. 187
8.4 On-Board Programming Modes.................................................................................... 188
8.4.1 Boot Mode ...................................................................................................... 189
8.4.2 User Progra m Mode......................................................................................... 194
8.5 Programming/Erasing Fla sh Memory ........................................................................... 195
8.5.1 Program Mode (n = 1 for a ddresses H'0000 to H'1FFFF and n= 2
for addresse s H'20000 to H'3FFFF).................................................................. 195
8.5.2 Program-Verify Mode (n =1 for addre sse s H'00000 to H'1FFFF an d n = 2
for addresse s H'20000 to H'3FFFF).................................................................. 196
8.5.3 Erase Mode (n = 1 for addresses H' 00000 to H'1FFFF a nd n = 2
for address H' 20000 to H' 3FFFF)..................................................................... 198
8. 5.4 E r a se-Verify Mode (n = 1 for addresse s H'00000 to H'1 FFFF and n = 2
for address H' 20000 to H' 3FFFF)..................................................................... 198
8.6 Flash Memory Protection............................................................................................. 200
8.6.1 Hardware Protection........................................................................................ 200
8.6.2 Software Protection ......................................................................................... 201
8.6.3 Error Prote ction............................................................................................... 202
8.7 Interrupt Handling when Programming/E rasing Fla sh Memory..................................... 203
8.8 Flash Memory Programmer Mode................................................................................ 204
8.8.1 Programmer Mode Sett ing............................................................................... 204
8.8.2 Socket Adapters and Memory Map.................................................................. 204
8.8.3 Programmer Mode Operation........................................................................... 205
8.8.4 Memory Read Mode........................................................................................ 207
8.8.5 Auto-Program Mode........................................................................................ 210
8.8.6 Auto-Erase Mode ............................................................................................ 212
8.8.7 Status Read Mode............................................................................................ 213
8.8.8 Status Polling.................................................................................................. 215
Rev. 2.0, 11/00, page vi of xviii
8.8.9 Programmer Mode Tra nsition Time................................................................. 216
8.8.10 Notes On Memory Programming..................................................................... 216
8.9 Flash Memory Programming and Erasi ng Preca utions .................................................. 217
8.10 Note on Switching from F-ZTAT Version to Mask ROM Version ................................ 219
Section 9 RAM.............................................................................................. 221
9.1 Overview..................................................................................................................... 221
9.1.1 Block Diagram................................................................................................ 221
Section 10 Clock Pulse Generator.................................................................. 223
10.1 Overview..................................................................................................................... 223
10.1.1 Block Diagram................................................................................................ 223
10.1.2 Re gister Configuration..................................................................................... 223
10.2 Register Descriptions................................................................................................... 224
10.2.1 Sta ndby Control Registe r (SBYCR)................................................................. 224
10.2.2 Low-Power Control Register (LPWRCR) ........................................................ 225
10.3 Oscillator..................................................................................................................... 226
10.3.1 Connecting a Crystal Resonator....................................................................... 226
10.3.2 Externa l Clock Input........................................................................................ 228
10.4 Duty Adjustment Circuit.............................................................................................. 231
10.5 Medium-Speed Clock Divider...................................................................................... 231
10.6 Bus Master Clock Selection Circuit.............................................................................. 231
10.7 Subclock Oscillator Circuit .......................................................................................... 232
10.7.1 Connecting 32.768 kHz Crystal Resonator....................................................... 232
10.7.2 Externa l Clock Input........................................................................................ 233
10.7.3 When Subclock is not Needed.......................................................................... 233
10.8 Subclock Waveform Shaping Ci rcuit............................................................................ 234
10.9 N o tes o n th e Resonator ................................................................................................ 234
Section 11 I/O Port........................................................................................ 235
11.1 Overview..................................................................................................................... 235
11.1.1 Port Functions................................................................................................. 235
11.1.2 Port Input........................................................................................................ 235
11. 1. 3 MOS Pull-Up Tran sisto r s ................................................................................ 237
11.2 Port 0........................................................................................................................... 238
11.2.1 Overview ........................................................................................................ 238
11.2.2 Re gister Configuration..................................................................................... 239
11.2.3 Pin Functions .................................................................................................. 240
11.2.4 Pin States ........................................................................................................ 240
11.3 Port 1........................................................................................................................... 241
11.3.1 Overview ........................................................................................................ 241
11.3.2 Re gister Configuration..................................................................................... 241
11.3.3 Pin Functions .................................................................................................. 245
Rev. 2.0, 11/00, page vii of xviii
11.3.4 Pin States ........................................................................................................ 246
11.4 Port 2 ........................................................................................................................... 247
11.4.1 Overview......................................................................................................... 247
11.4.2 Re gister Configuration..................................................................................... 247
11.4.3 Pin Functions................................................................................................... 251
11.4.4 Pin States ........................................................................................................ 253
11.5 Port 3 ........................................................................................................................... 254
11.5.1 Overview......................................................................................................... 254
11.5.2 Re gister Configuration..................................................................................... 254
11.5.3 Pin Functions................................................................................................... 258
11.5.4 Pin States ........................................................................................................ 260
11.6 Port 4 ........................................................................................................................... 261
11.6.1 Overview......................................................................................................... 261
11.6.2 Re gister Configuration..................................................................................... 261
11.6.3 Pin Functions................................................................................................... 264
11.6.4 Pin States ........................................................................................................ 266
11.7 Port 5 ........................................................................................................................... 267
11.7.1 Overview......................................................................................................... 267
11.7.2 Re gister Configuration..................................................................................... 267
11.7.3 Pin Functions................................................................................................... 271
11.7.4 Pin States ........................................................................................................ 272
11.8 Port 6 ........................................................................................................................... 273
11.8.1 Overview......................................................................................................... 273
11.8.2 Re gister Configuration..................................................................................... 274
11.8.3 Pin Functions................................................................................................... 277
11.8.4 Operation........................................................................................................ 278
11.8.5 Pin States ........................................................................................................ 279
11.9 Port 7 ........................................................................................................................... 280
11.9.1 Overview......................................................................................................... 280
11.9.2 Re gister Configuration..................................................................................... 280
11.9.3 Pin Functions................................................................................................... 282
11.9.4 Pin States ........................................................................................................ 282
11.10 Port 8........................................................................................................................... 283
11.10.1 Overview......................................................................................................... 283
11.10.2 Register Configuration..................................................................................... 283
11.10.3 Pin Functions................................................................................................... 286
11.10.4 Pin States ........................................................................................................ 288
Section 12 Timer A........................................................................................289
12.1 Overview..................................................................................................................... 289
12.1.1 Features........................................................................................................... 289
12.1.2 Block Diagram................................................................................................ 290
12.1.3 Re gister Configuration..................................................................................... 290
Rev. 2.0, 11/00, page viii of xviii
12.2 Descriptions of Respective Registers............................................................................ 291
12.2.1 Timer Mode Register A (TMA)....................................................................... 291
12.2.2 T imer Counter A (TCA) .................................................................................. 293
12.2.3 Module Stop Control Re gister (MSTPCR)....................................................... 293
12.3 Operation..................................................................................................................... 294
12.3.1 Operation as the Interval Timer........................................................................ 294
12.3.2 Operation of the Timer for Clocks.................................................................... 294
12.3.3 Ini tializing the Counts...................................................................................... 294
Section 13 Timer B........................................................................................ 295
13.1 Overview..................................................................................................................... 295
13.1.1 Features........................................................................................................... 295
13.1.2 Block Diagram................................................................................................ 295
13.1.3 Pin Configuration............................................................................................ 296
13.1.4 Re gister Configuration..................................................................................... 296
13.2 Descriptions of Respective Registers............................................................................ 297
13.2.1 Timer Mode Register B (TMB)........................................................................ 297
13.2.2 T imer Counter B (TCB)................................................................................... 299
13.2.3 Timer Load Register B (TLB).......................................................................... 299
13.2.4 Port Mode Register 5 (PMR5) ......................................................................... 300
13.2.5 Module Stop Control Re gister (MSTPCR)....................................................... 300
13.3 Operation..................................................................................................................... 302
13.3.1 Operation as the Interval Timer........................................................................ 302
13.3.2 Operation as the Auto Reload Timer................................................................ 302
13.3.3 Event Coun ter ................................................................................................. 302
Section 14 Timer J......................................................................................... 303
14.1 Overview..................................................................................................................... 303
14.1.1 Features........................................................................................................... 303
14.1.2 Block Diagram................................................................................................ 303
14.1.3 Pin Configuration............................................................................................ 305
14.1.4 Re gister Configuration..................................................................................... 305
14.2 Descriptions of Respective Registers............................................................................ 306
14.2.1 Timer Mode Register J (TMJ).......................................................................... 306
14.2.2 Timer J Control Register (TMJC) .................................................................... 310
14. 2. 3 Timer J Statu s Re g i ste r (T MJS) ....................................................................... 312
14.2.4 T imer Counter J (TCJ)..................................................................................... 313
14.2.5 T imer Counter K (TCK) .................................................................................. 313
14.2.6 Timer Load Register J (TLJ)............................................................................ 314
14.2.7 Timer Load Register K (TLK)......................................................................... 314
14.2.8 Module Stop Control Re gister (MSTPCR)....................................................... 315
14.3 Operation..................................................................................................................... 316
14.3.1 8-bi t Reload Time r (TMJ-1)............................................................................. 316
Rev. 2.0, 11/00, page ix of xviii
14.3.2 8-bi t Reload Time r (TMJ-2)............................................................................. 316
14.3.3 Remote Controlled Data Transmission............................................................. 317
Section 15 Timer L ........................................................................................321
15.1 Overview..................................................................................................................... 321
15.1.1 Features........................................................................................................... 321
15.1.2 Block Diagram................................................................................................ 322
15.1.3 Re gister Configuration..................................................................................... 323
15.2 Descriptions of Respective Registers............................................................................ 324
15.2.1 Timer L Mode Register (LMR)........................................................................ 324
15.2.2 L inear Time Counter (LTC)............................................................................. 326
15.2.3 Reload/Compare Match Register (RCR)........................................................... 326
15.2.4 Module Stop Control Re gister (MSTPCR)....................................................... 327
15.3 Operation..................................................................................................................... 328
15.3.1 Compare Match Clear Operation...................................................................... 328
Section 16 Timer R........................................................................................331
16.1 Overview..................................................................................................................... 331
16.1.1 Features........................................................................................................... 331
16.1.2 Block Diagram................................................................................................ 331
16.1.3 Pin Configuration............................................................................................ 333
16.1.4 Re gister Configuration..................................................................................... 333
16.2 Descriptions of Respective Registers............................................................................ 334
16.2.1 Timer R Mode Register 1 (TMRM1)................................................................ 334
16.2.2 Timer R Mode Register 2 (TMRM2)................................................................ 336
16.2.3 Timer R Control/Status Register (TMRCS)...................................................... 339
16.2.4 Timer R Capture Register 1 (TMRCP1)........................................................... 341
16.2.5 Timer R Capture Register 2 (TMRCP2)........................................................... 342
16.2.6 Timer R Load Register 1 (TMRL1) .................................................................. 342
16.2.7 Timer R Load Register 2 (TMRL2) .................................................................. 343
16.2.8 Timer R Load Register 3 (TMRL3) .................................................................. 343
16.2.9 Module Stop Control Re gister (MSTPCR)....................................................... 344
16.3 Operation..................................................................................................................... 345
16.3.1 Re load Timer Counte r Equipped with Capturing Function TMRU-1 ................. 345
16.3.2 Re load Timer Counte r Equipped with Capturing Function TMRU-2 ................. 346
16.3.3 Re load Counter Timer TMRU-3 ...................................................................... 346
16.3.4 Mode I d entification......................................................................................... 347
16.3.5 Reeling Controls .............................................................................................. 347
16.3.6 Acceleration and Braking Processes of the Capstan Motor................................ 347
16.3.7 Slow Tracking Mono-multi Function ............................................................... 348
16.4 Interrupt Cause ............................................................................................................ 350
16.5 Exemplary Settings for Respective Functions............................................................... 351
16.5.1 Mode I d entification......................................................................................... 351
Rev. 2.0, 11/00, page x of xviii
16.5.2 Reeling Controls.............................................................................................. 352
16.5.3 Slow Tracking Mono-multi Function ............................................................... 352
16.5.4 Acceleration and Braking Processes of the Capstan Motor................................ 353
Section 17 Timer X1...................................................................................... 355
17.1 Overview..................................................................................................................... 355
17.1.1 Features........................................................................................................... 355
17.1.2 Block Diagram................................................................................................ 356
17.1.3 Pin Configuration............................................................................................ 357
17.1.4 Re gister Configuration..................................................................................... 358
17.2 Descriptions of Respective Registers............................................................................ 359
17.2.1 Free Running Counter (FRC)........................................................................... 359
17.2.2 Output Comparing Register A and B (OCRA and OCRB)................................ 360
17.2.3 Input Capture Register A Through D (ICRA T hrough ICRD)........................... 361
17.2.4 Timer Interrupt Enabling Register (TIER)........................................................ 363
17.2.5 Timer Control/Status Register X (TCSRX) ...................................................... 366
17.2.6 Timer Control Register X (TCRX)................................................................... 370
17.2.7 Timer Output Comparing Control Register (TOCR)......................................... 372
17.2.8 Module Stop Control Re gister (MSTPCR)....................................................... 375
17.3 Operation..................................................................................................................... 376
17.3.1 Operation of the Timer X1............................................................................... 376
17.3.2 Counting Timing of the FRC ........................................................................... 377
17.3.3 Output Comparing Signal Outputting Timing................................................... 378
17.3.4 FRC Clearing Timing...................................................................................... 378
17.3.5 Input Capture Signal Inputting Timing............................................................. 379
17.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Ti ming........................... 380
17.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing....................... 381
17.3.8 Overflow Flag (CVF) Setting Up Timing......................................................... 381
17.4 Operation Mode of the Timer X1 ................................................................................. 382
17.5 Interrupt Causes........................................................................................................... 383
17.6 Exemplary Uses of the Timer X1 ................................................................................. 384
17.7 Precautions when Using the Timer X1.......................................................................... 385
17.7.1 Competition between Writing and Clearing with the FRC ................................ 385
17.7.2 Comp etition between Writing and Coun ting Up with the FRC.......................... 386
17.7.3 Competi tion between Writing and C omparing Matc h with th e OC R................. 3 8 7
17.7.4 Changing Over the Internal Clocks and Counter Operations............................. 388
Section 18 Watchdog Timer (WDT).............................................................. 391
18.1 Overview..................................................................................................................... 391
18.1.1 Features........................................................................................................... 391
18.1.2 Block Diagram................................................................................................ 392
18.1.3 Re gister Configuration..................................................................................... 393
18.2 Register Descriptions................................................................................................... 394
Rev. 2.0, 11/00, page xi of xviii
18.2.1 Watchd og Time r Count er (W TCNT)................................................................ 394
18.2.2 Watchdog Timer Control/Status Register (WTCSR)......................................... 394
18.2.3 System Control Register (SYSCR)................................................................... 397
18.2.4 Notes o n R egis ter Ac cess................................................................................. 397
18.3 Operation..................................................................................................................... 399
18.3.1 Wa tch dog Timer Operatio n.............................................................................. 399
18.3.2 Interval Ti mer Operat io n ................................................................................. 400
18. 3. 3 Timing of Setting of Overflow Fla g (OVF) ...................................................... 401
18.4 Interrupts..................................................................................................................... 402
18.5 Usage Notes................................................................................................................. 402
18.5.1 Contenti on be tween Wa tch dog Timer Count er (WTCNT) Write
and I n c rem e nt.................................................................................................. 402
18.5.2 Changing Value of CKS2 to CKS0 .................................................................. 403
18.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode............... 403
Section 19 8-Bit PWM...................................................................................405
19.1 Overview..................................................................................................................... 405
19.1.1 Features........................................................................................................... 405
19.1.2 Block Diagram................................................................................................ 405
19.1.3 Pin Configuration............................................................................................ 406
19.1.4 Re gister Configuration..................................................................................... 406
19.2 Register Descriptions................................................................................................... 407
19.2.1 Bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) ............ 407
19.2.2 8-bi t PWM Control Register (PW8CR)............................................................ 408
19.2.3 Port Mode Register 3 (PMR3).......................................................................... 409
19.2.4 Module Stop Control Re gister (MSTPCR)....................................................... 410
19.3 8-Bit PWM Operation.................................................................................................. 411
Section 20 12-Bit PWM.................................................................................413
20.1 Overview..................................................................................................................... 413
20.1.1 Features........................................................................................................... 413
20.1.2 Block Diagram................................................................................................ 414
20.1.3 Pin Configuration............................................................................................ 415
20.1.4 Re gister Configuration..................................................................................... 415
20.2 Register Descriptions................................................................................................... 416
20.2.1 12-Bit PWM Control Re gisters (CPWCR, DPWCR)........................................ 416
20.2.2 12-Bit PWM Data Re gisters (CPWDR, DPWDR)............................................ 419
20.2.3 Module Stop Control Re gister (MSTPCR)....................................................... 420
20.3 Operation..................................................................................................................... 421
20.3.1 Outp u t Wav ef o rm............................................................................................ 421
Section 21 14-Bit PWM.................................................................................423
21.1 Overview..................................................................................................................... 423
Rev. 2.0, 11/00, page xii of xviii
21.1.1 Features........................................................................................................... 423
21.1.2 Block Diagram................................................................................................ 424
21.1.3 Pin Configuration............................................................................................ 424
21.1.4 Re gister Configuration..................................................................................... 425
21.2 Register Descriptions................................................................................................... 426
21.2.1 PWM Control Register (PWCR)...................................................................... 426
21.2.2 PWM Data Registers U and L (PWDRU, PWDRL).......................................... 427
21.2.3 Module Stop Control Re gister (MSTPCR)....................................................... 428
21.3 14-Bit PW M Ope ration................................................................................................ 429
Section 22 Prescalar Unit............................................................................... 431
22.1 Overview..................................................................................................................... 431
22.1.1 Features........................................................................................................... 431
22.1.2 Block Diagram................................................................................................ 432
22.1.3 Pin Configuration............................................................................................ 433
22.1.4 Re gister Configuration..................................................................................... 433
22.2 Registers...................................................................................................................... 434
22.2.1 Input Capture Register 1 (ICR1) ...................................................................... 434
22.2.2 Prescalar Unit Control/Status Register (PCSR)................................................. 434
22.2.3 Port Mode Register 1 (PMR1) ......................................................................... 437
22.3 N o ise Cance l C ircuit.................................................................................................... 437
22.4 Operation..................................................................................................................... 438
22. 4. 1 Prescala r S (PSS)............................................................................................. 438
22.4.2 Pres c alar W (P SW).......................................................................................... 4 3 9
22.4.3 Sta ble Osci llation Wait Time Count................................................................. 439
22.4.4 8-Bi t PWM...................................................................................................... 440
22.4.5 8-Bi t Input Capture Using IC Pin..................................................................... 440
22.4.6 Frequency Division Clock Output.................................................................... 440
Section 23 Serial Communication Interf ace 1 (SCI 1)..................................... 441
23.1 Overview..................................................................................................................... 441
23.1.1 Features........................................................................................................... 441
23.1.2 Block Diagram................................................................................................ 443
23.1.3 Pin Configuration............................................................................................ 444
23.1.4 Re gister Configuration..................................................................................... 444
23.2 Register Descriptions................................................................................................... 445
23.2.1 Receive Shift Register (RSR)........................................................................... 445
23.2.2 Receive Data Register (RDR1) ........................................................................ 445
23.2.3 Transmit Shift Register (TSR) ......................................................................... 446
23.2.4 Transmit Data Register (TDR1)....................................................................... 446
23.2.5 Serial Mode Register (SMR1).......................................................................... 447
23.2.6 Serial Control Regist er (SCR1)........................................................................ 450
23.2.7 Serial Status Register (SSR1)........................................................................... 453
Rev. 2.0, 11/00, page xiii of xviii
23.2.8 Bi t Rate Register (BRR1) ................................................................................ 457
23.2.9 Ser ial Interface Mode R egis ter (SC MR 1 )......................................................... 464
23.2.10 Module Stop Control Register (MSTPCR)....................................................... 465
23.3 Operation..................................................................................................................... 466
23.3.1 Overview......................................................................................................... 466
23.3.2 Operation in Asynchronous Mode.................................................................... 468
23.3.3 Multiproc ess or Com munication Function......................................................... 478
23.3.4 Operation in Clock Synchronous Mode............................................................ 486
23.4 SCI1 Interrupt s ............................................................................................................ 494
23.5 Usage Notes................................................................................................................. 495
Section 24 Serial Communication Interf ace 2 (SCI 2) .....................................499
24.1 Overview..................................................................................................................... 499
24.1.1 Features........................................................................................................... 499
24.1.2 Block Diagram................................................................................................ 500
24.1.3 Pin Configuration............................................................................................ 501
24.1.4 Re gister Configuration..................................................................................... 501
24.2 Register Descriptions................................................................................................... 502
24.2.1 Starting Address Register (STAR) ................................................................... 502
24.2.2 Ending Address Register (EDAR).................................................................... 502
24.2.3 Serial Control Regist er 2 (SCR2)..................................................................... 503
24.2.4 Seri al Control Status Register 2 (SCSR2)......................................................... 504
24.2.5 Module Stop Control Re gister (MSTPCR)....................................................... 507
24.3 Operation..................................................................................................................... 508
24.3.1 Clock .............................................................................................................. 508
24.3.2 Data Transfer Format....................................................................................... 508
24.3.3 Data Transfer Operations................................................................................. 511
24.4 Interrupt Sources.......................................................................................................... 515
Section 25 I2C Bus In t erf ace (IIC).................................................................517
25.1 Overview..................................................................................................................... 517
25.1.1 Features........................................................................................................... 517
25.1.2 Block Diagram................................................................................................ 518
25.1.3 Pin Configuration............................................................................................ 519
25.1.4 Re gister Configuration..................................................................................... 520
25.2 Register Descriptions................................................................................................... 521
25.2.1 I2C Bus Data Register (ICDR) .......................................................................... 521
25.2.2 Slave Address Register (SAR) ......................................................................... 524
25.2.3 Second Slave Address Register (SARX) .......................................................... 526
25.2.4 I2C Bus Mode Register (ICMR) ....................................................................... 527
25.2.5 I2C Bus Control Registe r (ICCR) ..................................................................... 531
25.2.6 I2C Bus Status Register (ICSR)........................................................................ 538
25.2.7 Serial/Timer Control Register (STCR) ............................................................. 543
Rev. 2.0, 11/00, page xiv of xviii
25.2.8 Module Stop Control Re gister (MSTPCR)....................................................... 545
25.3 Operation..................................................................................................................... 546
25.3.1 I2C Bus Data Format........................................................................................ 546
25.3.2 Master Transmit Operation.............................................................................. 547
25.3.3 Master Receive Operation................................................................................ 550
25.3.4 Slave Receive Operation .................................................................................. 553
25.3.5 Slav e Transmit Op er ation ................................................................................ 5 5 6
25.3.6 IRIC Setting Timing and SCL Control............................................................. 558
25.3.7 Nois e C anceler................................................................................................ 560
25.3.8 Sample Flowcharts.......................................................................................... 560
25.3.9 Initialization of Internal State........................................................................... 565
25.4 Usage Notes................................................................................................................. 567
Section 26 A/D Converter .............................................................................. 573
26.1 Overview..................................................................................................................... 573
26.1.1 Features........................................................................................................... 573
26.1.2 Block Diagram................................................................................................ 574
26.1.3 Pin Configuration............................................................................................ 575
26.1.4 Re gister Configuration..................................................................................... 576
26.2 Register Descriptions................................................................................................... 577
26.2.1 Software-Triggered A/D Result Register (ADR) .............................................. 577
26.2.2 Hardware-Triggered A/D Result Register (AHR)............................................. 577
26.2.3 A/D Control Register (ADCR)......................................................................... 579
26.2.4 A/D Control/Status Register (ADCSR) ............................................................ 582
26.2.5 Trigger Select Register (ADTSR) .................................................................... 585
26.2.6 Port Mode Register 0 (PMR0) ......................................................................... 585
26.2.7 Module Stop Control Re gister (MSTPCR)....................................................... 586
26.3 Interface to Bus Master................................................................................................ 587
26.4 Operation..................................................................................................................... 588
26.4.1 Software-Triggered A/D Conversion................................................................ 588
26.4.2 Hardware- or External- Trigger ed A/D Conversion........................................... 589
26.5 Interrupt Sources.......................................................................................................... 590
Section 27 Address Trap Controller (ATC).................................................... 591
27.1 Overview..................................................................................................................... 591
27.1.1 Features........................................................................................................... 591
27.1.2 Block Diagram................................................................................................ 591
27.1.3 Re gister Configuration..................................................................................... 592
27.2 Register Descriptions................................................................................................... 592
27.2.1 Address Trap Control Register (ATCR)........................................................... 592
27.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) ................................................ 593
27.3 P r ecautions in Usage.................................................................................................... 595
27.3.1 Basic Operations............................................................................................. 595
Rev. 2.0, 11/00, page xv of xviii
27.3.2 Enable............................................................................................................. 597
27.3.3 Bcc Instruction................................................................................................ 597
27.3.4 BSR Instruction............................................................................................... 601
27.3.5 JSR Instruction................................................................................................ 602
27. 3. 6 JMP Inst r uct ion ............................................................................................... 603
27.3.7 RTS Instruction............................................................................................... 604
27.3.8 SLEEP Instruction........................................................................................... 604
27.3.9 Comp eting Int errup t ........................................................................................ 607
Section 28 Servo Circuits...............................................................................611
28.1 Overview..................................................................................................................... 611
28.1.1 Functions......................................................................................................... 611
28.1.2 Block Diagram................................................................................................ 612
28.2 Servo Port.................................................................................................................... 614
28.2.1 Overview......................................................................................................... 614
28.2.2 Block Diagram................................................................................................ 614
28.2.3 Pin Configuration............................................................................................ 617
28.2.4 Re gister Configuration..................................................................................... 618
28.2.5 Register Descriptions ....................................................................................... 618
28.2.6 DFG/DPG Input Signals.................................................................................. 625
28.3 Reference Signal Generators ........................................................................................ 626
28.3.1 Overview......................................................................................................... 626
28.3.2 Block Diagram................................................................................................ 626
28.3.3 Re gister Configuration..................................................................................... 628
28.3.4 Register Descriptions ....................................................................................... 629
28.3.5 Description of Operation.................................................................................. 635
28.4 HSW (Head-switch) Timing Generator......................................................................... 650
28.4.1 Overview......................................................................................................... 650
28.4.2 Block Diagram................................................................................................ 650
28.4.3 Composition.................................................................................................... 652
28.4.4 Re gister Configuration..................................................................................... 653
28.4.5 Register Descriptions ....................................................................................... 653
28.4.6 Description of Operation.................................................................................. 669
28.4.7 Interrupt.......................................................................................................... 675
28.4.8 Cautions.......................................................................................................... 676
28.5 Four-head High-speed Switching Circuit for Special Playback...................................... 677
28.5.1 Overview......................................................................................................... 677
28.5.2 Block Diagram................................................................................................ 677
28.5.3 Pin Configuration............................................................................................ 678
28.5.4 Register Description........................................................................................ 678
28.6 Drum Speed Error Detector.......................................................................................... 681
28.6.1 Overview......................................................................................................... 681
28.6.2 Block Diagram................................................................................................ 681
Rev. 2.0, 11/00, page xvi of xviii
28.6.3 Re gister Configuration..................................................................................... 683
28.6.4 Register Descriptions....................................................................................... 684
28.6.5 Description of Operation ................................................................................. 689
28.6.6 fH Corre ction in Trick Play Mode..................................................................... 691
28.7 Drum Phase Error Detector .......................................................................................... 692
28.7.1 Overview ........................................................................................................ 692
28.7.2 Block Diagram................................................................................................ 692
28.7.3 Re gister Configuration..................................................................................... 694
28.7.4 Register Descriptions....................................................................................... 695
28.7.5 Description of Operation ................................................................................. 698
28.7.6 Phas e C o mpariso n........................................................................................... 700
28.8 Capstan Spe ed E rror Det ector ...................................................................................... 701
28.8.1 Overview ........................................................................................................ 701
28.8.2 Block Diagram................................................................................................ 701
28.8.3 Re gister Configuration..................................................................................... 703
28.8.4 Register Descriptions....................................................................................... 704
28.8.5 Description of Operation ................................................................................. 708
28.9 Capstan Pha se Error Detector....................................................................................... 710
28.9.1 Overview ........................................................................................................ 710
28.9.2 Block Diagram................................................................................................ 710
28.9.3 Re gister Configuration..................................................................................... 712
28.9.4 Register Descriptions....................................................................................... 713
28.9.5 Description of Operation ................................................................................. 716
28.10 X-Value and Tracking Adjustment Circuit .................................................................... 718
28.10.1 Overview ........................................................................................................ 718
28.10.2 Block Diagram................................................................................................ 718
28.10.3 Register Descriptions....................................................................................... 720
28.11 Digital Filters ............................................................................................................... 723
28.11.1 Overview ........................................................................................................ 723
28.11.2 Block Diagram................................................................................................ 724
28.11.3 Arithmetic Buffer............................................................................................ 726
28.11.4 Register Configuration..................................................................................... 727
28.11.5 Register Descriptions....................................................................................... 728
28.1 1.6 Filt er C h aracter istics........................................................................................ 736
28.11.7 Operations in Case of Transient Response........................................................ 738
28.11.8 Initialization of Z-1 ........................................................................................... 738
28.12 Additional V Signal Generator..................................................................................... 740
28.12.1 Overview ........................................................................................................ 740
28.12.2 Pin Configuration............................................................................................ 741
28.12.3 Register Configuration..................................................................................... 741
28.12.4 Register Description........................................................................................ 741
28.12.5 Additional V Pulse Signal................................................................................ 743
28.13 CTL Circuit................................................................................................................. 746
Rev. 2.0, 11/00, page xvii of xviii
28.13.1 Overview......................................................................................................... 746
28.13.2 Block Diagram................................................................................................ 747
28.13.3 Pin Configuration............................................................................................ 748
28.13.4 Register Configuration..................................................................................... 748
28.13.5 Register Descriptions....................................................................................... 749
28.13.6 Operation........................................................................................................ 763
28.13.7 CTL Input Section........................................................................................... 766
28.13.8 Duty Discriminator.......................................................................................... 769
28.13.9 CTL Output Section......................................................................................... 775
28.1 3.1 0 Trap ezoid Waveform Circuit......................................................................... 778
28.13.11 Note on CTL Interrupt .................................................................................. 779
28.14 Frequency Dividers...................................................................................................... 780
28.14.1 Overview......................................................................................................... 780
28.14.2 CTL Frequency Divider................................................................................... 780
28.14.3 CFG Frequency Divider................................................................................... 784
28. 1 4.4 DFG Noise R emo val Circ uit............................................................................ 793
28.15 Sync Signal Detector.................................................................................................... 795
28.15.1 Overview......................................................................................................... 795
28.15.2 Block Diagram................................................................................................ 796
28.15.3 Pin Configuration............................................................................................ 797
28.15.4 Register Configuration..................................................................................... 797
28.15.5 Register Descriptions....................................................................................... 798
28.15.6 Noise Detection............................................................................................... 806
28.15.7 Sync Signal Detector Activation ...................................................................... 809
28.16 Servo Interrupt............................................................................................................. 810
28.16.1 Overview......................................................................................................... 810
28.16.2 Register Configuration..................................................................................... 810
28.16.3 Register Description........................................................................................ 810
28.17 Module Stop Control Reigster (MSTPCR).................................................................... 817
Section 29 Electrical Characteristics...............................................................819
29.1 Absolute Maximum Ratings......................................................................................... 819
29.2 Electrical Characteristics of HD64F2194...................................................................... 820
29.2.1 DC Characte ristics of HD64F2194 ................................................................... 820
29.2.2 All owable Output Currents of HD64F2194, HD64F2194C............................... 826
29.2.3 AC Characte ristics of HD64F2194, HD64F2194C ........................................... 827
29.2.4 Seri al Interface Timi ng of HD64F2194, HD64F2194C..................................... 830
29.2.5 A/D Converter Characteristics of HD64F2194, HD64F2194C.......................... 835
29.2.6 Servo Section Electrical Characteristics of HD64F2194, HD64F2194C............ 836
29. 2. 7 FLASH Mem or y Charac ter i sti c s...................................................................... 839
29.2.8 Usage Note...................................................................................................... 840
29.3 El ectrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A.......................................................... 841
Rev. 2.0, 11/00, page xviii of xviii
29.3.1 DC Characte ristics of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A............................................. 841
29.3.2 All owable Output Currents of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A......................... 847
29.3.3 AC Characte ristics of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A............................................. 848
29.3.4 Seri al Interface Timi ng of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A......................... 852
29.3.5 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A......................... 857
29.3.6 Servo Section Electrical Characteristics of HD6432194, HD6432193,
HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A.... 858
Appendix A Instruction Set............................................................................ 861
A.1 Instructions.................................................................................................................. 861
A.2 Instruction Codes......................................................................................................... 872
A.3 Operation Code Map.................................................................................................... 882
A.4 Number of Execution States......................................................................................... 886
A.5 Bus Status During Instruction Execution ...................................................................... 896
A.6 Change of Condit ion Codes.......................................................................................... 905
Appendix B Internal I/O Registers................................................................. 910
B.1 Addresses .................................................................................................................... 910
B.2 Func tion List............................................................................................................... . 917
Appendix C Pin Circuit Diagrams............................................................... 1018
C.1 Pin Circuit Diagrams................................................................................................. 1018
Appendix D Port States in the Difference Processing States........................ 1032
D.1 Pin Circuit Diagrams................................................................................................. 1032
Appendix E Usage Notes............................................................................ 1033
E.1 Power Supply Rise and Fall Order ............................................................................. 1033
E.2 Pin Handli ng When the High-Speed Switching Ci rcuit for Four-Head Speci al
Playback Is Not Used................................................................................................ 1034
E.3 Sample External Circuits........................................................................................... 1035
Appendix F List of Product Codes.............................................................. 1036
Appendix G External Dimensions ............................................................... 1037
Rev. 2.0, 11/ 00, page 1 of 1037
Section 1 Overview
1.1 Overview
The H8S/ 2194 Series, and H8S/2194C Series comprise microcomputers (MCUs) built around the
H8S/ 2000 CPU, employing Hitachi's proprietary architecture, and equipped with supporting
modules on-chi p.
The H8S/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Serie s.
The H8S/2194 Series, and H8S/2194C Series are incorporated with digital servo circuit, ROM,
RAM, seven types of timers, three types of PWM, two types of serial communication interface,
I2C bus interface, A/D converter, and I/O port as on-chip supporting modules.
The on-chip ROM is either flash memory (F-ZTAT *) or mask ROM, with a capacity of 256,
192, 160, 128, 112, 96, or 80 kbytes. ROM is connected to the CPU via a 16-bit data bus,
enabling both byte and word data to be accessed in one state. Instruction fetching has been
speeded up, and processing speed increased.
The fea t ures of the H8S/2194 Serie s, a nd H8S/2194C Series are shown in ta ble 1. 1.
Note: * F-ZTAT is a trademark of Hitachi, Ltd.
Rev. 2.0, 11/ 00, page 2 of 1037
Table 1.1 Features
Item Specifications
CPU ■General-r egist er ar chitect ur e
•Sixteen 16-bit general regist er s ( also usable as sixteen 8-bit r egister s or
eight 32-bit r egister s)
■High-speed operation suitable for real-time control
•Maximum oper at ing f r equency: 10 M Hz/4 t o 5. 5 V
Operable by 32 kHz subclock
•High-speed arithmetic operations
8/16/32-bit register - register add/ subt ract: 100 ns ( 10 M Hz operation)
16 × 16-bit r egister - r egister m ult iply: 2000 ns (10 M Hz operation)
32 ÷ 16-bit regist er - r egister divide: 2000 ns (10 M Hz oper at ion)
■Instr uct ion set suitable for high- speed oper at ion
•Sixty-five basic instructions
•8/16/32- bit t r ansf er / ar it hm et ic and logic instructions
•Unsigned/signed multiply and divide instr uct ions
•Powerful bit-manipulation instruct ions
■CPU operating modes
•Advanced mode: 16-M byte address space
Timer ■Seven t ypes of timer ar e incor por at ed
(1) Timer A
•8-bit interval timer
•Clock source can be selected among 8 types of inter nal clock of which
frequencies are divided fr om t he syst em clock (φ) and subclock (φSUB)
•Functions as clock time base by subclock input
(2) Timer B
•Functions as 8-bit int er val t imer or r eload t imer
•Clock source can be selected among 7 types of inter nal clock or ext er nal
event input
(3) Timer J
•Functions as two 8-bit down counter s or one 16-bit down counter ( r eload
timer / event counter t imer /timer out put, et c. , 5 types of oper ation modes)
•Remote contr olled tr ansm it f unct ion
•Take up/Supply Reel Pulse Frequency division
Rev. 2.0, 11/ 00, page 3 of 1037
Item Specifications
Timer (4) Timer L
•8-bit up/ down counter
•Clock source can be selected among 2 types of inter nal clock, CFG
frequency division signal, and PB and REC-CTL (cont r ol pulse)
•Compare- m at ch clear ing funct ion/ aut o r eload f unct ion
(5) Timer R
•Three reload t imer s
•Mode discrimination
•Reel control
•Capstan mot or acceleration/decelerat ion detection function
•Slow tracking mono-multi
(6) Timer X1
•16-bit f r ee- r unning count er
•Clock source can be selected among 3 types of inter nal clock and DVCFG
•Two output com par e out puts
•Four input capt ur e input s
(7) Watchdog t imer
•Functions as watchdog t imer or 8- bit inter v al tim er
•Generat es r eset signal or NMI at over flow
Prescaler unit •Divides system clock frequency and generat es frequency division clock
for suppor ting module funct ions
•Divides subclock f r equency and gener at es input clock f or Tim er A (clock
time base)
•Generat es 8- bit PWM f r equency and dut y per iod
•8-bit input capt ure at ext er nal signal edge
•Frequency division clock output enabled
PWM ■Three t y pes of PWM ar e incor por at ed
(1) 14-bit PWM : Pulse resolut ion type x 1 channel
(2) 8-bit PWM: Duty control type x 4 channels
(3) 12-bit PWM : Pulse pitch cont r ol t ype x 2 channels
Rev. 2.0, 11/ 00, page 4 of 1037
Item Specifications
Serial
communication
interface ( SCI)
■Two types of ser ial comm unication inter face is incorporat ed
(1) SCI1
•Asynchronous mode or synchr onous m ode select able
•Desired bit rat e selectable with built-in baud rate generat or
•Multiprocessor com m unicat ion funct ion
(2) SCI2
•32-byte data autom at ically tr ansf er r able
•Transfer clock selectable among seven t ypes of int ernal/ ext er nal clock
I2C bus interface •Co n for ms to Phillip s I2C bus interface standard
•Single master mode/ slave mode
•Arbitrat ion lost condit ion can be identified
•Supports t wo slave addresses
A/D converter •Resolution: 10 bits
•Input : 12 channels
•High-speed conversion: 13.4 µs minimum conversion time ( 10 M Hz
operation)
•Sample-and-hold f unct ion
•A/D conversion can be activated by sof t ware or ext er nal tr igger
Address tr ap
controller •Int er r upt occur s when the pr eset addr ess is f ound dur ing bus cycle
•To-be-t rapped addresses can be individually set at thr ee dif f er ent
locations
I/O port •60 input/output pins
•8 input-only pins
•Can be switched for each suppor t ing module
Servo circuit ■Digit al serv o circuits on- chip
•Input and out put circ uits
•Error det ection circuit
•Phase and gain compensation
Sync signal
detector ■On-chip sync signal detection circuit
•Can separately detect hor izontal and ver t ical sync signals
•Noise detection funct ion
Rev. 2.0, 11/ 00, page 5 of 1037
Item Specifications
Memory •Flash memory or mask ROM
•High-speed static RAM
Power-down
state •M edium - speed m ode
•Sleep mode
•Module stop m ode
•Standby mode
•Subclock operation
Subactive mode, wat ch m ode, subsleep m ode
Interrupt
controller •Seven external interr upt pins (
10,
,
,54
to
,54
)
•38 internal inter r upt sour ces
•Three prior ity levels settable
Clock pulse
generator ■Two t ypes of clock pulse generat or on- chip
•System clock pulse generator : 8 t o 10 M Hz
•Subclock pulse generator: 32. 768 kHz
Packages •112-pin plastic QFP (FP-112)
Product lineup
Product Nam e ROM RAM
H8S/2194C 256 kbytes 6 kbyt es
H8S/2194B 192 kbytes 6 kbyt es
H8S/2194A 160 kbytes 6 kbyt es
H8S/2194 128 kbytes 3 kbytes
H8S/2193 112 kbytes 3 kbytes
H8S/2192 96 kbytes 3 kbytes
H8S/2191 80 kbytes 3 kbytes
Product Code
Series Mask RO M
Versions F-ZTAT
Versions ROM/RAM
(bytes) Packages
HD6432194C HD64F2194C 256 k/6 k FP-112
HD6432194B 192 k/6 k FP-112
H8S/2194C
HD6432194A 160 k/6 k FP-112
HD6432194 HD64F2194 128 k/ 3 k FP-112
HD6432193 112 k/3 k FP-112
HD6432192 96 k/3 k FP-112
H8S/2194
HD6432191 80 k/3 k FP-112
Rev. 2.0, 11/ 00, page 6 of 1037
1.2 Internal Block Diagram
An internal bl ock di a gram of t he c hi p is shown in figure 1. 1.
P23/SDA
P25/SI2
P22/SCK1
P26/SO2
P21/SO1
P27/SCK2
P20/SI1
P24/SCL
V
SS
V
SS
V
SS
V
SS
V
CC
V
CC
V
CC
V
SS
MD0
FWE
RES
NMI
OSC2
OSC1
X2
X1
V
CC
AUDIO FF
DRMPWM
VIDEO FF
DFG
Csync
SV
SS
SV
CC
Vpulse
EXCTL/PS4
CLT(+)
CAPPWM
CTLSMT(i)
CTLBias
CTLFB
CLT(-)
CTL REF
CFG
CTLAmp(o)
C.Rotary/PS0
COMP/PS2
DPG/PS3
H.Amp SW/PS1
P13/IRQ3
P15/IRQ5
P12/IRQ2
R A M
R O M
H8S/2000 CPU
P16/IC
P11/IRQ1
P17/TMOW
P10/IRQ0
P14/IRQ4
P03/AN3
P05/AN5
P02/AN2
P06/AN6
P01/AN1
P07/AN7
P00/AN0
P04/AN4
ANA
AN9
AN8
ANB
AV
CC
AV
SS
P83/SV2
P85
P82/SV1
P86
P81/EXCAP
P87
P80/EXTTRG
P84
P33/PWM1
P35/PWM3
P32/PWM0
P36/BUZZ
P31/STRB
P37/TMO
P30/CS
P34/PWM2
P43/FTIC
P45/FTOA
P42/FTIB
P46/FTOB
P41/FTIA
P47
P40/PWM14
P44/FTID
P51
P53/TRIG
P50/ADTRG
P52/TMBI
P73/PPG3
P75/PPG5
P72/PPG2
P76/PPG6
P71/PPG1
P77/PPG7
P70/PPG0
P74/PPG4
P63/RP3
P65/RP5
P62/RP2
P66/RP6
P61/RP1
P67/RP7
P60/RP0
P64/RP4
S C I 1
S C I 2
Port 1 Port 2Port 0
Port 4 Port 3
Port 5Port 6Port 7
Port 8
Sync signal
detection
analog
port
External address bus
External data bus
External data bus
External address bus
Subclock pulse
generator
System clock
pulse generator
Interrupt controller
8-bit PWM
Watchdog timer
I C bus
interface
Timer L
2
A/D converter
Servo pins (CTL input/output
amplifier, three-level output, etc.)
Servo circuit
Internal data bus
Internal address bus
Bus
controller
Address trap
controller
Prescaler unit
Timer A
Timer B
Timer J
Timer R
Timer X1
14-bit PWM
Figure 1.1 Internal Block Diagram of H8S/2194 Series
Rev. 2.0, 11/ 00, page 7 of 1037
1.3 Pin Arrangement and Functions
1.3.1 Pin Arrangement
The pin arrangement of the chip is shown in figure 1.2.
V
SS
P72/PPG2
V
CC
P71/PPG1
P70/PPG0
P67/RP7
P66/RP6
P65/RP5
P64/RP4
P63/RP3
P62/RP2
P61/RP1
P60/RP0
MD0
V
CC
OSC2
V
SS
OSC1
RES
X2
X1
NMI
FWE
P17/TMOW
P16/IC
P15/IRQ5
P14/IRQ4
P13/IRQ3
CTLREF
V
SS
Vpulse
V
CC
DFG
DPG/PS3
EXCTL/PS4
COMP/PS2
H.Amp sw/PS1
C.Rotary/PS0
DRM PWM
CAP PWM
VIDEO FF
AUDIO FF
Csync
P87
P86
P85
P84
P83/SV2
P82/SV1
P81/EXCAP
P80/EXTTRG
P77/PPG7
P76/PPG6
P75/PPG5
P74/PPG4
P73/PPG3
1CTL(+)
FP-112
(Top view)
84
2SV
SS
83
3CTL(–) 82
4CTLBias 81
5CTLFB 80
6CTLAmp(o) 79
7CTLSMT(i) 78
8CFG 77
9SV
CC
76
10AV
CC
75
11P00/AN0 74
12P01/AN1 73
13P02/AN2 72
14P03/AN3 71
15P04/AN4 70
16P05/AN5 69
17P06/AN6 68
18P07/AN7 67
19AN8 66
20AN9 65
21ANA 64
22ANB 63
23
AV
SS
62
24
P50/ADTRG 61
25P51 60
26P52/TMBI 59
27P53/TRIG 58
28P40/PWM14 57
29 P41/FTIA
112 30 P42/FTIB
111 31 P43/FTIC
110 32 P44/FTID
109 33 P45/FTOA
108 34 P46/FTOB
107 35 P47106 36 P30/CS105 37 P31/STRB
104 38 P32/PWM0
103 39 P33/PWM1
102 40 P34/PWM2
101 41 P35/PWM3100 42 P36/BUZZ
99 43 V
SS
98 44 P37/TMO
97 45 V
CC
96 46 P20/SI1
95 47 P21/SO1
94 48 P22/SCK1
93 49 P23/SDA
92 50 P24/SCL
91 51 P25/SI2
90 52 P26/SO2
89 53 P27/SCK288 54 P10/IRQ0
87 55 P11/IRQ1
86 56 P12/IRQ2
85
Figure 1.2 Pin Arrangement of H8S/2194 Series
Rev. 2.0, 11/ 00, page 8 of 1037
1.3.2 Pin Functions
Table 1.2 summarizes the functions of the chip’s pins.
Table 1.2 Pin Functions
Type Symbol Pin No. I/O Name and Funct i on
Vcc 45, 70,
82, 109 Input Power supply:
All Vcc pins should be connected to the system
power supply (+5V)
Vss 43, 68,
84, 111 Input Ground:
All Vss pins should be connected to the system
power supply (0V)
SVcc 9 I nput Servo power supply:
SVcc pin should be connect ed t o t he servo
analog power supply (+5V)
SVss 2 I nput Servo gr ound:
SVss pin should be connect ed t o t he servo
analog power supply (0V)
AVcc 10 Input Analog power supply:
Power supply pin for A/D converter . I t should be
connected to the system power supply (+5V)
when the A/D convert er is not used
Power
supply
AVss 23 Input Analog gr ound:
Ground pin f or A/ D convert er . I t should be
connected to t he system power supply (0V)
OSC1 67 Input
OSC2 69 Output
Connected t o a cr y stal oscillat or . It can also
input an external clock. See sect ion 10, Clock
Pulse Generat or , f or t ypical connection
diagram s f o r a cryst al osc illat or and ext er nal
clock input
X1 65 Input
Clock
X2 64 Output
Connected t o a 32. 768 kHz c r y st al os cillator.
See section 10, Clock Pulse Generator, for
typical connection diagrams
Operating
mode
control
MD0 71 Input Mode pins:
These pins set the oper at ing mode. These pins
should not be changed while the MCU is in
operation
Rev. 2.0, 11/ 00, page 9 of 1037
Type Symbol Pin No. I/O Name and Funct i on
5(6
66 Input Reset input:
When this pin is driven low, the chip is reset
System
control
FWE 62 Input Flash memory enable:
Enables/disables flash memor y pr ogr am m ing.
This pin is available only with MCU with flash
memory on-chip. For mask ROM type, do not
connect anything t o t his pin
,54
54 Input External interr upt r equest 0:
External inter r upt input pin for which rising edge
sense, falling edge sense or both edges sense
are selectable
,54
,54
,54
,54
,54
55
56
57
58
59
Input External inter r upt request s 1 t o 5:
External inter r upt input pins for which rising or
falling edge sense are selectable
Interrupts
10,
63 Input Nonmaskable interrupt:
Nonmaskable interrupt input pin for which rising
edge sense, f a lling edge sense or both edges
sense are selectable
,&
60 Input Input capture input:
Input capt ur e input pin f or pr escaler unit
Prescaler
unit
TMOW 61 Out put Frequency division clock output:
Output pin for clock of which fr equency is
divided by prescaler
TMBI 26 Input Timer B event input:
Input pin for event s to be input to Tim er B
counter
,54
,54
55
56 Input Timer J event input:
Input pin for event s to be input to Tim er J RDT-
1or RDT-2 counter
TMO 44 Output Timer J t im er out put :
Out put pin for toggle at under flow of RDT-1 of
Timer J, or r em ot e controlled transmit data
Timers
BUZZ 42 Output Timer J buzzer out put :
Out put pin for toggle which is selectable among
fixed fr equency, 1Hz fr equency divided fr om
subclock (32 kHz), and f r equency division CTL
signal
Rev. 2.0, 11/ 00, page 10 of 1037
Type Symbol Pin No. I/O Name and Funct i on
,54
57 Input Timer R input capture:
Input pin for input capt ur e of Tim er R TMRU-1 or
TMRU-2
FTOA
FTOB 33
34 Out put Timer X1 output compare A and B output :
Out put pin for output com par e A and B of Tim er
X1
Timers
FTIA
FTIB
FTIC
FTID
29
30
31
32
Input Timer X1 input capt ur e A, B, C and D input:
Input pin for input capt ur e A, B, C and D of
Timer X1
PWM0
PWM1
PWM2
PWM3
38
39
40
41
Out put 8-bit PWM squar e wavefor m output :
Out put pin for waveform gener ated by 8-bit
PWM 0, 1, 2 and 3
PWM
PWM14 28 Output 14-bit PWM squar e wavef or m out put:
Out put pin for waveform gener ated by 14-bit
PWM
SCK1
SCK2 48
53 Input
/output SCI clock input/output:
Clock input pins f or SCI 1 and 2
SI1
SI2 46
51 Input SCI receive data input :
Receive data input pins for SCI 1 and 2
SO1
SO2 47
52 Out put SCI transm it dat a output:
Transmit dat a out put pins for SCI 1 and 2
STRB 37 Output SCI2 strobe out put :
This pin outputs str obe pulse f or each byt e
transmit by SCI2
Serial
commu-
nication
interface
(SCI)
&6
36 Input SCI 2 chip select input:
This pin controls the t r ansf er start of SCI2
SCL 50 Input
/output I2C bus interface clock input/out put :
Clock input / output pin for I 2C bus interf ace
I2C bus
interface
SDA 49 Input
/output I2C bus interface dat a input/output :
Data input/output pin for I2C bus interface
Rev. 2.0, 11/ 00, page 11 of 1037
Type Symbol Pin No. I/O Name and Funct i on
AN7 t o
AN0 18 to 11 Input Analog input channels 7 to 0:
Analog data input pins. A/D conversion is
start ed by a software t r iggering
AN8
AN9
ANA
ANB
19
20
21
22
Input Analog input channels 8, 9, A and B:
Analog data input pins. A/D conversion is
started by an exter nal, hardware, or sof tware
triggering
A/D
converter
$'75*
24 Input A/D conversion external tr igger input :
Pin for input of an ext er nal t r igger to star t A/ D
conversion
AUDIO FF 99 Output Audio FF:
Out put pin for audio head switching signal
VIDEO FF 100 Output Video FF:
Output pin for video head switching signal
CAPPWM 101 Out p u t Caps tan mix:
12-bit PWM out put pin giving result of capst an
speed error and phase er r or aft er f ilter ing
DRMPWM 102 Output Drum mix:
12-bit PWM out put pin giving result of dr um
speed error and phase er r or aft er f ilter ing
Vpulse 110 Output Additional V pulse:
Three-level output pin f or additional V signal
synchronized to t he Video FF signal
C.Rotary
/PS0 103 Output,
input/
output
Color rotary signal:
Output pin for color signal processing contr ol
signal in f our -head special-effect s playback
H.AmpSW
/PS1 104 Output,
input/
output
Head-amp switch:
Output pin for pr eam plifier out put select signal in
four- head special-ef f ect s playback. This pin can
also be used as a general port when not used
COMP
/PS2 105 Input,
input/
output
Compare input:
Input pin f or signal giving the result of
preamplifier output com par ison in four - head
special-effect s playback. This pin can also be
used as a general port when not used
CTL (+ )
CTL (-) 1
3Input
/output CTL head (+) and (-) pins:
I/O pins for CTL signals
Servo
circuits
CTL Bias 4 Input CTL primary amp bias supply:
Bias supply pin f or CTL primar y am p
Rev. 2.0, 11/ 00, page 12 of 1037
Type Symbol Pin No. I/O Name and Funct i on
CTL Amp
(o) 6 Output CTL amp output:
Out put pin for CTL amp
CTL SMT
(l) 7 Input CTL Schmitt am p input :
Input pin for CTL Schmit t am p
CTLFB 5 Input CLT feedback input:
Input pin for CTL amp high- r ange char act er ist ics
control
CTLREF 112 Output CTL amp refer ence volt age out put :
Output pin for 1/ 2Vcc (SV)
CFG 8 I nput Capstan FG input :
Schmitt com par at or input pin for CFG signal
DFG 108 Input Drum FG input:
Schmitt input pin f or DFG signal
DPG/PS3 107 Input,
input/
output
Drum PG input :
Schmitt input pin f or DPG signal. This pin can
also be used as a general port when not used
EXCTL
/PS4 106 Input,
input/
output
External CTL input:
Input pin for ext ernal CTL signal. This pin can
also be used as a general port when not used
Csync 98 Input Mixed sync signal input:
Input pin f or m ixed sync signal
EXCAP 91 Input Capstan external sync signal input:
Signal input pin f or ext er nal synchr onization of
capstan phase contr ol
EXTTRG 90 Input External trigger signal input:
Signal input pin f or synchr onization with
refer ence signal generat or
SV1 92 Output Servo monit or out put pin 1:
Out put pin for servo m odule inter nal signal
SV2 93 Output Servo monit or out put pin 2:
Out put pin for servo m odule inter nal signal
Servo
circuits
PPG7 to
PPG0 89 t o
85, 83,
81, 80
Output PPG:
Out put pin for HSW timing generat or . To be
used when head switching is required as well as
Audio FF and Video FF
Rev. 2.0, 11/ 00, page 13 of 1037
Type Symbol Pin No. I/O Name and Function
P07 to P00 11 to 18 Input Port 0:
8-bit input pins
P17 to P10 61 to 54 Input
/output Port 1 :
8-bit I / O pins
P27 to P20 53 to 46 Input
/output Port 2 :
8-bit I / O pins
P37 to P30 44,
42 to 36 Input
/output Port 3 :
8-bit I / O pins
P47 to P40 35 to 28 Input
/output Port 4 :
8-bit I / O pins
P53 to P50 27 to 24 Input
/output Port 5 :
4-bit I / O pins
P67 to P60 79 to 72 Input
/output Port 6 :
8-bit I / O pins
P77 to P70 89 to
85, 83,
81, 80
Input
/output Port 7 :
8-bit I / O pins
P87 to P80 97 to 90 Input
/output Port 8 :
8-bit I / O pins
RP7 to RP0 79 to 72 Output Realtime out put por t:
8-bit r ealtim e out put pins
I/O port
TRIG 27 Input Realtime output port t r igger input:
Input pin for r ealt ime out put port t r igger
Rev. 2.0, 11/ 00, page 14 of 1037
1.4 Dif f eren ces bet ween H8S /2194C S eries and H8S/ 2194 Series
Though the H8S/2194C series is compatible with the H8S/2194 series and their supporting
modules are almost identical, there are some differences between them as shown below. For
details, see the following sections.
Table 1.3 Differences between H8S/2194C series and H8S/2194 series
H8S/2194C Series H8S/2194 Series
ROM H8S/2194C: 256 kbytes
H8S/2194B: 192 kbytes
H8S/2194A: 160 kbytes
H8S/2194: 128 kbytes
H8S/2193: 112 kbytes
H8S/2192: 96 kbytes
H8S/2191: 80 kbytes
RAM H8S/2194C: 6 kbytes
H8S/2194B: 6 kbytes
H8S/2194A: 6 kbytes
H8S/2194: 3 kbytes
H8S/2193: 3 kbytes
H8S/2192: 3 kbytes
H8S/2191: 3 kbytes
Timer J Five operating modes: TM J- 2 input
clock s ou r c e s : PSS= φ/16384, φ/2048,
or φ/1024; underf low of TM J- 1,
external clock (I RQ2)
Four operat ing m odes: TM J- 2 input
clock s ou r c e s : PSS= φ/ 16384 or
φ/2048; under f low of TM J- 1, exter nal
clock (IRQ2)
Servo circuit In t he r ef er ence signal generat or , the
servo circuit selects whet her
refer ence signals are generated with
VD when it is in PB mode, or in f r ee-
run
In t he r ef er ence signal generat or ,
when the servo circ uit is in PB mode,
refer ence signals are generated in
free-run
Flash ROM 256 kbytes
When the f lash ROM cont r ol f lag is
set, use t he E (er ase) bit and the P
(program) bit in flash memory control
register 1 ( FM LCR1).
128 kbytes
When the f lash ROM cont r ol f lag is
set, use t he E (er ase) bit and t he P
(program) bit in flash memory control
register 2 ( FM LCR2).
Rev. 2.0, 11/ 00, page 15 of 1037
Section 2 CPU
2.1 Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture
that is upward-compatible with the H8/300 and H8/300H CPUs. T he H8S/ 2000 CPU ha s si x teen
16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space,
and is ideal for realtime control.
2.1.1 Features
The H8S/ 2000 CPU has the following features.
• Upward-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addre ssing mode s
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes (4 Gbytes architecturally)
• High-speed operation
All frequently-used instructions execute in one or two states
Maximum clock rate: 10 MHz
8/16/32-bit register-register add/subtract: 100 ns
8 × 8-bit register-register multiply: 1200 ns
Rev. 2.0, 11/ 00, page 16 of 1037
16 ÷ 8-bit regi ster-re gi ster di vi de: 1200 ns
16 × 16-bit register-register multiply: 2000 ns
32 ÷ 16-bit re giste r-re giste r di vide : 2000 ns
• Two CPU operating modes
Normal mode*/Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Note: * Normal mode is not available for this LSI.
2.1.2 Differences between H8S/ 2600 CPU and H8S/2000 CPU
The diffe re nce s bet ween t he H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register i s supported onl y by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and ST MAC a re support e d onl y by t he
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions differ as follows.
Number of Execut i on St at es
Instruction Mnemonic H8S/2600 H8S/2000
MUL XU.B Rs, Rd 3 12MULXU
MULXU.W Rs , Er d 4 20
MULXS.B Rs, Rd 4 13MULXS
MULXS.W Rs , Er d 5 21
There are also differences in the address space, EXR register functions, power-down state, etc.,
depending on t he product .
2.1.3 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general re gi sters and c ont rol re gi sters
Eight 16-bi t ext e nded re gi sters, and one 8-bi t c ont rol re gi ster, ha ve bee n a dded.
Rev. 2.0, 11/ 00, page 17 of 1037
• Expanded addre ss space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced a ddre ssing mode
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
2.1.4 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional c ont rol re gi ster
One 8-bit cont rol regi ste r has bee n a dded.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Rev. 2.0, 11/ 00, page 18 of 1037
2.2 CPU Operat in g Mod es
The H8S/ 2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total
address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of
16 Mbytes for the program area and a maximum of 4 Gbytes for the data area).
The mode is selected by the mode pins of the microcontroller.
CPU operating mode
Normal mode*
Advanced mode
Maximum 64 kbytes for program
and data areas combined
Maximum 16 Mbytes for program
and data areas combined
Note: * Normal mode is not available for this LSI.
Figure 2.1 CPU Operating Modes
(1) Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
(a) Address Space
A maximum address space of 64 kbytes can be accessed.
(b) Extende d Re giste rs (En)
The ext e nded re gi sters (E0 t o E 7) ca n be used as 16-bit re giste rs, or a s the upper 16-bi t
segments of 32-bit registers. When En is used as a 16-bit register it can contain any
value, e ve n when the c orresponding ge ne ral re giste r (Rn) i s used as an addre ss registe r.
If the general register is referenced in the register indirect addressing mode with pre-
decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the
value in the corresponding extended register (En) will be affected.
(c) Instruc t ion Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
Rev. 2.0, 11/ 00, page 19 of 1037
(d) Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H' 0000 is allocated to the exception vector table.
One branch address is stored per 16 bits. The configuration of the exception vector table
in normal mode is shown in figure 2.2. For details of the exception vector table, see
section 5, Exception Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
Exception vector 1
Exception vector 2
Exception vector table
(Reserved for system use)
Figure 2. 2 Exc e ption Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR
instructions uses an 8-bit absolute address included in the instruction code to specify a
memory operand that contains a branch address. In normal mode the operand is a 16-bit
word operand, provi ding a 16-bi t bra nc h addre ss. Branc h a ddresses can be store d in t he
top area from H'0000 to H'00FF. Note that this area is also used for the exception vector
table.
Rev. 2.0, 11/ 00, page 20 of 1037
(e) Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC
and condition-code register (CCR) are pushed onto the stack in exception handling, they
are stored a s shown in figure 2. 3. T he e xt ende d c ontrol re giste r (E XR) is not pushed onto
the stack. For details, see section 5, Exception Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(16 bits) CCR
CCR*
PC
(16 bits)
SP SP
Note: * Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode
(2) Advanced Mode
(a) Address Space
Linear access is provided to a 16-Mbyte maximum address space (architecturally a
maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum
of 4 Gbytes for program and data areas combined).
(b) Extende d Re giste rs (En)
The ext e nded re gi sters (E0 t o E 7) ca n be used as 16-bit re giste rs, or a s the upper 16-bi t
segments of 32-bit re giste rs or addre ss registers.
(c) Instruc t ion Set
All instruct i ons and addre ssing mode s can be used.
Rev. 2.0, 11/ 00, page 21 of 1037
(d) Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode the top area starting at H'00000000 is allocated to the exception vector
table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address
is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see
section 5, Exception Handling.
H'00000000
H'00000003
H'00000004
H'0000000B
H'0000000C
Exception vector table
Reserved
Reset exception vector
(Reserved for system use)
Reserved
Exception vector 1
Reserved
H'00000010
H'00000008
H'00000007
Figure 2. 4 Exc e ption Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR
instructions uses an 8-bit absolute address included in the instruction code to specify a
memory operand that contains a branch address. In advanced mode the operand is a 32-
bit longword opera nd, provi ding a 32-bi t bra nc h addre ss. The uppe r 8 bit s of the se 32
bits are a re served a re a t ha t i s rega rded a s H'00. Branc h a ddresses can be store d in t he
area from H'00000000 t o H'000000FF. Note t ha t t he first pa rt of thi s range is al so the
exception vector table.
Rev. 2.0, 11/ 00, page 22 of 1037
(e) Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a
subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack
in exce pt ion ha ndl ing, t he y are store d as shown in figure 2. 5. T he ext e nded c ont rol
register (EXR) is not pushed onto the stack. For details, see section 5, Exception
Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(24 bits)
CCR
PC
(24 bits)
SP SP
Reserved
Figure 2.5 Stack Structure in Advanced Mode
Rev. 2.0, 11/ 00, page 23 of 1037
2.3 Address Space
Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.
(b) Advanced mode
H'0000
H'FFFF
H'00000000
H'FFFFFFFF
H'00FFFFFF
(a) Normal mode*
Data area
Program area
Cannot be used
with this LSI
Note: * Normal mode is not available for this LSI.
Figure 2.6 Memory Map
Rev. 2.0, 11/ 00, page 24 of 1037
2.4 Register Configuration
2.4.1 Overview
The CPU has the int e rnal re giste rs shown in figure 2. 7. T here a re t wo type s of registe rs:
general re giste rs and c ontrol re giste rs.
T – – – – I2 I1 I0EXR 76543210
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
General Registers (Rn) and Extended Registers (En)
Control Registers (CR)
[Legend]
SP
PC
EXR
T
I2 to I0
CCR
I
UI
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
IUIHUNZVC
CCR 76543210
: Half-carry flag
: User bit
: Negative flag
: Zero flag
: Overflow flag
: Carry flag
H
U
N
Z
V
C
: Stack pointer
: Program counter
: Extended control register
: Trace bit
: Interrupt mask bits
: Condition-code register
: Interrupt mask bit
: User bit or interrupt mask bit
Note: * Does not affect operation in this LSI.
*
Fi g ur e 2 .7 CP U Regi st e r s
Rev. 2.0, 11/ 00, page 25 of 1037
2.4.2 General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a
data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers
are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to
ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E regi ste rs (E0 to E 7) a re a l so referre d t o as ext e nded re gi sters.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen
8-bit regi ste rs.
Figure 2.8 illustrates the usage of the general registers. The usage of each register can be
selected independently.
Address registers
32-bit registers 16-bit registers 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
Rev. 2.0, 11/ 00, page 26 of 1037
SP (ER7)
Free area
Stack area
Figure 2. 9 Stack
2.4.3 Control Register s
The cont rol regi ste rs are t he 24-bit progra m c ount er (PC), 8-bit e xte nde d cont rol regi ste r (EXR),
and 8-bit c ondi ti on-c ode re gi ster (CCR).
(1) Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
(When an instruction is fetched, the least significant PC bit is regarded as 0.)
(2) Extended Control Register (EXR)
An 8-bit register. In this LSI, this register does not affect operation.
Bit 7: Trace Bi t (T)
This bit is reserved. In this LSI, this bit does not affect operation.
Bits 6 to 3: Reserved
These bits are reserved. They are always read as 1.
Bits 2 to 0: Interrupt Mask Bits (I2 to I0)
These bits are reserved. In this LSI, these bits do not affect operation.
(3) Condit i o n: Code Re giste r ( CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit
(I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7: Interrupt Mask Bit (I)
Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit
setting.) The I bit is set to 1 by hardware at the start of an exception-handling sequence.
For details, see section 6, Interrupt Controller.
Rev. 2.0, 11/ 00, page 27 of 1037
Bit 6: User Bit or Interr upt Mask Bit (UI)
Can be written and read by software using the LDC, STC, ANDC, ORC , an d XORC
instructions. This bit can also be used as an interrupt mask bit. For details, see section 6,
Interrupt Controller.
Bit 5: Half-Carr y F lag (H )
When t h e ADD.B, ADDX. B, SUB.B, SUBX. B , CMP. B , or NEG. B i n st r uction is
executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
oth e r wi se. W h e n t h e ADD.W , SUB .W, CMP.W , o r NE G.W inst r u ction is executed, the
H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When
the ADD. L , SUB.L, CMP.L , o r NE G.L inst r uction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to 0 otherwise.
Bit 4: User Bit (U)
Can be written and read by software using the LDC, STC, ANDC, ORC , an d XORC
instructions.
Bit 3: Negative F l ag (N)
Stores the value of the most significant bit (sign bit) of data.
Bit 2: Zero F l ag (Z)
Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1: Over fl ow Flag (V)
Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.
Bit 0: Carry Fl ag (C)
Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
(a) Add instructions, to indicate a carry
(b) Subtract instructions, to indicate a borrow
(c) Shift and rotate instructions, to store the carry
The carry flag is also used as a bit accumulator by bit-manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each
instruction on the flag bits, see section 29, Appendix A.1, List of Instructions.
Operat i ons c a n be perform e d on t he CCR bi t s by the L DC, STC, ANDC, ORC, a nd XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional
branch (Bcc ) i nstruct i ons.
2.4.4 Initial Regi ster Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not
initialized. The stack pointer should therefore be initialized by an MOV. L inst r u ction executed
immediately after a reset.
Rev. 2.0, 11/ 00, page 28 of 1037
2.5 Dat a F orm at s
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-
bit BCD data.
2.5.1 Ge neral Regi ster Data For mats
Figure 2.10 shows the data formats in general registers.
70
70
MSB LSB
MSB LSB
7043
Upper digit Lower digit
Don't care
Don't care
Don't care
7043
Upper digit Lower digit
70
Don't care
65432710
70
Don't care 65432710
Don't care
Data FormatData type
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
General Register
RnH
RnL
RnH
RnL
RnH
RnL
Figure 2. 10 G e neral Regi ster Data For mats (1)
Rev. 2.0, 11/ 00, page 29 of 1037
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
En Rn
Data Type
Word data
Word data
Longword data
General Register
Rn
En
ERn
Data format
ERn
En
Rn
RnH
RnL
MSB
LSB
: General register ER
: General register E
: General register R
: General register RH
: General register RL
: Most significant bit
: Least significant bit
[Legend]
Figure 2. 10 G e neral Regi ster Data For mats (2)
Rev. 2.0, 11/ 00, page 30 of 1037
2.5.2 Memory Data For mats
Figure 2.11 shows the data formats in memory.
The CPU can access word data and longword data in memory, but word or longword data must
begin at an even address. If an attempt is made to access word or longword data at an odd
address, no address error occurs but the least significant bit of the address is regarded as 0, so the
access starts at the preceding address. This also applies to instruction fetches.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Address
Address L
Address L
Address 2M
Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
1-bit data
Byte data
Word data
Longword data
Data Type Data Format
Address 2M+1
Figure 2. 11 M e mory Data For mats
When ER7 (SP) is used as an address register to access the stack, the operand size should be
word size or longword size.
Rev. 2.0, 11/ 00, page 31 of 1037
2.6 Instruction Set
2.6.1 Overview
The H8S/ 2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Tabl e 2 .1 Instruc t i o n Cl a ssi f i cation
Function Instructions Size Types
MOV BWL
POP*1, PUSH*1WL
LDM, STM L
Data transfer
MOVFPE*3, M OVTPE*3B
5
ADD, SUB, CMP, NEG BWL
ADDX, SUBX, DAA, DAS B
INC, DEC BWL
ADDS, SUBS L
MULXU, DI VXU, M ULXS, DI VXS BW
EXTU, EXTS WL
Arithmetic
TAS*4B
19
Logic operations AND, OR, XO R, NOT BWL 4
Shif t SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
ROTXL, RO TXR BWL 8
Bit m a n ipula tion RSET, BCLR, BNO T , BTST, BL D, BIL D, BST,
BIST, BAND, BIAND, BOR, BIO R, BXO R,
BIXOR
B14
Branch Bcc*2, JMP, BSR, JSR, RTS 5
System c o ntr ol TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC,
XORC, NO P 9
Block d ata t rans fer EEPMO V 1
Total : 65 t ypes
Notes: B: byte size; W: wor d size; L: longword size.
1. POP.W Rn and PUSH.W Rn are identical to MO V. W @SP+, Rn and MOV. W Rn, @ -
SP.
POP.L ERn and PUSH.L ERn are identical to MOV. L @ SP+, ERn and MO V. L ERn,
@-SP.
2. Bcc is the general name for condit ional branch instruct ions.
3. Not available in t his LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.0, 11/ 00, page 32 of 1037
2. 6.2 Instructi o ns and Addressing M o de s
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000
CPU can use.
Tabl e 2 .2 Combi nat i o ns o f Inst r ucti o ns and Addressing M o de s
Addressing Modes
Function
Arithmetic operationsSystem control
Branch
Logic
operation
Instruction
MOV
POP, PUSH
LDM, STM
ADD, CMP
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
NEG
EXTU, EXTS
TAS
*
2
MOVFPE,
MOVTPE
*
1
MULXU,
DIVXU
MULXS,
DIVXS
AND, OR,
XOR
ANDC,
ORC, XORC
NOT
Bcc, BSR
JMP, JSR
RTS
TRAPA
RTE
SLEEP
LDC
STC
NOP
Shift
Bit manipulation
Block data transfer
Data transfer
BWL
#xx
—
—
BWL
WL
B
—
—
—
—
—
—
—
—
—
BWL
B
—
—
—
—
—
—
—
B
—
—
—
—
—
BWL
Rn
—
—
BWL
BWL
B
L
BWL
B
BWL
WL
—
—
BW
BW
BWL
—
BWL
—
—
—
—
—
—
B
B
—
BWL
B
—
BWL
@ERn
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
B
—
BWL
@(d:16, ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
BWL
@(d:32, ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
BWL
@-ERn/@ERn+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
B
@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
BWL
@aa:16
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
B
—
—
@aa:24
—
—
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BW
[Legend]
B: Byte
W: Work
L: Longword
Note: *1 Cannot be used in this LSI.
*2 Only register ER0, ER1, ER4, or ER5 should be used when using t he TAS instruct ion.
Rev. 2.0, 11/ 00, page 33 of 1037
2. 6.3 Tabl e o f Instruct i o ns Cl a ssi f i ed by F unc t i o n
Table 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
table 2. 3 i s define d be low.
Operation Not a t i on
Rd General r egister (destination) *
Rs General r egister (source) *
Rn General r egister *
ERn General r egister (32-bit r egist er )
(EAd) Destination operand
(EAs) Source operand
EXR Extended contr ol register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (o v erf lo w) f lag in CCR
C C (carry) flag in CCR
PC Program count er
SP Stack pointer
#IMM Imm ediat e dat a
Disp Displacement
+ Addition
−Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Logical exclusive O R
→Move
∼NOT (logic al c o mplem e n t)
:8/ : 16/ : 24/:32 8-, 16- , 24-, or 32- bit length
Note: *Gener al register s include 8-bit r egister s ( R0H to R7H, R0L to R7L), 16- bit r egister s
(R0 to R7, E0 to E7), and 32- bit r egister s ( ER0 to ER7).
Rev. 2.0, 11/ 00, page 34 of 1037
Table 2.3 Data Transfe r Instr uc ti ons
Instruction Size*Function
MOV B/W/L (EAs) → Rd, Rs → ( EAd )
Moves data between two general register s or between a general
register and m em or y, or m oves imm ediat e dat a t o a gener al
register
MOVFPE B Cannot be used in this LSI
MOVTPE B Cannot be used in this LSI
POP W/L @ SP+ → Rn
Pops a general register f r om t he st ack
POP.W Rn is identical to M O V. W @ SP+, Rn
POP.L ERn is identical to MO V. L @ SP+, ERn
PUSH W/L Rn → @-SP
Pushes a general register ont o t he st ack
PUSH. W Rn is identical to MOV.W Rn, @-SP
PUSH. L ERn is identical to MOV.L ERn, @ - SP
LDM L @SP+ → Rn (register list)
Pops two or mor e gener al register s f r om t he stack
STM L Rn (r egist er list) → @-SP
Pushes two or mor e general r egister s ont o t he stack
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
L: Longword
Rev. 2.0, 11/ 00, page 35 of 1037
Tabl e 2 .4 Ari thm e t i c Instr uc t i o ns
Instruction Size*1Function
ADD
SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Perfor m s addit ion or subt raction on data in t wo general
register s, or on immediate data and data in a general register .
(Im mediate byte data cannot be subt r act ed from byt e dat a in a
general register . Use the SUBX or ADD instruction)
ADDX
SUBX BRd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Perfor m s addit ion or subt raction with carr y on byte data in two
general register s, or on im m ediate data and data in a general
register
INC
DEC B/W /L Rd ± 1 → Rd, Rd ± 2 → Rd
Increm ent s or decr em ent s a gener al r egister by 1 or 2. ( Byt e
operands can be increment ed or decr em ent ed by 1 only)
ADDS
SUBS BRd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtr act s t he value 1, 2, or 4 to or f r om dat a in a 32- bit
register
DAA
DAS B/W Rd decimal adjust → Rd
Decimal-adjusts an addition or subtr act ion result in a general
regist er by r eferr ing t o t he CCR t o pr oduce 4-bit BCD dat a
MULXU B/W Rd × Rs → Rd
Perfor m s unsigned m ultiplication on data in t wo general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×16 bits → 32
bits
MULXS B/W Rd × Rs → Rd
Perfor m s signed m ultiplication on data in t wo general regist er s:
either 8 bits × 8 bit s → 16 bits or 16 bit s ×16 bits → 32 bits
DIVXU B/W Rd ÷ Rs → Rd
Perform s unsigned division on data in two general registers:
either 16 bits ÷ 8 bits × 8- bit quot ient and 8- bit r em ainder or 32
bits ÷ 16 bits × 16- bit quotient and 16-bit r em ainder
Rev. 2.0, 11/ 00, page 36 of 1037
Instruction Size*1Function
DIVXS B/W Rd ÷ Rs → Rd
Perform s signed division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quot ient and 8- bit r em ainder or 32 bit s ÷
16 bits → 16-bit quot ient and 16- bit r em ainder
CMP B/W/L Rd - Rs, Rd - #IMM
Compares dat a in a general regist er with dat a in anot her
general r egist er or wit h immediat e data, and s et s CCR bit s
according to the r esult
NEG B/W/L 0 - Rd → Rd
Takes the two's com plement ( ar ithm et ic complement ) of data in
a general register
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16- bit r egist er t o word size, or t he
lower 16 bits of a 32- bit r egist er t o longword size, by padding
with zeros on the left
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16- bit r egist er t o word size, or t he
lower 16 bits of a 32- bit r egist er t o longword size, by ext ending
the sign bit
TAS B @ERd - 0, 1 → (<bit 7> of @ERd) *2
Tests mem or y cont ents, and set s t he m ost significant bit ( bit 7)
to 1
Note: *1 Size r ef er s t o t he oper and size.
B: Byte
W: Word
L: Longword
*2 Only register ER0, ER1, ER4, or ER5 should be used when using t he TAS instruct ion.
Rev. 2.0, 11/ 00, page 37 of 1037
Tabl e 2 .5 Logi c Instr uc t i o ns
Instruction Size*Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Perfor m s a logical AND operation on a general register and
another gener al r egister or immediate data
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Perfor m s a logical OR operat ion on a general r egister and
another gener al r egister or immediate data
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Perfor m s a logical exclusive OR operation on a general r egister
and another gener al r egister or immediate data
NOT B/W/L ~ Rd → Rd
Takes the one's complem ent ( logical complement ) of gener al
register contents
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
L: Longword
Tabl e 2 .6 Shift Instruct i o ns
Instruction Size*Function
SHAL
SHAR B/W/ L Rd (shift) → Rd
Perfor m s an ar it hm et ic shift on general regist er cont ent s
A 1-bit or 2- bit shif t is possible
SHLL
SHLR B/W/ L Rd (shift) → Rd
Perfor m s a logical shift on gener al regist er cont ents
A 1-bit or 2- bit shif t is possible
ROTL
ROTR B/W/L Rd (rotate) → Rd
Rotates general regist er cont ent s
1-bit or 2- bit r ot ation is possible
ROTXL
ROTXR B/W/L Rd (rotate) → Rd
Rotates general regist er cont ent s t hr ough t he car r y f lag
1-bit or 2- bit r ot ation is possible
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
L: Longword
Rev. 2.0, 11/ 00, page 38 of 1037
Tabl e 2 .7 Bit M a ni pul a t i o n Instruct i o ns
Instruction Size*Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general regist er or m em or y oper and to
1. The bit num ber is specified by 3-bit imm ediat e dat a or the
lower three bit s of a gener al r egister
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memor y oper and
to 0. The bit num ber is specified by 3- bit im m ediate data or t he
lower three bit s of a gener al r egister
BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Invert s a specif ied bit in a general register or m em or y oper and.
The bit number is specified by 3-bit imm ediate data or t he lower
three bit s of a gener al r egister
BTST B ~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general regist er or m em or y oper and
and sets or clears t he Z flag accordingly. The bit number is
specified by 3-bit imm ediate data or t he lower t hr ee bit s of a
general register
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry f lag with a specified bit in a general regist er or
memor y oper and and st or es t he r esult in the carry f lag
BIAND B C ∧ [~(<bit-No.> of <EAd>)] → C
ANDs the carry f lag with t he inverse of a specified bit in a
general register or m em or y oper and and st or es t he result in the
carry flag
The bit number is specified by 3-bit imm ediat e dat a
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the car r y f lag with a specified bit in a general register or
memor y oper and and stores t he r esult in t he car r y f lag
BIOR B C∨ [~(<bit-No.> of <EAd>)] → C
ORs the car r y flag with the inverse of a specified bit in a gener al
register or memory oper and and stores t he r esult in the carry
flag
The bit number is specified by 3-bit imm ediat e dat a
Rev. 2.0, 11/ 00, page 39 of 1037
Instruction Size*Function
BOXR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carr y f lag with a specified bit in a general
register or m em or y oper and and stores t he r esult in the car r y
flag
BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carr y f lag with the inverse of a specif ied bit in
a general register or m em or y oper and and st or es the result in
the carr y f lag
The bit number is specified by 3-bit imm ediate data
BLD B (<bit-No.> of <EAd>) → C
Transfer s a specified bit in a general r egister or mem or y
operand to the carr y f lag
BILD B ~ (<bit-No.> of <EAd>) → C
Transfer s t he invers e of a specified bit in a gener al regist er or
memor y oper and t o t he car r y f lag
The bit number is specified by 3-bit imm ediat e dat a
BST B C → (<bit-No.> of <EAd>)
Transfer s t he car r y flag value to a specified bit in a general
register or m em or y oper and
BIST B ~ C → (<bit-No.> of <EAd>)
Transfer s t he invers e of t he car r y f lag value to a specified bit in
a general register or m em or y oper and
The bit number is specified by 3-bit imm ediat e dat a
Note: *Size refers t o t he oper and size.
B: Byte
Rev. 2.0, 11/ 00, page 40 of 1037
Tabl e 2 .8 Bra nc h Inst r uc t i o ns
Instruction Size*Function
Bcc Branches to a specif ied address if a specif ied condition is true
The branching conditions are listed below
JMP Branches unconditionally to a specified address
BSR Branches to a subroutine at a specified address
JSR Branches to a subrout ine at a specif ied address
RTS Returns fr om a subr out ine
Mnemonic Description Condition
BRA (BT) Always (Tr ue ) Always
BRN (BF) Never (False) Never
BHI HIgh CVZ = 0
BLS Low of Same CVZ = 1
BCC (BHS) Car ry Clea r (Hig h or Sam e ) C = 0
BCS (BLO) Carry Set (LOw) C = 1
BNE Not Equal Z = 0
BEQ EQual Z = 1
BVC oVerflow Clear V = 0
BVS oVerflow Set V = 1
BPL PLus N = 0
BMI MInus N = 1
BGE Gr eater or Equal NV = 0
BLT Less Than N ⊕ V = 1
BGT Great er Than Z∨ (N ⊕ V) = 0
BLE Less or Equal Z∨ (N ⊕ V) = 1
Rev. 2.0, 11/ 00, page 41 of 1037
Tabl e 2 .9 Syste m Co nt r o l Inst r uc t i o ns
Instruction Size*Function
TRAPA Start s t r ap- instr uct ion except ion handling
RTE Returns f r om an except ion- handling rout ine
SLEEP Causes a transition t o a power- down stat e
LDC B/W (EAs) → CCR, (EAs) → EXR
Moves content s of a gener al r egister or m em or y or imm ediat e
data t o CCR or EXR. Although CCR and EXR are 8- bit
register s, word- s ize t r ansf er s ar e per form ed bet ween t hem and
memor y . The upper 8 bits ar e valid
STC B/W CCR → (EAd) , EXR → (EAd)
Transf ers CCR or EXR c ont ents to a gener al r egis t er or
mem or y . Although CCR and EXR are 8- bit regis t er s , word-s ize
transfers ar e per f or med between them and m emory. The upper
8 bits are valid
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs t he CCR or EXR cont ent s wit h immediate data
ORC B CCR∨ #IMM → CCR, EXR∨ #IMM → EXR
Logically O Rs the CCR or EXR contents with imm ediate data
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exc lusiv e- ORs t he CCR or EXR c ontents wit h
immediate dat a
NOP PC + 2 → PC
Only increment s t he pr ogr am count er
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
Rev. 2.0, 11/ 00, page 42 of 1037
Table 2.10 Block Data Transfe r Instr uc ti ons
Instruction Size*Function
EEPMOV.B if R4L ≠ 0 t hen
Repeat @ER5+→@er6+
R4L−1→R4L
Unt il R4L = 0
else next;
EEPMOV.W if R4 ≠ 0 t hen
Repeat @ER5+→@er6+
R4−1→R4
Unt il R4 = 0
else next;
Transfer s a dat a block according t o par am et er s set in general
registers R4L or R4, ER5, and ER6
R4L or R4: size of block (bytes)
ER5: start ing source addr ess
ER6: starting destination address
Execution of the next inst r uct ion begins as soon as the t r ansf er
is co mpleted
Rev. 2.0, 11/ 00, page 43 of 1037
2.6. 4 Basic Instr uct i on F or mats
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.12 shows examples of instruction formats.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B@(d:16, Rn), Rm, etc.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
rn rm
op
EA (disp)
(4) Operation field, effective address extension, and condition field
op cc EA (disp) BRA d:16, etc.
Fig ure 2.12 Instruct i on F or mats (Exampl e s)
(1) Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
(2) Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits
or 4 bits. Some instructions have two register fields. Some have no register field.
(3) Effective Address Extension
Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
(4) Condition Field
Specifies the branching condition of Bcc instructions.
Rev. 2.0, 11/ 00, page 44 of 1037
2. 6.5 Notes on Use o f B i t - M a ni pul a t i o n Instruct i o ns
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit
manipulation, then write back the byte of data. Caution is therefore required when using these
instructions on a register containing write-only bits, or a port.
The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the
relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt
handling routine, etc.
Rev. 2.0, 11/ 00, page 45 of 1037
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressi ng Mode
The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset
of these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit-manipulation instructions use register direct, register
indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR,
BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in
the opera nd.
Tabl e 2 .11 Addressing M o de s
No. Addressing M ode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/ @ ( d: 32, ERn)
4 Register indirect with post- increm ent
Register indirect with pre- decr ement @ERn+
@-ERn
5 Absolute address @aa: 8/ #@ aa: 16/@aa: 24/ @aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program - count er r elat ive @(d:8,PC)/ @ ( d:16,PC)
8 Memor y indirect @@aa:8
(1) Register Direct–Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register
containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0
to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-
bit registers.
(2) Register Indirect–@Ern
The register field of the instruction code specifies an address register (ERn) which contains
the address of the operand in memory. If the address is a program instruction address, the
lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H' 00).
(3) Register Indirect with Displacement–@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a
memory operand. A 16-bit displacement is sign-extended when added.
Rev. 2.0, 11/ 00, page 46 of 1037
(4) Register Indirect with Post-Increment or Pre-Decrement–@ERn+ or @-ERn
(a) Register indirect with post-increment–@ERn+
The register field of the instruction code specifies an address register (ERn) which
contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to t he addre ss registe r cont e nts and t he sum is stored i n t he a ddre ss register. T he
value added is 1 for byte access, 2 for word access, or 4 for longword access. For word
or longword access, the register value should be even.
(b) Register indirect with pre-decrement–@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register
field in the instruction code, and the result becomes the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access,
2 for word access, or 4 for longword access. For word or longword access, the register
value should be e ven.
(5) Absolute Addre ss–@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute
address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits
long (@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1
(H'FFFF). For a 16-bi t ab sol ut e a ddre ss th e uppe r 16 bit s a re a si gn e xt e nsi on. A 32-bi t
absolute address can access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The
upper 8 bits are all assumed to be 0 (H'00).
Table 2.12 indicates the accessible absolute address ranges.
Tabl e 2 .12 Absol ut e Addr ess Access Ra ng e s
Absolute Addr ess Norm al Mode Advanced Mode
8 bits
(@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits
(@aa:16) H'000000 to H007FFF, H'FF8000 to
H'FFFFFF
Data address
32 bits
(@aa:32)
Program inst r uct ion
address 24 bits
(@aa:24)
H'0000 to H'FFFF
H'000000 to H'FFFFFF
Rev. 2.0, 11/ 00, page 47 of 1037
(6) Immediate–#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.
The ADDS, SUB S, I NC , and DEC i n st r uctions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a
bit nu m b e r . The T R APA i n st r u ction contains 2-bit immediate data in its instruction code,
specifying a ve ct or a ddress.
(7) Program-Counter Relati ve –@(d:8, P C) or @(d:16, P C)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction is sign-extended and added to the 24-bit PC contents to generate
a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are
all assumed to be 0 (H'00). The PC value to which the displacement is added is the address
of the first byt e of the ne xt i nstruc ti on, so the possible bra nc hing ra nge is -126 to + 128 byt es
(-63 to +64 words) or -32766 to +32768 byte s (-16383 to + 16384 words) from the bra nc h
instructi on. T he re sult ing va l ue should be a n eve n num ber.
(8) Memory Indirect–@@aa:8
This m od e can b e u se d by t h e JMP and JSR i n st r u ctions. The instruction code contains an 8-
bit absolute address specifying a memory operand. This memory operand contains a branch
address. The upper bits of the absolute address are all assumed to be 0, so the address range
is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode the memory operand is a word operand and the branch address is 16 bits
long. In advanced mode the memory operand is a longword operand, the first byte of which
is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further
details, see section 5, Exception Handling.
(a) Normal Mode (b) Advanced Mode
Branch address Specified by
@aa:8
Specified by
@aa:8 Reserved
Branch address
Figure 2.13 Branch Address Specification in Memory Indirect Mode
Rev. 2.0, 11/ 00, page 48 of 1037
If an odd address is specified in word or longword memory access, or as a branch address,
the least significant bit is regarded as 0, causing data to be accessed or an instruction code to
be fetched at the address preceding the specified address. (For further information, see
section 2.5.2, Memory Data Formats.)
2.7.2 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode.
In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit
address.
Rev. 2.0, 11/ 00, page 49 of 1037
Table 2.13 Effective Address Calculation
No. Addressing M ode and
Inst r uct i on For m at Eff ective Address
Calculat ion Effect i ve Addr ess ( EA)
1 Register direct (Rn)
op rm rn
Operand is gener al regist er
contents
2 Register indirect ( @ ERn)
General register contents
31 0 31 0
rop
24 23
Don’t
care
3 Register indirect with displacement
@(d:16, ERn) or @ ( d: 32, ERn)
General register contents
Sign extension disp
31 0
31 0
31 0
op r disp Don’t
care
24 23
4 Register indirect with post- incr em ent or pr e- decr em ent
• Register indirect with post- increm ent @ ERn+
General register contents
1, 2, or
4
31 0 31 0
r
op
Don’t
care
24 23
• Register indirect with pre- decr ement @–ERn
General register contents
1, 2, or
4
Byte
Word
Longword
1
2
4
Operand
Size Value
Added
31 0
31 0
op rDon’t
care
24 23
Rev. 2.0, 11/ 00, page 50 of 1037
No. Addressing M ode and
Inst r uct i on For m at Eff ective Address
Calculat ion Effect i ve Addr ess ( EA)
5 Absolute addr ess
@aa:8
@aa:16
@aa:32
31 08 7
@aa:24
31 016 15
31 0
31 0
op abs
op abs
abs
op
op
abs
H'FFFF
24 23
Don’t
care
Don’t
care
Don’t
care
Don’t
care
24 23
24 23
24 23
Sign
exten-
sion
6 I m m ediate #xx: 8/#xx:16/ #xx: 32
op IMM
Operand is imm ediat e dat a
7 Progr am-count er r elat ive
@(d:8, PC)/ @ ( d:16, PC)
0
0
23
23
disp 31 0
24 23
op disp
PC contents
Don’t
care
Sign
exten-
sion
Rev. 2.0, 11/ 00, page 51 of 1037
No. Addressing M ode and
Inst r uct i on For m at Eff ective Address
Calculat ion Effect i ve Addr ess ( EA)
8 M em or y indirect @ @aa:8
• Nor m a l mode *
0
0
31 8 7
0
15
H'000000 31 0
16 15
op abs
abs
Memory
contents
H'00
24 23
Don’t
care
• Advanced mode
31
0
31 8 7
0
abs
H'000000
31 0
24 23
op abs
Memory contents Don’t
care
Note: *Not available in this LSI.
Rev. 2.0, 11/ 00, page 52 of 1037
2.8 Processin g St ates
2.8.1 Overview
The CPU has four main processing states: the reset state, exception-handling state, program
execution state, and power-down state. Figure 2.14 shows a diagram of the processing states.
Figure 2.15 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal processing flow in response
to a reset, interrupt or trap instruction.
Program execution
state
The CPU executes program instructions in sequence.
Power-down state
CPU operation is stopped
to conserve power.*
Sleep mode
Standby mode
Processing
states
Note: *
The power-down state also includes a medium-speed mode, modue stop mode, sub-active mode,
sub-sleep mode and watch mode.
Figure 2. 14 P r oce ssing States
Rev. 2.0, 11/ 00, page 53 of 1037
Reset state
Exception-handling state
Sleep mode
Standby mode
Power-down state
Program execution state
Interrupt request
External interrupt request
RES = High
Request for exception handling
SLEEP instruction
with LSON=0,
SSBY=0
SLEEP instruction
with LSON=0,
SSBY=0
Notes:
End of exception handling
*1
*2
1.
2.
From any state, a transition to the reset state occurs whenever RES goes low. A transition can
also be made to the reset state when the watchdog timer overflows.
The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For
details, see section 4, Power-Down State.
Figure 2. 15 State Tr ansitions
2.8.2 Reset State
When the
5(6
input goes low all current processing stops and the CPU enters the reset state.
All interrupts are disabled in the reset state. Reset exception handling starts when the
5(6
signal cha nge s from low to hi gh.
The reset state can also be entered by a watchdog timer overflow. For details, see section 17,
Watchdog Timer.
Rev. 2.0, 11/ 00, page 54 of 1037
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exce pt ion Handl i ng and T he ir Priori t y
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14
indicates the types of exception handling and their priority. Trap instruction exception
handling is always accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in
SYSCR.
Table 2.14 Exception Handling Types and Priority
Prior i ty Type of Except i on Detecti on Timi ng St ar t of Except i on Handling
Reset Synchronized with
clock Exception handling st ar t s
immediately af t er a low-t o- high
transit ion at the
5(6
pin, or when the
watchdog timer overf lows
Inter r upt End of instruct ion
execution or end of
exception-handling
sequence*1
When an interr upt is requested,
exception handling start s at the end
of the cur rent instr uct ion or cur r ent
exception-handling sequence
High
Low Trap instr uct ion When TRAPA
instruction is executed Exception handling starts when a tr ap
(TRAPA) instr uc tion is e x e cu ted*2
Notes: 1. I nterr upts are not detec t ed at the end of the ANDC, ORC, XO RC, and LDC
instructions, or imm ediately af t er r eset except ion handling.
2. Trap instruct ion exception handling is always accept ed in the pr ogram execut ion stat e.
(2) Reset Exception Handling
After the
5(6
pin has gone low and the reset state has been entered, when
5(6
goes high
again, reset exception handling starts. When reset exception handling starts the CPU fetches
a start address (vector) from the exception vector table and starts program execution from
that a ddre ss. All i nte rrupt s, i ncl udi ng NMI, are disabl e d during re set exc e pti on ha ndli ng a nd
after it ends.
(3) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack
pointer (ER7) and pushes the program counter and other control registers onto the stack.
Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the
CPU fetches a start address (vector) from the exception vector table and program execution
starts from tha t start a ddress.
Figure 2.16 shows the stack after exception handling ends.
Rev. 2.0, 11/ 00, page 55 of 1037
PC
(16 bits)
SP CCR
CCR
*1
PC
(24 bits)
SP CCR
Normal Mode Advanced Mode
*2
Notes: 1. Ignored when returning.
2. Normal mode is not available for this LSI.
Figure 2. 16 Stack Structure afte r Exce ption Handling (Examples)
2.8.4 Pr ogram Exe c ution State
In this state the CPU executes program instructions in sequence.
Rev. 2.0, 11/ 00, page 56 of 1037
2.8.5 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in
which the CPU does not stop. There are five modes in which the CPU stops operating: sleep
mode, standby mode, subsleep mode, and watch mode. There are also three other power-down
modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode,
the CPU operates on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode
are power-down modes that use subclock input. For details, see section 4, Power-Down State.
(1) Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bi t (SSBY) i n t he sta ndby c ont rol re gist e r (SBYCR) a nd t he L SON bi t i n t he l ow-
power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop
immediately after execution of the SLEEP instruction. The contents of CPU registers are
retained.
(2) Standby Mode
A transition to standby mode is made if the SLEEP instruction is executed while the SSBY
bit i n SBYCR i s set t o 1 a nd t he L SON bit i n L PWRCR a nd t he T MA3 bi t in th e T MA
(timer A) are both cleared to 0. In standby mode, the CPU and clock halt and all MCU
operations stop. As long as a specified voltage is supplied, the contents of CPU registers and
on-chip RAM are retained.
Rev. 2.0, 11/ 00, page 57 of 1037
2.9 Basic Timing
2.9.1 Overview
The CPU is driven by a system clock, denoted by the symbol φ. T he pe ri od from one ri sing edge
of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one or two
states. Different methods are used to access on-chip memory and on-chip supporting modules.
2.9.2 On-Chip Memory (ROM , RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2. 17 shows the on-chip memory access cycle.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Bus cycle
T1
Address
Read data
Write data
Read access
Write access
Figure 2.17 On-Chip Memory Access Cycle
Rev. 2.0, 11/ 00, page 58 of 1037
2. 9.3 On-Chip Suppor t i ng M o dul e Ac cess T i m i ng
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16
bits wide, depending on the particular internal I/O register being accessed. Figure 2.18 shows
the access timing for the on-chip supporting modules.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Bus cycle
T1
Address
Read access
Write access
Read data
Write data
T2
Fi g ur e 2 .18 O n- Chi p Suppo r t i ng M o dul e Access Cycle
2.10 Usage Note
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Hitachi H8S or H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4,
or ER5 is used.
Rev. 2.0, 11/ 00, page 59 of 1037
Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
This LSI has one operating mode (mode 1). This mode is selected depending on settings of the
mode pin (MD0).
Table 3.1 lists the MCU operating modes.
Table 3.1 MCU Operating Mode Selection
MCU Oper at i ng Mode M D0 CPU Operat ing Mode Descript i on
00
1 1 Advanced Single-chip mode
The CPU' s architecture allows for 4 Gbytes of address space, but this LSI actually accesses a
maximum of 16 Mbytes.
Mode 1 operation starts in single-chip mode after reset release.
This LSI can only be used in mode 1. This means that the mode pins must be set at mode 1. Do
not changes the inputs at the mode pins during operation.
3.1.2 Register Configuration
This LSI has a mode control register (MDCR) that indicates the inputs at the mode pin (MD0)
and a system control register (SYSCR) and that controls the operation of this LSI. Table 3.2
summarizes these registers.
Table 3.2 MCU Registers
Name Abbreviation R/W Initial Value Address*
Mode contr ol r egister MDCR R/W Undeter m ined H'FFE9
Syst e m contr ol regis t e r SYSCR R/W H'09 H'FFE8
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 60 of 1037
3.2 Register Descrip t io ns
3. 2.1 Mo de Co nt r o l Re g i st e r (M DCR)
0
—*
1
0
2
0
3
0
4
0
5—————
0
6
—
0
7
—
——————
—R
MDS0
0
Bit :
Initial value :
R/W
:
Note: *
Determined by MD0 pin
MDCR is an 8-bit read-only register monitors the current operating mode of this LSI.
Bit 7 to 1: Reserved.
These bit s ca nnot be m odifi e d and a re al ways set a t 0.
Bit 0: Mode Select 0 (MDS0)
This bit indicates the value which reflects the input levels at mode pin (MD0) (the current
operat ing m ode ). Bi t MDS0 corre sponds t o MD0 pi n. It i s rea d-onl y bi t a nd c a nnot be written
to. The mode pin (MD0) input levels are latched into these bits when MDCR is read.
3. 2.2 System Cont r o l Regi st e r ( SYSCR)
0
—
1
1
0
R/W
2
0
R/W
3
1
4
0
R/W
5
0
6
—
0
7
—
——— RR
INTM1 INTM0 XRST NMIEG1 NMIEG0
0
Bit :
Initial value :
R/W :
Bits 7 and 6: Reserved.
Rev. 2.0, 11/ 00, page 61 of 1037
Bit s 5 and 4 : Inter r upt c o ntrol m odes 1 and 0 ( INTM1, INT M 0 )
These bits are for selecting the interrupt control mode of the interrupt controller. For details of
the interrupt control modes, see section 6. 4, Interrupt Operation.
Bit 5 Bit 4
INTM1 INTM0 Interrupt
Control Mode Descript i on
0 0 Int er r upt is cont r olled by bit I (Initial value)0
1 1 Int er r upt is cont r olled by bits I and UI , and I CR
0 2 Cannot be used in this LSI1
1 3 Cannot be used in this LSI
Bit 3 : E x ter nal Reset (XRST )
Indicates the reset source. When the watchdog timer is used, a reset can be generated by
watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to
1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 A reset is gener at ed by wat chdog t im er over f low
1 A reset is generated by an exter nal reset (Initial value)
Bits 2 and 1: NMI edge select 1 and 0 (NMIG1, 0)
Select the input edge for NMI interrupt.
Bit 2 Bit 1
NIMIEG1 NIMIEG0 Description
0 An inter r upt request occu r s at falling edge of NMI input (I nitial value)0
1 An interrupt request occur s at r ising edge of NM I input
1*An inter r upt request occur s at rising or f alling edge of NMI input
Note: *Don't care
Bit 0: Reserved.
Rev. 2.0, 11/ 00, page 62 of 1037
3.3 Operating Mode Descriptions
3.3.1 Mode 1
The CPU can access a 16 Mbyte address space in advanced mode.
Rev. 2.0, 11/ 00, page 63 of 1037
3.4 Address Map
H8S/2191 H8S/2192
Memory indirect
branch address
Absolute address, 16 bits
3 kbytes
Vector area
On-chip ROM
(80 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
(3kbytes)
Vector area
On-chip ROM
(96 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
(3kbytes)
H'000000 H'000000
H'017FFF
H'FFD000
H'FFD2FF
H'FFF3B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
H'0000FF
H'007FFF
H'013FFF
H'FF8000
H'FFD000
H'FFD2FF
H'FFF3B0
H'FFFF00
H'FFFFAF
H'FFFFB0
H'FFFFFF
Absolut e address,
8 bits
Absolute address, 16 bits
Figure 3.1 Address Map (1)
Rev. 2.0, 11/ 00, page 64 of 1037
H8S/2193 H8S/2194
Vector area
On-chip ROM
(112 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
(3kbytes)
Vector area
On-chip ROM
(128 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
(3kbytes)
H'000000 H'000000
H'01FFFF
H'FFD000
H'FFD2FF
H'FFF3B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
H'01BFFF
H'FFD000
H'FFD2FF
H'FFF3B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
Figure 3.2 Address Map (2)
Rev. 2.0, 11/ 00, page 65 of 1037
H8S/2191A H8S/2194B
Memory indirect
branch address
Absolute address, 16 bits
6 kbytes
Vector area
On-chip ROM
(160 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
(6 kbytes)
Vector area
On-chip ROM
(192 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
(6 kbytes)
H'000000 H'000000
H'02FFFF
H'FFD000
H'FFD2FF
H'FFE7B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
H'0000FF
H'007FFF
H'027FFF
H'FF8000
H'FFD000
H'FFD2FF
H'FFE7B0
H'FFFF00
H'FFFFAF
H'FFFFB0
H'FFFFFF
Absolute address,
8 bits
Absolute address, 16 bits
Figure 3.3 Address Map (3)
Rev. 2.0, 11/ 00, page 66 of 1037
H8S/2194C
Vector area
On-chip ROM
(256 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
(6 kbytes)
H'000000
H'03FFFF
H'FFD000
H'FFD2FF
H'FFE7B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
Figure 3.4 Address Map (4)
Rev. 2.0, 11/ 00, page 67 of 1037
Section 4 Power-Down State
4.1 Overview
In addition to the normal program execution state, this LSI has a power-down state in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip supporting modules, and
so on.
This LSI operating modes are as follows:
1. High-speed m ode
2. Medium -spee d mode
3. Subactive mode
4. Sleep mode
5. Subsleep mode
6. Watch mode
7. Module stop m ode
8. Standby m ode
Of these, 2 to 8 are power-down modes. Certain combinations of these modes can be set.
After a reset , t he MCU is in high-spee d m ode.
Table 4.1 shows the internal chip states in each mode, and table 4.2 shows the conditions for
transition to the various modes. Figure 4.1 shows a mode transition diagram.
Rev. 2.0, 11/ 00, page 68 of 1037
Table 4.1 Internal Chip State s in Each Mode
Function High-
Speed Medium-
Speed Sleep Module
Stop Watch Subactive Subsleep Standby
System clock Functioning Functioning Functioning Functioning Halted Halted Halted Halted
Subclock pulse
generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Instructions Halted Halted Halted HaltedCPU
operation Registers Functioning Medium-
speed Retained Functioning Retained Subclock
operation Retained Retained
NIMI
IRQ0
IRQ1
Functioning Functioning Functioning Functioning
IRQ2
IRQ3
IRQ4
External
interrupts
IRQ5
Functioning Functioning Functioning Functioning
Halted Halted Functioning Halted
Timer A Functioning Functioning Functioning Functionin
g
/halted
(retained)
Subclock
operation Subclock
operation Subclock
operation Halted
(retained)
Timer B
Timer J
Timer L
Timer R
Functionin
g
/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
Timer X1
Functioning Functioning Functioning
Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
Watchdog
timer Functioning Functioning Functioning Functioning Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
PSU Functioning Subclock
operation Subclock
operation Subclock
operation Halted
IIC
SCI1
Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
SCI2
14-bit PWM
8-bit PWM
Functionin
g
/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
A/D
Functioning Functioning Functioning
Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
I/O Functioning Functioning Retained Functioning Halted Functioning Retained Halted
12-bit PWM
On-chip
supporting
module
operation
Servo Functioning Functioning Halted
(reset) Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
Notes: 1. "Halt ed ( r etained)" means that internal regist er values are retained. The int er nal state
is "operation suspended."
2. "Halted ( reset)" means that inter nal register values and internal states ar e initialized.
3. In module stop m ode, only modules for which a st op set t ing has been made are halted
(reset or ret ained).
4. In the power- down m ode, t he analog sect ion of the servo circuit s ar e not tur ned of f ,
therefore Vcc (Ser vo) cur r ent does not go low. When power-down is needed,
externally shut down the analog syst em power.
Rev. 2.0, 11/ 00, page 69 of 1037
Program-halted state
Conditions for mode transition (1) Conditions for mode transition (2)
Interruption factor
Sleep
(high-speed)
mode
Sleep
(medium-speed)
mode
Subsleep
mode
Program execution state
Reset state
Flag
SLEEP
instruction
Interrupt
LSON SSBY TMA3 DTON
a010*
b*110
c0111
d1111
e00**
f101*
gSCK1 to 0 = 0
hSCK1 to 0 ≠ 0 (either 1 bit = 0)
Power-down mode
Active
(high-speed)
mode
Active
(medium-speed)
mode
Subactive
mode
Program-halted state
Watch
mode
Standby
mode
NMI, IRQ0
to
1
NMI, IRQ0
to
1, Timer A interruption
All interruption (excluding servo system)
NMI, IRQ0
to
5, Timer A interruption
1
2
3
4
Interrupt
Interrupt
SLEEP
instruction
SLEEP
instruction
e
Note: When a transition is made between
modes by means of an interrupt,
transition cannot be made on interrupt
source generation alone. Ensure that
interrupt handling is performed after
accepting the interrupt request
SLEEP
instruction a
1
Interrupt
1
2
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
a
b
ghd
SLEEP
instruction
c
e
3
Interrupt 2
Interrupt 3
Interrupt 2Interrupt 4
c
SLEEP
instruction
d
b
b
SLEEP
instruction SLEEP
instruction 1
Note: * Don't care
Figure 4. 1 M ode Tr ansitions
Rev. 2.0, 11/ 00, page 70 of 1037
Table 4.2 Power-Down Mode Transition Condi tions
Control Bi t St at es at Tim e of
Transition
State bef or e
Transition SSBY TMA3 LSON DTON State af t er Tr ansi tion
by SLEEP Ins t ruct i o n Stat e af t er Return
by Int er r upt
0*0*Sleep High-speed
/medium-speed*1
0*1*
100*Standby High-speed
/medium-speed*1
101*
1100 Watch High-speed
/medium-speed*1
1110 Watch Subactive
1101
High-speed
/medium-
speed
1111 Subactive
00**
010*
011*Subsleep Subactive
10**
1100 Watch High-speed
/medium-speed*2
1110 Watch Subactive
1101 High-speed
/medium-speed*2
Subactive
1111
Notes: *Don't car e
: Do not set .
1. Returns to t he st at e bef ore tr ansition.
2. Mode varies depending on the st at e of SCK1 to SCK0.
Rev. 2.0, 11/ 00, page 71 of 1037
4.1.1 Register Configuration
The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR
registers. Table 4.3 summarizes these registers.
Table 4.3 Power-Down State Registers
Name Abbreviation R/W Initial Value Address*
Standby c ont rol regis t er SBYCR R/W H'00 H'FFEA
Low-power contr ol regist er LPWRCR R/ W H'00 H'FFEB
MSTPCRH R/W H'FF H'FFECModule stop cont r ol register
MSTPCRL R/W H'FF H'FFED
Timer m ode r egist er TMA R/W H'30 H'FFBA
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 72 of 1037
4.2 Register Descript i on s
4. 2.1 Standby Co ntrol Re g i st e r (SBYCR)
0
0
1
0
R/W
2
0
3
——
——
0
4
0
R/W
5
0
6
0
7
R/WR/W
STS1
R/W
STS2
0
R/W
SSBY STS0 SCK1 SCK0
Bit :
Initial value :
R/W :
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'00 by a reset.
Bit 7: Software Standby (SSBY)
Determines the operating mode, in combination with other control bits, when a power-down
mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by
a mode transition due to an interrupt, etc.
Bit 7
SSBY Description
0 Transition to s leep m ode af ter exec ut ion of SLEEP inst r uction in high-s peed m ode
or medium - speed m ode
Transit ion to subsleep m ode after ex ecution of SLEEP ins t ruct ion in subac t ive
mode (I nit ial value)
1 Transition to st andby m ode, subactive mode, or watch mode aft er execut ion of
SLEEP instr uc t ion in high-speed mode or medium- s peed m ode
Transition to wat ch m ode or high- speed m ode af t er execution of SLEEP
instruction in subactive mode
Bit s 6 to 4 : St a ndby T i m e r Select 2 to 0 (STS2 to STS0)
These bits select the time the MCU waits for the clock to stabilize when standby mode, watch
mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-
speed mode by means of a specific interrupt or instruction. With crystal oscillation, see table
4.5 and make a selection according to the operating frequency so that the standby time is at least
10 ms (the oscillation settling time). With an external clock, any selection can be made.
(With FLASH ROM versi on, do not se t t he st a ndby time to 16 states.)
Rev. 2.0, 11/ 00, page 73 of 1037
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Standby time = 8192 states
0 0 1 Standby time = 16384 states
0 1 0 Standby time = 32768 states
0 1 1 Standby time = 65536 states
1 0 0 Standby time = 131072 states
1 0 1 Standby time = 262144 states
11*St andby time = 16 stat es *1
Notes: *Don't car e
1. With FLASH RO M ver sion, do not set the standby t ime t o 16 st ates.
The standby t ime is 32 st at es when t r ansited t o medium-speed m ode φ/32 (SCK1=1,
SCK0=0).
Bit 3, 2: Reser ved.
These bit s ca nnot be m odifi e d and a re al ways rea d as 0.
Bits 1, 0: System Clock Select 1, 0 (SCK1, SCK0)
These bits select the CPU clock for the bus master in high-speed mode and medium-speed mode.
Bit 1 Bit 0
SCK1 SCK0 Description
0 0 Bus mast er is in high-speed mode ( I nitial value)
0 1 M edium- speed clock is φ/16
1 0 M edium- speed clock is φ/32
1 1 M edium- speed clock is φ/64
Rev. 2.0, 11/ 00, page 74 of 1037
4. 2.2 Low-Powe r Co nt r o l Re g i st e r (LPWRCR)
0
0
1
0
R/W R/W
2
0
3
0
4
———
———
0
5
0
6
0
7
R/W
NESEL
R/W
LSON
0
R/W
DTON SA1 SA0
Bit :
Initial value :
R/W :
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset.
Bit 7: Direct-Transfer On Flag (DTON)
Specifies whether a direct transition is made between high-speed mode, medium-speed mode,
and subactive mode when making a power-down transition by executing a SLEEP instruction.
The operating mode to which the transition is made after SLEEP instruction execution is
determined by a combination of other control bits.
Bit 7
DTON Description
0•When a SLEEP inst r uc t ion is ex ecuted in high-speed mode or m edium -speed
mode, a transition is made t o sleep m ode, st andby m ode, or watch mode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive m ode, a transition is m ade
to subsleep mode or watc h m ode (Init ial value)
1•When a SLEEP inst r uc t ion is ex ecuted in high-speed mode or m edium -speed
mode, transition is made directly to subact ive mode, or a transition is made t o
sleep mode or standby m ode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive m ode, a transition is m ade
directly to high- speed m ode, or a tr ansition is made to subsleep mode
Bit 6: Low-Speed On Flag (LSON)
Determines the operating mode in combination with other control bits when making a power-
down transition by executing a SLEEP instruction. Also controls whether a transition is made to
high-speed mode or to subactive mode when watch mode is cleared.
Rev. 2.0, 11/ 00, page 75 of 1037
Bit 6
LSON Description
0•When a SLEEP inst r uc t ion is ex ecuted in high-speed mode or m edium -speed
mode, transition is made t o sleep m ode, st andby m ode, or watch mode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive m ode, a transition is m ade
to watch m ode, or directly t o high-speed m ode
•After wat ch m ode is cleared, a t ransition is made to high- speed m ode
(Init ial value)
1•When a SLEEP inst r uc t ion is ex ecuted in high-speed mode a tr ans it ion is m ade
to watch m ode, subact ive mode, sleep mode or standby mode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive m ode, a transition is m ade
to subsleep mode or watc h m ode
•After wat ch m ode is cleared, a tr ansition is made to subactive mode
Bit 5: Noise Elimination Sampling Frequency Select (NESEL)
Selects the frequency at which the subclock (φw) generated by the subclock pulse generator is
sampled with the clock (φ) generated by the system clock oscillator. When φ = 5 MHz or highe r,
clear this bit to 0.
Bit 5
NESEL Description
0 Sampling at φ divided by 16
1 Sampling at φ divided by 4
Bits 4 to 2: Reserved.
These bit s ca nnot be m odifi e d and a re al ways rea d as 0.
Bit 1 , 0 : Subac tive m ode cloc k select 1, 0 (SA1, SA0)
These bits select the CPU operating clock in the subactive mode. These bits cannot be modified
in the subactive mode.
Bit 1 Bit 0
SA1 SA0 Description
0 0 O per at ing clock of CPU is φw/8 (Initial v alu e )
0 1 O per at ing clock of CPU is φw/4
1*Operat ing clock of CPU is φw/2
Note: *Don't care
Rev. 2.0, 11/ 00, page 76 of 1037
4.2.3 Time r Regi ster A (TMA)
0
0
1
0
R/W
2
0
3
0
4
1
5
——
1
6
0
7
R/WR/WR/WR/W
TMA3
R/W
TMA2
R/W
TMAIE
0
R/(W)*
TMAOV TMA1 TMA0
Bit :
Initial value :
R/W :
Note: *
Only 0 can be written, to clear the flag.
The timer register A (TMA) controls timer A interrupts and selects input clock.
Only Bit 3 is explained here. For details of other bits, see section 12.2.1, Timer Mode Register
A.
TMA is a readable/writable register which is initialized to H'30 by a reset.
Bit 3: Clock source, prescaler select (TMA3)
Selects Timer A clock source between PSS a n d PSW.
Also controls transition operation to the power-down mode. The operation mode to which the
MCU is transited after SLEEP instruction execution is determined by the combination with other
control bits than this bit.
For details, see the description of Clock Select 2 to 0 in section 12.2.1, Timer Mode Register A.
Bit 3
TMA3 Description
0•Timer A counts φ-based prescaler (PSM) divided clock pulses
•When a SLEEP inst r uc t ion is ex ecuted in high-speed mode or m edium -speed
mode, a transition is made t o sleep m ode or sof t war e st andby m ode
(Init ial value)
1•Timer A counts φw- based pr escaler ( PSM) divided clock pulses
•When a SLEEP inst r uc t ion is ex ecuted in high-speed mode or m edium -speed
mode, a transition is made t o sleep m ode, wat ch m ode, or subact ive mode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive m ode, a transition is m ade
to subsleep mode, watc h m ode, or high- speed m ode
Rev. 2.0, 11/ 00, page 77 of 1037
4. 2.4 Module St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode
control.
MSTPCR is initialized to H'FFFF by a reset.
MSTRCRH and M ST P CRL B i t s 7 t o 0: M o dul e Stop ( M ST P 1 5 to M ST P 0 )
These bits specify module stop mode. See table 4.4 for the method of selecting on-chip
supporting module s.
MSTPCRH, MSTPCRL
Bits 7 to 0
MSTP 15 to MSTP 0 Descript i on
0 Module stop mode is cleared
1 Module stop mode is set (Initial value)
Rev. 2.0, 11/ 00, page 78 of 1037
4.3 Medium - S p eed Mod e
When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode
changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU
operates on the operating clock (φ16, φ32 or φ64) specified by the SCK1 and SCK0 bits. The
on-chip supporting modules other than the CPU always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect
to the bus master operating clock. For example, if φ16 is selected as the operating clock, on-
chip memory is accessed in 16 states, and internal I/O registers in 32 states.
Medium-speed mode is cleared by clearing the both bits SCK1 and SCK0 to 0. A transition is
made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit i n
LPWRCR are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by
an inte rrupt , me di um-spee d m ode i s restore d.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit
in LPWRCR and the TMA3 bit in TMA (Timer A) are both cleared to 0, a transition is made to
software standby mode. When standby mode is cleared by an external interrupt, medium-speed
mode is restore d.
When the
5(6
pin is driven low, a transition is made to the reset state, and medium-speed mode
is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
Figure 4.2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode
Internal ,
supporting module clock
CPU clock
Internal address bus
Internal write signal
SBYCR SBYCR
Figure 4.2 Medium-Speed Mode Transition and Clearance Timing
Rev. 2.0, 11/ 00, page 79 of 1037
4.4 S leep Mod e
4.4.1 Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit i n
LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation
stops but the contents of the CPU's internal registers are retained. Other supporting modules
(excludi ng t he servo c i rcui t and 12-bi t PWM) do not stop.
4.4.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or with the
5(6
pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, sleep mode is cleared and interrupt exception
handling is started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts
other tha n NMI have be en m a sked by the CPU.
(2) Clearing with the
5(6
Pin
When the
5(6
pin is driven low, the reset state is entered. When the
5(6
pin is driven hi gh
after t he prescri be d reset i nput pe ri od, the CPU begins reset exc e pti on ha ndli ng.
Rev. 2.0, 11/ 00, page 80 of 1037
4.5 Module Stop Mode
4.5.1 Module Stop Mode
Module stop mode c a n be set for i ndivi dua l on-c hi p supporting m odul es.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 4. 4 shows MSTP bits and the on-chi p supporting m odul es.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating again at the end of the bus cycle. In module stop mode, the internal states of
modules other than the SCI1, A/D converter, Timer X1, and Servo circuit, are retained.
After reset release, all modules are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Tabl e 4 .4 MSTP B i t s a nd Correspondi ng O n- Chi p Suppo r t i ng M o dul e s
Register Bit Module
MSTP15 Timer A
MSTP14 Timer B
MSTP13 Timer J
MSTP12 Timer L
MSTP11 Timer R
MSTP10 Timer X1
MSTP9
MSTPCRH
MSTP8 Serial communication inter f ace 1 ( SCI1)
MSTP7 Serial communication inter f ace 2 ( SCI2)
MSTP6 I2C bus interface ( I I C)
MSTP5 14-bit PWM
MSTP4 8-bit PWM
MSTP3
MSTP2 A/D converter
MSTP1 Servo circuit, 12- bit PWM
MSTPCRL
MSTP0
Rev. 2.0, 11/ 00, page 81 of 1037
4.6 Standby Mode
4. 6.1 Standby M o de
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit i n
LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode is
entered. In this mode, the CPU, on-chip supporting modules, and oscillator (except for subclock
oscillator) all stop. However, contents of the CPU's internal registers and data in the built-in
RAM as well as functions of the SCII, timer X1 and built-in peripheral circuits (except the servo
circuit) are maintained in the current state. The I/O port, at this time, is caused to the high
impedance state.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
4.6.2 Cle a r i ng St andby M o de
Standby mode is cleared by an external interrupt (NMI pin, or pin
,54
to
,54
, or by means of
the
5(6
pin.
(1) Clearing with an Interrupt
When an NMI,
,54
to
,54
interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire chip, standby mode is cleared, and interrupt exception handling is started.
Standby mode cannot be cleared with an
,54
to
,54
interrupt i f the c orresponding e na ble
bit has been cleared to 0 or has been masked by the CPU.
(2) Clearing with the
5(6
Pin
When the
5(6
pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire chip. Note that the
5(6
pin must be he l d
low until clock oscillation stabilizes. When the
5(6
pin goes high, the CPU begins reset
except i on handl i ng.
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode
Bits STS2 to STS0 in SBYCR should be set as describe d be low.
(1) Using a Crystal Oscillator
Set bits STS2 to STS0 so that the standby time is at least 10 ms (the oscillation settling time).
Table 4.5 shows the standby times for different operating frequencies and settings of bits
STS2 to ST S0 .
Rev. 2.0, 11/ 00, page 82 of 1037
Table 4.5 Oscillation Settling Time Settings
STS2 STS1 STS0 Standby Ti m e 10 MHz 8 M Hz Unit
0 8192 states 0.8 1. 0
0
1 16384 states 1.6 2. 0
0 32768 states 3.3 4. 1
0
1
1 65536 states 6.6 8. 2
0 131072 states 13.1 16. 40
1 262144 states 26.2 32. 8
ms
1
1*16 states*11.6 2.0 µs
: Recommended time setting
Note: *Don't care
(2) Using an Externa l Cloc k
Any value can be set.
Note: 1. With Flash memory version, do not set the standby time to 16 states. The standby
time is 32 states when transited to medium-speed mode φ/ 32 (SCK1 = 1, SCK0 = 0).
Rev. 2.0, 11/ 00, page 83 of 1037
4.7 Wat ch Mode
4.7.1 Watch Mode
If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode
when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3
bit in TMA (Timer A) is set to 1, the CPU makes a transition to watch mode.
In this mode, the CPU and all on-chip supporting modules except Timer A stop. As long as the
prescribed voltage is supplied, the contents of some of the CPU's internal registers and on-chip
RAM are retained, and I/O ports are placed in the high-impedance state.
4.7.2 Clear ing Watch Mode
Watch mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin
,54
to
,54
), or by
means of the
5(6
pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, watch mode is cleared and a transition is made to
high-spee d m ode or m ed iu m- spee d m ode i f t he L SON bi t i n L PW RCR is cleared to 0, or to
subactive mode if the LSON b i t is set to 1. W h e n m a k i n g a t r a n sition to medium-speed
mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are
supplied to the entire chip, and interrupt exception handling is started.
Watch mode cannot be cleared with an
,54
to
,54
interrupt i f the c orresponding e na ble
bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the
relevant interrupt has been disabled by the interrupt enable register or masked by the CPU.
See section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, for the
oscillation settling time setting when making a transition from watch mode to high-speed
mode.
(2) Clearing with the
5(6
Pin
See (2) Clearing with the
5(6
Pin in section 4.6.2, Clearing Standby Mode.
Rev. 2.0, 11/ 00, page 84 of 1037
4.8 Subsleep Mode
4.8.1 Subsleep Mode
If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,
the LSON bi t i n L PW RCR i s set t o 1, and t he T MA3 bi t i n T MA (Timer A) is set to 1, the CPU
makes a transition to subsleep mode.
In this mode, the CPU and all on-chip supporting modules other than Timer A stop. As long as
the prescribed voltage is supplied, the contents of the CPU, some of its on-chip registers and on-
chip RAM are retained, and I/O ports retain their states prior to the transition.
4. 8.2 Clear i ng Subsleep Mode
Subsleep mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin
,54
to
,54
), or
by means of the
5(6
pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, subsleep mode is cleared and interrupt exception
handling is started. Subsleep mode cannot be cleared with an
,54
to
,54
interrupt i f the
corresponding enable bit has been cleared to 0, or with an on-chip supporting module
interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable
register or m a sked by the CPU.
(2) Clearing with the
5(6
Pin
See (2) Clearing with the
5(6
Pin in section 4.6.2, Clearing Standby Mode.
Rev. 2.0, 11/ 00, page 85 of 1037
4.9 Subactive Mode
4. 9.1 Subac t i v e M o de
If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the
DTON bit in LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, the CPU makes a
transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bi t i n
LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in
subsleep mode, a transition is made to subactive mode.
In subactive mode, the CPU performs sequential program execution at low speed on the
subclock. In this mode, all on-chip supporting modules other than Timer A stop.
4. 9.2 Clear i ng Suba c t i v e M o de
Subsleep mode is cleared by a SLEEP instruction, or by means of the
5(6
pin.
(1) Clearing with a SLEEP Instruction
When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON
bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, subactive
mode is cleared and a transition is made to watch mode. When a SLEEP instruction is
executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit i n L PW RCR i s se t t o
1, and the TMA3 bit in TMA (Timer A) is set to 1, a transition is made to subsleep mode.
When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON
bit i s se t to 1 and the L SON b i t i s cleared to 0 in LPWRCR, and the PSS bi t in T C SR
(WDT1) is set to 1, a transition is made directly to high-speed or medium-speed mode.
Fort details of direct transition, see section 4.10, Direct Transition.
(2) Clearing with the
5(6
Pin
See (2) Clearing with the
5(6
Pin in section 4.6.2, Clearing Standby Mode.
Rev. 2.0, 11/ 00, page 86 of 1037
4.10 Direct Transit i on
4.10.1 Overview of Direct Transition
There a re thre e opera t ing m ode s in which t he CPU execut e s programs: hi gh-spee d
mode, medium-speed mode, and subactive mode. A transition between high-speed mode and
subactive mode without halting the program* is called a direct transition. A direct transition can
be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction.
After the transition, direct transition interrupt exception handling is started.
(1) Direct Transition from High-Speed Mode to Subactive Mode
If a SLEEP instruction is executed in high-speed mode while the SSBY bit in SBYCR, the
LSON bit a nd DT ON bi t i n L PWRCR, and t h e T MA3 bi t i n T MA (Timer A) are all set to 1,
a transition is made to subactive mode.
(2) Direct Transition from Subactive Mode to High-Speed Mode/Medium-Speed Mode
If a SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to
1, t h e L SON b i t i s cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the TMA3 bit
in TMA (Timer A) is set to 1, after the elapse of the time set in bits STS2 to STS0 in
SBYCR, a transition is made to directly to high-speed mode.
Note: * At the time of transition from subactive mode to high- or medium-speed mode, an
oscillation stabilization wait time is generated.
Rev. 2.0, 11/ 00, page 87 of 1037
Section 5 Exception Handling
5.1 Overview
5.1.1 Exception Handling Types and Priority
As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Trap instruction
exceptions are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the i nt errupt c ont rol m ode se t by t he INT M0 and INT M1 bit s in SYSCR.
Table 5.1 Exception Types and Priority
Priority Exception
Type Start of Except ion Handli ng
Reset Start s imm ediat ely aft er a low-to- high t r ansition at the
5(6
pin, or
when the watchdog t imer over f lows
Trace*1St ar t s when execution of t he cur r ent instr uct ion or except ion
handling ends, if the t r ace ( T) bit is set t o 1
Inter r upt Starts when execution of t he cur r ent instruct ion or except ion
handling ends, if an interr upt r equest has been issued*2
Direct tr ansition Start ed by a direct t r ansit ion resulting f r om execut ion of a SLEEP
instruction
High
Low Trap instruction
(TRAPA)*3Sta rte d by e x ec u tion o f a tr ap in str u c t io n ( T RAPA)
Notes: 1. Traces are enabled only in interrupt contr ol modes 2 and 3. (They cannot be used in
this LSI. ) Tr ace except ion handling is not executed af ter execut ion of an RTE
instruction.
2. I nterr up t detec tion is n o t perf o r med on c o mpletion o f ANDC, ORC, XORC, o r L DC
instruction execut ion, or on com pletion of r eset except ion handling.
3. Trap instruct ion except ion handling requests ar e accept ed at all tim es in the pr ogr am
execution stat e.
Rev. 2.0, 11/ 00, page 88 of 1037
5.1.2 Exception Handling Operati on
Exceptions originate from various sources. Trap instructions and interrupts are handled as
follows:
[1] The program counter (PC) and condition-code register (CCR) are pushed onto the stack.
[2] The interrupt mask bits are updated. The T bit is cleared to 0.
[3] A vector address corresponding to the exception source is generated, and program execution
starts from tha t addre ss.
For a reset exc e pti on, ste ps [2] and [3] above a re c a rrie d out .
5.1.3 Exception Sources and Vector Table
The exception sources are classified as shown in figure 5.1. Different vector addresses are
assigned to diffe re nt e xc ept i on sources.
Table 5. 2 l ists the e xce pt ion source s and t hei r ve ct or a ddresses.
Exception sources
• Reset
• Interrupts
• Trap instruction
• Trace (cannot be used in this LSI)
• Direct transition
External interrupts NMI, IRQ5 to IRQ0
Internal interrupts Interrupt sources in on-chip supporting modules
…
…
Figure 5.1 Exception Sources
Rev. 2.0, 11/ 00, page 89 of 1037
Table 5.2 Exception Vector Table
Exception Sour ce Vector Number Vector Address*1
Reset 0 H'0000 to H'0003
1 H'0004 to H'0007
2 H'0008 to H'000B
3 H'000C to H'000F
4 H'0010 to H'0013
Reserved for system use
5 H'0014 to H'0017
Direct tr ansit ion 6 H'0018 to H001B
External inter r upt NMI 7 H'001C to H'001F
8 H'0020 to H'0023
9 H'0024 to H'0027
10 H'0028 to H'002B
Trap instruct ion ( 4 sour ces)
11 H'002C to H'002F
12 H'0030 to H'0033
13 H'0034 to H'0037
14 H'0038 to H'003B
Reserved for system use
15 H'003C to H'003F
#0 16 H'0040 to H'0043
#1 17 H'0044 to H'0047
Address tr ap
#2 18 H'0048 to H'004B
Int er nal inter r upt ( I C) 19 H'004C t o H'004F
Int er nal inter r upt ( HSW1) 20 H'0050 to H'0053
IRQ0 21 H'0054 to H'0057
IRQ1 22 H'0058 to H'005B
IRQ2 23 H'005C t o H'005F
IRQ3 24 H'0060 to H'0063
IRQ4 25 H'0064 to H'0067
External inter r upt
IRQ5 26 H'0068 to H'006B
Reserved 27
33
H'006C to H'006F
H'0084 to H'0087
Internal interrupt*230
67
H'0088 to H'008B
H'010C to H'010F
Notes: 1. Lower 16 bits of the addr ess.
2. For details on internal interrupt vector s, see sect ion 6. 3. 3, Interrupt Exception Vector
Table.
Rev. 2.0, 11/ 00, page 90 of 1037
5.2 Reset
5.2.1 Overview
A reset has the hi ghe st exc e pti on pri orit y.
When the
5(6
pin goes low, all processing halts and the MCU enters the reset state. A reset
initializes the internal state of the CPU and the registers of on-chip supporting modules.
Immediately after a reset, interrupt control mode 0 is set.
Reset exc e pti on ha ndli ng be gins when the
5(6
pin change s from l ow to high.
The MCUs can also be reset by overflow of the watchdog timer. For details, see section 17,
Watchdog Timer.
5. 2.2 Reset Se que nce
The MCU enters the reset state when the
5(6
pin goes low.
To ensure that the chip is reset, hold the
5(6
pin low during the oscillation stabilizing time of
the clock oscillator when powering on. To reset the chip during operation, hold the
5(6
pin low
for at least 20 states. For pin states in a reset, see Appendix D.1, Pin Circuit Diagrams.
When the
5(6
pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows:
[1] The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
[2] The reset e xce pt ion ve c tor a ddre ss is read and t ra nsferred t o t he PC, and progra m exe c uti on
starts from the address indicated by the PC.
Figures 5.2 shows example s of the re set sequenc e .
Rev. 2.0, 11/ 00, page 91 of 1037
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
Vector
fetch
(1)
(2)
(3)
(4)
: Reset exception vector address ((1) = H'0000 or H'000000)
: Start address (contents of reset exception vector address)
: Start address ((3) = (2))
: First program instruction
(1) (3)
High level
Internal
processing Fetch of first program
instruction
(2) (4)
Figure 5. 2 Reset Sequence (M ode 1)
5. 2.3 Inte r rupts af t e r Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt
requests, including NMI, are disabled immediately after a reset. Since the first instruction of a
program is always executed immediately after the reset state ends, make sure that this instruction
initializes the stack pointer (example: MOV.L #xx:32, SP).
Rev. 2.0, 11/ 00, page 92 of 1037
5.3 Interrupts
Interrupt e xc ept i on handl i ng ca n be reque ste d by seven e xt erna l sources (NMI and IRQ5 to
IRQ0) and interna l sources in t he on-chi p supporti ng modul e s. Figure 5. 3 shows the inte rrupt
sources and the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI),
A/D converter (ADC), I2C bus interface (IIC), servo circuits, synchronized detection, address
trap, etc. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
either three priority/mask levels to enable multiplexed interrupt control.
For details on interrupts, see section 6, Interrupt Controller.
WDT*
(1)
PSU (1)
TMR (15)
SCI (6)
ADC (1)
IIC (1)
Servo circuits (9)
Synchronized detection (1)
Address trap (3)
Interrupts
Internal
interrupts
External
interrupts
Notes: Numbers in parentheses are the numbers of interrupt sources.
When the watchdog timer is used as an interval timer, it generates an interrupt
request at each counter overflow.
*
NMI (1)
IRQ5 to IRQ0 (6)
Figure 5.3 Interrupt Sources and Number of Interrupts
Rev. 2.0, 11/ 00, page 93 of 1037
5.4 Trap Inst ru ction
Trap i n st r u c t ion exc e p t ion h a n d l i n g st a r t s wh e n a TRAPA i n st r u ction is executed. Trap
instruction exception handling can be executed at all times in the program execution state.
The T RAPA inst r uction fetches a start address from a vector table entry corresponding to a
vector number from 0 to 3, as specified in the instruction code.
Table 5.3 shows the status of CCR and EXR after execution of trap instruction exception
handling.
Table 5.3 Status of CCR and EXR afte r Tr ap Instr uc ti on Exc e pti on H andl i ng
CCR EXR*
Interrupt
Control Mode I UI I2 to I0 T
01
111
Legend:
1: Set to 1
0: Cleared to 0
: Retains value prior to execut ion.
*: Does not af f ect oper ation in this LSI.
Rev. 2.0, 11/ 00, page 94 of 1037
5.5 S t ack S t at us aft er Excep t i on H an dl in g
Figure 5.4 shows the stack after completion of trap instruction exception handling and interrupt
except i on handl i ng.
CCR
CCR*
PC
(16 bits)
SP
Note: * Ignored on return.
Interrupt control modes 0 and 1
Figure 5. 4 (1) Stack Status after Exception Handling (Normal M ode)*
Note: * Normal mode is not available for this LSI.
CCR
PC
(24 bits)
SP
Interrupt control modes 0 and 1
Figure 5. 4 (2) Stack Status after Exception Handling (Advanced Mode)
Rev. 2.0, 11/ 00, page 95 of 1037
5.6 Not es on Use of the St ack
When accessing word data or longword data, this chip assumes that the lowest address bit is 0.
The stack should always be accessed by word transfer instruction or longword transfer
instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the
following instruc t ions to save re giste rs:
PUSH.W Rn (or MOV.W Rn, @- SP)
PUSH.L ERn (or MOV.L E Rn, @ - SP)
Use the following i nstruc ti ons to re store re gi sters:
POP.WRn (or MOV. W @ SP+ , Rn)
POP.L ERn (or MOV.L @ SP+ , E Rn)
Setting SP to an odd value may lead to a malfunction. Figure 5.5 shows an example of what
happens when the SP value i s odd.
SP
[Legend] : Condition-code register
: Program counter
: General register R1L
: Stack pointer
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
R1L
PC
SP CCR
PC
SP
CCR
PC
R1L
SP
Note: This diagram illustrates an example in which the interrupt control mode is 0, is advanced mode.
TRAPA instruction executed MOV.B R1L, @-ER7
SP set to H'FFFEFF Data saved above SP Contents of CCR lost
Figure 5.5 Operation when SP Value is Odd
Rev. 2.0, 11/ 00, page 96 of 1037
Rev. 2.0, 11/ 00, page 97 of 1037
Section 6 Interrupt Controller
6.1 Overview
6.1.1 Features
This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the
following fea t ures:
(1) Two Interrupt Cont rol Modes
• Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR).
(2) Priorities Settable with ICR
• An interrupt control register (ICR) is provided for setting interrupt priorities. Three
priority levels can be set for each module for all interrupts except NMI.
(3) Independent Vector Addresses
• All interrupt sources are assigned independent vector addresses, making it unnecessary
for the source t o be ide nt ifi e d in t he int e rrupt ha ndl ing rout i ne.
(4) Seven Exte rna l Int e rrupt Pins
• NMI is the highest-priority interrupt, and is accepted at all times. Falling edge, rising
edge, or both edge detection can be selected for the NMI interrupt.
• Falling edge, rising edge, or both edge detection can be selected for interrupt IRQ0.
• Falling edge or rising edge can be individually selected for interrupts IRQ5 to IRQ1.
Rev. 2.0, 11/ 00, page 98 of 1037
6.1.2 Block Diagram
A block diagram of the interrupt controller is shown in figure 6.1.
NM input
IRQ input
Internal
interrupt
requests
[Legend]
IEGR
IENR
IRQR
ICR
SYSCR
: IRQ edge select register
: IRQ enable register
: IRQ status register
: Interrupt control register
: System control register
NMI input unit
Interrupt
request
Vector
number
I, UI
IRQ input
unit IRQR
IEGR IENR
ICR
CPU
Interrupt controller
SYSCR
INTM1, INTM0
NMIEG1, NMIEG0
CCR
Priority
determina-
tion
Figure 6.1 Block Diagram of Interrupt Controller
Rev. 2.0, 11/ 00, page 99 of 1037
6.1.3 Pin Configuration
Table 6.1 summarizes the pins of the interrupt controller.
Table 6.1 Interrupt Controller Pins
Name Symbol I/O Function
Nonmaskable
interrupt
10,
Input Nonmaskable ex t ernal inter rupt; rising, f alling, or
both edges can be selected
External inter r upt
request
,54
Input Maskable external int er rupts; rising, falling, or bot h
edges can be selected
External inter r upt
requests 1 t o 5
,54
to
,54
Input Maskable ex t e r nal int errupt s : rising, or f alling
edges can be selected
6.1.4 Register Configuration
Table 6.2 summarizes the registers of the interrupt controller.
Table 6.2 Interrupt Controller Registers
Name Abbreviation R/W Initial Value Address*1
Syst e m contr ol regis t e r SYSCR R/W H'00 H'FFE8
IRQ edge select register IEGR R/W H'00 H'FFF0
IRQ enable r egister I ENR R/ W H'00 H'FFF1
IRQ st at us r egister IRQR R/ ( W)*2H'00 H'FFF2
Int e r r upt cont r o l r egister A ICRA R/W H'00 H'FFF3
Int e r r upt cont r o l r egister B ICRB R/W H'00 H'FFF4
Int e r r upt cont r o l r egister C ICRC R/W H'00 H'FFF5
Int e r r upt cont r o l r egister D ICRD R/W H'00 H'FFF6
Port m ode r egist er 1 PMR1 R/W H'00 H'FFCE
Notes: 1. Lower 16 bits of the addr ess.
2. Only 0 can be written, for f lag clearing.
Rev. 2.0, 11/ 00, page 100 of 1037
6.2 Register Descript i on s
6. 2.1 System Cont r o l Regi st e r ( SYSCR)
0
0
1
0
R/W
2
0
R/W
3
0
R
4
0
R/W
5
0
R/W
0
7NMIEG0NMIEG1XRSTINTM0INTM1
0
6
——
——
—
—
Bit :
Initial value :
R/W :
SYSCR is an 8-bit readable register that selects the interrupt control mode and the detected edge
for
10,
.
Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3. 2.2, System
Control Re gi st er (SYSCR).
SYSCR is initialized to H'00 by a reset.
Bit s 5 and 4 : Inter r upt Cont r o l Mode ( INTM1, INT M 0 )
These bits select one of two interrupt control modes for the interrupt controller. The INTM1 bit
must not be set to 1.
Bit 5 Bit 4
INTM1 INTM0 I nterrupt Cont rol
Mode Description
0 0 Inter r upt s ar e controlled by I bit (I nit ial value)0
1 1 Int er r upt s ar e controlled by I and UI bits and I CR
0Cannot be used in this LSI1
1Cannot be used in this LSI
Bit 2 and 1:
10,
10,
Pin Detected Edge Select (NMIEG1, NMIEG0)
Selects the detected edge for the
10,
pin.
Bit 2 Bit 1
NIMIEG1 NIMIEG0 Description
0 I nt er r upt request generat ed at falling edge of
10,
pin (I n itial v alu e )0
1 Interr upt r equest generated at r ising edge of
10,
pin
1*Int er r upt request generated at both falling and r ising edges of
10,
pin
Note: *Don't care
Rev. 2.0, 11/ 00, page 101 of 1037
6. 2.2 Interrupt Co ntrol Re g i st e rs A to D ( ICRA t o ICRD)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7ICR4 ICR3 ICR2 ICR1 ICR0
0
R/W
ICR7
R/WR/WR/W
ICR6 ICR5
6
Bit :
Initial value :
R/W :
The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for
interrupt s othe r tha n NMI.
The correspondence between ICR settings and interrupt sources is shown in table 6.3.
The ICR registers are initialized to H'00 by a reset.
Bit 7 to 0 : Int e rr upt Co nt r o l L e v e l ( ICR7 to ICR0 )
Sets the cont rol le ve l for t he corre sponding i nte rrupt source.
Bit n
ICRn Description
0 Corresponding inter r upt sour ce is cont r ol level 0 (non-pr ior ity ) (Init ial value)
1 Corresponding interr upt sour ce is cont r ol level 1 (priority)
(n = 7 to 0)
Table 6.3 Correspondence between Interrupt Sources and ICR Settings
ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 CIRA0ICRA
Reserved Input
capture HSW1 IRQ0 IRQ1 IRQ2
IRQ3 IRQ4
IRQ5 Reserved
ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0ICRB
Reserved Reserved Servo
(drum,
capstan
latch)
Timer A Timer B Timer J Timer R Timer L
ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0ICRC
Time r X1 Synchro-
nized
detection
Watchdog
timer Servo IIC SCI1
(UART) SCI2
(with 32-
bit buffe r)
A/D
ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0ICRD
HSW2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Rev. 2.0, 11/ 00, page 102 of 1037
6.2.3 IRQ Enable Register (IENR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
R/WR/WR/W
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
6
——
——
Bit :
Initial value :
R/W :
IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt
requests IRQ5 to IRQ0.
IENR is initialized to H'00 by a reset.
Bits 7 and 6: Reserved
Do not write 1 to them.
Bits 5 to 0: IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E)
These bits select whether IRQ5 to IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0 IRQ n inter r upt disabled (Init ial value)
1 IRQ n inter r upt enabled
(n = 5 to 0)
Rev. 2.0, 11/ 00, page 103 of 1037
6.2.4 IRQ Edge Select Registers (IEGR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
—
—R/WR/WR/W
IRQ4EG
R/W
IRQ5EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0
0
6
Bit :
Initial value :
R/W :
IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins
,54
to
,54
.
IEGR register is initialized to H'00 by a reset.
Bit 7: Reserved
Do not write 1 to it.
Bits 6 to 2:
,54
,54
to
,54
,54
Pins Detected Edge Select (IRQ5EG to IRQ1EG)
These bits select detected edge for interrupts IRQ5 to IRQ1.
Bits 6 to 2
IRQnEG Description
0 Int errupt r eques t gener ated at f alling edge of
,54Q
pin input (Init ial value)
1 Int er r upt request gener at ed at rising edge of
,54Q
pin input
(n = 5 to 1)
Bits 1 and 0:
,54
,54
Pin Detected Edge Select (IRQ0EG1, IRQ0EG0)
These bits select detected edge for interrupt IRQ0.
Bit 1 Bit 0
IRQ0EG1 IRQ0EG0 Description
0 0 I nterr upt request gener ated at f a lling edge of
,54
pin input (Init ial
value)
0 1 I nt er rupt r equest gener at ed at rising edge of
,54
pin input
1*Int er r upt request generated at both falling and r ising edges of
,54
pin
input
Note: *Don't care
Rev. 2.0, 11/ 00, page 104 of 1037
6. 2.5 IRQ Sta t us Re g i st e r ( IRQ R)
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
5
00
7
R/(W)*
R/(W)*
R/(W)*
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
6
——
——
Note: * Only 0 can be written, to clear the flag.
Bit :
Initial value :
R/W :
IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt
requests.
IRQR is initialized to H'00 by a reset.
Bit 7 and 6: Reserved
Do not write 1 to them.
Bits 5 to 0: IRQ5 to IRQ0 Flags
These bits indicate the status of IRQ5 to IRQ0 interrupt requests.
Bit n
IRQnF Description
0 [Clearing conditions] (Init ial value)
Cleared by reading IRQnF set t o 1, then writ ing 0 in IRQnF
When IRQn int er r upt exception handling is executed
1 [Sett ing conditions]
(1) When a f alling edge occ ur s in
,54Q
input while f alling edge detection is s et
(I RQnEG = 0)
(2) When a rising edge occurs in
,54Q
input while rising edge detection is set
(I RQnEG = 0)
(3) When a falling or rising edge occurs in
,54
input while both-edge detect ion is
set (IRQ0EG1 = 1)
(n = 5 to 0)
Rev. 2.0, 11/ 00, page 105 of 1037
6.2.6 Port Mode Regi ster (PM R1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W
PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10
R/WR/WR/W
6
Bit :
Initial value :
R/W :
Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is
specified for each bit.
PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset.
Only bits 5 to 0 are explained here. For details, see section 10, I/O Port.
Bits 5 to 0: P15/
,54
,54
to P10/
,54
,54
pin switching (PMR15 to PMR10)
These bits are for setting the P1n/
,54Q
pin as the i nput /out put pin for P1n or as the
,54Q
pin for
externa l int e rrupt re que st input .
Bit n
PMR1n Description
0 P1n/
,54Q
pin functions as the P1n input/output pin (Initial value)
1 P1n/IRQ n pin funct ions as t he
,54Q
input pin
(N = 5 to 0)
The following is the notes on switching the pin function by PMR1.
(1) When the port is set a s the
,&
input pin or
,54
to
,54
input pin, t he pin l e vel m ust be
High or Low regardless of active mode or power-down mode. Do not set the pin level at Medium.
(2) Switching the pin function of P16/
,&
or P15/
,54
to P10/
,54
may be mistakenly identified
as edge detection and detection signal may be generated. To prevent this, operate as follows:
(a) Set the interrupt enable/disable flag to disable before switching the pin function.
(b) Clear the applicable interrupt request flag to 0 after switching the pin function and
execut i ng anot he r instruc t ion.
(Program exam pl e)
:
MOV.B R0L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt disabled
MOV.B R1L,@PMR1 ⋅⋅⋅⋅⋅⋅ Pin function change
NOP ⋅⋅⋅⋅⋅⋅ Optional instruction
BCLR m @IRQR ⋅⋅⋅⋅⋅⋅ Applicable interrupt clear
MOV.B R1L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt enabled
:
Rev. 2.0, 11/ 00, page 106 of 1037
6.3 Interrup t So urces
Interrupt sources compr ise external interr upts (NMI an d IRQ5 to IRQ0) and inter nal interr upts.
6.3.1 Exter nal Interrupts
There are seven extern al in terr upt sour ces; NMI and IRQ5 to IRQ0. Of these, NMI, and IRQ1 to
IRQ0 can be used to restor e this ch ip from standby mode.
(1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the
interrupt control mode and the status of the CPU interrupt mask bits. The NMIEG1 and
NMIEG0 bits in SYSCR can be used to select whether an interrupt is requested at a risi ng,
falling edge or both edges on the
10,
pin.
The vec t or numbe r for NMI inte rrupt e xc ept i on handl i ng is 7.
(2) IRQ5 to IRQ0 Interrupts
Int er rupts IRQ5 to IRQ0 are requested by a n input signa l a t pins
,54
to
,54
. Inte rrupts
IRQ5 to IRQ0 have the fol l owing fea t ures:
(a) Using IEGR, it is possible to select wh ether an in terrupt is generated by a low level,
fallin g edge, risin g edge, or both edges, at pin
,54
.
(b) Using IEGR, it is possible to select wh ether an in terrupt is generated by a low level,
fallin g edge, risin g edge, or both edges, at pin s
,54
to
,54
.
(c) Ena blin g or di sablin g of i nter rupt requests IRQ5 to IRQ0 can be selected with IE NR.
(d) The interrupt con tr ol level can be set with ICR.
(e) The status of inter rupt requests IRQ5 to IRQ0 is in dicated in IRQR. IRQR flags can be
cleared to 0 by software.
A block diagra m of int e rrupts IRQ5 to IRQ0 is shown in figure 6. 2.
Clear signal
R
SQ
Edge detection
circuit
IRQnEG IRQnF
IRQnE
Note: n = 5 to 0
IRQn interrupt
request
IRQn input
Figure 6. 2 Bl oc k Diagram of Interrupts IRQ5 to IRQ0
Rev. 2.0, 11/ 00, page 107 of 1037
Figure 6.3 shows the timing of IRQnF setting.
Internal
IRQnF
IRQn
input pin
Figure 6. 3 Ti mi ng of IRQnF Setting
The vector n umbers for IRQ5 to IRQ0 interrupt exception handlin g are 21 to 26.
Upon detection of IRQ5 to IRQ0 interrupts, the applicable pin is set in the port mode register 1
(PMR1) as
,54Q
pin .
Rev. 2.0, 11/ 00, page 108 of 1037
6. 3.2 Internal Int e r rupts
There a re 38 sources for int e rnal i nte rrupt s from on-chi p supporti ng modul e s.
(1) For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If any one of these is set
to 1, an interrupt request is issued to the interrupt controller.
(2) The interrupt control level can be set by means of ICR.
6.3.3 Interrupt Exception Vector Table
Table 6.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of ICR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 6.4.
Table 6.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Priority Interrupt Source Origin of Interrupt
Source Vector
No. Vector address ICR Remarks
Reset External pin 0 H'0000 to H'0003
1 H'0004 to H'0007
2 H'0008 to H'000B
3 H'000C to H'000F
4 H'0010 to H'0013
Reserved
5 H'0014 to H'0017
Direct transition Instruction 6 H'0018 to H'001B
NMI External pin 7 H'001C to H'001F
TRAPA#0 8 H'0020 to H'0023
TRAPA#1 9 H'0024 to H'0027
TRAPA#2 10 H'0028 to H'002B
Tr ap inst ruct ion
TRAPA#3
Instruction
11 H'002C to H'002F
12 H'0030 to H'0033
13 H'0034 to H'0037
14 H'0038 to H'003B
High
Low
Reserved
15 H'003C to H'003F
Rev. 2.0, 11/ 00, page 109 of 1037
Priority Interrupt Source Origin of Interrupt
Source Vector
No. Vector address ICR Remarks
#0 16 H'0040 to H'0043
#1 17 H'0044 to H'0047
Address trap
#2
ATC
18 H'0048 to H'004B
IC PSU 19 H'004C to H'004F ICRA6
HSW1 Servo circuit 20 H'0050 to H'0053 ICRA5
IRQ0 21 H'0054 to H'0057 ICRA4
IRQ1 22 H'0058 to H'005B ICRA3
IRQ2 23 H'005C to H'005F
IRQ3 24 H'0060 to H'0063
ICRA2
IRQ4 25 H'0064 to H'0067
IRQ5
External pin
26 H'0068 to H'006B
ICRA1
27 H'006C to H'006F
28 H'0070 to H'0073
29 H'0074 to H'0077
30 H'0078 to H'007B
31 H'007C to H'007F
32 H'0080 to H'0083
Reserved
33 H'0084 to H'0087
Drum latch 1 (speed) 34 H'0088 to H'008B
Capstan latch 1 (speed)
Servo circuit
35 H'008C to H'008F
ICRB5
TMAI Timer A 36 H'0090 to H'0093 ICRB4
TMBI Timer B 37 H'0094 to H'0097 ICRB3
TMJ1I 38 H'0098 to H'009B
TMJ2I
Timer J
39 H'009C to H'009F
ICRB2
TMR1I 40 H'00A0 to H'00A3
TMR2I 41 H'00A4 to H'00A7
TMR3I
Timer R
42 H'00A8 to H'00AB
ICRB1
High
Low TMLI Timer L 43 H'00AC to H'00AF ICRB0
Rev. 2.0, 11/ 00, page 110 of 1037
Priority Interrupt Source Origin of Interrupt
Source Vector
No. Vector address ICR Remarks
ICXA Timer X1 44 H'00B0 to H'00B3
ICXB 45 H'00B4 to H'00B7
ICXC 46 H'00B8 to H'00BB
ICXD 47 H'00BC to H'00BF
OCX1 48 H'00C0 to H'00C3
OCX2 49 H'00C4 to H'00C7
OVFX 50 H'00C8 to H'00CB
ICRC7
VD interrupts Sync signal
detection 51 H'00CC to H'00CF ICRC6
Reserved 52 H'00D0 to H'00D3
8-bit interval timer Watchdog timer 53 H'00D4 to H'00D7 ICRC5
CTL 54 H'00D8 to H'00DB
Drum latch 2 (speed) 55 H'00DC to H'00DF
Capstan latch 2 (speed) 56 H'00E0 to H'00E3
Drum latch 3 (phase) 57 H'00E4 to H'00D7
Capstan latch 3 (phase)
Servo circuit
58 H'00E8 to H'00EB
ICRC4
IIC IIC 59 H'00 E C to H'00EF ICRC3
ERI 60 H'00F0 to H'00F3
RXI 61 H'00F4 to H'00F7
TXI 62 H'00F8 to H'00FB
SCI1
TEI
SCI1
(UART)
63 H'00FC to H'00FF
ICRC2
TEI 64 H'0100 to H'0103SCI2
ABTI
SCI2
65 H'0104 to H'0107
ICRC1
A/D conversion end A/D 66 H'0108 to H'010B ICRC0
High
Low HSW2 Servo circuit 67 H'010C to H'010F ICRD7
Rev. 2.0, 11/ 00, page 111 of 1037
6.4 Int erru p t Op erat ion
6. 4.1 Inte r rupt Cont r o l Mode s a nd Inter r upt O pe ration
Interrupt operations in this LSI differ depending on the interrupt control mode.
NMI interrupts and address trap interrupts are accepted at all times except in the reset state. In
the ca se of IRQ int errupt s and on-c hip supporti ng m odule i nte rrupt s, a n ena bl e bi t is provide d
for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 6. 5 shows the int errupt c ontrol m odes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated
by the I and UI bit s in t he CPU's CCR.
Table 6.5 Interrupt Control Modes
SYSCRInterrupt
Control
Mode INTM1 INTM0 Priority Setting
Register Interrupt
Mask Bit s Descript i on
0 0 ICR I Interrupt mask control is
perfor med by the I bit
Priority can be set with I CR
1
0
1 ICR I , UI 3-le v e l in ter rupt m a s k c on tr o l is
perfor med by the I and UI bits
Priority can be set with I CR
Figure 6.4 shows a block diagram of the priority decision circuit.
Interrupt control modes 0 and 1
I
Interrupt source
UI
Vector number
Interrupt acceptance
control and 3-level
mask control
Default priority
determination
I C R
Figure 6.4 Block Diagram of Interrupt Priority Determination Operation
Rev. 2.0, 11/ 00, page 112 of 1037
(1) Interrupt Acceptance Control and 3-Level Control
In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is
performed by means of the I and UI bits in CCR, and ICR (control level).
Table 6.6 shows the interrupts selected in each interrupt control mode.
Table 6.6 Interrupts Selected in Each Interrupt Control Mode
Inter r upt Mask BitInterrupt
Control
Mode I UI Selected I nterr upt s
0*All int er r upt s ( cont r ol level 1 has priority)0
1*NMI and addr ess t r ap int er r upt s
0*All int er r upt s ( cont r ol level 1 has priority)
0 NMI, addr ess t r ap and cont r ol level 1 interrupt s
1
1
1 NM I and addr ess t r ap int er r upt s
Note: *Don't care
(2) Default Priority Determination
The priority is determined for the selected interrupt, and a vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected
and has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 6.7 shows operations and control signal functions in each interrupt control mode.
Tabl e 6 .7 Ope r a tions and Co nt r o l Si g na l F uncti o ns i n E ach Inte r rupt Co ntrol M o de
Setting Int er r upt Accept ance Cont r ol ,
3-Level Contr ol
Interrupt
Control
Mode INTM1 INTM0 I UI ICR Default Priority
Determination
00
{
IM PR
{
1
0
1
{
IM IM PR
{
Legend:
{
: Int er r upt oper at ion cont r ol perform ed
IM: Used as inter r upt m ask bit
PR: Sets priority
: Not used
Rev. 2.0, 11/ 00, page 113 of 1037
6. 4.2 Interrupt Co ntrol M o de 0
Enabli ng a nd disabl i ng of IRQ inte rrupt s and on-chi p supporti ng modul e int e rrupts ca n be set by
means of the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared to
0, and di sable d when set to 1. Cont rol le ve l 1 i nt errupt source s have hi ghe r priori t y.
Figure 6.5 shows a flowchart of the interrupt acceptance operation in this case.
(1) If an inte rrupt source oc c urs when the c orre sponding int e rrupt e na ble bi t i s set t o 1, an
interrupt request is sent to the interrupt controller.
(2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt
requests are held pending. If a number of interrupt requests with the same control level
setting are generated at the same time, the interrupt request with the highest priority
according to the priority system shown in table 6.4 is selected.
(3) The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If
the I bit is set to 1, only an NMI or an address trap interrupt is accepted, and other interrupt
requests are he l d pendi ng.
(4) When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
(5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved
on the stack shows the address of the first instruction to be executed after returning from the
interrupt ha ndli ng rout ine .
(6) Next, the I bit in CCR is set to 1. This disables all interrupts except NMI and address trap.
(7) A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Rev. 2.0, 11/ 00, page 114 of 1037
Program execution state
Interrupt
generated?
NMI
Address trap
interrupt?
Control level 1
interrupt?
I C
I = 0
Yes
Yes
Yes
Yes Yes
Yes
Yes
No
Yes
Yes
Yes Yes
No
No
No
No
No
No
Save PC and CCR
I 1
Read vector address
Branch to interrupt handling routine
I C No
No
H S W 1H S W 1
H S W 2H S W 2
Hold pending
Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in
Interr upt Co nt r o l M o de 0
Rev. 2.0, 11/ 00, page 115 of 1037
6. 4.3 Interrupt Co ntrol M o de 1
Three-level masking is implemented for IRQ interrupts and on-chip supporting module
interrupts by means of the I and UI bits in the CPU's CCR, and ICR.
(1) Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled
when set to 1.
(2) Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
For example , i f the i nte rrupt ena bl e bi t for an i nt errupt re quest i s set t o 1, and H' 04, H'00, H'00
and H'00 are set in ICRA, ICRB, ICRC and ICRD respectively, (i.e. IRQ2 interrupt is set to
control level 1 and other interrupts to control level 0), the situation is as follows:
(1) When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IC > HSW1 > ...)
(2) When I = 1 a nd UI = 0, only NMI, a ddress trap a nd IRQ2 int errupt s are ena bl ed
(3) When I = 1 a nd UI = 1, only NMI and addre ss trap i nte rrupt s are e na ble d
Figure 6.6 shows the state transitions in these cases.
Only NMI, address trap and
IRQ2 interrupts enabled
All interrupts enabled
Exception handling
execution or UI 1
Exception handling
execution or
I 1, UI 1
I 0
I 1, UI 0
UI 0I 0
Only NMI and address trap
interrupts enabled
Figure 6.6 Example of State Transitions in Interrupt Control Mode 1
Figure 6.7 shows an operation flowchart of interrupt reception.
Rev. 2.0, 11/ 00, page 116 of 1037
(1) If an inte rrupt source oc c urs when the c orre sponding int e rrupt e na ble bi t i s set t o 1, an
interrupt request is sent to the interrupt controller.
(2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt
requests are held pending. If a number of interrupt requests with the same control level
setting are generated at the same time, the interrupt request with the highest priority
according to the priority system shown in table 6.4 is selected.
(3) The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0.
If the I bit is set to 1, only NMI and address trap interrupts are accepted, and other interrupt
requests are he l d pendi ng.
An interrupt re que st set t o i nte rrupt cont rol le ve l 1 ha s priori ty ove r a n int e rrupt re que st set
to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1
and the UI bit is cleared to 0.
When both t he I bit a nd the UI bit are set to 1, onl y NMI and addre ss trap int e rrupts are
accepted, and other interrupt requests are held pending.
(4) When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
(5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved
on the stack shows the address of the first instruction to be executed after returning from the
interrupt ha ndli ng rout ine .
(6) Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI and address
trap.
(7) A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Rev. 2.0, 11/ 00, page 117 of 1037
Program execution state
NMI
I C
Yes
Yes
Yes
Yes Yes
Yes
Yes
No
Yes
Yes
Yes Yes
No
No
No
No
No
No
I C No
No
H S W 1H S W 1
H S W 2H S W 2
Yes
No
Yes
No
Interrupt
generated?
Address trap
interrupt?
Control level 1
interrupt?
I = 0 I = 0
UI = 0
Save PC and CCR
I 1, UI 1
Read vector address
Branch to interrupt handling routine
Hold pending
Figure 6.7 Flowchart of Procedure Up to Interrupt Acceptance in
Interr upt Co nt r o l M o de 1
Rev. 2.0, 11/ 00, page 118 of 1037
6. 4.4 Interrupt E xcept i o n H a ndl ing Se que nce
Figure 6.8 shows the int errupt e xce pt ion ha ndl ing seque nc e. T he exa m ple shown is for the c ase
where interrupt control 0 is set in advanced mode, and the program area and stack area are in on-
chip me m ory.
(1)
(1) Instruction prefetch address (Not executed.
This is the contents of the saved PC, the
return address.)
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(2)(4)
(6)(8)
(10)(12)
(13)
(9)(11)
(14)
(3) (5) (7) (9) (11) (13)
Internal
address bus
Interrupt
request signal
Internal read
signal
Internal
write signal
Internal
data bus (2) (4) (6) (8) (10) (12) (14)
Stack Vector fetch
Interrupt level
determination
Wait for end of
instruction
Interrupt
acceptance
Internal
operation Internal
operation
Instruction
prefetch Interrupt handling routine
instruction prefetch
Instruction code (Not executed.)
(3) Instruction prefetch address (Not executed.)
(5) SP-2
(7) SP-4
Figure 6.8 Interrupt Exception Handling
Rev. 2.0, 11/ 00, page 119 of 1037
6. 4.5 Interrupt Re spo nse T i m e s
Table 6.8 shows interrupt response times-the interval between generation of an interrupt request
and exec ut ion of t he first i nstruc ti on i n the i nte rrupt handl i ng routi ne . The symbol s used in ta bl e
6.8 are explained in table 6.9.
Tabl e 6 .8 Inter rupt Re spo nse T i m e s
No. Number of States Advanced Mode
1 Interr upt pr ior ity determ ination*13
2 Number of wait st at es unt il executing instruction ends*21 to 19+2⋅SI
3 PC, CCR stac k s av e 2⋅Sk
4 Vector fetch 2⋅SI
5 Instruction fetch*32⋅SI
6 Int er nal pr ocessing*42
Total (using on-chip mem ory) 12 to 32
Notes: 1. Two states in case of internal interr upt.
2. Refer s to MULXS and DI VXS ins truc t ions .
3. Prefetch after int er r upt acceptance and interr upt handling routine pref etch.
4. Internal pr ocessing aft er int er r upt accept ance and int er nal processing aft er vector
fetch.
Table 6.9 Number of States in Interrupt Handling Routine Execution
Obj ect of Access
Symbol Internal Memory
Instruction fetch SI
Branch address read SJ
Stack manipulation SK
1
Rev. 2.0, 11/ 00, page 120 of 1037
6.5 Usage Notes
6. 5.1 Contenti o n be t we e n Int e rrupt G ene r a tion and Disabl i ng
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an in te rrupt i s gene rated during execution of the instruction, the interrupt concerned
will still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for
the higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 6.9 shows an example in which the OCIAE bit in timer X1 TIER is cleared to 0.
TIER address
Internal
address bus
Internal
write signal
OCIAE
OCFA
OCIA
interrupt signal
TIER write cycle
by CPU OCIA interrupt
exception handling
Figure 6.9 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the int e rrupt i s ma sked.
Rev. 2.0, 11/ 00, page 121 of 1037
6. 5.2 Instructi o ns tha t Di sa bl e Int errupts
Instruct i ons t ha t di sa bl e i nt errupt s a re L DC, ANDC, ORC, a nd XORC. Aft e r a ny of th ese
instructions is executed, all interrupts except NMI are disabled and the next instruction is always
executed. When the I bit or UI bit is set by one of these instructions, the new value becomes
valid two states after execution of the instruction ends.
6.5.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B in st r uction and t h e E EPMOV. W i n st r u ction.
With the EEPMOV.B i nstruc t ion, a n i nte rrupt reque st (i ncl udi ng NMI) issued during the t ra nsfer
is not accepted until the move is completed.
With the EEPMOV.W i n st r u ct i on, if a n i nte rrupt reque st i s issued during the t ransfer, i nt errupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W inst r u ction, the
following codi ng should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
6. 5.4 Whe n NM I is Disa bl ed
When NMI is disabled, t he input l eve l to t he
10,
pin must be fi xe d high or l ow. It i s
recommended that the NMI interrupt exception handling address be set to the NMI vector
address (H'00001C to H'00001F) and that the RTE instruction also be set to the NMI exception
handling a ddre ss.
<Program Exa m ple >
.ORG H’00001C
.DATA.L NMI
.
.
.
.
NMI:RTE
Rev. 2.0, 11/ 00, page 122 of 1037
Rev. 2.0, 11/ 00, page 123 of 1037
Section 7 ROM (H8S/2194 Series)
7.1 Overview
The H8S/ 2194 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2193 has
112 kbytes, t he H8S/2192 has 96 kbyte s, a nd t he H8S/2191 has 80 kbyte s. T he ROM is
connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one
state, enabling faster instruction fetches and higher processing speed.
The flash memory versions of the H8S/2194 can be erased and programmed on-board as well as
with a general-purpose PROM programmer.
7.1.1 Bloc k Diagram
Figure 7.1 shows a block di agra m of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'01FFFE
H'000001
H'000003
H'01FFFF
Figure 7. 1 ROM Bl ock Diagram (H 8S/2194)
Rev. 2.0, 11/ 00, page 124 of 1037
7.2 Overview of F l ash Memory
7.2.1 Features
The features of the flash memory are summarized below.
• Four flash memory operating modes
— Program mode
— Erase mode
— Program-verify m ode
— Erase-veri fy m ode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase
(in single-block units). When erasing all blocks, the individual blocks must be erased
sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28-
kbyte, and 32-kbyt e bloc ks.
• Programming/erase times
The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming,
equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
— Boot mode
— User program mode
• Automatic bit rate adjustment
If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and
MCU's bit rates.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
Rev. 2.0, 11/ 00, page 125 of 1037
7.2.2 Block Diagram
Module bus
Bus interface/controller
Flash memory
(128 kbytes)
Operat-
ing
mode
FLMCR1 *
*
*
*
STCR
FLMCR1
FLMCR2
EBR1
EBR2
: Serial timer control register
: Flash memory control register 1
: Flash memory control register 2
: Erase block register 1
: Erase block register 2
[Legend]
Internal address bus
Internal data bus (16 bits)
STCR
FWE pin
Mode pin
FLMCR2
EBR1
EBR2
Note: * These registers are exclusively used for the flash
memory. If you try to read these addresses with the
mask ROM version, values read becomes uncertain.
Data write is also disabled with the above version.
Figure 7. 2 Bl oc k Diagram of Fl ash Memor y
Rev. 2.0, 11/ 00, page 126 of 1037
7.2.3 Flash Memory O per ating Modes
(1) Mode Transiti ons
When each mode pin and the FWE pin are set in the reset state and a reset-start is executed,
the MCU enters one of t he opera t ing m ode s shown in figure 7. 3. In user mode , fl ash
memory can be read but not programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and
programmer mode.
Boot mode
On-board program mode
User
program
mode
User mode
Reset state
Programmer
mode
FWE = 1, MD0 = 0,
P12 = P13 = P14 = 1
RES = 0
RES = 0
FWE = 1
SWE = 1
FWE = 0
or
SWE = 0
RES = 0
MD0 = 1, FWE = 0
RES = 0
Only make a transition between user mode
and user program mode when the CPU is not
accessing the flash memory.
*1 MD0=0,P12=P13=1,P14=0
Note:
*1
Figure 7. 3 F l ash Memory M ode Tr ansitions
Rev. 2.0, 11/ 00, page 127 of 1037
(2) On-Board Programming Modes
(a) Boot m ode
Flash memory RAM
Host
Programming control
program
SCI
Application program
(old version)
New application
program
New application
program
Flash memory
This LSI
This LSI
This LSI
This LSI
RAM
Host
SCI
Application program
(old version)
Boot program area
Programming control
program
New application
program
Flash memory RAM
Host
SCI
Flash memory
preprograming
erase
Boot program
Flash memory
Program execution state
RAM
Host
SCI
New application
program
Boot program
Programming control
program
"#
!"
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
the LSI (originally incorporated in the chip) is
started and the programing control program in
the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Boot programBoot program
Boot program area Boot program
area
Programming
control program
Figure 7. 4 Boot M ode
Rev. 2.0, 11/ 00, page 128 of 1037
(b) User program mode
<Flash memory>
<This LSI>
<RAM>
<Host>
Programming/erase control program
SCI
Boot program
New application
program
<This LSI>
<RAM>
<Host>
SCI
<Flash memory>
<This LSI>
<RAM>
<Host>
SCI
Flash memory erase
Boot program
New application
program
<This LSI>
Program execution state
<RAM>
<Host>
SCI
Programming/erase
control program
1. Initial state 2. Programming/erase control program transfer
3. Flash memory initialization 4. Writing new application program
FWE assessment program
Transfer program
Application
program
(old version)
,
FWE assessment program
Transfer program
Programming/erase control program Programming/erase control program
<Flash memory>
New application
program
Boot program
FWE assessment program
Transfer program
(1) The FWE assessment program that confirms that
the FWE pin has been driven high, and (2) the
program that will transfer the programming/erase
control program from the flash memory to on-chip RAM
should be written into the flash memory by the user
beforehand. (3) The programming/erase control
program should be prepared in the host or in the flash
memory.
When user program mode is entered, user software
confirms this fact, executes the transfer program in the
flash memory, and transfers the programming/erase
control program to RAM.
The programming/erase control program in RAM is
executed, and the flash memory is initialized (to H'FF).
Erasing can be performed in block units, but not in byte
units.
Next, the new application program in the host is written
into the erased flash memory blocks. Do not write to
unerased blocks.
New application
program
<Flash memory>
Boot program
FWE assessment program
Transfer program
Application
program
(old version)
Figure 7. 5 User P r ogram M ode (Example )
Rev. 2.0, 11/ 00, page 129 of 1037
(3) Difference s bet ween Boot Mode a nd User Program Mode
Table 7.1 Differences between Boot Mode and User Program Mode
Boot M ode User Progr am Mode
Entire memory erase Yes Yes
Block erase No Yes
Program m ing contr ol pr ogr am*Program/program-verify Erase/erase-verify
Program/program-verify
Note: *To be provided by the user , in accor dance with t he r ecom m ended algorit hm .
(4) Block Configuration
The fla sh me mory i s divi ded i nt o two 32-kbyte bl ocks, two 8-kbyte bl ocks, one 16-kbyt e
block, one 28-kbyt e bloc k, a nd four 1-kbyte bl ocks.
8k bytes
Address H'00000
Address H'1FFFF
128 kbytes
32 kbytes
128-kbyte version
32 kbytes
28 kbytes
1 kbyte
1 kbyte
1 kbyte
1 kbyte
16 kbytes
8k bytes
Figure 7. 6 F l ash Memory Bl oc k Configuration
Rev. 2.0, 11/ 00, page 130 of 1037
7.2.4 Pin Configuration
The flash memory is controlled by means of the pins shown in table 7. 2.
Table 7.2 Flash Memory Pins
Pin Nam e Abbr evi ation I/O Funct ion
Reset
5(6
Input Reset
Flash write enable FWE Input Flash program/ er ase pr ot ect ion by har dware
Mode 0 MD0 Input Sets t his LSI oper ating mode
Port 12 P12 Input Sets this LSI operat ing m ode when MD0 = 0
Port 13 P13 Input Sets this LSI operat ing m ode when MD0 = 0
Port 14 P14 Input Sets this LSI operat ing m ode when MD0 = 0
Transmit dat a SO1 Out put Serial transmit dat a out put
Receive data SI1 I nput Serial receive data input
7.2.5 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 7.3.
In order to access these registers, the FLSHE bit in STCR must be set to 1.
Table 7.3 Flash Memory Regi sters
Register Name Abbreviat i on R/W Initial
Value Address*5Access
Size
Flash memor y cont r ol r egister 1 FLMCR1*4R/W*1H'00*2H'FFF8 8
Flash memor y cont r ol r egister 2 FLMCR2*4R/W*1H'00*3H'FFF9 8
Erase block register 1 EBR1*4R/W*1H'00*3H'FFFA 8
Erase block register 2 EBR2*4R/W*1H'00*3H'FFFB 8
Serial timer cont r ol r egister STCR R/W H'00 H'FFEE 8
Notes: 1. When the FWE bit in FLMCR1 is not set at 1, wr ites ar e disabled.
2. When a high level is input to the FWE pin, the initial value is H'80.
3. When a low level is input t o t he FW E pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, t hese r egist er s ar e initialized to H'00.
4. FLMCR1, FLMCR2, EBR1, and EBR2 ar e 8- bit registers. Only byte accesses are
valid for these r egister s, the access requiring 2 stat es.
5. Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 131 of 1037
7.3 Fla sh Mem ory Regist er Descri p t io n s
7.3.1 Fl ash Memory Control Regi ster 1 (FLM CR1)
7
FWE
—*
R
6
SWE
0
R/W
5
—
0
—
4
—
0
—
3
EV
0
R/W
0
P
0
R/W
2
PV
0
R/W
1
E
0
R/W
Bit
Initial value
R/W
:
:
:
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify
mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is
entered by setting SWE to 1 when FWE = 1, then setting the PSU bi t i n FL MCR2, a nd fi nally
setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the
ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized by a reset, in power-
down state (excluding the medium-speed mode, module stop mode, and sleep mode), or when a
low level is input to the FWE pin. Its initial value is H'80 when a high level is input to the FWE
pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will
return H'00, and writes are invalid.
Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to the EV and PV
bits only when FWE=1 and SWE=1; writes to the E bit only when FWE = 1, SWE = 1, and ESU
= 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1 .
Bit 7: Flash Write Enable (F WE)
Sets hardware protection against flash memory programming/erasing.
Bit 7
FWE Description
0 When a low level is input t o the FWE pin (hardware- pr otected st at e)
1 When a high level is input to the FWE pin
Rev. 2.0, 11/ 00, page 132 of 1037
Bit 6: Software Wr ite Enable (SWE)
Enables or disables flash memory programming. SWE should be set before setting bits ESU,
PSU, EV, PV, E , P, a nd E B9 t o E B0, a nd shoul d not be cleared at the same time as these bits.
Bit 6
SWE Description
0 Writes ar e disabled (Init ial value)
1 Writ es ar e enabled
[Sett ing condition] Sett ing is available when FWE = 1 is select ed
Bit 5 and 4: Reserved
These bit s ca nnot be m odifi e d and a re al ways rea d as 0.
Bit 3: Erase-Veri fy (EV)
Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit
at the same time.
Bit 3
EV Description
0 Erase-ver ify m ode clear ed (Init ial value)
1 Transition to er ase- ver ify m ode
[Sett ing condition] Sett ing is available when FWE = 1 and SWE = 1 are selected
Bit 2: Program-Verify (PV)
Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, E V, E, or P
bit at the same time.
Bit 2
PV Description
0 Program - ver ify m ode clear ed (Init ial value)
1 Transition t o pr ogr am - ver ify m ode
[Sett ing condition] Sett ing is available when FWE = 1 and SWE = 1 are selected
Rev. 2.0, 11/ 00, page 133 of 1037
Bit 1: Erase (E)
Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, E V, PV, o r P b i t at
the same time.
Bit 1
E Description
0 Erase mode cleared (Init ial value)
1 Transition t o er ase m ode
[Sett ing condition] Sett ing is available when FWE = 1, SWE = 1, and ESU = 1 are
selected
Bit 0: Progr am (P )
Selects program mode transition or clearing. Do not set the SWE, PSU, E SU, EV, PV, o r E b i t
at the same time.
Bit 0
P Description
0 Program m ode clear ed (Init ial value)
1 Transition t o pr ogr am m ode
[Sett ing condition] Setting is available when FWE = 1, SWE = 1, and PSU = 1 are
selected
Rev. 2.0, 11/ 00, page 134 of 1037
7.3.2 Flash Memory Control Regi ster 2 (FLM CR2)
7
FLER
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
PSU
0
R/W
2
—
0
—
1
ESU
0
R/W
Bit
Initial value
R/W
:
:
:
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory
program/erase protection (error protection) and performs setup for flash memory program/erase
mode. FLMCR2 is initialized to H'00 by a reset. The ESU and PSU bi t s are cleared to 0 in
power-down state (excluding the medium-speed mode, module stop mode, and sleep mode),
hardware protect mode, or software protect mode.
Bit 7: Flash Memor y Er ror (F LER)
Indicates that an error has occurred during an operation on flash memory (programming or
erasing). When FLER is set to 1, flash memory goes to the error-protection state.
Bit 7
FLER Description
0 Flash memor y is oper at ing normally
Flash memor y pr ogr am / er ase protect ion (er ror pr ot ect ion) is disabled
[Clearing condition] Reset or har dware standby mode (Initial value)
1 An error has occur red during flash memory pr ogr am m ing/ er asing
Flash memor y pr ogr am / er ase protect ion (er ror pr ot ect ion) is enabled
[Sett ing condition] See section 7. 6. 3, Er r or Pr ot ect ion
Bits 6 to 2: Reserved
These bit s ca nnot be m odifi e d and a re al ways rea d as 0.
Bit 1: Erase Setup (ESU)
Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1.
Do not se t t h e SWE, PSU, E V, PV, E , or P b i t at the same time.
Bit 1
ESU Description
0 Erase setup cleared (I nitial value)
1 Erase setup
[Sett ing condition] When FW E = 1, and SWE = 1
Rev. 2.0, 11/ 00, page 135 of 1037
Bit 0: Progr am Setup (PSU)
Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in
FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 0
PSU Description
0 Program setup cleared (Init ial value)
1 Program setup
[Sett ing condition] When FW E = 1, and SWE = 1
Rev. 2.0, 11/ 00, page 136 of 1037
7.3.3 Erase Block Register s 1 and 2 (EBR1, EBR2)
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
EB8
0
R/W
2
—
0
—
1
EB9
0
R/W
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit
EBR1
Initial value
R/W
:
:
:
:
Bit
EBR2
Initial value
R/W
:
:
:
:
EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1
and 0 in EBR1 (128-kbyte versions only) and bits 7 to 0 in EBR2 are readable/writable bits.
EBR1 and EBR2 are each initialized to H'00 by a reset, in power-down state (excluding the
medium-speed mode, module stop mode, and sleep mode), when a low level is input to the FWE
pin, or when a high l e vel i s input t o t he FWE pi n and t he SWE bi t in FLMCR1 is not set . W hen
a bit i n E BR1 or EBR2 i s set, t he c orre sponding bloc k c an be e rased. Othe r bl ocks are e rase-
protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set).
The flash memory block configuration is shown in table 7.4.
Table 7.4 Flash Memory Er ase Bloc ks
Block (Si ze)
128-kbyte Ver si ons Address
EB0 (1 kbyte) H'000000 t o H'0003FF
EB1 (1 kbyte) H'000400 t o H'0007FF
EB2 (1 kbyte) H'000800 t o H'000BFF
EB3 (1 kbyte) H'000C00 to H'000FFF
EB4 (28 kbytes) H'001000 to H'007FFF
EB5 (16 kbytes) H'008000 to H'00BFFF
EB6 (8 kbytes) H'00C000 to H'00DFFF
EB7 (8 kbyt es) H'00E000 to H'00FFFF
EB8 (32 kbytes) H'010000 to H'017FFF
EB9 (32 kbyt es) H'018000 to H'01FFFF
Rev. 2.0, 11/ 00, page 137 of 1037
7.3.4 Serial/Timer Control Register (STCR)
7
—
0
—
6
IICX
0
R/W
5
IICRST
0
R/W
4
—
0
—
3
FLSHE
0
R/W
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
R/W
:
:
:
STCR is an 8-bit readable/writable register that controls register access, the I2C bus inte rfac e
operating mode, and on-chip flash memory (in F-ZTAT versions), and also selects the I2C bus
interface serial clock frequency. For details on functions not related to on-chip flash memory,
see section 25.2.7, Serial/Timer Control Register (STCR), and desc riptions of individual
modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset.
Bits 6, 5: I2C Contr o l ( IICX, IICRST)
These bits control the operation of the I2C bus interface. For details, see section 24, I2C Bus
Interface.
Bit 3: Flash Memor y Control Regi ster Enable (F LSHE)
Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If
FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash
memory control register contents are retained.
Bit 3
FLSHE Description
0 Flash memory cont r ol r egister s deselected (Initial value)
1 Flash memory cont r ol r egister s selected
Bits 7, 4 and 2 to 0: Reserved
Rev. 2.0, 11/ 00, page 138 of 1037
7.4 On- Board Programm ing Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot
mode and user program mode. The pin settings for transition to each of these modes are shown
in tabl e 7. 5. For a dia gra m of t he tra nsit ions to t he vari ous fla sh mem ory m odes, see fi gure 7. 3.
Table 7.5 Setting On-Board Programmi ng Modes
Mode Pin
Mode Name FWE M D0 P12 P13 P14
Boot mode 1 0 1*21*21*2
User progr am m ode 1*11
Notes: 1. In user pr ogr am m ode, the FWE pin should not be const ant ly set t o 1. Set FW E to 1
to make a transition t o user pr ogr am m ode bef ore perf or m ing a progr am/er ase/ ver if y
operation.
2. Can be used as I/O ports af ter boot m ode is initiated.
Rev. 2.0, 11/ 00, page 139 of 1037
7.4.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in
the host before ha nd. The c hanne l 1 SCI to be used i s set t o asynchronous mode .
When a re set -start i s exec ut ed a ft er t he MCU's pins have be en set t o boot m ode , the boot
program built into the MCU is started and the programming control program prepared in the host
is serially transmitted to the MCU via the SCI1. In the MCU, the programming control program
received via the SCI1 is written into the programming control program area in on-chip RAM.
After the transfer is completed, control branches to the start address of the programming control
program area and the programming control program execution state is entered (flash memory
programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 7.7, and the boot program mode
execut i on proce dure in fi gure 7. 8.
SI1
SO1 SCI1
This LSI
Flash memory
Write data reception
Verify data
transmission
Host
On-chip RAM
Figure 7. 7 System Configuration in Boot Mode
Rev. 2.0, 11/ 00, page 140 of 1037
Start
Set pins to boot mode and
execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
Host transmits programming
control program sequentially in
byte units
Transfer received programming
control program to on-chip RAM
This LSI calculates bit rate and
sets value in bit rate register
Host transmits number of
programming control program
bytes (N), upper byte followed by
lower byte
This LSI transmits received
programming control program to
host as verify data (echo-back)
n = 1
End of transmission
n = N?
n+1 n
Note :
Yes
No
This LSI measures low period of
H'00 data transmitted by host
After bit rate adjustment, transmits
one H'00 data byte to host to
indicate end of adjustment
Upon receiving H'55, this LSI
transmits one H'AA data byte to
host
Host confirms normal reception of
bit rate adjustment end indication
(H'00) and transmits one H'55
data byte
Execute programming control
program transferred to on-chip
RAM
This LSI transmits received
number of bytes to host as verify
data (echo-back)
If a memory cell does not operate normally and cannot be erased, one
H'FF byte is transmitted as an erase error, and the erase operation and
subsequent operations are halted.
After confirming that all flash
memory data has been erased,
this LSI transmits one H'AA data
byte to host
Check flash memory data, and if
data has already been written,
erase all blocks
Figure 7. 8 Boot M ode Exe cution Pr oc edure
Rev. 2.0, 11/ 00, page 141 of 1037
(1) Automatic SCI Bit Rate Adjustment
Start
bit Stop
bit
D0 D1 D2 D3 D4 D5 D6 D7
Low period (9 bits) measured (H'00 data) High period
(1 or more bits)
Fig ure 7.9 Automatic SCI Bi t Rate Adjustme nt
When boot mode is initiated, the MCU measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate
of the transmission from the host from the measured low period, and transmits one H'00 byte to
the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If
reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations. Depending on the host's transmission bit rate and the MCU's system clock
frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure
correct SCI operation, the host's transfer bit rate should be set to (2400, 4800, or 9600) bps.
Table 7.6 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU's bit rate is possible. The boot program should be executed within this
system clock range.
Table 7.6 System Clock Frequencies for which Automatic Adjustment of This LSI Bit
Rate i s Possi ble
Host Bit Ra t e System Clock Frequency f or w hi ch Aut omatic Adjust m ent
of Thi s LSI Bit Rate is Possi ble
9600 bps 8 MHz to 10 M Hz
4800 bps 4 MHz to 10 M Hz
Rev. 2.0, 11/ 00, page 142 of 1037
(2) On-Chip RAM Are a Divi sions in Boot Mode
In boot mode , t he 2048-byt e ar ea from H' FFE FB0 t o H' FFF7AF i s rese rve d for use by th e
boot program, as shown in figure 7.10. The area to which the programming control program
is tra nsfe rre d i s H' FFF7B0 t o H' FFFF2F (1920 byt e s). T he boot progra m a r e a c a n be use d
when the programming control program transferred into RAM enters the execution state. A
stack area should be set up as required.
H'FFEFB0
H'FFF7B0
Programming
control program
area
(1920 bytes)
Reserved area
(128 bytes)
H'FFFFAF
H'FFFF30
Boot program
area*
(2048 bytes)
Note: * The boot program area cannot be used until a transition is made to the execution
state for the programming control program transferred to RAM. Note that the boot
program reamins stored in this area after a branch is made to the programming
control program.
Figure 7. 10 RAM Areas in Boot Mode
Rev. 2.0, 11/ 00, page 143 of 1037
(3) Notes on Use of Boot Mode:
(a) When reset is released in boot mode, it measures the low period of the input at the SCI1's
SI1 pin. The reset should e nd with SI1 pin hi gh. Afte r the re set e nds, i t ta ke s about 100
states for the chip to get ready to measure the low period of the SI1 pin input.
(b) In boot mode, if any data has been programmed into the flash memory (if all data is not
1), all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
(c) Interrupts cannot be used while the flash memory is being programmed or erased.
(d) The SI1 and SO1 pins should be pulled up on the board.
(e) Before branching to the programming control program (RAM area H'FFF3B0), the chi p
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR
= 1).
The contents of the CPU's internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control
program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls,
etc., a stack area must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
(f) Boot mode can be entered by making the pin settings shown in table 7.5 and executing a
reset-start.
When the chip detects the boot mode setting at reset release*1, it retains that state
internally.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then
setting the FWE pin and mode pins, and executing reset release*1. Boot m ode ca n a lso be
cleared by a WDT overflow reset.
If the mode pin input levels are changed in boot mode, the boot mode state will be
maintained in the microcomputer, and boot mode continued, unless a reset occurs.
However, the FWE pin must not be driven low while the boot program is running or flash
memory is being programmed or erased*2.
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4
states) with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 7.9, Flash
Memory Programming and Erasing Precautions.
Rev. 2.0, 11/ 00, page 144 of 1037
7.4.2 User Program M ode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means of FWE control and supply of
programming data, and storing a program/erase control program in part of the program area as
necessary.
In this mode, the chip starts up in mode 1 and applies a high level to the FWE pin.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external m e mory.
Figure 7.11 shows the procedure for executing the program/erase control program when
transferred t o on-c hip RAM.
Clear FWE *
FWE = high *
Branch to flash memory
application program
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Transfer program/erase
control program to RAM
MD0 = 1
Reset start
Write the FWE assessment program and
transfer program (and the program/erase
control program if necessary) beforehand
Note: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only
when the flash memory is programmed or erased. Also, while a high level is applied to the
FWE pin, the watchdog timer should be activated to prevent overprogramming or
overerasing due to program runaway, etc.
* For further information on FWE application and disconnection, see section 7.9, Flash
Memory Programming and Erasing Precautions.
Figure 7.11 User Program Mode Execution Procedure
Rev. 2.0, 11/ 00, page 145 of 1037
7.5 P rogram ming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU and E SU bi t s i n FL MCR2, a nd t h e P, E , PV, and E V bi t s in FL MCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program
that controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in
FLMCR1, a nd th e E SU and PSU bi t s i n FL MCR2, i s e xe c ut e d by a progra m i n fl a sh
memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Perform programming in the erased state. Do not perform additional programming
on previously programmed addresses.
7.5.1 Pr ogram M ode
Follow the procedure shown in the program/program-verify flowchart in figure 7.12 to write
data or programs to flash memory. Performing program operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 32
bytes at a time.
Table 29.9 in section 29.2.7, Flash Memory Characteristics, lists wait time (x, y, z, α, β, γ, ε and
η) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and
FLMCR2) and the maximum write count (N).
Followi ng the elapse of (x) µs or more a fte r t he SWE bi t i s set t o 1 in fl a sh mem ory c ontrol
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram
data area, and the 32-byte data in the reprogram data area written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80,
H'A0, H' C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program
address and program data are latched in the flash memory. A 32-byte data transfer must be
performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the
extra a ddre sses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway,
etc. Set more than (y + z + α + β) µs as the WDT ove rfl ow period. Afte r t his, prepa ra ti on for
program mode (program setup) is carried out by setting the PSU bit in FL MCR2, a nd a ft e r t he
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
FLMCR1. The time during which the P bit is set is the flash memory programming time. Make
a program setting so that the time for one programming operation is within the range of (z) µs.
Rev. 2.0, 11/ 00, page 146 of 1037
7.5.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared, then the PSU bit i n FL MCR2 i s cleared at least (α) µs later). The watchdog
timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to
program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify
mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy
write should be executed after the elapse of ( γ) µs or more. W he n the fl ash me m ory is rea d i n
this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least
(ε) µs after the dummy write before performing this read operation. Next, the originally written
data is compared with the verify data, and reprogram data is computed (see figure 7.12) and
transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-
verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1. If reprogramming is
necessary, set program mode again, and repeat the program/program-verify sequence as before.
However, ensure that the program/program-verify sequence is not repeated more than (N) times
on the same bits.
Rev. 2.0, 11/ 00, page 147 of 1037
START
End of
programming Programming
failure
Set SWE bit in FLMCR1
Wait (x) µs
Store 32-byte program data in program data area
and reprogram data area
n = 1
m = 0
Enable WDT
Set PSU bit in FLMCR2
Wait (y) µs
Set P bit in FLMCR1
Wait (z) µs
Start of programming
Clear P bit in FLMCR1
Wait ( ) µs
Wait ( ) µs
NO
NO
NO NO
YES
YES
YES
Wait ( ) µs
Wait ( ) µs
*
5
*
3
*
2
*
5
*
5
*
5
*
5
*
5
*
5
*
5
*
4
*
1
*
5
Wait ( ) µs
Clear PSU bit in FLMCR2
Disable WDT
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Reprogram data computation
*
4
Transfer reprogram data to reprogram data area
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
End of programming
Program data = verify data?
End of 32-byte
data verification?
m = 0?
Increment address
YES
Clear SWE bit in FLMCR1
n N?
n n+1
Notes:
Program data
0
0
1
1
Verify data
0
1
0
1
Reprogram data
1
0
1
1
Comments
Do not reprogram bits for which
programming has been completed.
Programming incomplete; reprogramming
should be performed.
—
Still in erased state; no action
1.
2.
3.
4.
5.
Write 32-byte data in RAM reprogram data
area consecutively to flash memory
Programming must be excuted in the erased state.
Do not perform additional programming on
addresses that have already been programmed.
RAM
Program data storage
area (32 bytes)
Reprogram data
storage area (32 bytes)
Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0,, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in
this case, H'FF data must be written to the extra addresses.
Verify data is read in 16-bit (word) units.
Even in case of the bit which is already-programmed in the 32-byte programming loop, perform additional
programming if the bit fails at the next verify.
An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents
of the latter are rewritten as programming progresses.
The values of x, y, z, , , , , and N are listed in section 29.2.7, Flash Memory Characteristics.
Figure 7.12 Program/Program-Verify Flowchart
Rev. 2.0, 11/ 00, page 148 of 1037
7.5.3 Erase Mode
Flash memory e ra sing should be pe rform ed bl oc k by bloc k fol lowing t he proce dure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 7.13.
Table 28.9 in section 28.2.7, Flash Memory Characteristics lists wait time (x, y, z, α, β, γ, ε and
η) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and
FLMCR2) and the maximum clearing count (N).
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased
in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in
flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent
overerasing in the event of program runaway, etc. Set more than (y + z + α + β) ms as the WDT
overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the
ESU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to
erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash
memory erase time. Ensure that the erase time does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
to 0) is not nec e ssary before sta rt ing t he era se proc edure .
7.5.4 Erase-Ver ify M ode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit in FLMCR2 is cleared at least ( α) µs later), the watchdog timer is cleared after the
elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the
EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should
be made to the addresses to be read. The dummy write should be executed after the elapse of (γ)
µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the
data at the latched address is read. Wait at least (ε) µs after the dummy write before performing
this read operation. If the read data has been erased (all 1), a dummy write is performed to the
next address, and erase-verify is performed. If the read data has not been erased, set erase mode
again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the
erase/erase-verify sequence is not repeated more than (N) times. When verification is
completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been completed on
all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1
bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-
verify sequence in the same way.
Rev. 2.0, 11/ 00, page 149 of 1037
End of erasing
START
Set SWE bit in FLMCR1
Set ESU bit in FLMCR2
Set E bit in FLMCR1
Wait (x) µs
Wait (y) µs
n = 1
Set EBR1, EBR2
Enable WDT
*2
*4
*2
Wait (z) ms *2
Wait ( ) µs *2
Wait ( ) µs *2
Wait ( ) µs
Set block start address to
verify address
*2
Wait ( ) µs *2
Wait ( ) µs
*2*2
*2
*3
*5
Start of erase
Clear E bit in FLMCR1
Clear ESU bit in FLMCR2
Set EV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1
Wait ( ) µs
Clear EV bit in FLMCR1
Clear SWE bit in FLMCR1
Disable WDT
Halt erase
*1
Verify data =
all 1?
End of erasing of
all erase blocks?
Erase failure
Clear SWE bit in FLMCR1
n N?
NO
NO
NO NO
YES
YES
YES
YES
Notes: 1.
2.
3.
4.
5.
Increment
address
n n+1
Last address
of block?
Preprogramming (setting erase block data to all 0) is not necessary.
The values of x, y, z, , , , , and N are listed in section 29.2.7, Flash Memory Characteristics.
Verify data is read in 16-bit (word) units.
Set only one bit in EBR1 or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 7. 13 Er ase/ Erase-Ver i fy Fl owchart (Single -Bloc k Erase)
Rev. 2.0, 11/ 00, page 150 of 1037
7.6 F lash Mem ory P rotect ion
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
7.6.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FLMCR2) and era se bloc k re giste rs 1 and 2 (E BR1, EBR2). In e rror
protection mode, FLMCR1, FLMCR2, EBR1 and EBR2 settings are retained. (See table 7.7.)
Table 7.7 Hardware Protection
Functions
Item Description Program Erase
FWE pin
protection •When a low level is input t o the FWE pin, FLMCR1,
FLMCR2, EBR1, and EBR2 are initialized, and the
program / er ase- pr otected st at e is ent er ed
Yes Yes
Reset/standby
protection •In a reset (including a WDT overflow reset) and in
power-down stat e ( excluding the m edium - speed
mode, m odule st op m ode, and sleep m ode) ,
FLMCR1, FLMCR2 (excluding the FLER bit), EBR1,
and EBR2 are initialized, and t he pr ogram/ er ase-
protected stat e is ent er ed
•In a reset via t he
5(6
pin, the r eset st ate is not
entered unless t he
5(6
pin is h e ld low u n til osc illa tion
st a biliz e s a ft e r p o we r in g o n. I n the c a s e of a rese t
during operat ion, hold t he
5(6
pin low for the
5(6
pulse widt h specif ied in the AC character istics section
Yes Yes
Rev. 2.0, 11/ 00, page 151 of 1037
7.6.2 Software Protec ti on
Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block
registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in
flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase
mode. (See table 7.8.)
Table 7.8 Software Protec tion
Functions
Item Description Program Erase
SWE bit
protection •Clearing the SWE bit to 0 in FLMCR1 sets t he
program / er ase- pr otected st at e f or all blocks
(Execute in on-chip RAM or external memory)
Yes Yes
Block
specification
protection
•Erase prot ect ion can be set f or individual blocks by
settings in erase block register s 1 and 2 ( EBR1,
EBR2)
•Setting EBR1 and EBR2 to H'00 places all blocks in
the erase- pr ot ected stat e
−Yes
Rev. 2.0, 11/ 00, page 152 of 1037
7.6.3 Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit.
However, PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
(1) When flash memory is read during programming/erasing (including a vector read or
instruction fetch)
(2) Immediately after exception handling (excluding a reset) during programming/erasing
(3) When a SLEEP instruction is executed during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 7.14 shows the flash memory state transition diagram.
: Memory read possible
: Verify-read possible
: Programming possible
: Erasing possible
RD
VF
PR
ER
: Memory read not possible
: Verify-read not possible
: Programming not possible
: Erasing not possible
RD
VF
PR
ER
RD VF PR ER FLER = 0
Error occurrence
Error occurrence
SLEEP instruction
execution
RES = 0
RES = 0
RES = 0
RD VF PR ER FLER = 0
Program mode
Erase mode Reset
(hardware protection)
RD VF PR ER FLER = 1 RD VF PR ER FLER = 1
Error protection mode Error protection mode
(Power-down state)
*1
Power-down state
*1
FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2
initialization state
FLMCR1, FLMCR2,
EBR1, EBR2 initialization
state
Power-down state
*1
release
*1: Watch mode, standby mode, and
subactive mode
Figure 7. 14 F l ash Memory State Tr ansitions
Rev. 2.0, 11/ 00, page 153 of 1037
7.7 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input is disabled when flash memory is being programmed or
erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot
mode*1, to give priority to the program or erase operation. There are three reasons for this:
(1) Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
(2) In the interrupt exception handling sequence during programming or erasing, the vector
would not be read correctly*2, possibly re sulti ng i n MCU runaway.
(3) If interrupt oc curre d duri ng boot progra m exe c uti on, i t would not be possible t o e xec ut e t he
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests, including NMI input, must therefore
be disabled inside and outside the MCU during FWE application. Interrupt is also disabled in
the error-protection state while the P or E bit remains set in FLMCR1.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by
the write control program is complete.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P or E bit is
set in FLMCR1), correct read data will not be obtained (undetermined values will be
returned).
• If the interrupt entry in the interrupt vector table has not been programmed yet,
interrupt exception handling will not be executed correctly.
Rev. 2.0, 11/ 00, page 154 of 1037
7.8 F lash Mem ory P rogramm er Mode
7.8.1 Pr ogramme r Mode Setti ng
Programs and data can be written and erased in programmer mode as well as in the on-board
programming modes. In programmer mode, the on-chip ROM can be freely programmed using
a PROM programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip
flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read
mode are supported with these device types. In auto-program mode, auto-erase mode, and status
read mode, a status polling procedure is used, and in status read mode, detailed internal signals
are output after execution of an auto-program or auto-erase operation.
7.8.2 Socket Adapters and Memory Map
In programmer mode, a socket adapter is mounted on the writer programmer. The socket
adapte r produc t c ode s are l i sted i n t abl e 7. 9.
Figure 7.15 shows the memory map in programmer mode.
Tabl e 7 .9 Socke t Ada pter Pro duc t Co de s
Product Codes Package Socket Adapter Pr oduct Code
HD64F2194 112-pin QFP M E2194ESHF1H
This LSI
H'000000
MCU mode Programmmer mode
H'01FFFF
H'00000
H'1FFFF
On-chip ROM area
(128 kbytes)
Figure 7.15 Memory Map in Programmer Mode
Rev. 2.0, 11/ 00, page 155 of 1037
7.8.3 Programme r Mode O per ation
Table 7.10 shows how the different operating modes are set when using programmer mode, and
table 7.11 lists the commands used in programmer mode. Details of each mode are given below.
(1) Memory Read Mode
Memory read m ode supports byte re a ds.
(2) Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
(3) Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is
used to confirm t he e nd of a uto-e ra sing.
(4) Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the FO6 signal. In status read mode, error information is output if an
error occurs.
Table 7.10 Settings for Each Operati ng Mode in Pr ogr ammer M ode
Pin Names
Mode FWE
&(
&( 2(
2( :(
:(
FO0 t o FO7 FA0 t o FA17
Read H or L L L H Data out put Ain
Out put disable H or L L H H Hi-z X
Command write H or L*3L H L Dat a input Ain*2
Chip disable*1H or L L X X Hi-z X
Notes: 1. Chip disable is not a standby st at e; int er nally, it is an operat ion st at e.
2. Ain indicates that t her e is also address input in auto- pr ogr am m ode.
3. For comm and writes when m aking a tr ansit ion to aut o- pr ogr am or auto-er ase m ode,
input a high level to the FWE pin.
Rev. 2.0, 11/ 00, page 156 of 1037
Table 7.11 Progr ammer M ode Commands
1st Cycle 2nd Cycle
Command Name Number of
Cycles Mode Address Data Mode Address Data
Memor y r ead m ode 1+n write X H'00 read RA Dout
Auto-pr ogr am m ode 129 write X H'40 wr ite WA Din
Auto-erase mode 2 write X H'20 write X H'20
Status r ead m ode 2 write X H'71 write X H'71
Notes: 1. In auto-pr ogram mode. 129 cycles are required f or com mand writing by a
simultaneous 128-byt e write.
2. In mem or y r ead m ode, the num ber of cycles depends on t he num ber of addr ess wr ite
cycles (n).
Rev. 2.0, 11/ 00, page 157 of 1037
7.8.4 Memory Read Mode
(1) After the end of an auto-program, auto-erase, or status read operation, the command wait
state is entered. To read memory contents, a transition must be made to memory read mode
by means of a command write before the read is executed.
(2) Command writes can be performed in memory read mode, just as in the command wait state.
(3) Once mem ory re ad m ode has bee n e nte re d, consec ut ive re ads ca n be perform e d.
(4) After power-on, memory read mode is entered.
Table 7.12 AC Characteristics in Memory Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
CE
ADDRESS
DATA H'00
OE
WE
Command write
t
wep
t
ceh
t
dh
t
ds
t
f
t
r
t
nxtc
Note: Data is latched on the rising edge of WE.
t
ces
Memory read mode
ADDRESS STABLE
DATA
Figure 7. 16 M e mory Read Mode Ti mi ng Waveforms after Command Write
Rev. 2.0, 11/ 00, page 158 of 1037
Table 7.13 AC Characteristics when Entering Another Mode from Memory Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
CE
ADDRESS
DATA H'XX
OE
WE
XX mode command write
t
wep
t
ceh
t
dh
t
ds
t
nxtc
Note: Do not enable WE and OE at the same time.
t
ces
ADDRESS STABLE
DATA
t
f
t
r
Figure 7.17 Timing Waveforms when Entering Another Mode from Memory Read Mode
Rev. 2.0, 11/ 00, page 159 of 1037
Table 7.14 AC Characteristics in Memory Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Access time tacc 20 µs
&(
output delay time tce 150 ns
2(
output delay time toe 150 ns
Out put disable delay time tdf 100 ns
Data output hold t ime toh 5ns
CE
ADDRESS
DATA
VIL
VIL
VIH
OE
WE t
acc
t
oh
t
oh
t
acc
ADDRESS STABLE ADDRESS STABLE
DATA
DATA
Figure 7. 18 Ti mi ng Waveforms for
&(
&(
/
2(
2(
Enable State Read
CE
ADDRESS
DATA
VIH
OE
WE
t
ce
t
acc
t
oe
t
oh
t
oh
t
df
t
ce
t
acc
t
oe
ADDRESS STABLE ADDRESS STABLE
DATA DATA
t
df
Figure 7. 19 Ti mi ng Waveforms for
&(
&(
/
2(
2(
Clocke d Re a d
Rev. 2.0, 11/ 00, page 160 of 1037
7.8.5 Auto-Program Mode
(a) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried
out by exec ut ing 128 c onsec uti ve byte t ransfers.
(b) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
(c) T he lower 8 bi t s of the t ra nsfer addre ss must be H'00 or H'80. If a va lue ot her t ha n an
effective address is input, processing will switch to a memory write operation but a write
error will be flagged.
(d) Memory address transfer is performed in the second cycle (figure 7. 20). Do not perform
transfer after the second cycle.
(e) Do not perform a command write during a programming operation.
(f) Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
(g) Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode
can also be used for this purpose (FO7 status polling uses the auto-program operation end
identification pin).
(h) The status polling FO6 and FO7 pin information is retained until the next command write.
Until the next command write is performed, reading is possible by enabling
&(
and
2(
.
Rev. 2.0, 11/ 00, page 161 of 1037
Table 7.15 AC Characteristics in Auto-Program
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
Status polling start t ime twsts 1ms
Status polling access time tspa 150 ns
Address setup t ime tas 0ns
Address hold time tah 60 ns
Memory write time twrite 1 3000 ms
:(
rise time tr30 ns
:(
fall time tf30 ns
Write set up time tpns 100 ns
Write end set up time tpnh 100 ns
CE
FWE
ADDRESS
FO7
OE
WE
t
nxtc
t
wsts
t
spa
t
nxtc
t
ces
t
ds
t
dh
t
wep
t
as
t
pnh
t
pns
t
ah
t
ceh
ADDRESS STABLE
Data transfer
1 byte to 128 bytes
FO6
Programming wait
DATA
DATA H'40 DATA
FO0 to 5 = 0
t
f
t
r
t
write
(1 to 3,000 ms)
Programming operation
end identification signal
Programming normal end
identification signal
Figure 7. 20 Auto-Progr am M ode Timi ng Wavefor ms
Rev. 2.0, 11/ 00, page 162 of 1037
7.8.6 Auto-Erase Mode
(a) Auto-erase mode supports only entire memory erasing.
(b) Do not perform a command write during auto-erasing.
(c) Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can
also be used for this purpose (FO7 status polling uses the auto-erase operation end
identification pin).
(d) The status polling FO6 and FO7 pin information is retained until the next command write.
Until the next command write is performed, reading is possible by enabling
&(
and
2(
.
Table 7.16 AC Characteristics in Auto-Erase Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
Status polling start t ime tests 1ms
Status polling access time tspa 150 ns
Memory erase time terase 100 40000 ms
:(
rise time tr30 ns
:(
fall time tf30 ns
Erase setup t ime t ens 100 ns
Erase end setup t ime t enh 100 ns
Rev. 2.0, 11/ 00, page 163 of 1037
CE
FWE
ADDRESS
FO5 to FO0
FO6
FO7
OE
WE t
erase
(100 to 40000ms)
t
ests
t
spa
t
nxtc
t
nxtc
t
ces
t
ceh
t
dh
CL
in
DL
in
t
ds
t
wep
t
ens
FO0 to 5 = 0
H'20 H'20
t
enh
Erase end
identification signal
Erase normal end
identification signal
t
f
t
r
Figure 7. 21 Auto-Erase Mode Ti mi ng Waveforms
7.8.7 Status Read Mode
(1) Status read mode is used to identify what type of abnormal end has occurred. Use this mode
when an abnormal end occurs in auto-program mode or auto-erase mode.
(2) The return code is retained until a command write for other than status read mode is
performed.
Table 7.17 AC Characteristics in Status Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
2(
output delay time toe 150 ns
Disable delay t im e tdf 100 ns
&(
output delay time tce 150 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
Rev. 2.0, 11/ 00, page 164 of 1037
CE
ADDRESS
DATA
OE
WE t
ces
t
nxtc
t
nxtc
t
df
Note: FO2 and FO3 are undefined.
t
ces
t
dh
t
ceh
t
ds
t
wep
t
wep
DATA
t
dh
t
ceh
t
ds
t
oe
t
ce
t
nxtc
H'71 H'71
t
f
t
r
t
f
t
r
Figure 7. 22 Status Read Mode Timing Waveforms
Table 7.18 Status Read Mode Return Commands
Pin Name FO7 FO6 FO5 FO4 FO3 FO2 FO1 FO0
Attribute Normal
end
identifica-
tion
Command
error Program-
ming error Erase
error Program-
ming or
erase
count
exceeded
Effective
address
error
Initial
value 00000000
Indica-
tions Normal
end: 0
Abnormal
end: 1
Command
error: 1
Otherwise:
0
Program-
min g error:
1
Otherwise:
0
Erase
error: 1
Otherwise:
0
Count
exceeded:
1
Otherwise:
0
Effective
address
error: 1
Otherwise:
0
Note: FO2 and FO3 are undef ined.
Rev. 2.0, 11/ 00, page 165 of 1037
7.8.8 Status Polling
(1) The FO7 status polling flag indicates the operating status in auto-program or auto-erase
mode.
(2) The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-
erase mode.
Table 7.19 Status Polling Output Truth Table
Pin Names Internal Operati on
in Pr ogr ess Abnormal End Normal End
FO7 0 1 0 1
FO6 0 0 1 1
FO0 t o FO5 0 0 0 0
Rev. 2.0, 11/ 00, page 166 of 1037
7.8.9 Programme r Mode Tr ansition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer
mode setup period. After the programmer mode setup time, a transition is made to memory read
mode.
Table 7.20 Command Wait State Transition Time Specifications
Item Symbol Min Max Unit
Standby release
(o s c illation s tabiliz a tion tim e) tosc1 10 ms
Program m er m ode set up time tbmv 10 ms
VCC hold time tdwn 0ms
VCC
RES
FWE
Memory read
mode
Command wait
state
Command
wait state
Normal/abnormal
end identifica-
tion
Auto-program mode
Auto-erase mode
tosc1 tbmv tdwn
Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low.
Don't care
Don't care
Figure 7.23 Oscillation Stabilization Time,
Boot Progr am Tr ansfe r Ti me , and Po we r Suppl y F al l Se que nc e
7.8.10 Notes On Memory Programmi ng
(1) When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
(2) When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. T he flash memory is initially in the erased state when the device is shipped by
Hitachi. For other chips for which the erasure history is unknown, it is recommended
that auto-erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Rev. 2.0, 11/ 00, page 167 of 1037
7.9 Flash Mem ory P rogram m i ng and Erasin g P recau t io ns
Precautions concerning the use of on-board programming mode and programmer mode are
summarized below.
(1) Use the Specified Voltages and Timing for Programming and Erasing
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip flash
memory.
Do not select the HN28F101 setting for the PROM programmer, and only use the specified
socket adapter. Incorrect use will result in damaging the device.
(2) Powering On and Off
Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin
low before turni ng off VCC.
When applying or disconnecting VCC, fix the FWE pin low and place the flash memory in the
hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a
power failure a nd subsequent re c overy.
(3) FWE Application/Disconnection
FWE application should be carried out when MCU operation is in a stable condition. If
MCU operation is not stable, fix the FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to
prevent unintentional programming or erasing of flash memory:
(a) Apply FWE when the VCC voltage has stabilized within its rated voltage range.
(b) In boot mode, apply and disconnect FWE during a reset.
(c) In user program mode, FWE can be switched between high and low level regardless of
the reset state. FWE input can also be switched during program execution in flash
memory.
(d) Do not apply FWE i f progra m runa way ha s occurre d.
(e) Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, a nd E bi t s i n FL MCR1 a n d
FLMCR2 are cleared.
Make sur e t h a t th e SWE, E SU, PSU, E V, PV, P, and E bi t s are n o t se t by mista ke whe n
applying or disconnecting FWE.
(4) Do Not Apply a Constant High Le ve l t o t he FWE Pin
Apply a high level to the FWE pin only when programming or erasing flash memory. A
system configuration in which a high level is constantly applied to the FWE should be
avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be
activated to prevent overprogramming or overerasing due to program runaway, etc.
Rev. 2.0, 11/ 00, page 168 of 1037
(5) Use the Recommended Algorithm when Programming and Erasing Flash Memory
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting
the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution
against program runaway, etc.
(6) Do Not Set or Clear the SWE Bit During Program Execution in Flash Memory
Clear the SWE bit before executing a program or reading data in flash memory.
When the SWE bit is set, data in flash memory can be rewritten, but flash memory should
only be accessed for verify operations (verification during programming/erasing).
(7) Do Not Use Interrupts while Flash Memory is Being Programmed or Erased
All interrupt requests, including NMI, should be disabled during FWE application to give
priority to program/erase operations.
(8) Do Not Perform Additional Programming. Erase the Memory before Reprogramming.
In on-board programming, perform only one programming operation on a 32-byte
programming unit block. In programmer mode, too, perform only one programming
operation on a 128-byte programming unit block. Programming should be carried out with
the entire programming unit block erased.
(9) Before Programming, Check that the Chip is Correctly Mounted in the PROM Programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer
socket, socket adapter, and chip are not correctly aligned.
(10)Do Not Touch the Socket Adapter or Chip During Programming.
Touching either of these can cause contact faults and write errors.
Rev. 2.0, 11/ 00, page 169 of 1037
7.10 Note on Swit ch in g f rom F - ZTAT Versi on t o Mask ROM Versi on
The mask ROM version does not have the internal registers for flash memory control that are
provided in t he F-ZTAT ve rsion. T abl e 7. 21 li sts the regi ste rs that a re pre sent in t he F-ZTAT
version but not in the mask ROM version. If a register listed in table 7.21 is read in the mask
ROM version, an undefined value will be returned. Therefore, if application software developed
on the F-ZTAT version is switched to a mask ROM version product, it must be modified to
ensure that the registers in table 7.21 have no effect.
Table 7.21 Registers Present in F-ZTAT Version but Abse nt i n M a sk RO M Ve r si o n
Register Abbreviation Address
Flash memory control regist er 1 FLMCR1 H'FFF8
Flash memory control regist er 2 FLMCR2 H'FFF9
Erase block r egis t er 1 EBR1 H'FFFA
Erase block r egis t er 2 EBR2 H'FFFB
Rev. 2.0, 11/ 00, page 170 of 1037
Rev. 2.0, 11/ 00, page 171 of 1037
Section 8 ROM (H8S/2194C Series)
8.1 Overview
The H8S/ 2194C has 256 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2194B
has 192 kbytes, the H8S/2194A has 160 kbytes. The ROM is connected to the CPU by a 16-bit
data bus. The CPU accesses both byte and word data in one state, enabling faster instruction
fetches and higher processing speed.
The flash memory versions of the H8S/2194C can be erased and programmed on-board as well
as with a general-purpose PROM programmer.
8.1.1 Bloc k Diagram
Figure 8.1 shows a block di agra m of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'03FFFE
H'000001
H'000003
H'03FFFF
Figure 8. 1 ROM Bl ock Diagram (H 8S/2194C)
Rev. 2.0, 11/ 00, page 172 of 1037
8.2 Overview of F l ash Memory
8.2.1 Features
The features of the flash memory are summarized below.
• Four flash memory operating modes
— Program mode
— Erase mode
— Program-verify m ode
— Erase-veri fy m ode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase
(in single-block units). When erasing all blocks, the individual blocks must be erased
sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28-
kbyte, and 32-kbyt e bloc ks.
• Programming/erase times
The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming,
equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
— Boot mode
— User program mode
• Automatic bit rate adjustment
If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and
MCU's bit rates.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
Rev. 2.0, 11/ 00, page 173 of 1037
8.2.2 Block Diagram
Module bus
Bus interface/controller
Flash memory
(256 kbytes)
Operat-
ing
mode
FLMCR1 *
*
*
*
STCR
FLMCR1
FLMCR2
EBR1
EBR2
: Serial timer control register
: Flash memory control register 1
: Flash memory control register 2
: Erase block register 1
: Erase block register 2
[Legend]
Internal address bus
Internal data bus (16 bits)
STCR
FWE pin
Mode pin
FLMCR2
EBR1
EBR2
Note: * These registers are exclusively used for the flash memory.
If you try to read these addresses with the mask ROM
version, values read becomes uncertain. Data write is
also disabled with the above version.
Figure 8. 2 Bl oc k Diagram of Fl ash Memor y
Rev. 2.0, 11/ 00, page 174 of 1037
8.2.3 Flash Memory O per ating Modes
(1) Mode Transiti ons
When each mode pin and the FWE pin are set in the reset state and a reset-start is executed,
the MCU enters one of t he opera t ing m ode s shown in figure 8. 3. In user mode , fl ash
memory can be read but not programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and
programmer mode.
Boot mode
On-board program mode
User
program
mode
User mode
Reset state
Programmer
mode
FWE = 1, MD0 = 0,
P12 = P13 = P14 = 1
RES = 0
RES = 0
FWE = 1
SWE = 1
FWE = 0
or
SWE = 0
RES = 0
MD0 = 1, FWE = 0
RES = 0
Only make a transition between user mode
and user program mode when the CPU is not
accessing the flash memory.
*1: MD0 = 0, P12 = P13 = 1, P14 = 0
Note:
*1
Figure 8. 3 F l ash Memory M ode Tr ansitions
Rev. 2.0, 11/ 00, page 175 of 1037
(2) On-Board Programming Modes
(a) Boot m ode
Flash memory RAM
Host
Programming control
program
SCI
Application program
(old version)
New application
program
New application
program
Flash memory
This LSI
This LSI
This LSI
This LSI
RAM
Host
SCI
Application program
(old version)
Boot program area
Programming control
program
New application
program
Flash memory RAM
Host
SCI
Flash memory
preprograming
erase
Boot program
Flash memory
Program execution state
RAM
Host
SCI
New application
program
Boot program
Programming control
program
"#
!"
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
the LSI (originally incorporated in the chip) is
started and the programing control program in
the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Boot programBoot program
Boot program area Boot program
area
Programming
control program
Figure 8. 4 Boot M ode
Rev. 2.0, 11/ 00, page 176 of 1037
(b) User program mode
<Flash memory>
<This LSI>
<RAM>
<Host>
Programming/erase control program
SCI
Boot program
New application
program
<This LSI>
<RAM>
<Host>
SCI
<Flash memory>
<This LSI>
<RAM>
<Host>
SCI
Flash memory erase
Boot program
New application
program
<This LSI>
Program execution state
<RAM>
<Host>
SCI
Programming/erase
control program
1. Initial state 2. Programming/erase control program transfer
3. Flash memory initialization 4. Writing new application program
FWE assessment program
Transfer program
Application
program
(old version)
,
FWE assessment program
Transfer program
Programming/erase control program Programming/erase control program
<Flash memory>
New application
program
Boot program
FWE assessment program
Transfer program
(1) The FWE assessment program that confirms that
the FWE pin has been driven high, and (2) the
program that will transfer the programming/erase
control program from the flash memory to on-chip RAM
should be written into the flash memory by the user
beforehand. (3) The programming/erase control
program should be prepared in the host or in the flash
memory.
When user program mode is entered, user software
confirms this fact, executes the transfer program in the
flash memory, and transfers the programming/erase
control program to RAM.
The programming/erase control program in RAM is
executed, and the flash memory is initialized (to H'FF).
Erasing can be performed in block units, but not in byte
units.
Next, the new application program in the host is written
into the erased flash memory blocks. Do not write to
unerased blocks.
New application
program
<Flash memory>
Boot program
FWE assessment program
Transfer program
Application
program
(old version)
Figure 8. 5 User P r ogram M ode (Example )
Rev. 2.0, 11/ 00, page 177 of 1037
(3) Difference s bet ween Boot Mode a nd User Program Mode
Table 8.1 Differences between Boot Mode and User Program Mode
Boot M ode User Progr am Mode
Entire memory erase Yes Yes
Block erase No Yes
Program m ing contr ol pr ogr am*Program/program-verify Erase/erase-verify
Program/program-verify
Note: *To be provided by the user , in accor dance with t he r ecom m ended algorit hm .
(4) Block Configuration
The fla sh me mory i s divi ded i nt o six 32-kbyte bl ocks, two 8-kbyte bl ocks, one 16-kbyt e
block, one 28-kbyt e bloc k, a nd four 1-kbyte bl ocks.
8 kbytes
Address H'000000
Address H'03FFFF
256 kbytes
32 kbytes
32 kbytes
32 kbytes
32 kbytes
32 kbytes
256-kbyte version
32 kbytes
28 kbytes
1 kbyte
1 kbyte
1 kbyte
1 kbyte
16 kbytes
8 kbytes
Figure 8. 6 F l ash Memory Bl oc k Configuration
Rev. 2.0, 11/ 00, page 178 of 1037
8.2.4 Pin Configuration
The flash memory is controlled by means of the pins shown in table 8. 2.
Table 8.2 Flash Memory Pins
Pin Nam e Abbr evi ation I/O Funct ion
Reset
5(6
Input Reset
Flash write enable FWE Input Flash program/ er ase pr ot ect ion by har dware
Mode 0 MD0 Input Sets t his LSI oper ating mode
Port 12 P12 Input Sets this LSI operat ing m ode when MD0 = 0
Port 13 P13 Input Sets this LSI operat ing m ode when MD0 = 0
Port 14 P14 Input Sets this LSI operat ing m ode when MD0 = 0
Transmit dat a SO1 Out put Serial transmit dat a out put
Receive data SI1 I nput Serial receive data input
8.2.5 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 8.3.
In order to access these registers, the FLSHE bit in STCR must be set to 1.
Table 8.3 Flash Memory Regi sters
Register Name Abbreviation R/W Initial Value Address*5
Flash memor y cont r ol r egister 1 FLMCR1*4R/W*1H'00*2H'FFF8
Flash memor y cont r ol r egister 2 FLMCR2*4R/W*1H'00*3H'FFF9
Erase block register 1 EBR1*4R/W*1H'00*3H'FFFA
Erase block register 2 EBR2*4R/W*1H'00*3H'FFFB
Serial timer cont r ol r egister STCR R/W H'00 H'FFEE
Notes: 1. When the FWE bit in FLMCR1 is not set at 1, wr ites ar e disabled.
2. When a high level is input to the FWE pin, the initial value is H'80.
3. When a low level is input t o t he FW E pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, t hese r egist er s ar e initialized to H'00.
4. FLMCR1, FLMCR2, EBR1, and EBR2 ar e 8- bit r egist er s. Only byte accesses are
valid for these r egister s, the access requiring 2 stat es.
5. Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 179 of 1037
8.3 Fla sh Mem ory Regist er Descri p t io n s
8.3.1 Fl ash Memory Control Regi ster 1 (FLM CR1)
7
FWE
—*
R
6
SWE
0
R/W
5
ESU1
0
R/W
4
PSU1
0
R/W
3
EV1
0
R/W
0
P1
0
R/W
2
PV1
0
R/W
1
E1
0
R/W
Bit
Initial value
R/W
:
:
:
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify
mode or e ra se-ve ri fy m ode for addre sse s H' 00000 t o H' 1FFFF i s ent e re d by setting SWE to 1
while FWE is 1 and then setting the EV1 bit or PV1 bit. Program mode for addresses H'00000
to H'1FFFF i s ent e r e d b y setting SWE to 1 while FWE is 1, then setting the PSU1 bi t , an d finally
setting the P1 bit. Erase mode for addresses H'00000 to H'1FFFF is en t ere d by setting SWE to 1
while FWE is 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized
by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and
sleep mode), or when a low level is input to the FWE pin. When a high level is input to the
FWE pin, its initial value is H'80 and when a low level is input, its initial value is H'00.
Writes to the SWE, ESU1, PSU1, EV1, a nd PV1 bi t s in FL MCR1 ar e e na bl e d onl y whe n FW E =
1 and SWE = 1; writes to the E1 bit only when FWE = 1, SWE = 1, and ESU1 = 1; and writes to
the P1 b i t o n l y when FW E = 1, SWE = 1, and PSU1 = 1 .
Bit 7: Flash Write Enable (F WE)
Sets hardware protection against flash memory programming/erasing.
Bit 7
FWE Description
0 When a low level is input t o the FWE pin (hardware- pr otected st at e)
1 When a high level is input to the FWE pin
Rev. 2.0, 11/ 00, page 180 of 1037
Bit 6: Software Write Enable (SWE)
Enables or disables flash memory programming. SWE should be set before setting bits 5 to 0,
bits 5 to 0 in FLMCR2, bit s 5 to 0 i n EBR1 a nd bi ts 7 to 0 i n E BR2.
Bit 6
SWE Description
0 Writes ar e disabled (Init ial value)
1 Writ es ar e enabled
[Sett ing condition] Sett ing is available when FWE = 1 is select ed
Bit 5: Erase-Setup Bit 1 (ESU1)
Prepa re s era se -m ode t ra nsi t i on for a ddre sse s H' 00000 t o H' 1FFFF. Se t E SU1 t o 1 be fore setting
the E 1 b i t to 1 . Do n ot set th e SWE , PSU1 , EV1 , PV1, E1, o r P1 b i t a t t h e same time.
Bit 5
ESU1 Description
0 Erase-set up cleared (I nitial value)
1 Erase-setup
[Sett ing condition] When FW E = 1 and SWE = 1
Bit 4: Progr am-Setup Bit 1 (PSU1)
Prepa re s era se -m ode t ra nsi t i on for a ddre sse s H' 00000 t o H' 1FFFF. Se t PSU1 t o 1 be fore setting
the P1 bit to 1. Do not set the SWE, ESU1, EV1, PV1, E1, or P1 bit at the same time.
Bit 4
PSU1 Description
0 Program - s et up cleared (I nitial value)
1 Program-setup
[Sett ing condition] When FW E = 1 and SWE = 1
Bit 3: Erase-Veri fy (EV1)
Selects erase-verify mode transition or clearing. Do not set the SWE, ESU1, PSU1, PV1, E 1 , o r
P1 bit at the same time.
Bit 3
EV1 Description
0 Erase-ver ify m ode clear ed (Init ial value)
1 Transition to er ase- ver ify m ode
[Sett ing condition] Sett ing is available when FWE = 1 and SWE = 1 are selected
Rev. 2.0, 11/ 00, page 181 of 1037
Bit 2: Program-Verify (PV1)
Selects program-verify mode transition or clearing. Do not set the SWE, ESU1, PSU1 , EV1 , E1 ,
or P1 bit at the same time.
Bit 2
PV1 Description
0 Program - ver ify m ode clear ed (Init ial value)
1 Transition t o pr ogr am - ver ify m ode
[Sett ing condition] Sett ing is available when FWE = 1 and SWE = 1 are selected
Bit 1: Erase (E1)
Selects erase mode transition or clearing. Do not set the SWE, ESU1, PSU1, E V1 , PV1 , or P1
bit at the same time.
Bit 1
E1 Description
0 Erase mode cleared (Init ial value)
1 Transition t o er ase m ode
[Sett ing condition] Sett ing is available when FWE = 1, SWE = 1, and ESU = 1 are
selected
Bit 0: Progr am (P 1)
Selects program mode transition or clearing. Do not set the SWE, PSU1, ESU1, EV1, PV1, o r
E1 bit at the same time.
Bit 0
P1 Description
0 Program m ode clear ed (Init ial value)
1 Transition t o pr ogr am m ode
[Sett ing condition] Setting is available when FWE = 1, SWE = 1, and PSU = 1 are
selected
Rev. 2.0, 11/ 00, page 182 of 1037
8.3.2 Flash Memory Control Regi ster 2 (FLM CR2)
7
FLER
0
R
6
—
0
—
5
ESU2
0
R/W
4
PSU2
0
R/W
3
EV2
0
R/W
0
P2
0
R/W
2
PV2
0
R/W
1
E2
0
R/W
Bit
Initial value
R/W
:
:
:
FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify
mode or e ra se-ve ri fy m ode for addre sse s H' 20000 t o H' 3FFFF i s ent e re d by setting SWE in
FLMCR1 to 1 while FWE in FLMCR1 is 1 and then setting the EV2 bit or PV2 bit. Program
mode for a ddre sse s H' 20000 t o H' 3FFFF i s e nt e re d by setting SWE in FLMCR1 to 1 while FWE
in FLMCR1 is 1, then setting the PSU2 bit, a n d f i n ally setting the P2 bit. Erase mode for
addresse s H'20000 to H'3FFFF is e nt e re d by setting SWE in FLMCR1 to 1 while FWE in
FLMCR1 is 1, then setting the ESU2 bit, and finally setting the E2 bit. FLMCR2 is initialized to
H'00 by a reset, in power-down state (excluding the medium-speed mode, module stop mode,
and sleep mode), when a low level is input to the FWE pin, or when a high level is input to the
FWE pin and the SWE bit in FLMCR1 is not set. However, FLER is initialized only by a reset.
Writes to the ESU2, PSU2, E V2, a nd PV2 bi t s i n FL MCR2 a re e na bl e d onl y whe n FW E i n
FLMCR1 = 1 and SWE in FLMCR1 = 1; writes to the E2 bit only when FWE in FLMCR1 = 1,
SWE in FLMCR1 = 1, and ESU2 = 1; and writes to the P2 bit only when FWE in FLMCR1 = 1,
SWE i n FL MCR1 = 1, a nd PSU2 = 1.
Bit 7: Flash Memor y Er ror (F LER)
Indicates that an error has occurred during an operation on flash memory (programming or
erasing). When FLER is set to 1, flash memory goes to the error-protection state.
Bit 7
FLER Description
0 Flash memor y is oper at ing normally
Flash memor y pr ogr am / er ase protect ion (er ror pr ot ect ion) is disabled
[Clearing condition] Reset or har dware standby mode (Initial value)
1 An error has occur red during flash memory pr ogr am m ing/ er asing
Flash memor y pr ogr am / er ase protect ion (er ror pr ot ect ion) is enabled
[Sett ing condition] See section 8. 8. 3, Er r or Pr ot ect ion
Bits 6: Reserved
This bit c a nnot be m odifi e d and i s al ways read a s 0.
Rev. 2.0, 11/ 00, page 183 of 1037
Bit 5: Erase-Setup Bit 2 (ESU2)
Prepa re s era se -m ode t ra nsi t i on for a ddre sse s H' 20000 t o H' 3FFFF. Se t E SU2 t o 1 be fore setting
the E 2 b i t to 1 . Do n ot set th e PSU2 , E V2, PV2, E2 , or P2 b i t at t h e same time.
Bit 5
ESU2 Description
0 Erase-set up cleared (I nitial value)
1 Erase-setup
[Sett ing condition] When FW E = 1 and SWE = 1
Bit 4: Progr am-Setup Bit 2 (PSU2)
Prepa re s era se -m ode t ra nsi t i on for a ddre sse s H' 20000 t o H' 3FFFF. Se t PSU2 t o 1 be fore setting
the P2 bit to 1. Do not set the ESU2, EV2, PV2, E2, or P2 bit at the same time.
Bit 4
PSU2 Description
0 Program - s et up cleared (I nitial value)
1 Program-setup
[Sett ing condition] When FW E = 1 and SWE = 1
Bit 3: Erase-Veri fy 2 (EV2)
Selects erase-verify mode transition or clearing for addresses H'20000 to H'3FFFF. Do n ot set
the E SU2, PSU2, PV2, E2, o r P2 b i t a t t h e same time.
Bit 3
EV2 Description
0 Erase-ver ify m ode clear ed (Init ial value)
1 Transition to er ase- ver ify m ode
[Sett ing condition] When FW E = 1 and SWE = 1
Bit 2: Program-Verify 2 (PV2)
Selects program-verify mode transition or clearing for addresses H' 20000 to H'3FFFF. Do n ot
set t h e ESU2, PSU2, EV2, E2, o r P2 b i t a t t h e same time.
Bit 2
PV2 Description
0 Program - ver ify m ode clear ed (Init ial value)
1 Transition t o pr ogr am - ver ify m ode
[Sett ing condition] When FW E = 1 and SWE = 1
Rev. 2.0, 11/ 00, page 184 of 1037
Bit 1: Erase 2 (E2)
Selects erase mode transition or clearing for addresses H'20000 to H'3FFFF. Do no t set the
ESU2, PSU2, E V2, PV2, or P2 b i t at t h e same time.
Bit 1
E2 Description
0 Erase mode cleared (Init ial value)
1 Transition t o er ase m ode
[Sett ing condition] When FW E = 1, SWE = 1, and ESU2 = 1
Bit 0: Progr am 2 (P 2)
Selects program-mode transition or clearing for addresses H' 20000 to H'3 FFFF. Do n o t se t th e
ESU2, PSU2, E V2, PV2, or E2 b i t at the same time.
Bit 0
P2 Description
0 Program - mode cleared (Init ial value)
1 Transition t o pr ogr am - m ode
[Sett ing condition] When FW E = 1, SWE = 1, and PSU2 = 1
Rev. 2.0, 11/ 00, page 185 of 1037
8.3.3 Erase Block Register s 1 (EBR1)
7
—
0
—
6
—
0
—
5
EB13
0
R/W
4
EB12
0
R/W
3
EB11
0
R/W
0
EB8
0
R/W
2
EB10
0
R/W
1
EB9
0
R/W
Bit
EBR1
Initial value
R/W
:
:
:
:
EBR1 is a register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module
stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is
input to t he FWE pi n a nd the SWE bit i n FLMCR1 is not set. W he n a bi t in E BR1 i s set, the
corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1
or EBR2 (more t ha n one bi t ca nnot be set ).
The flash memory block configuration is shown in table 8.3.
8.3.4 Erase Block Register s 2 (EBR2)
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit
EBR2
Initial value
R/W
:
:
:
:
EBR2 is a register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module
stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is
input to t he FWE pi n a nd the SWE bit i n FLMCR1 is not set. W he n a bi t in E BR2 i s set, the
corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1
or EBR2 (more t ha n one bi t ca nnot be set ).
The flash memory block configuration is shown in table 8.4.
Rev. 2.0, 11/ 00, page 186 of 1037
Table 8.4 Flash Memory Er ase Bloc ks
Block (Si ze)
128-kbyte Ver si ons Address
EB0 (1 kbyte) H'000000 t o H'0003FF
EB1 (1 kbyte) H'000400 t o H'0007FF
EB2 (1 kbyte) H'000800 t o H'000BFF
EB3 (1 kbyte) H'000C00 to H'000FFF
EB4 (28 kbytes) H'001000 to H'007FFF
EB5 (16 kbytes) H'008000 to H'00BFFF
EB6 (8 kbytes) H'00C000 to H'00DFFF
EB7 (8 kbyt es) H'00E000 to H'00FFFF
EB8 (32 kbytes) H'010000 to H'017FFF
EB9 (32 kbyt es) H'018000 to H'01FFFF
EB10 (32 kbytes) H'020000 t o H'027FFF
EB11 (32 kbyt es) H'028000 to H'02FFFF
EB12 (32 kbytes) H'030000 t o H'037FFF
EB13 (32 kbyt es) H'038000 to H'03FFFF
Rev. 2.0, 11/ 00, page 187 of 1037
8.3.5 Serial/Timer Control Register (STCR)
7
—
0
—
6
IICX
0
R/W
5
IICRST
0
R/W
4
—
0
—
3
FLSHE
0
R/W
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
R/W
:
:
:
STCR is an 8-bit readable/writable register that controls register access, the I2C bus inte rfac e
operating mode, and on-chip flash memory (in F-ZTAT versions), and also selects the I2C bus
interface serial clock frequency. For details on functions not related to on-chip flash memory,
see section 25.2.7, Serial/Timer Control Register (STCR), and desc riptions of individual
modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset.
Bits 6 to 5: I2C Contro l ( IICX, IICRST)
These bits control the operation of the I2C bus interface. For details, see section 25, I2C Bus
Interface.
Bit 3: Flash Memor y Control Regi ster Enable (F LSHE)
Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If
FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash
memory control register contents are retained.
Bit 3
FLSHE Description
0 Flash memory cont r ol r egister s deselected (Initial value)
1 Flash memory cont r ol r egister s selected
Bits 7, 4 and 2 to 0: Reserved
Rev. 2.0, 11/ 00, page 188 of 1037
8.4 On- Board Programm ing Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot
mode and user program mode. The pin settings for transition to each of these modes are shown
in tabl e 8. 5. For a dia gra m of t he tra nsit ions to t he vari ous fla sh mem ory m odes, see fi gure 8. 3.
Table 8.5 Setting On-Board Programmi ng Modes
Mode Pin
Mode Name FWE M D0 P12 P13 P14
Boot mode 1 0 1*21*21*2
User progr am m ode 1*11
Notes: 1. In user pr ogr am mode, t he FW E pin should not be constantly set t o 1. Set FWE t o 1
to make a transition t o user pr ogr am m ode bef ore perf or m ing a progr am/er ase/ ver if y
operation.
2. Can be used as I/O ports af ter boot m ode is initiated.
Rev. 2.0, 11/ 00, page 189 of 1037
8.4.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in
the host before ha nd. The c hanne l 1 SCI to be used i s set t o asynchronous mode .
When a re set -start i s exec ut ed a ft er t he MCU's pins have be en set t o boot m ode , the boot
program built into the MCU is started and the programming control program prepared in the host
is serially transmitted to the MCU via the SCI1. In the MCU, the programming control program
received via the SCI1 is written into the programming control program area in on-chip RAM.
After the transfer is completed, control branches to the start address of the programming control
program area and the programming control program execution state is entered (flash memory
programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 8.7, and the boot program mode
execut i on proce dure in fi gure 8. 8.
SI1
SO1 SCI1
This LSI
Flash memory
Write data reception
Verify data
transmission
Host
On-chip RAM
Figure 8. 7 System Configuration in Boot Mode
Rev. 2.0, 11/ 00, page 190 of 1037
Start
Set pins to boot mode and
execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
Host transmits programming
control program sequentially in
byte units
Transfer received programming
control program to on-chip RAM
This LSI calculates bit rate and
sets value in bit rate register
Host transmits number of
programming control program
bytes (N), upper byte followed by
lower byte
This LSI transmits received
programming control program to
host as verify data (echo-back)
n = 1
End of transmission
n = N?
n+1 n
Note :
Yes
No
This LSI measures low period of
H'00 data transmitted by host
After bit rate adjustment, transmits
one H'00 data byte to host to
indicate end of adjustment
Upon receiving H'55, this LSI
transmits one H'AA data byte to
host
Host confirms normal reception of
bit rate adjustment end indication
(H'00) and transmits one H'55
data byte
Execute programming control
program transferred to on-chip
RAM
This LSI transmits received
number of bytes to host as verify
data (echo-back)
If a memory cell does not operate normally and cannot be erased, one
H'FF byte is transmitted as an erase error, and the erase operation and
subsequent operations are halted.
After confirming that all flash
memory data has been erased,
this LSI transmits one H'AA data
byte to host
Check flash memory data, and if
data has already been written,
erase all blocks
Figure 8. 8 Boot M ode Exe cution Pr oc edure
Rev. 2.0, 11/ 00, page 191 of 1037
(1) Automatic SCI Bit Rate Adjustment
Start
bit Stop
bit
D0 D1 D2 D3 D4 D5 D6 D7
Low period (9 bits) measured (H'00 data) High period
(1 or more bits)
Fig ure 8.9 Automatic SCI Bi t Rate Adjustme nt
When boot mode is initiated, the MCU measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate
of the transmission from the host from the measured low period, and transmits one H'00 byte to
the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If
reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations. Depending on the host's transmission bit rate and the MCU's system clock
frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure
correct SCI operation, the host's transfer bit rate should be set to (2400, 4800, or 9600) bps.
Table 8.6 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU's bit rate is possible. The boot program should be executed within this
system clock range.
Table 8.6 System Clock Frequencies for which Automatic Adjustment of This LSI Bit
Rate i s Possi ble
Host Bit Ra t e System Clock Frequency f or w hi ch Aut omatic Adjust m ent
of Thi s LSI Bit Rate is Possi ble
9600 bps 8 MHz to 10 M Hz
4800 bps 4 MHz to 10 M Hz
Rev. 2.0, 11/ 00, page 192 of 1037
(2) On-Chip RAM Are a Divi sions in Boot Mode
In boot mode, t he RAM area i s divi ded i nt o; t he are a for use by the boot program a nd the
area to which programming control program is transferred by the SCI, as shown in figure
8.10. The boot program area cannot be used until a transition is made to the execution state
in boot mode for the programming control program transferred to RAM.
H'FFE7B0
H'FFF3AF
Programming
control program
area
(2944 bytes)
Reserved area
(128 bytes)
H'FFFFAF
H'FFFF2F
Boot program
area*
(3 kbytes)
Note: * The boot program area cannot be used until a transition is made to the execution
state for the programming control program transferred to RAM. Note that the boot
program reamins stored in this area after a branch is made to the programming
control program.
Figure 8. 10 RAM Areas in Boot Mode
Rev. 2.0, 11/ 00, page 193 of 1037
(3) Notes on Use of Boot Mode:
(a) When reset is released in boot mode, it measures the low period of the input at the SCI1's
SI1 pin. The reset should e nd with SI1 pin hi gh. Afte r the re set e nds, i t ta ke s about 100
states for the chip to get ready to measure the low period of the SI1 pin input.
(b) In boot mode, if any data has been programmed into the flash memory (if all data is not
1), all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
(c) Interrupts cannot be used while the flash memory is being programmed or erased.
(d) The SI1 and SO1 pins should be pulled up on the board.
(e) Before branching to the programming control program (RAM area H'FFF3B0), the chi p
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR
= 1).
The contents of the CPU's internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control
program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls,
etc., a stack area must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
(f) Boot mode can be entered by making the pin settings shown in table 8.6 and executing a
reset-start.
When the chip detects the boot mode setting at reset release*1, it retains that state
internally.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then
setting the FWE pin and mode pins, and executing reset release*1. Boot m ode ca n a lso be
cleared by a WDT overflow reset.
If the mode pin input levels are changed in boot mode, the boot mode state will be
maintained in the microcomputer, and boot mode continued, unless a reset occurs.
However, the FWE pin must not be driven low while the boot program is running or flash
memory is being programmed or erased*2.
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4
states) with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 8.9, Flash
Memory Programming and Erasing Precautions.
Rev. 2.0, 11/ 00, page 194 of 1037
8.4.2 User Program M ode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means of FWE control and supply of
programming data, and storing a program/erase control program in part of the program area as
necessary.
In this mode, the chip starts up in mode 1 and applies a high level to the FWE pin.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external m e mory.
Figure 8.11 shows the procedure for executing the program/erase control program when
transferred t o on-c hip RAM.
Clear FWE *
FWE = high *
Branch to flash memory
application program
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Transfer program/erase
control program to RAM
MD0 = 1
Reset start
Write the FWE assessment program and
transfer program (and the program/erase
control program if necessary) beforehand
Note: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only
when the flash memory is programmed or erased. Also, while a high level is applied to the
FWE pin, the watchdog timer should be activated to prevent overprogramming or
overerasing due to program runaway, etc.
* For further information on FWE application and disconnection, see section 8.9, Flash
Memory Programming and Erasing Precautions.
Figure 8.11 User Program Mode Execution Procedure (Preliminary)
Rev. 2.0, 11/ 00, page 195 of 1037
8.5 P rogram ming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, progra m -ve ri fy mode , a nd e ra se-ve ri fy m ode . For a ddre sses H' 00000 t o H' 1FFFF,
transitions to these modes can be made by setting the PSU1, ESU1 , P1, E1, PV1 a n d E V1 bits in
FLMCR1 and for a ddre sse s H'20000 to H'3FFFF, t r a nsitions to these modes can be made by
setting the PSU2, E SU2, P2, E 2 , PV2 a nd E V1 bi t s in FL MCR2.
The flash memory cannot be read while being programmed or erased. Therefore, the program
that controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU1, PSU1, EV1, PV1 ,
E1, a nd P1 bi t s in FL MCR1, and t he E SU2, PSU2, E V2, PV2, E 2 and P2 bi t s i n
FLMCR2, is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Perform programming in the erased state. Do not perform additional programming
on previously programmed addresses.
Do not program a ddre sse s H'00000 to H'1FFFF and H' 20000 t o H'3FFFF at t he sa m e
time. Operation is not guaranteed if both areas are programmed at the same time.
8.5.1 Program Mode (n = 1 for addresses H'0000 to H'1FFFF and n= 2 for addresses
H'20000 to H'3FFFF)
Follow the procedure shown in the program/program-verify flowchart in figure 8.12 to write
data or programs to flash memory. Performing program operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 32
bytes at a time.
Table 29.9 in section 29.2.7, Flash Memory Characteristics, lists wait time (x, y, z, α, β, γ, ε and
η) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and
FLMCR2) and the maximum write count (N).
Followi ng the elapse of (x) µs or more a fte r t he SWE bi t i s set t o 1 in fl a sh mem ory c ontrol
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram
data area, and the 32-byte data in the reprogram data area written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80,
H'A0, H' C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program
address and program data are latched in the flash memory. A 32-byte data transfer must be
performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the
extra a ddre sses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway,
etc. Set more than (y + z + α + β) µs as the WDT ove rfl ow period. Afte r t his, prepa ra ti on for
Rev. 2.0, 11/ 00, page 196 of 1037
program mode (program setup) is carried out by setting the PSUn bit in FL MCRn, and a ft e r t he
elapse of (y) µs or more, the operating mode is switched to program mode by setting the Pn bit
in FLMCRn. The time during which the Pn bit is set is the flash memory programming time.
Make a program setting so that the time for one programming operation is within the range of
(z) µs.
8.5.2 Program-Verify Mode (n =1 for addresses H'00000 to H'1FFFF and n = 2 for
addresses H'20000 to H'3FFFF)
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the Pn bit in
FLMCRn is cleared, then the PSUn bit i n FL MCRn i s cleared at least (α) µs later). The
watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched
to program-verify mode by setting the PVn bit in FLMCRn. Before reading in program-verify
mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy
write should be executed after the elapse of ( γ) µs or more. W he n the fl ash me m ory is rea d i n
this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least
(ε) µs after the dummy write before performing this read operation. Next, the originally written
data is compared with the verify data, and reprogram data is computed (see figure 8.12) and
transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-
verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1. If reprogramming is
necessary, set program mode again, and repeat the program/program-verify sequence as before.
However, ensure that the program/program-verify sequence is not repeated more than (N) times
on the same bits.
Rev. 2.0, 11/ 00, page 197 of 1037
START
End of
programming Programming
failure
Set SWE bit in FLMCR1
Wait (x) µs
Store 32-byte program data in program data area
and reprogram data area
n = 1
m = 0
Enable WDT
Set PSU bit in FLMCR1 or FLMCR2
Wait (y) µs
Set P bit in FLMCR1 or FLMCR2
Wait (z) µs
Start of programming
Clear P bit in FLMCR1 or FLMCR2
Wait ( ) µs
Wait ( ) µs
NO
NO
NO NO
YES
YES
YES
Wait ( ) µs
Wait ( ) µs
*
5
*
3
*
2
*
5
*
5
*
5
*
5
*
5
*
5
*
5
*
4
*
1
*
5
Wait ( ) µs
Clear PSU bit in FLMCR1 or FLMCR2
Disable WDT
Set PV bit in FLMCR1 or FLMCR2
H'FF dummy write to verify address
Read verify data
Reprogram data computation
*
4
Transfer reprogram data to reprogram data area
Clear PV bit in FLMCR1 or FLMCR2
Clear SWE bit in FLMCR1
m = 1
End of programming
Program data = verify data?
End of 32-byte
data verification?
m = 0?
Increment address
YES
Clear SWE bit in FLMCR1
n N?
n n+1
Notes:
Program data
0
0
1
1
Verify data
0
1
0
1
Reprogram data
1
0
1
1
Comments
Do not reprogram bits for which
programming has been completed.
Programming incomplete; reprogramming
should be performed.
—
Still in erased state; no action
1.
2.
3.
4.
5.
Write 32-byte data in RAM reprogram data
area consecutively to flash memory
Programming must be excuted in the erased state.
Do not perform additional programming on
addresses that have already been programmed.
RAM
Program data storage
area (32 bytes)
Reprogram data
storage area (32 bytes)
Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0,, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in
this case, H'FF data must be written to the extra addresses.
Verify data is read in 16-bit (word) units.
Even in case of the bit which is already-programmed in the 32-byte programming loop, perform additional
programming if the bit fails at the next verify.
An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents
of the latter are rewritten as programming progresses.
The values of x, y, z, , , , , and N are listed in section 29.2.7, Flash Memory Characteristics.
Figure 8.12 Program/Program-Verify Flowchart
Rev. 2.0, 11/ 00, page 198 of 1037
8.5.3 Erase Mode (n = 1 for addresses H'00000 to H'1FFFF and n = 2 for address
H'20000 to H'3FFFF)
Flash memory e ra sing should be pe rform ed bl oc k by bloc k fol lowing t he proce dure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 8.13.
Table 28.9 in section 28.2.7, Flash Memory Characteristics lists wait time (x, y, z, α, β, γ, ε and
η) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and
FLMCR2) and the maximum clearing count (N).
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased
in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in
flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent
overerasing in the event of program runaway, etc. Set more than (y + z + α + β) ms as the WDT
overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the
ESUn bit in FLMCRn, and after the elapse of (y) µs or more, the operating mode is switched to
erase mode by setting the En bit in FLMCR1. The time during which the En bit is set is the
flash memory erase time. Ensure that the erase time does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
to 0) is not nec e ssary before sta rt ing t he era se proc edure .
8.5.4 Erase-Verify Mode (n = 1 for addresses H'00000 to H'1FFFF and n = 2 for
address H'20000 to H'3FFFF)
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared, then
the ESU bit in FLMCR2 is cleared at least ( α) µs later), the watchdog timer is cleared after the
elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the
EVn bit in FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should
be made to the addresses to be read. The dummy write should be executed after the elapse of (γ)
µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the
data at the latched address is read. Wait at least (ε) µs after the dummy write before performing
this read operation. If the read data has been erased (all 1), a dummy write is performed to the
next address, and erase-verify is performed. If the read data has not been erased, set erase mode
again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the
erase/erase-verify sequence is not repeated more than (N) times. When verification is
completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been completed on
all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1
bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-
verify sequence in the same way.
Rev. 2.0, 11/ 00, page 199 of 1037
End of erasing
START
Set SWE bit in FLMCR1
Set ESU bit in FLMCR1 or FLMCR2
Set E bit in FLMCR1 or FLMCR2
Wait (x) µs
Wait (y) µs
n = 1
Set EBR1, EBR2
Enable WDT
*
2
*
4
*
2
Wait (z) ms
*
2
Wait ( ) µs
*
2
Wait ( ) µs
*
2
Wait ( ) µs
Set block start address to
verify address
*
2
Wait ( ) µs
*
2
Wait ( ) µs
*
2
*
2
*
2
*
3
*
5
Start of erase
Clear E bit in FLMCR1 or FLMCR2
Clear ESU bit in FLMCR1 or FLMCR2
Set EV bit in FLMCR1 or FLMCR2
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1 or FLMCR2
Wait ( ) µs
Clear EV bit in FLMCR1 or FLMCR2
Clear SWE bit in FLMCR1
Disable WDT
Halt erase
*
1
Verify data =
all 1?
End of erasing of
all erase blocks?
Erase failure
Clear SWE bit in FLMCR1
n N?
NO
NO
NO NO
YES
YES
YES
YES
Notes: 1.
2.
3.
4.
5.
Increment
address
n n+1
Last address
of block?
Preprogramming (setting erase block data to all 0) is not necessary.
The values of x, y, z, , , , , and N are listed in section 29.2.7, Flash Memory Characteristics.
Verify data is read in 16-bit (word) units.
Set only one bit in EBR1 or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 8. 13 Er ase/ Erase-Ver i fy Fl owchart (Single -Bloc k Erase)
Rev. 2.0, 11/ 00, page 200 of 1037
8.6 F lash Mem ory P rotect ion
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
8.6.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FLMCR2) and era se bloc k re giste rs 1 and 2 (E BR1, EBR2). (See t abl e 8. 7. )
Table 8.7 Hardware Protection
Functions
Item Description Program Erase
FWE pin
protection •When a low level is input t o the FWE pin, FLMCR1,
FLMCR2, EBR1, and EBR2 are initialized, and the
program / er ase- pr otected st at e is ent er ed
Yes Yes
Reset/standby
protection •In a reset (including a WDT overflow reset) and in
power-down stat e ( excluding the m edium - speed
mode, m odule st op m ode, and sleep m ode) ,
FLMCR1, FLMCR2 (excluding the FLER bit), EBR1,
and EBR2 are initialized, and t he pr ogram/ er ase-
protected stat e is ent er ed
•In a reset via t he
5(6
pin, the r eset st ate is not
entered unless t he
5(6
pin is h e ld low u n til osc illa tion
st a biliz e s a ft e r p o we r in g o n. I n the c a s e of a rese t
during operat ion, hold t he
5(6
pin low for the
5(6
pulse widt h specif ied in the AC character istics section
Yes Yes
Rev. 2.0, 11/ 00, page 201 of 1037
8.6.2 Software Protec ti on
Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block
registers 1 and 2 (EBR1, EBR2). When softwa re protection is in effect, setting the P1 or E1 bit
in flash memory control register 1 (FLMCR1), or setting the P2 or E2 bit in flash memory
control register 2 (FLMCR2) does not cause a transition to program mode or erase mode. (See
table 8.8.)
Table 8.8 Software Protec tion
Functions
Item Description Program Erase
SWE bit
protection •Clearing the SWE bit to 0 in FLMCR1 sets t he
program / er ase- pr otected st at e f or all blocks
(Execute in on-chip RAM or external memory)
Yes Yes
Block
specification
protection
•Erase prot ect ion can be set f or individual blocks by
settings in erase block register s 1 and 2 ( EBR1,
EBR2)
•Setting EBR1 and EBR2 to H'00 places all blocks in
the erase- pr ot ected stat e
−Yes
Rev. 2.0, 11/ 00, page 202 of 1037
8.6.3 Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, E1, P2 or E2
bit. However, PV1, EV1, PV2 or EV2 bit setting is enabled, and a transition can be made to
verify mode .
FLER bit setting conditions are as follows:
(1) When flash memory is read during programming/erasing (including a vector read or
instruction fetch)
(2) Immediately after exception handling (excluding a reset) during programming/erasing
(3) When a SLEEP instruction is executed during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 8.14 shows the flash memory state transition diagram.
: Memory read possible
: Verify-read possible
: Programming possible
: Erasing possible
RD
VF
PR
ER
: Memory read not possible
: Verify-read not possible
: Programming not possible
: Erasing not possible
RD
VF
PR
ER
RD VF PR ER FLER = 0
Error occurrence
Error occurrence
SLEEP instruction
execution
RES = 0
RES = 0
RES = 0
RD VF PR ER FLER = 0
Program mode
Erase mode Reset
(hardware protection)
RD VF PR ER FLER = 1 RD VF PR ER FLER = 1
Error protection mode Error protection mode
(Power-down state)*
1
Power-down state*
1
FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2
initialization state
FLMCR1, FLMCR2,
EBR1, EBR2 initialization
state
Power-down state*
1
release
*1: Watch mode, standby mode, and
subactive mode
Figure 8. 14 F l ash Memory State Tr ansitions
Rev. 2.0, 11/ 00, page 203 of 1037
8.7 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input is disabled when flash memory is being programmed or
erased (when the Pn or En bit is set in FLMCRn), and while the boot program is executing in
boot mode*1, to give priority to the program or erase operation. There are three reasons for this:
(1) Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
(2) In the interrupt exception handling sequence during programming or erasing, the vector
would not be read correctly*2, possibly re sulti ng i n MCU runaway.
(3) If interrupt oc curre d duri ng boot progra m exe c uti on, i t would not be possible t o e xec ut e t he
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests, including NMI input, must therefore
be disabled inside and outside the MCU during FWE application. Interrupt is also disabled in
the error-protection state while the Pn or En bit remains set in FLMCRn.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by
the write control program is complete.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the Pn or En bit
is set in FLMCRn), correct read data will not be obtained (undetermined values will
be returne d).
• If the interrupt entry in the interrupt vector table has not been programmed yet,
interrupt exception handling will not be executed correctly.
Rev. 2.0, 11/ 00, page 204 of 1037
8.8 F lash Mem ory P rogramm er Mode
8.8.1 Pr ogramme r Mode Setti ng
Programs and data can be written and erased in programmer mode as well as in the on-board
programming modes. In programmer mode, the on-chip ROM can be freely programmed using
a PROM programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip
flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read
mode are supported with these device types. In auto-program mode, auto-erase mode, and status
read mode, a status polling procedure is used, and in status read mode, detailed internal signals
are output after execution of an auto-program or auto-erase operation.
8.8.2 Socket Adapters and Memory Map
In programmer mode, a socket adapter is mounted on the writer programmer. The socket
adapte r produc t c ode s are l i sted i n t abl e 8. 9.
Figure 8.15 shows the memory map in programmer mode.
Tabl e 8 .9 Socke t Ada pter Pro duc t Co de s
Product Codes Package Socket Adapter Pr oduct Code
HD64F2194C 112-pin QFP ME2194ESHF1H
This LSI
H'000000
MCU mode Programmmer mode
H'03FFFF
H'00000
H'3FFFF
On-chip ROM area
(256 kbytes)
Figure 8.15 Memory Map in Programmer Mode
Rev. 2.0, 11/ 00, page 205 of 1037
8.8.3 Programme r Mode O per ation
Table 8.10 shows how the different operating modes are set when using programmer mode, and
table 8.11 lists the commands used in programmer mode. Details of each mode are given below.
(1) Memory Read Mode
Memory read m ode supports byte re a ds.
(2) Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
(3) Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is
used to confirm t he e nd of a uto-e ra sing.
(4) Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the FO6 signal. In status read mode, error information is output if an
error occurs.
Table 8.10 Settings for Each Operati ng Mode in Pr ogr ammer M ode
Pin Names
Mode FWE
&(
&( 2(
2( :(
:(
FO0 t o FO7 FA0 t o FA17
Read H or L L L H Data out put Ain
Out put disable H or L L H H Hi-z X
Command write H or L*3L H L Dat a input Ain*2
Chip disable*1H or L L X X Hi-z X
Notes: 1. Chip disable is not a standby st at e; int er nally, it is an operat ion st at e.
2. Ain indicates that t her e is also address input in auto- pr ogr am m ode.
3. For comm and writes when m aking a tr ansit ion to aut o- pr ogr am or auto-er ase m ode,
input a high level to the FWE pin.
Rev. 2.0, 11/ 00, page 206 of 1037
Table 8.11 Progr ammer M ode Commands
1st Cycle 2nd Cycle
Command Name Number of
Cycles Mode Address Data Mode Address Data
Memor y r ead m ode 1+n write X H'00 read RA Dout
Auto-pr ogr am m ode 129 write X H'40 wr ite WA Din
Auto-erase mode 2 write X H'20 write X H'20
Status r ead m ode 2 write X H'71 write X H'71
Notes: 1. In auto-pr ogram mode. 129 cycles are required f or com mand writing by a
simultaneous 128-byt e write.
2. In mem or y r ead m ode, the num ber of cycles depends on t he num ber of addr ess wr ite
cycles (n).
Rev. 2.0, 11/ 00, page 207 of 1037
8.8.4 Memory Read Mode
(1) After the end of an auto-program, auto-erase, or status read operation, the command wait
state is entered. To read memory contents, a transition must be made to memory read mode
by means of a command write before the read is executed.
(2) Command writes can be performed in memory read mode, just as in the command wait state.
(3) Once mem ory re ad m ode has bee n e nte re d, consec ut ive re ads ca n be perform e d.
(4) After power-on, memory read mode is entered.
Table 8.12 AC Characteristics in Memory Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
CE
ADDRESS
DATA H'00
OE
WE
Command write
t
wep
t
ceh
t
dh
t
ds
t
f
t
r
t
nxtc
Note: Data is latched on the rising edge of WE.
t
ces
Memory read mode
ADDRESS STABLE
DATA
Figure 8. 16 M e mory Read Mode Ti mi ng Waveforms after Command Write
Rev. 2.0, 11/ 00, page 208 of 1037
Table 8.13 AC Characteristics when Entering Another Mode from Memory Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
CE
ADDRESS
DATA H'XX
OE
WE
XX mode command write
t
wep
t
ceh
t
dh
t
ds
t
nxtc
Note: Do not enable WE and OE at the same time.
t
ces
ADDRESS STABLE
DATA
t
f
t
r
Figure 8.17 Timing Waveforms when Entering Another Mode from Memory Read Mode
Rev. 2.0, 11/ 00, page 209 of 1037
Table 8.14 AC Characteristics in Memory Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Access time tacc 20 µs
&(
output delay time tce 150 ns
2(
output delay time toe 150 ns
Out put disable delay time tdf 100 ns
Data output hold t ime toh 5ns
CE
ADDRESS
DATA
VIL
VIL
VIH
OE
WE t
acc
t
oh
t
oh
t
acc
ADDRESS STABLE ADDRESS STABLE
DATA
DATA
Figure 8. 18 Ti mi ng Waveforms for
&(
&(
/
2(
2(
Enable State Read
CE
ADDRESS
DATA
VIH
OE
WE
t
ce
t
acc
t
oe
t
oh
t
oh
t
df
t
ce
t
acc
t
oe
ADDRESS STABLE ADDRESS STABLE
DATA DATA
t
df
Figure 8. 19 Ti mi ng Waveforms for
&(
&(
/
2(
2(
Clocke d Re a d
Rev. 2.0, 11/ 00, page 210 of 1037
8.8.5 Auto-Program Mode
(a) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried
out by exec ut ing 128 c onsec uti ve byte t ransfers.
(b) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
(c) T he lower 8 bi t s of the t ra nsfer addre ss must be H'00 or H'80. If a va lue ot her t ha n an
effective address is input, processing will switch to a memory write operation but a write
error will be flagged.
(d) Memory address transfer is performed in the second cycle (figure 8. 20). Do not perform
transfer after the second cycle.
(e) Do not perform a command write during a programming operation.
(f) Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
(g) Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode
can also be used for this purpose (FO7 status polling uses the auto-program operation end
identification pin).
(h) The status polling FO6 and FO7 pin information is retained until the next command write.
Until the next command write is performed, reading is possible by enabling
&(
and
2(
.
Rev. 2.0, 11/ 00, page 211 of 1037
Table 8.15 AC Characteristics in Auto-Program
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
Status polling start t ime twsts 1ms
Status polling access time tspa 150 ns
Address setup t ime tas 0ns
Address hold time tah 60 ns
Memory write time twrite 1 3000 ms
:(
rise time tr30 ns
:(
fall time tf30 ns
Write set up time tpns 100 ns
Write end set up time tpnh 100 ns
CE
FWE
ADDRESS
FO7
OE
WE
t
nxtc
t
wsts
t
spa
t
nxtc
t
ces
t
ds
t
dh
t
wep
t
as
t
pnh
t
pns
t
ah
t
ceh
ADDRESS STABLE
Data transfer
1 byte to 128 bytes
FO6
Programming wait
DATA
DATA H'40 DATA
FO0 to 5 = 0
t
f
t
r
t
write
(1 to 3,000 ms)
Programming operation
end identification signal
Programming normal end
identification signal
Figure 8. 20 Auto-Progr am M ode Timi ng Wavefor ms
Rev. 2.0, 11/ 00, page 212 of 1037
8.8.6 Auto-Erase Mode
(a) Auto-erase mode supports only entire memory erasing.
(b) Do not perform a command write during auto-erasing.
(c) Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can
also be used for this purpose (FO7 status polling uses the auto-erase operation end
identification pin).
(d) The status polling FO6 and FO7 pin information is retained until the next command write.
Until the next command write is performed, reading is possible by enabling
&(
and
2(
.
Table 8.16 AC Characteristics in Auto-Erase Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
Status polling start t ime tests 1ms
Status polling access time tspa 150 ns
Memory erase time terase 100 40000 ms
:(
rise time tr30 ns
:(
fall time tf30 ns
Erase setup t ime t ens 100 ns
Erase end setup t ime t enh 100 ns
Rev. 2.0, 11/ 00, page 213 of 1037
CE
FWE
ADDRESS
FO5 to FO0
FO6
FO7
OE
WE t
erase
(100 to 40000ms)
t
ests
t
spa
t
nxtc
t
nxtc
t
ces
t
ceh
t
dh
CL
in
DL
in
t
ds
t
wep
t
ens
FO0 to 5 = 0
H'20 H'20
t
enh
Erase end
identification signal
Erase normal end
identification signal
t
f
t
r
Figure 8. 21 Auto-Erase Mode Ti mi ng Waveforms
8.8.7 Status Read Mode
(1) Status read mode is used to identify what type of abnormal end has occurred. Use this mode
when an abnormal end occurs in auto-program mode or auto-erase mode.
(2) The return code is retained until a command write for other than status read mode is
performed.
Table 8.17 AC Characteristics in Status Read Mode
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit
Command write cycle tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup time tces 0ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width t wep 70 ns
2(
output delay time toe 150 ns
Disable delay t im e tdf 100 ns
&(
output delay time tce 150 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
Rev. 2.0, 11/ 00, page 214 of 1037
CE
ADDRESS
DATA
OE
WE t
ces
t
nxtc
t
nxtc
t
df
Note: FO2 and FO3 are undefined.
t
ces
t
dh
t
ceh
t
ds
t
wep
t
wep
DATA
t
dh
t
ceh
t
ds
t
oe
t
ce
t
nxtc
H'71 H'71
t
f
t
r
t
f
t
r
Figure 8. 22 Status Read Mode Timing Waveforms
Table 8.18 Status Read Mode Return Commands
Pin Name FO7 FO6 FO5 FO4 FO3 FO2 FO1 FO0
Attribute Normal
end
identifica-
tion
Command
error Program-
ming error Erase
error Program-
ming or
erase
count
exceeded
Effective
address
error
Initial
value 00000000
Indica-
tions Normal
end: 0
Abnormal
end: 1
Command
error: 1
Otherwise:
0
Program-
min g error:
1
Otherwise:
0
Erase
error: 1
Otherwise:
0
Count
exceeded:
1
Otherwise:
0
Effective
address
error: 1
Otherwise:
0
Note: FO2 and FO3 are undef ined.
Rev. 2.0, 11/ 00, page 215 of 1037
8.8.8 Status Polling
(1) The FO7 status polling flag indicates the operating status in auto-program or auto-erase
mode.
(2) The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-
erase mode.
Table 8.19 Status Polling Output Truth Table
Pin Names Internal Operati on
in Pr ogr ess Abnormal End Normal End
FO7 0 1 0 1
FO6 0 0 1 1
FO0 t o FO5 0 0 0 0
Rev. 2.0, 11/ 00, page 216 of 1037
8.8.9 Programme r Mode Tr ansition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer
mode setup period. After the programmer mode setup time, a transition is made to memory read
mode.
Table 8.20 Command Wait State Transition Time Specifications
Item Symbol Min Max Unit
Standby release
(o s c illation s tabiliz a tion tim e) tosc1 10 ms
Program m er m ode set up time tbmv 10 ms
VCC hold time tdwn 0ms
VCC
RES
FWE
Memory read
mode
Command wait
state
Command
wait state
Normal/abnormal
end identifica-
tion
Auto-program mode
Auto-erase mode
tosc1 tbmv tdwn
Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low.
Don't care
Don't care
Figure 8.23 Oscillation Stabilization Time,
Boot Progr am Tr ansfe r Ti me , and Po we r Suppl y F al l Se que nc e
8.8.10 Notes On Memory Programmi ng
(1) When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
(2) When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. T he flash memory is initially in the erased state when the device is shipped by
Hitachi. For other chips for which the erasure history is unknown, it is recommended
that auto-erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Rev. 2.0, 11/ 00, page 217 of 1037
8.9 Flash Mem ory P rogram m i ng and Erasin g P recau t i on s
Precautions concerning the use of on-board programming mode and programmer mode are
summarized below.
(1) Use the Specified Voltages and Timing for Programming and Erasing
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports Hitachi microcomputer device type with 256-kbyte on-chip flash
memory.
Do not select the HN28F101 setting for the PROM programmer, and only use the specified
socket adapter. Incorrect use will result in damaging the device.
(2) Powering On and Off
Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin
low before turni ng off VCC.
When applying or disconnecting VCC, fix the FWE pin low and place the flash memory in the
hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a
power failure a nd subsequent re c overy.
(3) FWE Application/Disconnection
FWE application should be carried out when MCU operation is in a stable condition. If
MCU operation is not stable, fix the FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to
prevent unintentional programming or erasing of flash memory:
(a) Apply FWE when the VCC voltage has stabilized within its rated voltage range.
(b) In boot mode, apply and disconnect FWE during a reset.
(c) In user program mode, FWE can be switched between high and low level regardless of
the reset state. FWE input can also be switched during program execution in flash
memory.
(d) Do not apply FWE i f progra m runa way ha s occurre d.
(e) Disconnect FWE only when the SWE, ESU1, ESU2, PSU1 , PSU2 , EV1 , EV2 , PV1, PV2 ,
P1, P2, E1 and E2 bits in FLMCR1 and FLMCR2 are cleared.
Make sur e t h a t th e SWE, E SU1, E SU2 , PSU1 , PSU2, EV1, EV2, PV1 , PV2, P1, P2 , E1
and E2 bits are not set by mistake when applying or disconnecting FWE.
(4) Do Not Apply a Constant High Le ve l t o t he FWE Pin
Apply a high level to the FWE pin only when programming or erasing flash memory. A
system configuration in which a high level is constantly applied to the FWE should be
avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be
activated to prevent overprogramming or overerasing due to program runaway, etc.
Rev. 2.0, 11/ 00, page 218 of 1037
(5) Use the Recommended Algorithm when Programming and Erasing Flash Memory
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting
the Pn or En bit in FL MCR1 and FLMCR2, the watchdog timer should be set beforehand as a
precaution against program runaway, etc.
(6) Do Not Set or Clear the SWE Bit During Program Execution in Flash Memory
Clear the SWE bit before executing a program or reading data in flash memory.
When the SWE bit is set, data in flash memory can be rewritten, but flash memory should
only be accessed for verify operations (verification during programming/erasing).
(7) Do Not Use Interrupts while Flash Memory is Being Programmed or Erased
All interrupt requests, including NMI, should be disabled during FWE application to give
priority to program/erase operations.
(8) Do Not Perform Additional Programming. Erase the Memory before Reprogramming.
In on-board programming, perform only one programming operation on a 32-byte
programming unit block. In programmer mode, too, perform only one programming
operation on a 128-byte programming unit block. Programming should be carried out with
the entire programming unit block erased.
(9) Before Programming, Check that the Chip is Correctly Mounted in the PROM Programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer
socket, socket adapter, and chip are not correctly aligned.
(10)Do Not Touch the Socket Adapter or Chip During Programming.
Touching either of these can cause contact faults and write errors.
Rev. 2.0, 11/ 00, page 219 of 1037
8.10 Note on Swit ch in g f rom F - ZTAT Versi on t o Mask ROM Versi on
The mask ROM version does not have the internal registers for flash memory control that are
provided in t he F-ZTAT ve rsion. T abl e 8. 21 li sts the regi ste rs that a re pre sent in t he F-ZTAT
version but not in the mask ROM version. If a register listed in table 8.21 is read in the mask
ROM version, an undefined value will be returned. Therefore, if application software developed
on the F-ZTAT version is switched to a mask ROM version product, it must be modified to
ensure that the registers in table 8.21 have no effect.
Table 8.21 Registers Present in F-ZTAT Version but Abse nt i n M a sk RO M Ve r si o n
Register Abbreviation Address
Flash memory control regist er 1 FLMCR1 H'FFF8
Flash memory control regist er 2 FLMCR2 H'FFF9
Erase block r egis t er 1 EBR1 H'FFFA
Erase block r egis t er 2 EBR2 H'FFFB
Rev. 2.0, 11/ 00, page 220 of 1037
Rev. 2.0, 11/ 00, page 221 of 1037
Section 9 RAM
9.1 Overview
The H8S/2194C, H8S/2194B, a nd H8S/2194A have 6 kbyt es, and t he H8S/2194, H8S/2193,
H8S/ 2192 and H8S/2191 have 3 kbytes, of on-chip high-speed static RAM. The on-chip RAM
is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be
accessed in one state. This makes it possible to perform fast word data transfer.
9.1.1 Bloc k Diagram
Figure 9.1 shows a block di agra m of the on-c hip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFF3B0
H'FFF3B2
H'FFF3B4
H'FFFFAE
H'FFF3B1
H'FFF3B3
H'FFF3B5
H'FFFFAF
Figure 9. 1 Bl oc k Diagram of RAM (H8S/2194)
Rev. 2.0, 11/ 00, page 222 of 1037
Rev. 2.0, 11/ 00, page 223 of 1037
Section 10 Clock Pulse Generator
10.1 Overview
This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ), t he bus
master clock, and internal clocks.
The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
10.1.1 Block Diagram
Figure 10.1 shows a block di agra m of the c loc k pul se gene ra tor.
System
clock
oscillator
Duty
adjustment
circuit Clock
selection
circuit
Medium-
speed clock
divider
Subclock
oscillator Subclock
division
circuit
OSC1
OSC2
X1
X2
/16, /32, /64
w/2, w/4, w/8
SUB
or SUB
Timer A
count clock
Internal clock
To supporting modules
Bus master clock
To CPU
SUB ( w/2, w/4, w/8)
Figure 10. 1 Bl oc k Diagram of Clock Pulse G e nerator
10.1.2 Register Configuration
The clock pulse generator is controlled by SBYCR and LPWRCR. Table 10.1 shows the register
configuration.
Table 10.1 CPG Registers
Name Abbreviation R/W Initial Value Address*
Standby c ont rol regis t er SBYCR R/ W H'00 H'FFEA
Low-power contr ol
register LPWRCR R/W H'00 H'FFEB
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 224 of 1037
10.2 Register Descript ion s
10. 2 .1 Standby Contr o l Regi st e r ( SB YCR)
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
—
0
—
0
SCK0
0
R/W
2
—
0
—
1
SCK1
0
R/W
Bit
Initial value
R/W
:
:
:
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1,
Standby Register (SBYCR). SBYCR is initialized to H'00 by a reset.
Bits 1 and 0: System Clock Select 1 and 0 (SCK1, SCK0)
These bits select the bus master clock for high-speed mode and medium-speed mode.
Bit 1 Bit 0
SCK1 SCK0 Description
0 Bus m ast er is in high-speed mode ( I nitial value)0
1 M edium - speed clock is φ/16
0 M edium - speed clock is φ/321
1 M edium - speed clock is φ/64
Rev. 2.0, 11/ 00, page 225 of 1037
10. 2 .2 Low- P o we r Co nt r o l Re g i st e r (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
—
0
—
3
—
0
—
0
SA0
0
R/W
2
—
0
—
1
SA1
0
R/W
Bit
Initial value
R/W
:
:
:
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, Low-
Power Control Registe r (L PWRCR).
LPWRCR is initialized to H'00 by a reset.
Bit s 1 and 0 : Subacti v e Mode Cl o c k Select (SA1, SA0)
Selects CPU clock for subactive mode. In subactive mode, writes are disabled.
Bit 1 Bit 0
SA1 SA0 Description
0 CPU operating clock is φw/8 (Init ia l v a lu e)0
1 CPU operating clock is φw/4
1*CPU operating clock is φw/2
Note: *Don't care
Rev. 2.0, 11/ 00, page 226 of 1037
10.3 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
10.3.1 Connecti ng a Crystal Resonator
(1) Circuit Configuration
A crystal resonator can be connected as shown in the example in figure 10. 2. An AT-cut
parallel-resonance crystal should be used.
OSC1
OSC2 R
f
C
L2
C
L1
C
L1 =
C
L2
= 10 to 22pF
R
f =
1M ± 20%
Figure 10. 2 Connection of Crystal Resonator (Example)
(2) Crystal Resonator
Figure 10.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that
has the characteristics shown in table 10.2 and the same frequency as the system clock (φ).
OSC1
C
L
AT-cut parallel-resonance type
OSC2
C
0
LR
s
Figure 10.3 Crystal Resonator Equivalent Circuit
Table 10.2 Crystal Resonator Paramete rs
Frequency (MHz) 8 10
RSmax (Ω)8060
COmax (pF) 7 7
Rev. 2.0, 11/ 00, page 227 of 1037
(3) Note on Board Design
When a crystal resonator is connected, the following points should be noted.
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 10. 4.
When designing the board, place the crystal resonator and its load capacitors as close as
possible to the OSC1 and OSC2 pins.
C
L2
Signal A Signal B
C
L1
This chip
OSC1
OSC2
Avoid
R
f
Figure 10.4 Example of Incorrect Board Design
Rev. 2.0, 11/ 00, page 228 of 1037
10. 3 .2 Ext e r na l Cloc k Input
(1) Circuit Configuration
An external c loc k signa l c a n be i nput as shown in the e xa mpl e s in figure 10. 5. If t he OSC2
pin is left open, make sure that stray capacitance is no more than 10 pF.
In example (b), make sure that the external clock is held high in standby mode, subactive
mode, subsleep mode, and watch mode.
OSC1
OSC2
External clock input
Open
(a) OSC2 pin left open
OSC1
OSC2
External clock input
(b) Completely clock input at OSC2 pin
Fig ure 10.5 Exter nal Cl oc k Input (Exampl e s)
Rev. 2.0, 11/ 00, page 229 of 1037
(2) Externa l Cloc k
The external clock signal should have the same frequency as the system clock (φ).
Table 10.3 and figure 10.6 show the input conditions for the external clock.
Tabl e 1 0 . 3 Ex t e r na l Cloc k Input Conditi o ns
VCC = 4.0 to 5. 5 V
It em Symbol M in Max Unit Test Condit i ons
External clock input low
pulse widt h tCPL 40 ns
External clock input
high pulse widt h tCPH 40 ns
External clock rise time tCPr 10 ns
External clock fall time tCPf 10 ns
Figure 10.6
t
CPH
t
CPL
t
CPr
t
CPf
OSC1
Fi g ur e 1 0 . 6 E xt e rnal Cloc k Input Timi ng
Table 10.4 shows the external clock output settling delay time, and figure 10.7 shows the
external clock output settling delay timing. The oscillator and duty adjustment circuit have a
function for a dj usting t he waveform of t he e xt erna l cl oc k input a t t he OSC1 pin. W hen t he
prescribed c l ock signa l is input a t t he OSC1 pin, i nte rna l c l ock signa l output i s fixed a ft er t he
elapse of the external clock output settling delay time (tDEXT). As the clock signal output is not
fixed during t he tDEXT period, the reset signal should be driven low to maintain the reset state.
Rev. 2.0, 11/ 00, page 230 of 1037
Table 10.4 External Cloc k Output Settling Delay Time
(Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5. 5 V, VSS = AVSS = 0 V)
Item Symbol Min Max Unit Notes
External clock output settling
delay time tDEXT*500 µs Figure 10.7
Note: *tDEXT includes 20 tCYC of
5(6
pulse width (tRESW).
t
DEXT
*
RES
(Internal)
OSC1
V
CC
4.0 V
Note: * t
DEXT
includes 20 t
cyc
of RES pulse width (t
RESW
).
Figure 10. 7 Exte r nal Clock Output Settling Delay Timi ng
Rev. 2.0, 11/ 00, page 231 of 1037
10.4 Dut y Adju stment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
10.5 Medium-Speed Clock Divider
The medium-speed divider divides the system clock to generate φ/16, φ/32, a nd φ/64 clocks.
10.6 Bus Master Clock S elect i on Circu it
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/16, φ/32 or φ/64) to be supplied to the bus master (CPU), according to the settings of
bits SCK2 t o SCK0 i n SB YCR .
Rev. 2.0, 11/ 00, page 232 of 1037
10.7 Subclock Oscillator Circuit
10.7.1 Connecti ng 32.768 kHz Crystal Resonator
When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in
figure 10. 8.
For precautions on connecting, see section 10.3. 1 (3), Note on Board Design.
The subclock input conditions are shown in figure 10.10.
X1
X2 C2
C1
C1 = C2 = 15 pF (Typ)
Figure 10. 8 Connecting a 32. 768 kHz Crystal Resonator (Example)
Figure 10.9 shows a crystal resonator equivalent circuit.
X1
C
S
C
0
= 1.5 pF (Typ)
R
S
= 14 k (Typ)
f
W
= 32.768 kHz
Note: Values shown are the reference values.
X2
C
0
L
s
R
s
Figure 10.9 32.768 kHz Crystal Resonator Equivalent Circuit
Rev. 2.0, 11/ 00, page 233 of 1037
10. 7 .2 Ext e r na l Cloc k Input
(1) Circuit Configuration
When external clock input connect to the X1 pin, and X2 pin should remain open as
connection example of figure 10.10.
X1
X2 Open
External clock input
Fig ure 10.10 Connec ti on Exampl e Whe n Inputti ng Exter nal Cl oc k
10.7.3 When Subclock is not Needed
Connect X1 pin to VCC, and X2 pin should remain open as shown in figure 10.11.
X1
X2
V
CC
Open
Figure 10.11 Terminal When Subclock is not Needed
Rev. 2.0, 11/ 00, page 234 of 1037
10.8 Subclock Waveform Shaping Circuit
To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a
clock obtained by dividing the φ clock. The sampling frequency is set with the NESEL bit in
LPWRCR. For details, see section 4.2.2, Low-Power Control Register (LPWRCR). The clock
is not sampled in subactive mode, subsleep mode, or watch mode.
10.9 Notes on the Resonator
Resonator characteristics are closely related to the user board design. Perform appropriate
assessment of resonator connection, mask version and F-ZTAT, by referring to the connection
example given in this section. The resonator circuit rate differs depending on the free capacity
of the resonat or a nd the e xec ut ion c i rcui t , so consult wit h t he re sonat or ma nufa ct ure r before
determination. Make sure the voltage applied to the resonator pin does not exceed the maximum
rated voltage.
Rev. 2.0, 11/ 00, page 235 of 1037
Section 11 I/O Port
11.1 Overview
11.1.1 Port Functions
This L SI has se ve n 8-bit I/ O port s (i nc ludi ng one CMOS hi gh-c urre nt port ), one 4-bi t I/ O port ,
and one 8-bit input port. Table 11.1 shows the functions of each port. Each I/O part a port
control register (PCR) that controls an input and output and a port data register (PDR) for storing
output data. The input and output can be controlled in a unit of bit. The pin whose peripheral
function is used both as an alternative function can set the pin function in a unit of bit by a port
mode regi ste r (PMR).
11. 1 .2 Port Input
(1) Reading a Port
• When a gene ra l port of PCR = 0 (i nput) i s rea d, the pi n le ve l i s rea d.
• When a gene ra l port of PCR = 1 (out put) i s rea d, the va lue of t he c orre sponding PDR bit
is read.
• When the pi ns (exc ludi ng AN7 to AN0 and RP7 to RP0 pins) set to the peri phe ral
function are read, the results are as given in items (1) and (2) according to the PCR value.
(2) Processing Input Pins
The general input port or general I/O port is gated by read signals. Unused pins can be left
open if the y a re not re ad. However, i f a n open pi n i s read, a fe edt hrough c urrent m ay a ppl y
during the read period according to an intermediate level. The read period is about one-state.
Relevant ports: P0, P1, P2, P3, P4, P5, P6, P7, P8
When an alternative pin is set to an alternative function other than the general I/O, always set
the pin level to a high or low level. If the pin is left open, a feedthrough current applies
according to an intermediate level, which adversely affects reliability, causes malfunctions,
and in the worst case may damage the pin.
Because the PMR is not initialized in low power consumption mode, pay attention to the pin
input le ve l a ft er t he mode ha s been shift e d to t he low power consumpt i on mode .
Relevant pins:
,&
,
,54
to
,54
, SC K1, SCK2 , SI1, SI2 ,
&6
, FTIA, FTIB, FTIC, FTID,
TRIG, TMBI,
$'75*
, EXCAP, EXTTRG
Rev. 2.0, 11/ 00, page 236 of 1037
Table 11.1 Port F unctions
Port Description Pins Alternative Functions
Function
Switching
Register
Port 0 P07 to P00 input-only
ports P70/AN7 to
P00/AN0 Analog data input channels 7 to 0 PMR0
P17/TMOW Prescalar unit frequency division clock
output
P16/
,&
Prescalar unit input capture input
Port 1 P17 to P10 I/O ports
(Built -in MOS pull-up
transistors)
P15/
,54
to
P10/
,54
External interrupt request input
PMR1
P27/SCK2 SCI2 clock I/O
P26/SO2 SCI2 transmit data output
P25/SI2 SCI2 receive data input
PMR2
P24/SCL I2C bus interface clock I/O
P23/SDA I2C bus interface data I/O ICCR
P22/SCK1 SCI1 clock I/O
P21/SO1 SCI1 transmit data output
Port 2 P27 to P20 I/O ports
(Built -in MOS pull-up
transistors)
P20/SI1 SCI1 receive data input
SMR
SCR
P37/TMO Timer J timer output
P36/BUZZ Timer J buzzer output
P35/PWM3 to
P32/PWM0 8-bit PWM output
P31/STRB SCI2 strobe output
Port 3 P37 to P30 I/O ports
(Built -in MOS pull-up
transistors)
P30/
&6
SCI2 chip select input
PMR3
P47 None
P46/FTOB Timer X output compa re B o u t p u t
P45/FTOA Timer X output compa re A o u t p u t TOCR
P44/FTID Timer X input capture D input
P43/FTIC Timer X input capture C input
P42/FTIB Timer X input capture B input
P41/FTIA Timer X input capture A input
Port 4 P47 to P40 I/O ports
P40/PWM14 14-bit PWM output PMR4
P53/TRIG Realtime output port trigger input
P52/TMBI Timer B event input PMR5
P51 None
Port 5 P53 to P50 I/O ports
P50/
$'75*
A/D conversion start external trigger
input ADTSR
Port 6 P67 to P60 I/O ports P67/RP7 to
P60/RP0 Realtime output port PMR6
Port 7 P77 to P70 I/O ports P77/PPG7 to
P70/PPG0 PPG output PMR7
P87 to P84 None
P83/SV2
P82/SV1 Servo monitor output
P81/EXCAP Capstan external synchronous signal
input
Port 8 P87 to P80 I/O ports
(High-current ports)
P80/EXTTRG External trigger signal input
PMR8
Rev. 2.0, 11/ 00, page 237 of 1037
11.1.3 MOS Pull -Up Transistors
The MOS pull -up t r an si st ors in port s 1 t o 3 c a n be switched on or off by the MOS pul l -up s elect
registers 1 to 3 (PUR1 to PUR3) in units of bits. Settings in PUR1 to PUR3 are valid when the
pin function is set to an input by PCR1 to PCR3. If the pin function is set to an output, the MOS
pull-up transistor is turned off. Fi gure 11.1 shows the circuit configuration of a pin with a MOS
pull-up tra nsistor.
When the pin whose peripheral function is used both as an alternative function is set to the
alternative output function, the MOS pul l-up t ra nsi st or i s turne d off. W he n t he pi n i s set t o t he
alternative input function, the MOS pull-up t ra nsi st or i s cont ro lled according to the PUR setting
regardle ss of PCR.
V
CC
PUR
LPWRM
LPWRM
PCR
PDR
PUR
PCR
PDR
: Low power consumption mode signal
(The MOS pull-up transistor is turned off in reset, standby, and
watch modes.)
: MOS pull-up select register
: Port control register
: Port data register
Input data
V
CC
V
SS
Figure 11.1 Circuit Configuration of Pin with MOS Pull-Up Transistor
Rev. 2.0, 11/ 00, page 238 of 1037
11.2 Port 0
11.2.1 Overview
Port 0 is an 8-bit input-only port. Table 11.2 shows the port 0 configuration.
Port 0 consists of pins that a re used both a s standa rd input port s (P07 to P00) and anal og i nput
channels (AN7 to AN0). It is switched by port mode register 0 (PMR0).
Table 11.2 Port 0 Configuration
Port Funct ion Alte r nat ive Function
P07 (standar d input por t ) AN7 (analog input channel)
P06 (standar d input por t ) AN6 (analog input channel)
P05 (standar d input por t ) AN5 (analog input channel)
P04 (standar d input por t ) AN4 (analog input channel)
P03 (standar d input por t ) AN3 (analog input channel)
P02 (standar d input por t ) AN2 (analog input channel)
P01 (standar d input por t ) AN1 (analog input channel)
Port 0
P00 (standar d input por t ) AN0 (analog input channel)
Rev. 2.0, 11/ 00, page 239 of 1037
11.2.2 Register Configuration
Table 11.3 shows the port 0 register configuration.
Table 11.3 Port 0 Regi ster Configuration
Name Abbrev. R/W Size Init ial Value Address *
Port m ode r egist er 0 PMR0 R/W Byte H'00 H'FFCD
Port dat a r egister 0 PDR0 R Byte H'FFC0
Note: *Lower 16 bits of t he addr ess.
(1) Port Mode Register 0 (PMR0)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR04 PMR03 PMR02 PMR01 PMR00PMR07 PMR06 PMR05
Bit :
Initial value :
R/W :
Port mode register 0 (PMR0) controls switching of each pin function of port 0. The switching is
specified in a unit of bit.
PMR0 is an 8-bit read/write enable register. When reset, PMR0 is initialized to H'00.
Bits 7 to 0: P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00)
PMR07 to PMR00 set s whethe r the P0n/ANn pin is used as a P0n input pin or a n ANn pin for
the ana l og input c hanne l of an A/D conve rt er.
Bit n
PMR0n Description
0 The P0n/ANn pin functions as a P0n input pin (Init ial value)
1 The P0n/ANn pin functions as an ANn input pin
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 240 of 1037
(2) Port Data Register 0 (P DR0)
01
R
2
R
34
RR
57 PDR04 PDR03 PDR02 PDR01 PDR00
R
PDR07
RRR
PDR06 PDR05
6
————————
Initial value :
R/W :
Bit :
Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0
(general input port), the pin state is read if PDR0 is read. When the corresponding bit of PMR0
is 1 (analog i nput cha nne l), 1 i s rea d if PDR0 is read.
PDR0 is an 8-bit read-onl y re giste r. W hen PDR0 is reset, i t s value s bec ome unde fine d.
11.2.3 Pin Functions
This section describes the pin functions of port 0 and their selection methods.
(1) P07/AN7 to P00/AN0
P07/AN7 to P00/AN0 are switched according to the PMR0n bit of PMR0 as shown below.
PMR0n Pin Function
0 P0n input pin
1 ANn input pin
(n = 7 to 0)
11.2.4 Pin States
Table 11.4 shows the pin 0 states in each operation mode.
Table 11.4 Port 0 P in States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
PN7/AN7 to
P00/AN0 High-
impedance High-
impedance High-
impedance High-
impedance High-
impedance High-
impedance High-
impedance
Rev. 2.0, 11/ 00, page 241 of 1037
11.3 Port 1
11.3.1 Overview
Port 1 is an 8-bit I/O port. Table 11. 5 shows the port 1 configuration.
Port 1 consists of pins that a re used both a s standa rd I/O ports (P17 to P10) and freque nc y
division cl oc k output (T MOW), i nput c a pture i nput (
,&
), or ext erna l int e rrupt re que st input s
(
,54
to
,54
). It is switched by port mode register 1 (PMR1) and port control register 1
(PCR1).
Port 1 can select the functions of MOS pul l -up t ra nsi st ors.
Table 11.5 Port 1 Configuration
Port Funct ion Alte r nat ive Function
P17 (standar d I / O por t) TMOW ( f r equency division clock output)
P16 (standar d I / O port )
,&
(input capt ur e input )
P15 (standar d I /O por t )
,54
(exter nal inter r upt request input )
P14 (standar d I /O por t )
,54
(exter nal inter r upt request input )
P13 (standar d I /O por t )
,54
(exter nal inter r upt request input )
P12 (standar d I /O por t )
,54
(exter nal inter r upt request input )
P11 (standar d I /O por t )
,54
(exter nal inter r upt request input )
Port 1
P10 (standar d I /O por t )
,54
(exter nal inter r upt request input )
11.3.2 Register Configuration
Table 11.6 shows the port 1 register configuration.
Table 11.6 Port 1 Regi ster Configuration
Name Abbrev. R/W Size Init ial Value Address *
Port m ode r egist er 1 PMR1 R/W Byte H'00 H'FFCE
Port cont r ol r egister 1 PCR1 W Byte H'00 H'FFD1
Port dat a r egist er 1 PDR1 R/W Byte H'00 H'FFC1
MOS pull-up select
register 1 PUR1 R/W Byte H'00 H'FFE1
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 242 of 1037
(1) Port Mode Register 1 (PMR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR14 PMR13 PMR12 PMR11 PMR10PMR17 PMR16 PMR15
Bit :
Initial value :
R/W :
Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is
specified in a unit of bit.
PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00.
Note the following items when the pin functions are switched by PMR1.
(1) If port 1 is set to a n
,&
input pin a nd
,54
to
,54
by PMR1, the pin level needs be set to
the high or low level regardless of the active mode and low power consumption mode. The
pin level must not be set to an intermediate level.
(2) When the pi n funct i ons of P16/
,&
and P15/
,54
to P10/
,54
are switched by PMR1, they
are incorrectly recognized as edge detection according to the state of a pin signal and a
detection signal may be generated. To prevent this, perform the operation in the following
procedure.
(a) Before switching the pin functions, inhibit an interrupt enable flag from being
interrupted.
(b) After having switched the pin functions, clear the relevant interrupt request flag to 0 by a
single instruction.
(Program Exam pl e)
:
MOV.B ROL,@IENR ⋅⋅⋅⋅⋅⋅ Inter rupt di sabl ed
MOV.B R1L,@PMR1 ⋅⋅⋅⋅⋅⋅ Pin funct i on change
NOP ⋅⋅⋅⋅⋅⋅ Optional instruction
BCLR m @IRQR ⋅⋅⋅⋅⋅⋅ Applicable interrupt clear
MOV.B R1L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt enabled
:
Bit 7: P17/TM O W Pi n Switching (PMR17)
PMR17 sets whether the P17/TMOW pin i s used as a P17 I/O pin or a TMOW pin for t he
frequency di vi sion cl oc k output .
Bit 7
PMR17 Description
0 The P17/TMOW pin funct ions as a P17 I/ O pin (Initial value)
1 The P17/TMOW pin funct ions as a TMOW output pin
Rev. 2.0, 11/ 00, page 243 of 1037
Bit 6: P16/
,&
,&
Pi n Swi t c hing ( P M R1 6 )
PMR16 sets whether the P16/
,&
pin as a P16 I/O pin or an
,&
pin for the i nput ca pt ure i nput of
the prescalar unit. The
,&
pin has a built-in noise cancel circuit. See section 21, Prescalar Unit.
Bit 6
PMR16 Description
0 The P16/
,&
pin functions as a P16 I/ O pin (I nit ial value)
1 The P16/
,&
pin functions as an
,&
input pin
Bits 5 to 0: P15/
,54
,54
to P10/
,54
,54
Pin Switching (PMR15 to PMR10)
PMR15 to PMR10 set whet her t he P1n/
,54Q
pin is used as a P1n I/O pin or an
,54Q
pin for the
externa l int e rrupt re que st input .
Bit n
PMR1n Description
0 The P1n/
,54Q
pin functions as a P1n I/ O pin (Init ial value)
1 The P1n/
,54Q
pin functions as an
,54Q
input pin
(n = 5 to 0)
(2) Port Control Register 1 (PCR1)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR14 PCR13 PCR12 PCR11 PCR10PCR17 PCR16 PCR15
Bit :
Initial value :
R/W :
Port control re gi ster 1 (PCR1) cont rol s the I/ Os of pins P17 to P10 of port 1 in a uni t of bi t .
When PCR1 is set to 1, t he corre sponding P17 to P10 pins bec ome out put pi ns, a nd when i t i s set
to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of
PCR1 and PDR1 become valid.
PCR1 is an 8-bit write-only register. When PCR1 is read, 1 is read. When reset, PCR1 is
initialized to H'00.
Bit n
PCR1n Description
0 The P1n pin functions as an input pin (Init ial value)
1 The P1n pin functions as an output pin
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 244 of 1037
(3) Port Data Register 1 (P DR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR14 PDR13 PDR12 PDR11 PDR10PDR17 PDR16 PDR15
Bit :
Initial value :
R/W :
Port data register 1 (PDR1) stores the data for the pins P17 to P10 of port 1. When PCR1 is 1
(output), the PDR1 values are directly read if port 1 is read. Accordingly, the pin states are not
affected. When PCR1 is 0 (input), the pin states are read if port 1 is read.
PDR1 is an 8-bit read/ write enable register. When reset, PDR1 is initialized to H'00.
(4) MOS Pull-Up Select Register 1 (PUR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR14 PUR13 PUR12 PUR11 PUR10PUR17 PUR16 PUR15
Bit :
Initial value :
R/W :
MOS pull-up s elector register 1 (PUR1) controls the on and off of the MOS pul l -up t ra nsi st or of
port 1. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid.
When the c orresponding bi t of PCR1 is set to 1 (out put ), the c orresponding bi t of PUR1 become s
invalid and the MOS pull-up t ra nsi st or is t urne d off.
PUR1 is an 8-bit read/ write enable register. When reset, PUR1 is initialized to H'00.
Bit n
PUR1n Description
0 The P1n pin has no MOS pull-up tr ansist or (Init ial value)
1 The P1n pin has a MOS pull-up pin
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 245 of 1037
11.3.3 Pin Functions
This section describes the port 1 pin functions and their selection methods.
(1) P17/TMOW
P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and the
PCR17 bit in PCR1.
PMR17 PCR17 Pi n Funct ion
0 P17 input pin
0
1 P17 out put pin
1*TMO W output pin
(2) P16/
,&
P16/
,&
is switched as shown below according to the PMR16 bit in PMR1, the NC on/off bit
in prescalar unit control/status register (PCSR), and the PCR16 bit in PCR1.
PMR16 PCR16 NC on/ off Pi n Function
0 P16 input pin
0
1
*
P16 output pin
0 Noise cancel invalid1*
1
,&
input pin
Noise cancel valid
(3) P15/
,54
to P10/
,54
P15/
,54
to P10/
,54
are switched as shown below according to the PMR1n bit in PMR1
and the PCR1n bit i n PCR1.
PMR1n PCR1n Pin Function
0 P1n input pin
0
1 P1n out put pin
1*
,54Q
input pin
(n = 5 to 0)
Notes: 1. * Don't car e.
2. The
,54
to
,54
input pins can se lect the leading or f alling edge as an edge sense
(the
,54
pin can select both edges). See section 6. 2. 4, Edge Select Register
(IEGR).
3.
,54
or
,54
can be used as a timer J event input and
,54
can be used as a timer
R input capture input. For det ails, see sect ion 14, "Timer J" or sect ion 16, "Timer R".
Rev. 2.0, 11/ 00, page 246 of 1037
11.3.4 Pin States
Table 11.7 shows the port 1 pin states in each operation mode.
Table 11.7 Port 1 P in States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P17/TMOW
P16/
,&
P15/
,54
to
P10/
,54
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: If the
,&
input pin and
,54
to
,54
input pins are set, the pin level need be set to the
high or low level r egar dless of t he act ive m ode and low power consumpt ion mode. Note
that t he pin level must not r each an int er m ediat e level.
Rev. 2.0, 11/ 00, page 247 of 1037
11.4 Port 2
11.4.1 Overview
Port 2 is an 8-bit I/O port. Table 11. 8 shows the port 2 configuration.
Port 2 consists of pins that a re used both a s standa rd I/O ports (P27 to P20) and SCI cloc k I/ O
(SCK1, SCK2), receive data input (SI1, SI2), send data output (SO1, SO2), I2C bus inte rfa ce
clock I/O (SCL), or data I/O (SCL). It is switched by port mode register 2 (PRM2), serial mode
register (SMR), serial control register 2 (SCR), I2C bus control re giste r (ICCR), a nd port c ont rol
register (PCR2).
Port 2 can select the MOS pull-up function.
Table 11.8 Port 2 Configuration
Port Funct ion Alte r nat ive Function
P27 (standar d I / O por t) SCK2 (SCI 2 clock I / O )
P26 (standar d I / O port ) SO2 ( SCI2 transm it dat a output)
P25 (standar d I / O port ) SI2 ( SCI2 r eceive dat a input )
P24 (standar d I / O port ) SCL (I2C bus interface clock I/O )
P23 (standar d I /O por t ) SDA (I 2C bus inter f ace dat a I /O)
P22 (standar d I / O port ) SCK1 (SCI1 clock I/O )
P21 (standar d I /O por t ) SO 1 ( SCI1 t r ansm it dat a out put)
Port 2
P20 (standar d I /O por t ) SI 1 ( SCI1 r eceive dat a input)
11.4.2 Register Configuration
Table 11.9 shows the port 2 register configuration.
Table 11.9 Port 2 Regi ster Configuration
Name Abbrev. R/W Size Init ial Value Address *
Port m ode r egist er 2 PMR2 R/W Byte H'1E H'FFCF
Port cont r ol r egister 2 PCR2 W Byte H'00 H'FFD2
Port dat a r egist er 2 PDR2 R/W Byte H'00 H'FFC2
MOS pull-up select
register 2 PUR2 R/W Byte H'00 H'FFE2
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 248 of 1037
(1) Port Mode Register 2 (PMR2)
0
0
1
1
2
1
3
1
4————
————
10
R/W
5
0
7
0
R/W R/WR/W
6PMR20PMR27 PMR26 PMR25
Bit :
Initial value :
R/W :
Port mode register 2 (PMR0) controls switching of each pin function of port 2. The switching is
specified in a unit of bit.
The switching of the P22/SCK1, P21/SO1, and P20/SI1 pin functions is controlled by SMR and
SCR. See section 23, SCI1.
PMR2 is an 8-bit read/write enable register. When reset, PMR2 is initialized to H'1E.
If the SCK1, SCK2, SI1, and SI1 input pins are set , the pi n le ve l ne e d be set t o the hi gh or low
level regardless of the active mode and low power consumption mode. Note that the pin level
must not reach an intermediate level
Bit 7: P27/SCK2 Pi n Switching (PMR27)
PMR27 sets whether the P27/SCK2 pin is used as a P27 I/O pin or an SKC2 pin for the SCI2
clock I/O.
Bit 7
PMR27 Description
0 The P27/SCK2 pin functions as a P27 I/O pin ( I nit ial value)
1 The P27/SCK2 pin functions as an SCK2 I/O pin
Bit 6: P26/SO2 P i n Switching (PMR26)
PMR26 sets whether the P26/SO2 pin as a P26 I/O pin or an SO2 pin for the SCI2 send dat a
output.
Bit 6
PMR26 Description
0 The P26/SO2 pin functions as a P26 I/O pin (I nitial value)
1 The P26/SO2 pin functions as an SO2 input pin
Rev. 2.0, 11/ 00, page 249 of 1037
Bit 5: P25/SI2 Pin Switching (PMR25)
PMR26 sets whether the P25/SI2 pin as a P25 I/O pin or an SI2 pin for the SCI2 receive data
input.
Bit 5
PMR25 Description
0 The P25/SI2 pin functions as a P25 I/O pin (Init ial value)
1 The P25/SI2 pin functions as an SI2 input pin
Bits 4 to 1: Reserved Bits
When the bits are read, 1 is always read. The write operation is invalid.
Bit 0: P26/SO2 Pin PMOS Control (PMR20)
PMR20 control s t he PMOS ON a nd OFF of t he P26/ SO2 pi n out put buffe r.
Bit 0
PMR20 Description
0 The P26/SO2 pin functions as CMOS output (Init ial value)
1 The P26/SO2 pin functions as NMOS open drain out put
(2) Port Control Register 2 (PCR2)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR24 PCR23 PCR22 PCR21 PCR20PCR27 PCR26 PCR25
Bit :
Initial value :
R/W :
Port control re gi ster 2 (PCR2) cont rol s the I/ Os of pins P27 to P20 of port 2 in a uni t of bi t .
When PCR2 is set to 1, t he corre sponding P27 to P20 pins bec ome out put pi ns, a nd when i t i s set
to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of
PCR2 and PDR2 are valid.
PCR2 is an 8-bit write-only register. When PCR2 is read, 1 is read. When reset, PCR2 is
initialized to H'00.
Bit n
PCR2n Description
0 The P2n pin functions as an input pin (Init ial value)
1 The P2n pin functions as an output pin
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 250 of 1037
(3) Port Data Register 2 (P DR2)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR24 PDR23 PDR22 PDR21 PDR20PDR27 PDR26 PDR25
Bit :
Initial value :
R/W :
Port data register 2 (PDR2) stores the data for the pins P27 to P20 of port 2. When PCR2 is 1
(output), the PDR2 values are directly read if port 2 is read. Accordingly, the pin states are not
affected. When PCR2 is 0 (input), the pin states are read if port 2 is read.
PDR2 is an 8-bit read/write enable register. When reset, PDR2 is initialized to H'00.
(4) MOS Pull-Up Select Register 2 (PUR2)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR24 PUR23 PUR22 PUR21 PUR20PUR27 PUR26 PUR25
Bit :
Initial value :
R/W :
MOS pull-up s elector register 2 (PUR2) controls the ON and OFF of t h e MOS pul l -up t ra nsi st or
of port 2. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid. If
the corre sponding bi t of PCR2 is set t o 1 (out put), t he corre sponding bi t of PUR2 becom e s
invalid and the MOS pull-up t ra nsi st or is t urne d off.
PUR2 is an 8-bit read/write enable register. When reset, PUR2 is initialized to H'00.
Bit n
PMR2n Description
0 The P2n pin has no MOS pull-up tr ansist or (Init ial value)
1 The P2n pin has a MOS pull-up tr ansist or
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 251 of 1037
11.4.3 Pin Functions
This section describes the port 2 pin functions and their selection methods.
(1) P27/SCK2
P27/SCK2 is switched as shown below according to the PMR27 bit in PMR2, the PCR27 bit
in PCR2, and the SCK2 to SCK0 bits in serial control register 2 (SCR2).
PMR27 PCR27 CKS2 t o CKS0 Pin Functi on
0 P27 input pin
0
1
*
P27 output pin
Ot her t han 111 SCK2 output pin1*
111 SCK2 input pin
Note: *Don't care.
(2) P26/SO2
P26/SO2 is switched as shown below according to the PMR26 bit in PMR2 and the PCR26
bit in PCR2.
PMR26 PCR26 Pi n Funct ion
0 P26 input pin
0
1 P26 out put pin
1*SO2 output pin
Note: *Don't care.
(3) P25/SI2
P25/SI2 is switched as shown below according to the PMR25 bit in PMR2 and the PCR25 bit
in PCR2.
PMR25 PCR25 Pi n Funct ion
0 P25 input pin
0
1 P25 out put pin
1*SI2 input pin
Note: *Don't care.
Rev. 2.0, 11/ 00, page 252 of 1037
(4) P24/SCL
P24/SCL2 is switched as shown below according to the ICE bit in the I2C bus c ontrol re giste r
and the PCR24 bit i n PCR2.
ICE PCR24 Pi n Funct ion
0 P24 input pin
0
1 P24 out put pin
1*SCL I/O pin
Note: *Don't care.
(5) P23/SDA
P23/ SDA i s switched as shown below according to the ICE bit in the I2C bus cont rol regi ste r
and the PCR23 bit i n PCR2.
ICE PCR23 Pi n Funct ion
0 P23 input pin
0
1 P23 out put pin
1*SDA I/O pin
Note: *Don't care.
(6) P22/SCK1
P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/
$
bit in
SMR, and the CKE1 and CKE0 bits in SCR.
CKE1 C/
$
$
CKE0 PCR22 Pin Function
0 P22 input pin
0
1 P22 output pin
0
1
0
1
SCK1 output pin
1*
*
*
SCK1 input pin
Note: *Don't care.
(7) P21/SO1
P21/SO1 is switched as shown below according to the PCR21 bit in PCR2 and the TE bit in
SCR.
Rev. 2.0, 11/ 00, page 253 of 1037
TE PCR21 Pin Funct ion
0 P21 input pin
0
1 P21 out put pin
1*SO1 output pin
Note: *Don't care.
(8) P20/SI1
P20/SI1 is switched as shown below according to the PCR20 bit in PCR2 and the RE bit in
SCR.
RE PCR20 Pin Function
0 P20 input pin
0
1 P20 out put pin
1*SI1 input pin
Note: *Don't care.
11.4.4 Pin States
Table 11.10 shows the port 2 pin states in each operation mode.
Table 11.10 Port 2 P i n States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P27/SCK2
P26/SO2
P25/SI2
P24/SCL
P23/SDA
P22/SCK1
P21/SO1
P20/SI1
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: I f t he SCK1, SCK2, SI1, and SI 2 input pins ar e set , the pin level needs be set to the high
or low level regardless of the act ive m ode and low power consumpt ion mode. Note that
the pin level must not r each an inter mediate level.
Rev. 2.0, 11/ 00, page 254 of 1037
11.5 Port 3
11.5.1 Overview
Port 3 is an 8-bit I/O port. Table 11. 11 shows the port 3 configuration.
Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer
output (TMO), buzzer output (BUZZ), 8-bit PWN outputs (PWN3 to PWN0), SCI2 strobe output
(STRB), or chip select input (
&6
). It is switched by port mode register 3 (PMR3) and port
control re gi ster 3 (PCR3).
Port 3 can select the MOS pull-up function.
Table 11.11 Port 3 Configuration
Port Funct ion Alte r nat ive Function
P37 (standar d I /O por t ) TM O (timer J t im er out put )
P36 (standar d I /O por t ) BUZZ (t imer J buzzer out put )
P35 (standar d I /O por t ) PWM 3 ( 8- bit PWM out put )
P34 (standar d I /O por t ) PWM 2 ( 8- bit PWM out put )
P33 (standar d I /O por t ) PWM 1 ( 8- bit PWM out put )
P32 (standar d I /O por t ) PWM 0 ( 8- bit PWM out put )
P31 (standar d I /O por t ) STRB (SCI2 str obe output)
Port 3
P30 (standar d I /O por t )
&6
(SCI2 chip select input)
11.5.2 Register Configuration
Table 11.12 shows the port 3 register configuration.
Table 11.12 Port 3 Regi ster Configuration
Name Abbrev. R/W Size Init i al Value Address*
Port m ode r egist er 3 PMR3 R/W Byte H'00 H'FFD0
Port cont r ol r egister 3 PCR3 W Byte H'00 H'FFD3
Port dat a r egist er 3 PDR3 R/W Byte H'00 H'FFC3
MOS pull-up select
register 3 PUR3 R/W Byte H'00 H'FFE3
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 255 of 1037
(1) Port Mode Register 3 (PMR3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR34 PMR33 PMR32 PMR31 PMR30PMR37 PMR36 PMR35
Bit :
Initial value :
R/W :
Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is
specified in a unit of bit.
PMR3 is an 8-bit read/write enable register. When reset, PMR3 is initialized to H'00.
If the
&6
input pin i s set, t he pi n l eve l nee d be set t o t he hi gh or l ow leve l rega rdl ess of the
active mode and low power consumption mode. Note that the pin level must not reach an
intermediate level.
Bit 7: P37/TM O Pi n Switching (PMR37)
PMR37 sets whether the P37/TMO pin is used as a P37 I/O pin or a TMO pin for the timer J
output timer.
Bit 7
PMR37 Description
0 The P37/TMO pin functions as a P37 I/O pin (I nitial value)
1 The P37/TMO pin functions as a TM O out put pin
Note: I f t he TM O pin is used for r em ot e cont rol sending, a careless timer output pulse may be
output when the r em ote contr ol mode is set af ter t he out put has been switched t o the
TMO output. Per f or m t he switching and set t ing in the f ollowing order.
[1] Set t he r emote cont r ol mode.
[2] Set t he TM J-1 and 2 counter dat a of the timer J.
[3] Switch the P37/ TM O pin t o t he TM O output pin.
[4] Set the ST bit to 1.
Bit 6: P 36/BUZZ Pi n Switching (PMR36)
PMR36 sets whether the P36/BUZZ pin as a P36 I/O pin or an BUZZ pin for the timer J buzzer
output. For the selection of the BUZZ output, see the 14.2.2, Timer J Control Register (TMJC).
Bit 6
PMR36 Description
0 The P36/BUZZ pin functions as a P36 I/ O pin (Initial value)
1 The P36/BUZZ pin functions as a BUZZ output pin
Rev. 2.0, 11/ 00, page 256 of 1037
Bits 5 to 2: P35/PWM 3 to P 32/P WM 0 Pi n Switching (PMR35 to PM R32)
PMR35 to PMR32 set whet her t he P3n/PWMm pin i s used as a P3n I/O pin or a PWMm pin for
the 8-bit PWM output .
Bit n
PMR3n Description
0 The P3n/PWMm pin f unct ions as a P3n I/ O pin ( I nit ial value)
1 The P3n/PWMm pin f unct ions as a PWMm output pin
(n = 5 to 2, m = 3 to 0)
Bit 1: P31/STRB Pin Switching (PMR31)
PMR31 sets whether the P31/STRB pin i s used as a P31 I/O pin or a n STRB pin for t he SCI2
strobe output.
Bit 1
PMR31 Description
0 The P31/STRB pin functions as a P31 I/O pin (Initial value)
1 The P31/STRB pin functions as an STRB output pin
Bit 0: P30/
&6
&6
Pi n Swi t c hing ( P M R3 0 )
PMR30 sets whether the P30/
&6
pin is used as a P30 I/O pin or a
&6
pin for the SCI2 chip select
input.
Bit 0
PMR30 Description
0 The P30/
&6
pin functions as a P30 I/ O pin (Init ial value)
1 The P30/
&6
pin functions as a
&6
input pin
Rev. 2.0, 11/ 00, page 257 of 1037
(2) Port Control Register 3 (PCR3)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR34 PCR33 PCR32 PCR31 PCR30PCR37 PCR36 PCR35
Bit :
Initial value :
R/W :
Port control re gi ster 3 (PCR3) cont rol s the I/ Os of pins P37 to P30 of port 3 in a uni t of bi t .
When PCR3 is set to 1, t he corre sponding P37 to P30 pins bec ome out put pi ns, a nd when i t i s set
to 0, they become input pins. When the relevant pin is set to a general I/O by PMR3, settings of
PCR3 and PDR3 become valid.
PCR3 is an 8-bit write-only register. When PCR3 is read, 1 is read. When reset, PCR3 is
initialized to H'00.
Bit n
PCR3n Description
0 The P3n pin functions as an input pin (Init ial value)
1 The P3n pin functions as an output pin
(n = 7 to 0)
(3) Port Data Register 3 (P DR3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR34 PDR33 PDR32 PDR31 PDR30PDR37 PDR36 PDR35
Bit :
Initial value :
R/W :
Port data register 3 (PDR3) stores the data for the pins P37 to P30 of port 3. When PCR3 is 1
(output), the PDR3 values are directly read if port 3 is read. Accordingly, the pin states are not
affected. When PCR3 is 0 (input), the pin states are read if port 3 is read.
PDR3 is an 8-bit read/write enable register. When reset, PDR3 is initialized to H'00.
Rev. 2.0, 11/ 00, page 258 of 1037
(4) MOS Pull-Up Select Register 3 (PUR3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR34 PUR33 PUR32 PUR31 PUR30PUR37 PUR36 PUR35
Bit :
Initial value :
R/W :
MOS pull-up s elector register 3 (PUR3) controls the ON and OFF of t h e MOS pul l -up t ra nsi st or
of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If
the corre sponding bi t of PCR3 is set t o 1 (out put), t he corre sponding bi t of PUR3 becom e s
invalid and the MOS pull-up t ra nsi st or is t urne d off.
PUR3 is an 8-bit read/write enable register. When reset, PUR3 is initialized to H'00.
Bit n
PCR3n Description
0 The P3n pin has no MOS pull-up tr ansist or (Init ial value)
1 The P3n pin has a MOS pull-up tr ansist or
(n = 7 to 0)
11.5.3 Pin Functions
This section describes the port 3 pin functions and their selection methods.
(1) P37/TMO
P37/TMO is switched as shown below according to the PMR37 bit in PMR3 and the PCR37
bit in PCR3.
PMR37 PCR37 Pi n Funct ion
0 P37 input pin
0
1 P37 out put pin
1*TMO out put pin
Note: *Don't care.
Rev. 2.0, 11/ 00, page 259 of 1037
(2) P36/BUZZ
P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the PCR36
bit in PCR3.
PMR36 PCR36 Pi n Funct ion
0 P36 input pin
0
1 P36 out put pin
1*BUZZ output pin
Note: *Don't care.
(3) P3 5 / PW M3 t o P3 2/PWM0
P35/PWM3 to P32/PWM0 are switched as shown below according to the PMR3n bit in
PMR3 and the PCR3n bit in PCR3.
PMR3n PCR3n Pin Function
0 P3n input pin
0
1 P3n out put pin
1*PWMm out put pin
(n = 5 to 2, m = 3 to 0)
Note: *Don't care.
(4) P31/STRB
P31/STRB is switched as shown below according to the PMR31 bit in PMR3 and the PCR31
bit in PCR3.
PMR31 PCR31 Pi n Funct ion
0 P31 input pin
0
1 P31 out put pin
1*STRB output pin
Note: *Don't care.
(5) P30/
&6
P30/
&6
is switched as shown below according to the PMR30 bit in PMR3 and the PCR30 bit
in PCR3.
PMR30 PCR30 Pi n Funct ion
0 P30 input pin
0
1 P30 out put pin
1*
&6
input pin
Note: *Don't care.
Rev. 2.0, 11/ 00, page 260 of 1037
11.5.4 Pin States
Table 11.13 shows the port 3 pin states in each operation mode.
Table 11.13 Port 3 P i n States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P37/TMO
P36/BUZZ
P35/PWM3
to
P32/PWM0
P31/STRB
P30/
&6
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: If the
&6
input pin is set, t he pin level need be set t o t he high or low level regardless of t he
active mode and low power consumpt ion mode. Note that the pin level must not r each an
interm ediate level.
Rev. 2.0, 11/ 00, page 261 of 1037
11.6 Port 4
11.6.1 Overview
Port 4 is an 8-bit I/O port. Table 11. 14 shows the port 4 configuration.
Port 4 consists of pins that a re used both a s standa rd I/O ports (P47 to P40) and output c ompa re
output (FTOA, FTOB), input c apt ure input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output
(PWM14). It is switched by port mode register 4 (PRM4), timer output compare control register
(TOCR), and port cont rol regi ste r 4 (PCR4).
Table 11.14 Port 4 Configuration
Port Funct ion Alte r nat ive Function
P47 (standar d I /O por t ) None
P46 (standar d I /O por t ) FTO B ( t im er X1 output compar e out put )
P45 (standar d I /O por t ) FTO A ( t im er X1 output compar e out put )
P44 (standar d I /O por t ) FTI D ( t imer X1 input capture input)
P43 (standar d I /O por t ) FTI C ( t imer X1 input capture input)
P42 (standar d I /O por t ) FTI B ( t imer X1 input captur e input)
P41 (standar d I /O por t ) FTI A ( t imer X1 input captur e input)
Port 4
P40 (standar d I /O por t ) PWM 14 ( 14- bit PWM out put )
11.6.2 Register Configuration
Table 11.15 shows the port 4 register configuration.
Table 11.15 Port 4 Regi ster Configuration
Name Abbrev. R/W Size Init ial Value Address *
Port m ode register 4 PM R4 R/W Byte H'FE H'FFDB
Port cont r ol r egister 4 PCR4 W Byte H'00 H'FFD4
Port dat a r egist er 4 PDR4 R/W Byte H'00 H'FFC4
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 262 of 1037
(1) Port Mode Register 4 (PMR4)
0
0
1
1
2
1
3
1
4
11
5
1
7
1R/W
6———————
———————
PMR40
Bit :
Initial value :
R/W :
Port mode register 4 (PMR4) controls switching of the P40/PWM14 pin function. The
switchings of the P46/FTOB and P45/FTOA functions are controlled by TOCR. See section 17,
Timer X1. The FTIA, FTIB, FTIC, and FTID inputs always function.
PMR4 is an 8-bit read/write enable register. When reset, PMR4 is initialized to H'FE.
Because the FTIA, FTIB, FTIC, and FTID inputs always function, the alternative pin need
always be set to the high or low level regardless of the active mode and low power consumption
mode. Note that the pin level must not reach an intermediate level (excluding reset, standby,
and watch modes).
Because the FTIA, FT IB, FTIC, and FTID inputs always function, each input uses the input edge
to the alternative general I/O pins P44, P43, P42, and P41 as input signals.
Bits 7 to 1: Reserved Bits
When the bits are read, 1 is always read. The write operation is invalid.
Bit 0: P40/P WM 14 Pi n Switching (PMR40)
PMR40 sets whether the P40/PWM pin is used as a P40 I/O pin or a PWM14 pin for t he 14-bi t
PWM square wave output.
Bit 0
PMR40 Description
0 The P40/PWM14 pin f unct ions as a P40 I/ O pin (Init ial value)
1 The P40/PWM14 pin f unct ions as a PWM14 output pin
Rev. 2.0, 11/ 00, page 263 of 1037
(2) Port Control Register 4 (PCR4)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR44 PCR43 PCR42 PCR41 PCR40PCR47 PCR46 PCR45
Bit :
Initial value :
R/W :
Port control re gi ster 4 (PCR4) cont rol s the I/ Os of pins P47 to P40 of port 4 in a uni t of bi t .
When PCR4 is set to 1, t he corre sponding P47 to P40 pins bec ome out put pi ns, a nd when i t i s set
to 0, they become input pins. When the relevant pin is set to a general I/O by PMR4, settings of
PCR4 and PDR4 become valid.
PCR4 is an 8-bit write-only register. When PCR4 is read, 1 is read. When reset, PCR4 is
initialized to H'00.
Bit n
PCR4n Description
0 The P4n pin functions as an input pin (Init ial value)
1 The P4n pin functions as an output pin
(n = 7 to 0)
(3) Port Data Register 4 (P DR4)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR44 PDR43 PDR42 PDR41 PDR40PDR47 PDR46 PDR45
Bit :
Initial value :
R/W :
Port data register 4 (PDR4) stores the data for the pins P47 to P40 of port 4. When PCR4 is 1
(output), the PDR4 values are directly read if port 3 is read. Accordingly, the pin states are not
affected. When PCR4 is 0 (input), the pin states are read if port 4 is read.
PDR4 is an 8-bit read/write enable register. When reset, PDR4 is initialized to H'00.
Rev. 2.0, 11/ 00, page 264 of 1037
11.6.3 Pin Functions
This section describes the port 4 pin functions and their selection methods.
(1) P47/FTCI
P47/FTCI is switched as shown below according to the PCR47 bit in PCR4.
PCR47 Pin Function
0 P47 input pin
1 P47 output pin
(2) P46/FTOB
P46/FTOB is switched as shown below according to the PCR46 bit in PCR4 and the OEB bit
in TOCR.
OEB PCR46 Pin Funct ion
0 P46 input pin
0
1 P46 out put pin
1*FTOB output pin
Note: *Don't care.
(3) P45/FTOA
P45/FTOA is switched as shown below according to the PCR45 bit in PCR4 and the OE A bit
in TOCR.
OEA PCR45 Pin Funct ion
0 P45 input pin
0
1 P45 out put pin
1*FTOA output pin
Note: *Don't care.
(4) P44/FTID
P44/FTID is switched as shown below according to the PCR44 bit in PCR4.
PCR44 Pin Function
0 P44 input pin
1 P44 output pin
FTID input pin
Rev. 2.0, 11/ 00, page 265 of 1037
(5) P43/FTIC
P43/FTIC is switched as shown below according to the PCR43 bit in PCR4.
PCR43 Pin Function
0 P43 input pin
1 P43 output pin
FTIC input pin
(6) P42/FTIB
P42/FTIB is switched as shown below according to the PCR42 bit in PCR4.
PCR42 Pin Function
0 P42 input pin
1 P42 output pin
FTIB input pin
(7) P41/FTIA
P41/FTIA is switched as shown below according to the PCR41 bit in PCR4.
PCR41 Pin Function
0 P41 input pin
1 P41 output pin
FTIA input pin
(8) P40/PWM14
P40/PWM14 is switched as shown below according to the PMR40 bit in PMR4 and the
PCR40 bit in PCR4.
PMR40 PCR40 Pi n Funct ion
0 P40 input pin
0
1 P40 out put pin
1*PWM14 input pin
Note: *Don't care.
Rev. 2.0, 11/ 00, page 266 of 1037
11.6.4 Pin States
Table 11.16 shows the port 4 pin states in each operation mode.
Table 11.16 Port 4 P i n States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P47
P46/FTOB
P45/FTOA
P44/FTID
P43/FTIC
P42/FTIB
P41/FTIA
P40/
PWM14
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: Because the FTI A, FTI B, FTI C, and FTI D inputs always funct ion, t he alternative pin need
be set t o t he high or low level regardless of t he active mode and low power consumption
mode. Note that t he pin level must not r each an inter m ediat e level (excluding reset,
standby, and wat ch m odes) .
Rev. 2.0, 11/ 00, page 267 of 1037
11.7 Port 5
11.7.1 Overview
Port 5 is a 4-bit I/O port. Table 11. 17 shows the port 5 configuration.
Port 5 consists of pins that are used both as standard I/O ports (P53 to P50) and realtime output
port trigger input (TRIG), timer B event input (TMBI), or A/D conversion start external trigger
input (
$
'75*
). It is switched by port mode register 5 (PMR5), A/D trigger select register
(ADTSR), and port cont rol re gi ster 5 (PCR5).
Table 11.17 Port 5 Configuration
Port Funct ion Alte r nat ive Function
P53 (standar d I /O por t ) TRI G ( r ealt ime out put port t r igger input)
P52 (standar d I /O por t ) TM BI ( t im er B event input )
P51 (standar d I /O por t ) None
Port 5
P50 (standar d I /O por t )
$'75*
(A/D conversion star t ext er nal
trigger input)
11.7.2 Register Configuration
Table 11.18 shows the port 5 register configuration.
Table 11.18 Port 5 Regi ster Configuration
Name Abbrev. R/W Size Init ial Value Address *
Port m ode register 5 PM R5 R/W Byte H'F1 H'FFDC
Port cont r ol r egister 5 PCR5 W Byte H'F0 H'FFD5
Port dat a r egist er 5 PDR5 R/W Byte H'F0 H'FFC5
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 268 of 1037
(1) Port Mode Register 5 (PMR5)
0
1
1
0
234
11
5
1
7
1
6—————
————— R/W
PMR51
0
R/W
PMR52
0
R/W
PMR53
Bit :
Initial value :
R/W :
Port mode register 5 (PMR5) controls switching of each pin function of port 5 and specifies the
edge sense of the timer B event input (TMBI).
The switching of the P50/
$'75*
pin function is controlled by ADTSR. See section 26, A/D
Converter.
PMR5 is an 8-bit read/write enable register. When reset, PMR5 is initialized to H'F1.
If the TRIG, TMBI, and
$'75*
pin pins are set, the alternative pin need always be set to the
high or low level regardless of the active mode and low power consumption mode. Note that the
pin level must not reach an intermediate level.
Bits 7 to 4: Reserved Bits
When the bits are read, 1 is always read. The write operation is invalid.
Bit 3: P53/TRIG Pi n Switching (PMR53)
PMR53 sets whether the P53/TRIG pin is used as a P53 I/O pin or a TRIG pin for the realtime
output port t ri gger i nput .
Bit 3
PMR53 Description
0 The P53/TRIG pin f unct ions as a P53 I/ O pin (Init ial value)
1 The P53/TRIG pin f unct ions as a TRIG input pin
Bit 2: P52/TM BI Pi n Switching (PMR52)
PMR52 sets whether the P52/TMBI pin is used as a P52 I/O pin or a TMBI pin for the timer B
event i nput .
Bit 2
PMR52 Description
0 The P52/TMBI pin functions as a P52 I/O pin (Init ial value)
1 The P52/TMBI pin functions as a TMBI input pin
Rev. 2.0, 11/ 00, page 269 of 1037
Bit 1 : T i m e r B e v e nt i nput e dg e select (PMR51)
PMR51 selects the input edge sense of the TMBI pin.
Bit 1
PMR51 Description
0 The tim er B ev ent input detec t s the falling edge ( Initial value)
1 The timer B event input detects t he r ising edge
Bit 0: Reserved Bit
When the bit is read, 1 is always read. The write operation is invalid.
(2) Port Control Register 5 (PCR5)
0
0
1
0
234
11
5
1
7
1
6————
———— W
PCR51
W
PCR50
0
W
PCR52
0
W
PCR53
Bit :
Initial value :
R/W :
Port control re gi ster 5 (PCR5) cont rol s the I/ Os of pins P53 to P50 of port 5 in a uni t of bi t .
When PCR5 is set to 1, t he corre sponding P53 to P50 pins bec ome out put pi ns, a nd when i t i s set
to 0, they become input pins. When the relevant pin is set to a general I/O, settings of PCR5 and
PDR5 are valid.
PCR5 is an 8-bit write-only register. When PCR5 is read, 1 is read. When reset, PCR5 is
initialized to H'F0.
Bits 7 to 4 are re served bi t s.
Bit n
PCR5n Description
0 The P5n pin functions as an input pin (Init ial value)
1 The P5n pin functions as an output pin
(n = 3 to 0)
Rev. 2.0, 11/ 00, page 270 of 1037
(3) Port Data Register 5 (P DR5)
0
0
1
0
234
11
5
1
7
1
6————
———— R/W
PDR51
R/W
PDR50
0
R/W
PDR52
0
R/W
PDR53
Bit :
Initial value :
R/W :
Port data register 5 (PDR5) stores the data for the pins P53 to P50 of port 5. When PCR5 is 1
(output), the PDR5 values are directly read if port 5 is read. Accordingly, the pin states are not
affected. When PCR5 is 0 (input), the pin states are read if port 5 is read.
PDR5 is an 8-bit read/write enable register. When reset, PDR5 is initialized to H'F0.
Bits 7 to 4 are re served bi t s.
Rev. 2.0, 11/ 00, page 271 of 1037
11.7.3 Pin Functions
This section describes the port 5 pin functions and their selection methods.
(1) P53/TRIG
P53/TRIG is switched as shown below according to the PMR53 bit in PMR5 and the PCR53
bit in PCR5.
PMR53 PCR53 Pi n Funct ion
0 P53 input pin
0
1 P53 out put pin
1*TRIG input pin
Note: *Don't care.
(2) P52/TMBI
P52/TMBI is switched as shown below according to the PMR52 bit in PMR5 and the PCR52
bit in PCR5.
PMR52 PCR52 Pi n Funct ion
0 P52 input pin
0
1 P52 out put pin
1*TMBI input pin
Note: *Don't care.
(3) P51
P51 is switched as shown below according to the PCR51 bit in PCR5.
PCR51 Pin Function
0 P51 input pin
1 P51 output pin
(4) P50/
$'75*
P50/
$'75*
is switched as shown below according to the PCR50 bit in PCR5 and the
TRGS1 and TRG0 bits in ADTSR.
TRGS1, TRGS0 PCR31 Pin Function
0 P50 input pin
Ot her t han 11
1 P50 output pin
11 *
$'75*
input pin
Note: *Don't care.
Rev. 2.0, 11/ 00, page 272 of 1037
11.7.4 Pin States
Table 11.19 shows the port 5 pin states in each operation mode.
Table 11.19 Port 3 P i n States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P53/TRIG
P52/TMBI
P51
P50/
$'57*
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: I f the TRI G , TMBI, and
$'75*
input pins are set, the alternative pin need always be set
to t he high or low level regardless of t he act ive m ode and low power consumpt ion mode.
Note that t he pin level must not r each an intermediate level.
Rev. 2.0, 11/ 00, page 273 of 1037
11.8 Port 6
11.8.1 Overview
Port 6 is an 8-bit I/O port. Table 11. 20 shows the port 6 configuration.
Port 6 consists of pins that are used both as standard I/O ports (P67 to P60) and realtime output
ports (RP7 to RP0). It is switched by port mode register 6 (PMR6) and port control register 6
(PCR6).
The realtime output function can instantaneously switch the output data by an external or
interna l tri gge r input .
Table 11.20 Port 6 Configuration
Port Funct ion Alte r nat ive Function
P67 (standar d I /O por t ) RP7 (r ealtim e out put por t pin)
P66 (standar d I /O por t ) RP6 (r ealtim e out put por t pin)
P65 (standar d I /O por t ) RP5 (r ealtim e out put por t pin)
P64 (standar d I /O por t ) RP4 (r ealtim e out put por t pin)
P63 (standar d I /O por t ) RP3 (r ealtim e out put por t pin)
P62 (standar d I /O por t ) RP2 (r ealtim e out put por t pin)
P61 (standar d I /O por t ) RP1 (r ealtim e out put por t pin)
Port 6
P60 (standar d I /O por t ) RP0 (r ealtim e out put por t pin)
Rev. 2.0, 11/ 00, page 274 of 1037
11.8.2 Register Configuration
Table 11.21 shows the port 6 register configuration.
Table 11.21 Port 6 Regi ster Configuration
Name Abbrev. R/W Size Init i al Value Address*
Port m ode r egist er 6 PMR6 R/W Byte H'00 H'FFDD
Port cont r ol r egister 6 PCR6 W Byte H'00 H'FFD6
Port dat a r egist er 6 PDR6 R/W Byte H'00 H'FFC6
Realtime output t r igger
select register RTPSR R/W Byte H'00 H'FFE5
Realtime output t r igger
edge select register RTPEGR R/W Byte H'FC H'FFE4
Port cont r ol register
slave 6 PCRS6 Byte H'00
Port dat a r egister slave 6 PDRS6 Byte H'00
Note: *Lower 16 bits of t he addr ess.
(1) Port Mode Register 6 (PMR6)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR64 PMR63 PMR62 PMR61 PMR60
0
R/W
PMR67
R/WR/WR/W
PMR66 PMR65
Bit :
Initial value :
R/W :
Port mode register 6 (PMR6) controls switching of each pin function of port 6. The switching is
specified in units of bits.
PMR6 is an 8-bit read/write enable register. When reset, PMR6 is initialized to H'00.
Bits 7 to 0: P67/RP7 to P60/ RP0 P in Switching (PMR67 to PM R60)
PMR67 to PMR60 set whet her t he P6n/RPn pin is used as a P6n I/O pin or a n RPn pin for t he
realtime output port.
Bit n
PMR6n Description
0 The P6n/RPn pin functions as a P6n I/ O pin (Initial value)
1 The P6n/RPn pin functions as an RPn output pin
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 275 of 1037
(2) Port Control Register 6 (PCR6)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR64 PCR63 PCR62 PCR61 PCR60
0
W
PCR67
WWW
PCR66 PCR65
Bit :
Initial value :
R/W :
Port control register 6 (PCR6) selects the general I/O of port 6 and controls the realtime output
in a unit of bit together with PMR6.
When PMR6 = 0, t he c orre sponding P67 to P60 pins becom e gene ra l out put pins if PCR6 is set
to 1, a nd the y be com e gene ra l i nput pins if i t is set t o 0.
When PMR6 = 1, PCR6 controls the corresponding RP7 to RP0 realtime output pins. For
details, see section 11.8.4, Operation.
PCR6 is an 8-bit write-only register. When PCR6 is read, 1 is read. When reset, PCR6 is
initialized to H'00.
PMR6 PCR6
Bit n Bit n
PMR6n PCR6n Description
0 The P6n/RPn pin funct ions as a P6n general I/O input pin
(Init ial value)
0
1 The P6n/RPn pin funct ions as a P6n general output pin
1*The P6n/RPn pin functions as an RPn realtime out put pin
Note: *Don't care. (n = 7 to 0)
(3) Port Data Register 6 (P DR6)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR64 PDR63 PDR62 PDR61 PDR60
0
R/W
PDR67
R/WR/WR/W
PDR66 PDR65
Bit :
Initial value :
R/W :
Port data register 6 (PDR6) stores the data for the pins P67 to P60 of port 6.
For PMR6 = 0, when PCR6 is 1 (output), the PDR6 values are directly read if port 6 is read.
Accordingly, the pin states are not affected. When PCR6 is 0 (input), the pin states are read if
port 6 is read.
For PMR6 = 1, port 6 becomes a realtime output pin. For details, see section 11. 8.4, Operation.
PDR6 is an 8-bit read/write enable register. When reset, PDR6 is initialized to H'00.
Rev. 2.0, 11/ 00, page 276 of 1037
(4) Realtime Output Trigger Select Register (RTPSR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7RTPSR4 RTPSR3 RTPSR2 RTPSR1 RTPSR0
0
R/W
RTPSR7
R/WR/WR/W
RTPSR6 RTPSR5
Bit :
Initial value :
R/W :
The realtime output trigger select register (RTPSR) sets whether the external trigger (TRIG pin
input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of
bit. For the internal trigger HSW, see section 28.4, HSW Timing Generation Circuit.
RTPSR is an 8-bit read/write enable register. When reset, RTPSR is initialized to H'00.
Bit n
RTPSRn Description
0 Selects the ext ernal trigger (TRIG pin input) as a t r igger input ( I nit ial value)
1 Selects the int er nal tr igger ( HSW) a trigger input
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 277 of 1037
(5) Real Time Output Trigger Edge Select Register (RTPEGR)
0
0
1
0
R/W
2
1
3
1
4
11
56
1
7——————
——————
RTPEGR1 RTPEGR0
1R/W
Bit :
Initial value :
R/W :
The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the
external or internal trigger input for the realtime output.
RTPEGR is an 8-bit read/write enable register. When reset, RTPEGR is initialized to H'FC.
Bits 7 to 2: Reserved Bits
When the bits are read, 1 is always read. The write operation is invalid.
Bits 1 and 0: Realtime Output Trigger Edge Select (RTPEGR1, RTPEGR0)
RTPEGR1 and RTPEGR0 select the edge sense of the external or internal trigger input for the
realtime output.
Bit 1 Bit 0
RTPEGR1 RTPEGR0 Description
0 I nhibits a trigger input (Init ial value)0
1 Selects the rising edge of a t r igger input
0 Selects the falling edge of a tr igger input1
1 Select s bot h t he leading and falling edges of a t r igger input
11.8.3 Pin Functions
This section describes the port 6 pin functions and their selection methods.
(1) P67/RP7 to P60/RP0
P67/RP7 to P60/RP0 are switched as shown below according to the PMR6n bit in PMR6 and
the PCR6n bit i n PCR6.
PMR6n PCR6n Pin Function Out put Value Value When PDR6n
was read
0 P6n input pin P6n pin
0
1 P6n out put pin PDR6n
0 High-impedance*
1
1
RPn output pin
PDRS6n*
PDR6n
Note: *When PMR6n = 1 (r ealtim e out put pin) , indicates t he st ate aft er t he PCR6n setup
value has been transf er r ed t o PCRS6n by a trigger input. (n = 7 t o 0)
Rev. 2.0, 11/ 00, page 278 of 1037
11.8.4 Operation
Port 6 can be used as a realtime output port or general I/O output port by PMR6. Port 6
functions as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0.
The operation per port 6 function is shown below. (See figure 11.2.)
P6/RP
RTPEGR write
[Legend]
PMR6
PCR6
PDR6
PCRS6
PDRS6
RTPSR
RTPEGR
HSW
TRIG
: Port mode register 6
: Port control register 6
: Port data register 6
: Port control register slave 6
: Port data register slave 6
: Realtime output trigger select register
: Realtime output trigger edge select register
: Internal trigger signal
: External trigger pin
RTPSR write
RMR6 write
RDR6 write
RCR6 write
RDR6 read
RTPEGR
Selection
circuit
Selection
circuit
Internal data bus
External trigger
TRIG
Internal trigger
HSW
CK
RTPSR
CK
RMR6
CK
RDR6
CK
RCR6
CK
RDRS6
CK
RCRS6
CK
Figure 11. 2 P or t 6 Function Bloc k Diagram
Rev. 2.0, 11/ 00, page 279 of 1037
(1) Operation of the Realtime Output Port (PMR6 = 1)
When PMR6 is 1, it operates as a realtime output port. When a trigger is input, PMR6
transfers the PDR6 data to PDRS6 and the PCR6 data to PCRS6, respectively. In this case,
when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin. When
PCRS6 is 0, the RP pin of the corresponding bit is output to the high-impedance state. In
other words, the pin output state (High or Low) or high-impedance state can instantaneously
be switched by a trigger input.
Adversely, when PDR6 is read, t he PDR6 value s are rea d re gardl e ss of the PCR6 and PCRS6
values.
(2) Operation of t he gene ra l I/ O port (PMR6 = 0)
When PMR6 is 0, it operates as a general I/O port. When data is written to PDR6, the same
data is also written to PDRS6. Accordingly, because both PDR6 and PDRS6 and both PCR6
and PCRS6 can be handled as one register, respectively, they can be used in the same way as
a normal general I/O port. In other words, if PCR6 is 1, the PDR6 data of the corresponding
bit is output t o the P6 pin. If PCR6 is 0, t he P6 pin of the c orresponding bi t bec om es an
input.
Adversely, a ssuming tha t PDR6 is read, the PDR6 value s are re a d when PCR6 is 1 and the
pin value s are rea d when PCR6 is 0.
11.8.5 Pin States
Table 11.22 shows the port 6 pin states in each operation mode.
Table 11.22 Port 6 P i n States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P67/RP7 to
P60/RP0 High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Rev. 2.0, 11/ 00, page 280 of 1037
11.9 Port 7
11.9.1 Overview
Port 7 is an 8-bit I/O port. Table 11. 23 shows the port 7 configuration.
Port 7 consists of pins that are used both as standard I/O ports (P77 to P70) and HSW timing
generation circuit (programmable pattern generator: PPG) o u t p uts (PPG7 to PPG0 ). It is
switched by port mode register 7 (PMR7) and port control register 7 (PCR7).
For the programmable generator (PPG), see section 28.4, HSW Timing Generation Circuit.
Table 11.23 Port 7 Configuration
Port Funct ion Alte r nat ive Function
P77 (standar d I /O por t ) PPG7 ( HSW t iming out put )
P76 (standar d I /O por t ) PPG6 ( HSW t iming out put )
P75 (standar d I /O por t ) PPG5 ( HSW t iming out put )
P74 (standar d I /O por t ) PPG4 ( HSW t iming out put )
P73 (standar d I /O por t ) PPG3 ( HSW t iming out put )
P72 (standar d I /O por t ) PPG2 ( HSW t iming out put )
P71 (standar d I /O por t ) PPG1 ( HSW t iming out put )
Port 7
P70 (standar d I /O por t ) PPG0 ( HSW t iming out put )
11.9.2 Register Configuration
Table 11.24 shows the port 7 register configuration.
Table 11.24 Port 7 Regi ster Configuration
Name Abbrev. R/W Size Init i al Value Address*
Port m ode r egist er 7 PMR7 R/W Byte H'00 H'FFDE
Port cont r ol r egister 7 PCR7 W Byte H'00 H'FFD7
Port cont r ol r egister 7 PDR7 R/W Byte H'00 H'FFC7
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 281 of 1037
(1) Port Mode Register 7 (PMR7)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR74 PMR73 PMR72 PMR71 PMR70
0
R/W
PMR77
R/WR/WR/W
PMR76 PMR75
Bit :
Initial value :
R/W :
Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is
specified in a unit of bit.
PMR7 is an 8-bit read/write enable register. When reset, PMR7 is initialized to H'00.
Bits 7 to 0: P77/PPG7 to P70/PPG0 Pin Switching (PMR77 to PMR70)
PMR77 to PMR70 set whe t he r t he P7n/ PPGn pin i s use d a s a P7n I/ O pi n or a PPGn pi n for t he
HSW timing generation circuit output.
Bit n
PMR7n Description
0 The P7n/PPGn pin funct ions as a P7n I/ O pin (Init ial value)
1 The P7n/PPGn pin funct ions as a PPGn out put pin
(n = 7 to 0)
(2) Port Control Register 7 (PCR7)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR74 PCR73 PCR72 PCR71 PCR70
0
W
PCR77
WWW
PCR76 PCR75
Bit :
Initial value :
R/W :
Port control re gi ster 7 (PCR7) cont rol s the I/ Os of pins P77 to P70 of port 7 in a uni t of bi t .
When PCR7 is set to 1, t he corre sponding P77 to P70 pins bec ome out put pi ns, a nd when i t i s set
to 0, t hey be c ome i nput pi ns. W he n the c orresponding pi n i s set to t he gene ra l I/ O by PMR7,
settings of PCR7 and PDR7 become valid.
PCR7 is an 8-bit write-only register. When PCR7 is read, 1 is read. When reset, PCR7 is
initialized to H'00.
Bit n
PCR7n Description
0 The P7n pin functions as an input pin (Init ial value)
1 The P7n pin functions as an output pin
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 282 of 1037
(3) Port Data Register 7 (P DR7)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR74 PDR73 PDR72 PDR71 PDR70
0
R/W
PDR77
R/WR/WR/W
PDR76 PDR75
Bit :
Initial value :
R/W :
Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7.
When PCR7 is 1 (output), the PDR7 values are directly read if port 7 is read. Accordingly, the
pin states are not affected. When PCR7 is 0 (input), the pin states are read if port 7 is read.
PDR7 is an 8-bit read/write enable register. When reset, PDR7 is initialized to H'00.
11.9.3 Pin Functions
This section describes the port 7 pin functions and their selection methods.
(1) P7 7 / PPG7 t o P70 / PPG0
P77/ PPG7 t o P70 / PPG0 a r e switched as shown below according to the PMR7n bit in PMR7
and the PCR7n bit i n PCR7.
PMR7n PCR7n Pin Functi on
0 P7n input pin
0
1 P7n output pin
1*PPGn input pin
Note: *Don't care. (n = 7 to 0)
11.9.4 Pin States
Table 11.25 shows the port 7 pin states in each operation mode.
Table 11.25 Port 7 P i n States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P77/PPG7
to
P70/PPG0
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Rev. 2.0, 11/ 00, page 283 of 1037
11.10 Port 8
11.10.1 Overview
Port 8 is an 8-bit I/O port. Table 11. 26 shows the port 8 configuration.
Port 8 is a CMOS hi gh-c urre nt I/ O port. The si nk c urrent i s 20 mA m a x. (V OL = 1. 5 V) and up
to four pins can simultaneously be set on.
Port 8 consists of pins that a re used both a s high-c urrent I/ O ports (P87 to P80) and servo
monitor out put (SV1, SV2), capsta n e xte rna l synchronous signal i nput (E XCAP), or exte rna l
trigger signal input (EXTTRG). It is switched by port mode register 8 (PMR8) and port control
register 8 (PCR8).
Table 11.26 Port 8 Configuration
Port Funct ion Alter native Function
P87 (high-curr ent I/O por t) None
P86 (high-curr ent I/O por t) None
P85 (high-curr ent I/O por t) None
P84 (high-curr ent I/O por t) None
P83 (high-curr ent I/O por t) SV2 (ser vo m onit or out put )
P82 (high-curr ent I/O por t) SV1 (ser vo m onit or out put )
P81 (high-current I/ O por t) EXCAP (capstan exter nal synchronous signal input)
Port 8
P80 (high-curr ent I/O por t) EXTTRG (external tr igger signal input)
11.10.2 Register Configuration
Table 11.27 shows the port 8 register configuration.
Table 11.27 Port 8 Regi ster Configuration
Name Abbrev. R/W Size Init ial Value Address *
Port m ode register 8 PM R8 R/W Byte H'F0 H'FFDF
Port cont r ol r egister 8 PCR8 W Byte H'00 H'FFD8
Port dat a r egist er 8 PDR8 R/W Byte H'00 H'FFC8
Note: *The address indicates t he low-order 16 bit s.
Rev. 2.0, 11/ 00, page 284 of 1037
(1) Port Mode Register 8 (PMR8)
0
0
1
0
R/W
2
0
R/W
3
0
4
11
56
1
7————
————
PMR83 PMR82 PMR81 PMR80
1R/WR/W
Bit :
Initial value :
R/W :
Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is
specified in a unit of bit.
PMR8 is an 8-bit read/write enable register. When reset, PMR8 is initialized to H'F0.
If the EXCAP and EXTTRG input pi ns are set , t he pi n l eve l nee d a lways be set t o the hi gh or
low level regardless of the active mode and low power consumption mode. Note that the pin
level must not reach an intermediate level.
Bits 7 to 4: Reserved Bits
When the bits are read, 1 is always read. The write operation is valid.
Bit 3: P83/SV2 Pin Switching (PMR83)
PMR83 sets whether the P83/SV2 pin is used as a P83 I/O pin or an SV2 pin for the servo
monitor output. For the selection of the SV2 output, see section 28, Servo Circuit.
Bit 3
PMR83 Description
0 The P83/SV2 pin functions as a P83 I/ O pin (Init ial value)
1 The P83/SV2 pin functions as an SV2 output pin
Bit 2: P82/SV1 Pin Switching (PMR82)
PMR82 sets whether the P82/SV1 pin is used as a P82 I/O pin or an SV1 pin for the servo
monitor output. For the selection of the SV1 output, see section 27, Servo Circuit.
Bit 2
PMR82 Description
0 The P82/SV1 pin functions as a P82 I/ O pin (Init ial value)
1 The P82/SV1 pin functions as an SV1 output pin
Rev. 2.0, 11/ 00, page 285 of 1037
Bit 1 : P81 / E XCAP P in Swit c hing (PMR8 1 )
PMR81 sets whether the P83/EXCAP pin is used as a P81 I/O pin or an E XTT RG pin for the
capstan e xt erna l synchronous signal i nput .
Bit 1
PMR81 Description
0 The P81/EXCAP pin f unctions as a P81 I/O pin (Initial value)
1 The P81/EXCAP pin f unctions as an EXCAP input pin
Bit 0: P80/EXTTRG Pi n Switching (PMR80)
PMR80 sets whether the P80/EXTT RG pin i s used as a P80 I/O pin or an E XTT RG pin for the
externa l tri gge r signal i nput.
Bit 0
PMR80 Description
0 The P80/EXTTRG pin functions as a P80 I/O pin ( I nit ial value)
1 The P80/EXTTRG pin functions as an EXTTRG input pin
(2) Port Control Register 8 (PCR8)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR84 PCR83 PCR82 PCR81 PCR80
0
W
PCR87
WWW
PCR86 PCR85
Bit :
Initial value :
R/W :
Port control re gi ster 8 (PCR8) cont rol s the I/ Os of pins P87 to P80 of port 8 in a uni t of bi t .
When PCR8 is set to 1, t he corre sponding P87 to P80 pins bec ome out put pi ns, a nd when i t i s set
to 0, they become input pins. When the corresponding pin is set to a general I/O, settings of
PCR8 and PDR8 become valid.
PCR8 is an 8-bit write-only register. When PCR8 is read, 1 is read. When reset, PCR8 is
initialized to H'00.
Bit n
PCR8n Description
0 The P8n pin functions as an input pin (Init ial value)
1 The P8n pin functions as an output pin
(n = 7 to 0)
Rev. 2.0, 11/ 00, page 286 of 1037
(3) Port Data Register 8 (P DR8)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR84 PDR83 PDR82 PDR81 PDR80
0
R/W
PDR87
R/WR/WR/W
PDR86 PDR85
Bit :
Initial value :
R/W :
Port data register 8 (PDR8) stores the data for the pins P87 to P80 of port 8.
When PCR8 is 1 (output), the PDR8 values are directly read if port 8 is read. Accordingly, the
pin states are not affected. When PCR8 is 0 (input), the pin states are read if port 8 is read.
PDR8 is an 8-bit read/write enable register. When reset, PDR8 is initialized to H'00.
11.10.3 Pin Functions
This section describes the port 8 pin functions and their selection methods.
(1) P87 to P84
P87 to P84 are switched as shown below according to the PCR8n bit in PCR8.
PCR8n Pin Function
0 P8n input pin
1 P8n output pin
(n = 7 to 4)
Note: *Don't care.
(2) P83/SV2
P83/SV2 is switched as shown below according to the PMR83 bit in PMR8 and the PCR83
bit in PCR8.
PMR83 PCR83 Pi n Funct ion
0 P83 input pin
0
1 P83n out put pin
1*SV2 output pin
Note: *Don't care.
Rev. 2.0, 11/ 00, page 287 of 1037
(3) P82/SV1
P82/SV1 is switched as shown below according to the PMR82 bit in PRM8 and the PCR82
bit in PCR8.
PMR82 PCR82 Pi n Funct ion
0 P82 input pin
0
1 P82 out put pin
1*SV1 output pin
Note: *Don't care.
(4) P81/EXCAP
P81/EXCAP is switched as shown below according to the PMR81 bit in PRM8 and the
PCR81 bit in PCR8.
PMR81 PCR81 Pi n Funct ion
0 P81 input pin
0
1 P81 out put pin
1*EXCAP input pin
Note: *Don't care.
(5) P80/EXTTRG
P80/EXTTRG is switched as shown below according to the PMR80 bit in PRM8 and the
PCR80 bit in PCR8.
PMR80 PCR80 Pi n Funct ion
0 P80 input pin
0
1 P80 out put pin
1*EXTTRG input pin
Note: *Don't care.
Rev. 2.0, 11/ 00, page 288 of 1037
11.10.4 P in States
Table 11.28 shows the port 8 pin states in each operation mode.
Table 11.28 Port 8 P i n States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P87 to P8 4
P83/SV2
P83/SV1
P81/
EXCAP
P80/
EXTTRG
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: I f t he EXCAP and EXTTRG input pins are set, t he pin level need always be set to the high
or low level regardless of the act ive m ode and low power consumpt ion mode. Note that
the pin level must not r each an inter mediate level.
Rev. 2.0, 11/ 00, page 289 of 1037
Section 12 Timer A
12.1 Overview
The Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a
32.768 kHz crystal oscillator.
12.1.1 Features
Features of the Timer A are as follows:
• Choices of eight different types of internal clocks (φ/16384, φ/8192, φ/4096, φ/1024, φ/512,
φ/256, φ/64 and φ/16) are available for your selection.
• Four different overflowing cycles (1s, 0.5s, 0.25s and 0.03125s) are selectable as a clock
timer. (When using a 32.768 kHz crystal oscillator.)
• Requests for interrupt will be output when the counter overflows.
Rev. 2.0, 11/ 00, page 290 of 1037
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the Timer A.
[Legend]
TMA
32 kHz
Crystal oscillator
Overflowing of
the interval
timer
System
clock
w
w/128
/16384, /8192,
/4096, /1024,
/512, /256,
/64, /16
TCA
: Timer mode register A
: Timer counter A
Note: * Selectable only when the prescaler W output ( w/128) is
working as the input clock to the TCA.
Prescaler S
(PSS) Interrupting
circuit
Prescaler unit
Prescaler W
(PSW)
TCA
1/4 TMA
Interrupt
requests
Internal data bus
8 *
64 *
128 *
256 *
Figure 12. 1 Bl oc k Diagram of the Time r A
12.1.3 Register Configuration
Table 12.1 shows the register configuration of the Timer A.
Table 12.1 Register configuration
Name Abbrev. R/W Size Init i al Value Address*
Timer m ode r egist er A TMA R/W Byte H'30 H'FFBA
Timer count er A TCA R Byte H'00 H'FFBB
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 291 of 1037
12.2 Descripti on s of Respective Regi st ers
12.2.1 Timer Mode Register A (TMA)
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5——
——
1
6
0
7
R/WR/WR/W
TMAIE
0
R/(W)*
TMAOV TMA3 TMA2 TMA1 TMA0
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer mode register A (TMA) works to control the interrupts of the Timer A and to select
the input c loc k.
TMA is an 8-bit read/write register. When reset, the TMA will be initialized to H'30.
Bit 7: Timer A Ove rfl ow Fl ag (TMAOV)
This is a status flag indicating the fact that the TCA is overflowing (H'FF → H'00).
Bit 7
TMAOV Description
0 [Clearing conditions] (Init ial value)
When 0 is written to the TM AO V flag af t er r eading t he TM AO V f lag under t he st atus
where TMAO V = 1
1 [Sett ing conditions]
When the TCA overf lows
Bit 6: Enabling Interrupt of the Timer A (TMAIE)
This bit works to permit/prohibit occurrence of interrupt of the Timer A (TMAI) when the TCA
ove r flows a n d when t h e T MAOV o f t h e T MA is set to 1 .
Bit 6
TMAIE Description
0 Prohibits occurr ence of interr upt of t he Timer A (TMAI) (Initial value)
1 Permit s occur r ence of interr upt of the Timer A ( TM AI)
Bits 5 and 4: Reserved
When they are read, 1 will always be readout. Writes are disabled.
Rev. 2.0, 11/ 00, page 292 of 1037
Bit 3: Selection of the Clock Source and Prescaler (TMA3)
This bit works to select the PSS or PSW as t he c l oc k sourc e for t he Timer A.
Bit 3
TMA3 Description
0 Sele cts the PSS a s the c loc k s o urce for th e Tim e r A ( Init ia l v alu e )
1 Selects the PSW as the clock source f or t he Tim er A
Bits 2 to 0: Clock Selection (TMA2 to TMA0)
These bits work to select the clock to input to the TCA. In combination with the TMA3 bit, the
choices are as follows:
Bit 3 Bit 2 Bit 1 Bit 0
TMA3 TMA2 TMA1 TMA0 Prescaler di vision r at i o ( inter val t imer )
or overf l ow cycle ( t ime base) Operation
mode
0 PSS, φ/16384 (Initial value)0
1 PSS, φ/8192
0 PSS, φ/4096
0
1
1 PSS, φ/1024
0 PSS, φ/5120
1 PSS, φ/256
0 PSS, φ/64
0
1
1
1 PSS, φ/16
Interval
timer mode
01s0
10.5s
0 0.25s
0
1
1 0.03125s
00
1
0
1
1
1
1
Works t o clear the PSW and TCA to H'00
Clock time
base mode
Note: φ = f osc
Rev. 2.0, 11/ 00, page 293 of 1037
12. 2 .2 Ti mer Co unt e r A ( T CA)
0
0
1
0
R
2
0
R
3
0
4567
RR
TCA3
0
R
TCA4
0
R
TCA5
0
R
TCA6
0
R
TCA7 TCA2 TCA1 TCA0
Bit :
Initial value :
R/W :
The timer counter A (TCA) is an 8-bit up-counter which counts up on inputs from the internal
clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA
When t h e TCA ov e r f l o ws, the T MAOV b i t of the TMA is set to 1.
The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11.
The TCA is always readable. When reset, the TCA will be initialized into H'00.
12. 2 .3 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP15 bit is set to 1, the Timer A stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop
Mode. When reset, the MSTPCR will be initialized into H'FFFF.
Bit 7: Module Stop (MSTP15)
This bit works to designate the module stop mode for the Timer A.
MSTPCRH
Bit 7
MSTP15 Description
0 Cancels t he m odule st op m ode of the Timer A
1 Sets the module st op m ode of t he Tim er A (Initial value)
Rev. 2.0, 11/ 00, page 294 of 1037
12.3 Operation
The Timer A is an 8-bit timer for use as an interval timer and as a clock time base connecting to
a 32.768 kHz crystal oscillator.
12.3.1 Operation as the Interval Timer
When the TMA3 bit of the TMA is cleared to 0, the Timer A works as an 8-bit interval timer.
When resetince the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A
continues counting up as the interval counter without interrupts right after resetting.
As the operation clock for the Timer A, selection can be made from eight different types of
int erna l c l oc k s bei ng out put from t he PSS by t he T MA2 t o T MA0 bi t s of t he T MA.
When the clock signal is input after the reading of the TCA reaches H'FF, the Timer A
ove r flows a n d t h e T MAOV b i t of the T MA w ill be set to 1. At this time, when the TMAIE bit
of the TMA is 1, i nte rrupt occ urs.
When overfl owing oc curs, the re adi ng of t he T CA ret urns to H'00 be fore re sumi ng count i ng up.
Consequently, it works as the interval timer to produce overflow outputs periodically at every
256 input cl oc ks.
12.3.2 Operation of the Timer for Cloc ks
When the TMA3 bit of the TMA is set to 1, the Timer A works as a time base for the clock.
As the overflow cycles for the Timer A, selection can be made from four different types by
counting t he cl oc k bei ng out put from t he PSW by the T MA1 bit and T MA0 bit of t he T MA.
12.3.3 Initializing the Counts
When the TMA3 and TMA2 bits are set to 11, the PSW and TCA will be cleared to H'00 to
come to a stop.
At this state, writing 10 to the TMA3 bit and TMA2 bit makes the Timer A to start counting
from H'00 under the time base mode for clocks.
After clearing the PSW and TCA using the TMA3 and TMA2 bits, writing 00 or 01 to the
TMA3 bit and TMA2 bit work to make the Timer A to start counting from H'00 under the
interval timer mode. However, since the PSS is not cleared, the period to the first count is not
constant.
Rev. 2.0, 11/ 00, page 295 of 1037
Section 13 Timer B
13.1 Overview
The Timer B is an 8-bit up-counter. The Timer B is equipped with two different types of
functions namely, the interval function and the auto reloading function.
13.1.1 Features
• Selection from choices of seven different types of internal clocks (φ/16384, φ/4096, φ/1024,
φ/512, φ/128, φ/32 and φ/8) or selection of external clock are possible.
• When the counter overflows, a interrupt request will be issued.
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the Timer B.
[Legend]
TMB
/16384
/4096
/1024
/512
/128
/32
/8
TMBI
TCB : Timer mode register B
: Timer counter B
TLB
TMBI : Timer re-loading register B
: Event input terminal of the Timer B
Re-loading
Clock sources
Overflowing
Timer B
Interrupt requests
Internal data bus
TCB
TMB
TLB
Interrupting
circuit
Figure 13. 1 Bl oc k diagram of the Time r B
Rev. 2.0, 11/ 00, page 296 of 1037
13.1.3 Pin Configuration
Table 13.1 shows the pin configuration of the Timer B.
Table 13.1 Pin Configuration
Name Abbrev. I/O Function
Event inputs t o t he Timer B TMBI I nput Event input pin f or inputs to the TCB
13.1.4 Register Configuration
Table 13.2 shows the register configuration of the Timer B.
The TCB and TLB are being allocated to the same address. Reading or writing determines the
accessing register.
Table 13.2 Register Configuration
Name Abbrev. R/W Size Init i al Value Address*
Timer m ode r egister B TMB R/W Byt e H'18 H'D110
Timer count er B TCB R Byte H'00 H'D111
Timer load register B TLB W Byte H'00 H'D111
Port m ode register 5 PM R5 R/W Byte H'F1 H'FFDC
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 297 of 1037
13.2 Descripti on s of Respective Regi st ers
13.2.1 Timer Mode Register B (TM B)
0
0
1
0
R/W
2
0
R/W
3
1
4
——
——
1
5
0
6
0
7
R/WR/W
TMBIE
R/(W)*
TMBIF
0
R/W
TMB17 TMB12 TMB11 TMB10
Note: Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The TMB is an 8-bit read/write register which works to control the interrupts, to select the auto
reloading function and to select the input clock.
When reset, the TMB is initialized to H'18.
Bit 7: Selecting the Auto Reloading Function (TMB17)
This bit works to select the auto reloading function of the Timer B.
Bit 7
TMB17 Description
0 Selects the int er val f unct ion (Init ial value)
1 Selects the aut o reloading function
Bit 6: Interrupt Requesting Flag for the Timer B (TM BIF)
This is an interrupt requesting flag for the Timer B. It indicates the fact that the TCB is
overflowing.
Bit 6
TMBIF Description
0 [Clearing conditions] (Init ial value)
When 0 is written after r eading 1
1 [Sett ing conditions]
When the TCB overf lows
Rev. 2.0, 11/ 00, page 298 of 1037
Bit 5: Enabling Interrupt of the Timer B (TMBIE)
This bit works to permit/prohibit occurrence of interrupt of the Timer B when the TCB
overflows and when the TMBIF is set to 1.
Bit 5
TMBIE Description
0 Prohibits occurr ence of interr upt of t he Timer B (Initial value)
1 Permit s occur r ence of interr upt of the Timer B
Bits 4 to 3: Reserved
When they are read, 1 will always be readout. Writes are disabled.
Bits 2 to 0: Clock Selection (TMB12 to TMB10)
These bits work to select the clock to input to the TCB. Selection of the rising edge or the
falling edge is workable with the external event inputs.
Bit 2 Bit 1 Bit 0
TMB12 TMB11 TMB10 Descriptions
0 0 0 Internal clock: Counts at φ/ 16384 (Initial value)
0 0 1 Internal clock: Counts at φ/4096
0 1 0 Internal clock: Counts at φ/1024
0 1 1 Internal clock: Counts at φ/512
1 0 0 Internal clock: Counts at φ/128
1 0 1 Internal clock: Counts at φ/32
1 1 0 Internal clock: Counts at φ/8
1 1 1 Counts at the rising edge and the f a lling edge of external
event inputs ( TMBI ) *
Note: *The edge selection for t he ext er nal event inputs is m ade by set t ing t he PM R51 of t he
port m ode register 5 ( PM R5). See sect ion 13. 2. 4, Por t M ode Register 5 ( PM R5).
Rev. 2.0, 11/ 00, page 299 of 1037
13.2.2 Timer Counter B (TCB)
0
0
1
0
R
2
0
R
345
0
6
0
7
RR
TCB15
0
R
TCB14
0
R
TCB13
R
TCB16
0
R
TCB17 TCB12 TCB11 TCB10
Bit :
Initial value :
R/W :
The TCB i s an 8-bi t re a dabl e regi ste r which works to count up by t he i nt erna l cl oc k input s and
external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB.
When the T CB overfl ows (H'FF → H'00 or H' FF → TLB setting), a interrupt request of the
Timer B will be issued.
When reset, the TCB is initialized to H'00.
13.2.3 Timer Load Register B (TLB)
0
0
1
0
W
2
0
W
345
0
6
0
7
WW
TLB15
0
W
TLB14
0
W
TLB13
W
TLB16
0
W
TLB17 TLB12 TLB11 TLB10
Bit :
Initial value :
R/W :
The TLB is an 8-bit write only register which works to set the reloading value of the TCB.
When the reloading value is set to the TLB, the value will be simultaneously loaded to the TCB
and the TCB starts counting up from the set value. Also, during an auto reloading operation,
when the TCB overflows, the value of the TLB will be loaded to the TCB. Consequently, the
overflowing cycle can be set within the range of 1 to 256 input clocks.
When reset, the TLB is initialized to H'00.
Rev. 2.0, 11/ 00, page 300 of 1037
13.2.4 Port M ode Regi ster 5 (P M R5)
01
0
R/W
2
0
R/W
34
1
567
————
—
—
————
PMR52
0
R/W
PMR53 PMR51
1111
Bit :
Initial value :
R/W :
The port mode register 5 (PMR5) works to changeover the pin functions of the port 5 and to
designate the edge sense of the event inputs of the Timer B (TMBI).
The PMR5 is an 8-bit read/write register. When reset, the PMR5 will be initialized to H'F1.
See section 11.7, Port 5 for other information than bit 1.
Bit 1: Selecting the Edges of the Event Inputs to t he T i m e r B (PM R51 )
This bit works to select the input edge sense of the TMBI pins.
Bit 1
PMR51 Description
0 Detects t he f alling edge of t he event inputs to the Timer B (Init ial value)
1 Detects t he r ising edge of t he event input s t o the Timer B
13. 2 .5 Module St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP14 bit is set to 1, the Timer B stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module stop
mode.
When reset, the MSTPCR is initialized to H'FFFF.
Rev. 2.0, 11/ 00, page 301 of 1037
Bit 6: Module Stop (MSTP14)
This bit works to designate the module stop mode for the Timer B.
MSTPCRH
Bit 6
MSTP14 Description
0 Cancels t he m odule st op m ode of the Timer B
1 Sets the module st op m ode of t he Tim er B (Initial value)
Rev. 2.0, 11/ 00, page 302 of 1037
13.3 Operation
13.3.1 Operation as the Interval Timer
When the TMB17 bit of the TMB is set to 0, the Timer B works as an 8-bit interval timer.
When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, the Timer B
continues counting up as the interval timer without interrupts right after resetting.
As the clock source for the Timer B, selection can be made from seven different types of
internal clocks being output from the prescaler unit by the TMB12 to TMB10 bits of the TMB or
an external clock through the TMBI input pin can be chosen instead.
When the clock signal is input after the reading of the TCB reaches H'FF, the Timer B overflows
and the TMBIF bit of the TMB will be set to 1. At this time, when the TMBIE bit of the TMB is
1, int errupt oc curs.
When overfl owing oc curs, the re adi ng of t he T CB re turns to H' 00 before re suming c ount ing up.
When a value is set to the TLB while the interval timer is in operation, the value which has been
set to the TLB will be loaded to the TCB simultaneously.
13.3.2 Operation as the Auto Rel oad Time r
When the TMB17 of the TMB is set to 1, the Timer B works as an 8-bit auto reload timer.
When a reload value is set in the TLB, the value is loaded onto the TCB at the same time, and
the TCB sta rt s counti ng up from the va lue .
When the clock signal is input after the reading of the TCB reaches H'FF, the Timer B overflows
and the T L B val ue is loa de d onto t he TCB, t he n the T CB cont i nues count i ng up from t he loa de d
value. Acc ordi ngly, ove rfl ow inte rva l c a n be set wit hin t he range of 1 t o 256 cl oc ks dependi ng
on the TLB value.
Clock source and interrupts in the auto reload operation are the same as those in the interval
operation. When the TLB value is re-set while the auto reload timer is in operation, the value
which has been set to the TLB will be loaded onto the TCB simultaneously.
13.3.3 Event Counter
The Timer B works as an event counter using the TMBI pin as the event input pin. When the
TMB12 to TMB10 are set to 111, the external event will be selected as the clock source and the
TCB counts up at the leading edge or the trailing edge of the TMBI pin inputs.
Rev. 2.0, 11/ 00, page 303 of 1037
Section 14 Timer J
14.1 Overview
The Timer J consists of twin 8-bit counters. It carries seven different operation modes such as
reloading and event counting.
14.1.1 Features
The Timer J consists of twin 8-bit reloading timers and it is usable under the various functions as
follows:
(a) Twin 8-bit reloading timers (Among the two, one is capable to make timer outputs)
(b) Twin 8-bit event counters (Capable to make reloading)
(c) 8-bit event counter (Capable to make reloading) + 8-bit reload timer
(d) 16-bit eve nt count e r (Capa bl e t o m ake 16-bi t re l oadi ng)
(e) 16-bit reload timer (Capable to make 16-bit reloading)
(f) Remote controlled transmissions
(g) "Take up/Supply reel pulse" dividing (8 bit × 2 uni ts)
14.1.2 Block Diagram
Figure 14.1 is a block diagram of the Timer J. The Timer J consists of two reload timers
namely, TMJ-1 and TMJ-2.
Rev. 2.0, 11/ 00, page 304 of 1037
[Legend]
TCJ
Note: * At the Low level under the timer mode.
TLJ
: Timer counter J
: Timer load register J
TCK
TLK
: Timer counter K
: Timer load register K
TMO
REMOout
: TMJ-1 timer output
: TMJ-2 toggle output
(Remote controller
transmission data)
BUZZ
Reloading register
(Burst/space
width register PS21,20
: Buzzer output
TGL : TMJ-2 toggle plug
PS21,20
ST
: TMJ-2 input clock selection
: Starting the remote controlled operation
PS11,10 : TMJ-1 input clock selection
8/16
T/R
: 8-bit/16-bit operation changeover
: Timer output/Remote controller output changeover
Internal data bus
Edge
detection
Toggle
T/R
Down-counter
(8-bit)
BUSS
Output
Control
Monitor
Output
Control
Toggle
Reloading
register
8/16
ST
PS11,10
Down-
counter (8-bit)
UnderÐ
flow Under-
flow
TCJ
TMJ-1 TMJ-2 TCK
PB/REC-CTL
DVCTL
TCA7
/4096
/8192
TGL
REMOout
TMO
TMO
BUZZ
Clock sources
IRQ2
/1024 (only for the H8S/2194C series)
/2048
/16384
Clock sources
IRQ1
/4
/256
/512
*
Synchronization
TLJ
Reloading
Reloading
TLK
TMJ-1
Interrupting circuit Interrupt request
by the TMJ1
Interrupt request
by the TMJ2
TMJ-2
Interrupting circuit
Figure 14. 1 Bl oc k Diagram of the Time r J
Rev. 2.0, 11/ 00, page 305 of 1037
14.1.3 Pin Configuration
Table 14.1 shows the pin configuration of the Timer J.
Table 14.1 Pin Configuration
Name Abbrev. I/O Function
Event input pin
,54
Input Event inputs t o t he TM J- 1
Event input pin
,54
Input Event inputs t o t he TM J- 2
14.1.4 Register Configuration
Table 14.2 shows the register configuration of the Timer J.
The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively.
Reading or writing determines the accessing register.
Table 14.2 Register Configuration
Name Abbrev. R/W Size Init ial Value Address *2
Timer m ode r egister J TMJ R/W Byte H'00 H'D13A
Timer J cont r ol regist er TMJC R/W Byt e H'09 H'D13B
Timer J status register TMJS R/(W)*1Byte H'3F H'D13C
Timer count er J TCJ R Byte H'FF H'D139
Timer count er K TCK R Byte H'FF H'D138
Timer load register J TLJ W Byte H'FF H'D139
Timer load register K TLK W Byte H'FF H'D138
Notes: 1. Only 0 can be written to clear t he f lag.
2. Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 306 of 1037
14.2 Descripti on s of Respective Regi st ers
14.2.1 Timer Mode Register J (TM J)
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ST
R/W
PS10
0
R/W
PS11 8/16 PS21 PS20 TGL T/R
Bit :
Initial value :
R/W :
The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2
and to set the operation mode.
The TMJ is an 8-bit register and Bit-1 is for read only and all the remaining bits are applicable
to read/write.
When reset, the TMJ is initialized to H'00.
Under all other modes than the remote controlling mode, writing into the TMJ works to initialize
the counters (TCJ and TCK) to H'FF.
Bits 7 and 6: Selecting the Inputti ng Cl oc k to the TM J-1 (P S11 and P S10)
These bits work to select the clock to input to the TMJ-1. Selection of the rising edge or the
falling edge is workable for counting by use of an external clock.
Bit 7 Bit 6
PS11 PS10 Description
0 Count ing by t he PSS, φ/512 (Initial value)0
1 Count ing by t he PSS, φ/256
0 Count ing by t he PSS, φ/41
1 Count ing at the rising edge or t he falling edge of t he ex t er nal c lock
inputs (
,54
) *
Note: *The edge selection for t he ext er nal clock inputs is made by setting the edge select
register ( IEGR). See sect ion 6.2.4, Edge Select Register (I EG R) f or m or e infor m at ion.
When using an ext er nal clock under the r em ote cont r olling m ode, s et the opposite
edge with the IRQ 1 and t he IRQ2 when using an external clock under t he r emote
contr olling mode. ( W hen I RQ 1 f alling, select IRQ2 r ising and when I RQ 1 r ising, s elect
IRQ2 falling)
Rev. 2.0, 11/ 00, page 307 of 1037
Bit 5: Starting the Remote Controlled Operation (ST)
This bit works to start the remote controlled operations.
When this bit is set to 1, clock signal is supplied to the TMJ-1 to start signal transmissions.
When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be
valid under the remote controlling mode, namely, when the Bit 0 (T/R bit) is 1 and the Bit 4
(8/16 bit) i s 0.
Under other modes than the remote controlling mode, it will be fixed to 0. When a shift to the
low power consumption mode is made during remote controlled operation, the ST bit will be
cleared to 0. When resuming operation after returning to the active mode, write 1.
Bit 5
ST Description
0 Wor ks to stop c lock signal supply to the TM J - 1 under t he r e m ot e c ont r olling m ode
(Init ial value)
1 Wor ks to supply clock signal t o t he TMJ-1 under the rem ot e c ont r olling mode
Bit 4: Switching Over Be twee n 8-bit/16-bit Oper ati ons (8/16)
This bit works to choose if using the Timer J as two units of 8-bit timer/counter or if using it as a
single unit of 16-bit timer/counter. Even under 16-bit operations, TMJ1I interrupt requests from
the TMJ-1 will be valid.
Bit 4
8/16 Description
0 Makes t he TM J- 1 and TM J- 2 oper ate separat ely (Init ial value)
1 Makes t he TM J- 1 and TM J- 2 oper ate altogether as 16-bit t im er / count er
Rev. 2.0, 11/ 00, page 308 of 1037
Bits 3 and 2: Selecting the Inputti ng Cl oc k to the TM J-2 (P S21 and P S20)
This bit works to select the clock to input to the TMJ-2. Selection of the leading edge or the
trailing edge is workable for counting by use of an external clock.
TMJC:Bit0 Bit 3 Bit 2
PS22*3PS21 PS20 Description
0 Counting by t he PSS, φ/ 16384 ( Initial value)0
1 Counting by t he PSS, φ/2048
0 Counting at underf lowing of the TMJ-1
1
1
1 Counting at t he leading edge or the tr ailing edge of
the exter nal clock inputs (
,54
) *1
0**2**2Counting by t he PSS, φ/1024 (available only the
H8S/2194C series)
Notes: 1. The edge selection for the ext er nal clock inputs is made by sett ing t he edge select
register ( IEGR). See sect ion 6.2.4, Edge Select Register (I EG R) f or m or e infor m at ion.
2. Don't care.
3. Available only in the H8S/2194C series.
Bit 1: TMJ-2 Toggle F lag (TG L)
This flag indicates the toggled status of the underflowing with the TMJ-2. Reading only is
workable.
It will be cleared to 0 under the low power consumption mode.
Bit 1
TGL Description
0 The toggle output of the TM J- 2 is 0 (Init ial value)
1 The toggle output of the TM J- 2 is 0
Bit 0: Switching Over Between Timer Output/Remote Controlling Output (T/R)
This bit works to select if using the timer outputs from the TMJ-1 as the output signal through
the TMO pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2
as the output signa l t hrough t he T MO pin.
Bit 0
T/R Description
0 Timer out put s from t he TM J- 1 (Init ial value)
1 Toggle outputs f rom t he TM J- 2 ( r em ote contr olled tr ansm ission data)
Rev. 2.0, 11/ 00, page 309 of 1037
Selecting the Operation Mode
The operation mode of the Timer J is determined by the Bit 4 (8/16) and Bit 0 (T/R) of the TMJ.
TMJ
Bit 4 Bit 0
8/16 T/R Description
0 8-bit timer × 2 (Init ia l v a lu e)0
1 Remote contr olling mode
1*16-bit t imer
Note: *Don't care.
When writing is made into the TMJ under the timer mode, the counters (TCJ and TCK) will be
initialized (H'FF). Consequently, writing into the reloading registers (TLJ an TLK) should be
conducted after finishing settings with the TMJ.
Under the remote controlling mode, although the TLJ and the TLK will not be initialized even
when writing is made into the TMJ, follow the sequence listed below when starting a remote
controll i ng opera t ion.
(1) Make setting to the remote controlling mode with the TMJ.
(2) Write the data into the TLJ and TLK.
(3) Start the remote controlled operation by use of the TMJ. (ST bit = 1)
Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be valid.
Rev. 2.0, 11/ 00, page 310 of 1037
14.2.2 Timer J Control Regi ster (TM JC)
01
0
2
0
R/W
3(PS22)*
—
(R/W)*
—
4
0
R/W
5
0
6
0
7
R/WR/W
MON1
R/W
BUZZ0
0
R/W
BUZZ1 MON0 TMJ2IE TMJ1IE
11
Bit :
Initial value :
R/W :
Note: * Bit 0 is readable/writable only in the H8S/2194C series.
The timer J control register works to select the buzzer output frequency and to control
permission/prohibition of interrupts.
The TMJC is an 8-bit read/write register.
When reset, the TMJC is initialized to H'09.
Bits 7 and 6: Selecting the Buzzer Output (BUZZ1 or BUZZ0)
This bit works to select if using the buzzer outputs as the output signal through the BUZZ pin or
if using the m oni tor signa l s as the out put signal t hrough the BUZZ pin.
When setting is made to the monitor signals, choose the monitor signal using the MON1 bit and
MON0 bi t .
Bit 7 Bit 6
BUZZ1 BUZZ0 Description Frequency w hen
φ = 10MHz
0φ/4096 (I nitial value) 2.44 kHz0
1φ/8192 1. 22 kHz
0 Wor ks to output m onitor signals1
1 W or ks t o out put BUZZ signals from t he Tim er J
Rev. 2.0, 11/ 00, page 311 of 1037
Bits 5 and 4: Selecting the Monitor Signals (MON1 or MON0)
These bits work to select the type of signals being output through the BUZZ pin for monitoring
purpose. These settings are valid only when the BUZZ1 and BUZZ0 bits are being set to 1 and
0.
When PB-CTL or REC-CTL is chosen, signal duties will be output as they are.
In case of DVCTL signals, signals from the CTL dividing circuit will be toggled before being
output. Signal waveforms divided by the CTL dividing circuit into "n-divisions" will further be
divided into halves. (Namely, "2n" divisions, 50% duty waveform).
In case of TCA7, Bit 7 of the counter of the Timer A will be output. (50% duty)
When the prescaler is being used with the Timer A, 1Hz outputs are available.
Bit 5 Bit 4
MON1 MON0 Description
0 PB or REC-CTL (Init ia l v alu e )0
1DVCTL
1*Out put s TCA7
Note: *Don't care.
Bits 3: Reserved
When this is read, 1 will always be readout. Writes are disabled.
Bit 2: Enabling Interrupt of the TMJ2I (TMJ2IE)
This bit works to permit/prohibit occurrence of TMJ2I interrupt of the TMJS i n 1 -set o f t h e
TMJ2I.
Bit 2
TMJ2IE Description
0 Prohibits occurr ence of TMJ2I int er r upt (Init ial value)
1 Permit s occur r ence of TMJ2I inter rupt
Bit 1: Enabling Interrupt of the TMJ1I (TMJ1IE)
This bit works to permit/prohibit occurrence of TMJ1I interrupt of the TMJS i n 1 -set o f t h e
TMJ1I.
Bit 1
TMJ1IE Description
0 Prohibits occurr ence of TMJ1I int er r upt (Init ial value)
1 Permit s occur r ence of TMJ1I inter rupt
Rev. 2.0, 11/ 00, page 312 of 1037
Bit 0: Reserved (for H8S/2194 series)
When this is read, 1 will always be readout. Writes are disabled.
Bit 0: Selecting the Input clock for TM J-2 (P S22) (for H 8S/ 2194C series)
This bit, together with bits 3 and 2 (PS21, PS20) in TMJ, selects the input clock for TMJ-2. For
details, see section 14.2.1, Timer Mode Register J (TMJ).
14.2.3 Timer J Status Register (TMJS)
012345
——————
——————
6
0
7
R/(W)*
TMJ1I
0
R/(W)*
TMJ2I
111111
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer J status register (TMJS) works t o i nd icate issuance of the interrupt request of the
Timer J. The TMJS is a n 8-bi t re a d/ wr ite register. When reset, the TMJS is i n itialized to H'3F.
Bit 7: TMJ2I Interrupt Requesting Flag (TMJ2I)
This is the T MJ2I inte rrupt re que sting fl a g. Thi s fla g is set when t he TMJ-2 underflows.
Bit 7
TMJ2I Description
0 [Clearing conditions] (Init ial value)
When 0 is written after r eading 1
1 [Sett ing conditions]
When the TM J- 2 under f lows
Bit 6: TMJ1I Interrupt Requesting Flag (TMJ1I)
This is the T MJ1I inte rrupt re que sting fl a g. Thi s fla g is set out when t he T MJ-1 underflows.
TMJ1I interrupt requests will also be made under a 16-bit operation.
Bit 6
TMJ1I Description
0 [Clearing conditions] (Init ial value)
When 0 is written after r eading 1
1 [Sett ing conditions]
When the TM J- 1 under f lows
Bits 5 to 0: Reserved
When they are read, 1 will always be readout. Writes are disabled.
Rev. 2.0, 11/ 00, page 313 of 1037
14.2.4 Timer Counter J (TCJ)
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR15
R
TDR16
1
R
TDR17 TDR14 TDR13 TDR12 TDR11 TDR10
Bit :
Initial value :
R/W :
The time counter J (TCJ) is an 8-bit readable down-counter which works to count down by the
internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11
and PS10 bits of the TMJ. TCJ values can be readout always. Nonetheless, when the 8/16 bit of
the TMJ is being set to 1 (means when setting is made to 16-bit operation), reading is possible
under the word command only.
At this time, the TCK of the TMJ-2 can be read by the upper 8 bits and the TCJ can be read by
the lower 8 bits.
When the T CJ underflows (H'00 → Reloading value), regardless of the operation mode setting
of t h e 8 / 1 6 b i t, t h e TMJ1I b i t of the T MJS will be set to 1. The TCJ and TLJ are being allocated
to the same address.
When reset, the TCJ is initialized to H'FF.
14.2.5 Timer Counter K (TCK)
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR25
R
TDR26
1
R
TDR27 TDR24 TDR23 TDR22 TDR21 TDR20
Bit :
Initial value :
R/W :
The time counter K (TCK) is an 8-bit readable down-counter which works to count down by the
internal clock inputs or external clock inputs. The inputting clock can be selected by the PS21
and PS20 bits of the TMJ. TCK values can be readout always. Nonetheless, when the 8/16 bit
of the TMJ is being set to 1 (means when setting is made to 16-bit operation), reading is possible
under the word command only.
At this time, the TCK can be read by the upper 8 bits and the TCJ of the TMJ-1 can be read by
the lower 8 bits.
When the T CK underflows (H'00 → Re l o a d i n g v a lue ) , the T MJ2 I bit of t h e TMJS will be set to
1.
The TCK and TLK are being allocated to the same address.
When reset, the TCK is initialized to H'FF.
Rev. 2.0, 11/ 00, page 314 of 1037
14.2.6 Timer Load Register J (TLJ)
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR15
W
TLR16
1
W
TLR17 TLR14 TLR13 TLR12 TLR11 TLR10
Bit :
Initial value :
R/W :
The timer load register J (TLJ) is an 8-bit write only register which works to set the reloading
value of the TCJ.
When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ
and the TCJ starts counting down from the set value. Also, during an auto reloading operation,
when the TCJ underflows, the value of the TLJ will be loaded to the TCJ. Consequently, the
underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the
8/16 bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), writing is
possible under the word command only.
At this time, the upper 8 bits can be written into the TLK of the TMJ-2 and the lower 8 bits can
be written into the TLJ.
The TLJ and TCJ are being allocated to the same address.
When reset, the TLJ is initialized to H'FF.
14.2.7 Timer Load Register K (TLK )
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR25
W
TLR26
1
W
TLR27 TLR24 TLR23 TLR22 TLR21 TLR20
Bit :
Initial value :
R/W :
The timer load register K (TLK) is an 8-bit write only register which works to set the reloading
value of the TCK.
When the reloading value is set to the TLK, the value will be simultaneously loaded to the TCK
and the TCK starts counting down from the set value. Also, during an auto reloading operation,
when the TCK underflows, the value of the TLK will be loaded to the TCK. Consequently, the
underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the
8/16 bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), writing is
possible under the word command only. At this time, the upper 8 bits can be written into the
TLK and the lower 8 bits can be written into the TLJ of the TMJ-1. The TLK and TCK are
being allocated to the same address.
When reset, the TLK is initialized to H'FF.
Rev. 2.0, 11/ 00, page 315 of 1037
14. 2 .8 Module St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP13 bit is set to 1, the Timer J stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop
Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 5: Module Stop (MSTP13)
This bit works to designate the module stop mode for the Timer J.
MSTPCRH
Bit 5
MSTP13 Description
0 Cancels t he m odule st op m ode of the Timer J
1 Sets the module st op m ode of t he Tim er J (Init ial value)
Rev. 2.0, 11/ 00, page 316 of 1037
14.3 Operation
14.3.1 8-bit Reload Timer (TMJ-1)
The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through
the
,54
pin are being used. By selecting the edge signals through the
,54
pin, it can also be
used as an event counter. While it is working as an event counter, its reloading function is
workable simultaneously. When data are written into the reloading register TLJ, these data will
be written into the counter TCJ simultaneously. Also, when the counter TCJ underflows, the
data of the reloading register TLJ will be reloaded to the counter TCJ.
When the counter underflows, TMJ1I interrupt requests will be issued.
The underflow will be toggled and, by a appropriate selection of the dividing clock, buzzer
outputs will be issued or carrier frequencies for remote controlling transmissions can be
acquired.
The TMJ-1 and TMJ-2, in combination, can be used as a 16-bit reload timer. Nonetheless, when
they are being used, in combination, as a 16-bit timer, word command only is valid and the TCK
works as the down counter for the uppe r 8 bit s and t he T CJ works as the down counte r for the
lower 8 bits, means a reloading register of total 16 bits.
When data are written into a 16-bit reloading register, the same data will be written into the 16-
bit counter.
Also, when the 16-bit counter underflows, the data of the 16-bit reloading register will be
reloaded into the counter.
Even when they are making a 16-bit operation, the TMJ1I interrupt requests of the TMJ-1 and
BUZZ outputs are effective. In case these functions are not necessary, make them invalid by
programming.
The TMJ-1 and TMJ-2, in combination, can be used for remote controlled data transmission.
Regarding the remote controlled data transmission, see section 14.3.3, Remote Controlled Data
Transmission.
14.3.2 8-bit Reload Timer (TMJ-2)
The TMJ-2 is an 8-bit down-counting reload timer. As the clock source, dividing clock, edge
signals through the
,54
pin or the unde rfl ow signals from t he TMJ-1 are be i ng used. By
selecting the edge signals through the
,54
pin, it can also be used as an event counter. While
it is working as an event counter, its reloading function is workable simultaneously.
When data are written into the reloading register TLK, these data will be written into the counter
TCK simultaneously. Also, when the counter TCK underflows, the data of the reloading register
TLK will be made to the data counter TCK.
When the counter underflows, TMJ2I interrupt requests will be issued.
The TMJ-2 and TMJ-1, in combination, can be used as a 16-bit reload timer. For more
information on the 16-bit reload timer, see section 14.3.1, 8-bit Reload Timer (TMJ-1).
The TMJ-2 and TMJ-1, in combination, can be operated by remote controlled data transmission.
Rev. 2.0, 11/ 00, page 317 of 1037
Regarding the remote controlled data transmission, see section 14.3.3, Remote Controlled Data
Transmission.
14.3.3 Remote Controlled Data Transmission
The Timer J is capable of making remote controlled data transmission. The carrier frequencies
for the remote controlled data transmission can be generated by the TMJ-1 and the burst width
duration and the space wi dth duration can be setup by the TMJ-2.
The data having been written into the reloading register TMJ-1 and into the burst/space duration
register (TLK) of the TMJ-2 will be loaded to the counter at the same time as the remote
controlled data transmission starts. (Remote controlled data transmission starting bit (ST) ← 1)
While remote controlled data transmission is being made, the contents of the burst/space
duration register will be loaded to the counter only while reloading is being made by underflow
signals. Even when a writing is made to the burst/space duration register while remote
controlled data transmission is being made, reloading operation will not be made until an
underflow signal i s issued. T he TMJ-2 issues TMJ2I interrupt re que sts by the unde rfl ow signals.
The TMJ-1 performs normal reloading operation (including the TMJ1I interrupt requests).
Figure 14.2 shows the output waveform for the remote controlled data transmission function.
When a shift to the low power consumption mode is effected while remote controlled data
transmission is being made, the ST bit will be cleared to 0. When resuming the remote
controlled data transmission after returning to the active mode, write 1.
Burst width Space width Burst width
TMJ-2 toggle output
= 1 TMJ-2 toggle output
= 0 TMJ-2 toggle
output = 1
Setting the
space width Setting the
burst width Setting the
space width
ST bit 1 Underflow Underflow Underflow
TMJ-1 can generate
the carrier frequencies
Remote controlled data
transmission outputs
Setting the remote
controlled mode
Setting the burst width
Figure 14.2 Remote Controlled Data Transmission Output Waveform
Rev. 2.0, 11/ 00, page 318 of 1037
TMJ-1
UDF
TMO
(BUZZ)
TMJ-2
UDF
REMOout
TMO
Remote controlled data
transmission output
Figure 14. 3 Ti me r O utput Timing
Rev. 2.0, 11/ 00, page 319 of 1037
When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being
set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of
the inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the
remote controlled data transmission starts. Consequently, when the TLK is updated during the
period after setting the ST bit to 1 until the next cycle of the inputting clock comes, the initial
burst width will be changed like shown in figure 14.4.
Therefore, when making remote controlled data transmission, determine I/O of the TGL bit at
the time of the first burst width control operation without fail. (Or, set the space width to the
TLK after waiting for a cycle of the inputting clock.)
After that , ope rat i ons can be c onti nue d by int e rrupts.
Similarly, pay attention to the control works when ending remote controlled data transmission.
Exemple)
1) Set the burst widt h wit h the T LK.
2) ST bit ← 1
3) Execut e the proc edure 4) i f the T GL fla g = 1.
4) Set the space width with the TLK under the status where the TGL flag = 1.
5] Make TMJ-2 interrupt .
6] Set the burst widt h wit h the T LK.
:
n) After making TMJ-2 interrupt, make setting of the ST ← 0 under the status where the
TGL flag = 0.
The period during which the
space width settig can be
made. (S)
Delay
Interrupt
Interrupt
TLK setting
(Burst width)
(B)
Burst width
according to (B) Space width
according to (S)
Stopping the remote controlled
data transmission
TGL flag
Inputting clock
to the TMJ-2
ST 0
Delay
ST 1
Remote controlled data
transmission starts here.
If an updating is made with the
TLK during this period, the burst
width will be changed.
Figure 14.4 Controls of the Remote Controlled Data Transmission
Rev. 2.0, 11/ 00, page 320 of 1037
Rev. 2.0, 11/ 00, page 321 of 1037
Section 15 Timer L
15.1 Overview
The Timer L is an 8-bit up/down counter using the control pulses or the CFG division signals as
the clock source.
15.1.1 Features
Features of the Timer L are as follows:
• Choices of two different types of internal clocks (φ/ 128 a nd φ/64), DVCFG2 (CFG division
signal 2), PB and REC-CTL (control pulses) are available for your selection.
— In case the PB-CTL is not available, such as when reproducing un-recorded tapes, tape
count ca n be ma de by the DVCFG2.
— Selection of the leading edge or the trailing edge is workable with the CTL pulse
counting.
• Interrupts occur when t he count e r overfl ows or underflows and at occ urre nce s of com pare
match clear.
• It is possible to switch over between the up-counting and down-counting functions with the
counter.
Rev. 2.0, 11/ 00, page 322 of 1037
15.1.2 Block Diagram
Figure 15.1 shows a block diagram of the Timer L.
[Legend]
Internal data bus
DVCFG2 : Division signal 2 of the CFG
PB and REC-CTL : Control pluses necessary when making
reproduction and storage
LMR : Timer L mode register
LTC : Linear time counter
RCR : Reload/compare match register
OVF : Overflow
UDF : Underflow
LMR
LTC
RCR
Comparator
Write
OVF/UDF
Reloading
Match clear
Interrupt request
Interrupting
circuit
DVCFG2
PB and
REC-CTL
INTERNAL CLOCK
/128
/64
Read
Figure 15. 1 Bl oc k Diagram of the Time r L
Rev. 2.0, 11/ 00, page 323 of 1037
15.1.3 Register Configuration
Table 15.1 shows the register configuration of the Timer L. The linear time counter (LTC) and
the reload compare patch register (RCR) are being allocated to the same address.
Reading or writing determines the accessing register.
Table 15.1 Register Configuration
Name Abbrev. R/W Size Init ial Value Address *
Timer L m ode r egister LMR R/W Byte H'30 H'D112
Linear time count er LTC R Byte H'00 H'D113
Reload/compare m at c h
register RCR W Byte H'00 H'D113
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 324 of 1037
15.2 Descripti on s of Respective Regi st ers
15.2.1 Timer L Mode Register (LM R)
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5
——
——
1
6
0
7
R/WR/WR/W
LMIE
0
R /(W)*
LMIF IMR3 IMR2 IMR1 IMR0
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer L mode register (LMR) is an 8-bit read/write register which works to control the
interrupts, to select between up-counting and down-counting and to select the clock source.
When reset, the LMR is initialized to H'30.
Bit 7: Timer L Interr upt Requesting Flag (LMIF)
This is the Timer L interrupt requesting flag. It indicates occurrence of overflow or underflow
of the LTC or occurrence of compare match clear.
Bit 7
LMIF Description
0 [Clearing conditions] (Init ial value)
When 0 is written after r eading 1
1 [Sett ing conditions]
When the LTC overf lows, under f lows or when compar e m at ch clear has occur r ed
Bit 6: Enabling Interrupt of the Timer L (LMIE)
This bit works to permit/prohibit occurrence of interrupt of the Timer L when the LTC
overflows, underflows or when compare match clear has occurred.
Bit 6
LMIE Description
0 Prohibits occurr ence of interr upt of t he Timer L (Init ial value)
1 Permit s occur r ence of interr upt of the Timer L
Bits 5 and 4: Reserved
When they are read, 1 will always be readout. Writes are disabled.
Bit 3 : Up- c o unt / Do wn-count Cont r o l ( L M R3 )
This bit is for selection if the Timer L is to be controlled to the up-counting function or down-
counting func t ion.
Rev. 2.0, 11/ 00, page 325 of 1037
(1) When Controlled to the Up-counting Function
• When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00
before starting counting up. When the LTC value and the RCR value match, the LTC
will be cleared to H' 00. Also, interrupt requests will be issued by the match signal.
(Compare patch clear function)
• When H'00 is set to the RCR, the counter makes 8-bit interval timer operation to issue a
interrupt request when overflowing occurs. (Interval timer function)
(2) When Controlled to the Down-counting Function
• When a val ue is set t o t he RCR, t he set va l ue i s rel oade d t o the L TC a nd c ounti ng down
starts from that value. When the LTC underflows, the value of the RCR will be reloaded
to the LTC. Also, when the LTC underflows, a interrupt request will be issued. (Auto
reload timer function)
Bit 3
LMR3 Description
0 Controlling to t he up- count ing f unct ion (Init ial value)
1 Controlling to t he up- count ing f unct ion
Bits 2 to 0: Clock Selection (LMR2 to LMR0)
The bits LMR2 to LMR0 work to select the clock to input to the Timer L. Selection of the
leading edge or the trailing edge is workable for counting by the PB and the REC-CTL.
Bit 2 Bit 1 Bit 0
R2 LMR1 LMR0 Description
0 Counts at the r ising edge of t he PB and REC-CTL
(Init ial value)
0
1 Count s at the falling edge of the PB and REC-CTL
0
1*Counts the DVCFG2
0*Counts at φ/ 128 of t he int ernal clock1
1*Counts at φ/ 64 of t he int ernal clock
Note: *Don't care.
Rev. 2.0, 11/ 00, page 326 of 1037
15.2.2 Linear Ti me Counter (LTC)
0
0
1
0
R
2
0
3
0
456
0
7
RRRR
LTC6
0
R
LTC5
0
R
LTC4
0
R
LTC7 LTC3 LTC2 LTC1 LTC0
Bit :
Initial value :
R/W :
The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be
selected by the LMR2 to LMR0 bits of the LMR.
When reset, the LTC is initialized to H'00.
15. 2 .3 Reloa d/ Co mpa r e Ma t c h Re g i st e r (RCR)
0
0
1
0
W
2
0
3
0
456
0
7
WWWW
RCR6
0
W
RCR5
0
W
RCR4
0
W
RCR7 RCR3 RCR2 RCR1 RCR0
Bit :
Initial value :
R/W :
The reload/compare match register (RCR) is an 8-bit write only register.
When the Timer L is being controlled to the up-counting function, when a compare match value
is set to the RCR, the LTC will be cleared at the same time and the LTC will then start counting
up from the initial value (H'00).
While, when the Timer L is being controlled to the down-counting function, when a reloading
value is set to the RCR, the same value will be loaded to the LTC at the same time and the LTC
will then start counting up from said value. Also, when the LTC underflows, the value of the
RCR will be reloaded to the LTC.
When reset, the RCR is initialized to H'00.
Rev. 2.0, 11/ 00, page 327 of 1037
15. 2 .4 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP12 bit is set to 1, the Timer L stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop
Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 4: Module Stop (MSTP12)
This bit works to designate the module stop mode for the Timer L.
MSTPCRH
Bit 4
MSTP12 Description
0 Cancels t he m odule st op m ode of the Timer L
1 Sets the module st op m ode of t he Tim er L ( I nitial value)
Rev. 2.0, 11/ 00, page 328 of 1037
15.3 Operation
The Timer L is an 8-bit up/down counter.
The inputting clock for the Timer L can be selected by the LMR2 to LMR0 bits of the LMR
from the choices of the internal clock (φ/128 a nd φ/ 64), DVCDG2, PB and REC-CTL.
The Timer L is provided with three different types of operation modes, namely, the compare
match clear mode when controlled to the up-counting function, the auto reloading mode when
controlled to the down-counting function and the interval timer mode.
Respective operation modes and operation methods will be explained below.
15.3.1 Compare M atch Clear O perati on
When the LMR3 bit of the LMR is cleared to 0, the Timer L will be controlled to the up-
counting func t ion.
When any other values than H'00 are written into the RCR, the LTC will be cleared to H'00
simultaneously before starting counting up.
Figure 15.2 shows the clear timing of the LTC. When the LTC value and the RCR value match
(compare match), the LTC readings will be cleared to H'00 to resume counting from H'00.
Figure 15.3 indicated on the next page shows the compare match clear timing.
RCR
LTC
Write signal
1 state
N
H' 00
Fi g ur e 1 5 . 2 RCR W r i t i ng a nd LT C Cl ear ing Timi ng Chart
Rev. 2.0, 11/ 00, page 329 of 1037
LTC
RCR
N H' 00N-1
N
Interrupt
request
Count-up
signal
Compare match
clear signal
PB-CTL
Figure 15. 3 Compare M atc h Cleari ng Timi ng Chart
(In case the rising edge of the PB-CTL is selected)
Rev. 2.0, 11/ 00, page 330 of 1037
Rev. 2.0, 11/ 00, page 331 of 1037
Section 16 Timer R
16.1 Overview
The Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function
and slow tracking function in addition to the reloading function and event counter function.
16.1.1 Features
The Timer R consists of triple 8-bit reloading timers. By combining the functions of three units
of reloading timers/counters and by combining three units of timers, it can be used for the
following applications:
(1) Applications making use of the functions of three units of reloading timers.
(2) For identification of the VCR mode.
(3) For reel controls.
(4) For acceleration and braking of the capstan motor when being applied to intermittent
movements.
(5) Slow tracking mono-multi applications.
16.1.2 Block Diagram
The Timer R consists of three units of reload timer counters, namely, two units of reload timer
counters equipped with capturing function (TMRU-1 and TMRU-2) and a unit of reload timer
counter (T MRU-3).
Figure 16.1 is a block diagram of the Timer R.
Rev. 2.0, 11/ 00, page 332 of 1037
Notes:
Internal bus
Internal bus
Clock sources
DVCTL
CFG
Clock
selection
(2 bits)
Reloading register
(8 bits)
Down-counter
(8 bits)
Capture register
(8 bits)
TMRI2
Interrupt request
TMRI1
Interrupt
request
TMRI3
Interrupt
request
TMRU-1
TMRCP1 *2
UnderÐ
flow
TMRU-3 Underflow
*1
TMRL3
PS31,30
External signals
IRQ3
/1024
/2048
/4096
Clock source
/64
/128
/256
Clock sources
/4
/256
/512
Down-counter
(8 bits)
Latch
clock
selection
Clock
selection
(2 bits)
Resetting
Available/
Not
available
CP/
SLM
SLW
CAPF
Capture register
(8 bits)
Down-counter
(8 bits)
Reloading register
(8 bits)
Acceleration/
braking
Reloading
Available/
not
available
Reloading
clock
selection
Reloading register
(8 bits)
RLD/
CAP
Clock
selection
(2 bits)
CPS
LAT PS21,20
CLR2
Res
Res
TMRCP2
UnderÐ
flowTMRU-2 CFG mask F/F
R
SQ
R
S
Q
Acceleration
braking
AC/BR
TMRL2
RLD
RLCK
TMRL1PS11,10
Interrupting circuit
1. When the DVCTL is being used as the clock source, reloading will be made when the counter underflows and when
the dividing clock is being used as the clock source, reloading will be made by the DVCTL.
2. When the LAT bit = 0, the capture signal against the TMRU-1 will not be output.
Figure 16. 1 Bl oc k Diagram of the Time r R
Rev. 2.0, 11/ 00, page 333 of 1037
16.1.3 Pin Configuration
Table 16.1 shows the pin configuration of the Timer R.
Table 16.1 Pin Configuration
Name Abbrev. I/O Function
Input capt ur e inputting pin
,54
Input Input capt ur e inputting for the Timer R
16.1.4 Register Configuration
Table 16.2 shows the register configuration of the Timer R.
Table 16.2 Register Configuration
Name Abbrev. R/W Size Init i al Value Address
Timer R mode r egister 1 TMRM1 R/W Byte H'00 H'D118
Timer R mode r egister 2 TMRM2 R/W Byte H'00 H'D119
Timer R contr ol/ st at us
register TMRCS R/W Byte H'03 H'D11F
Timer R captur e r egist er 1 TM RCP1 R Byte H'FF H'D11A
Timer R captur e r egist er 2 TM RCP2 R Byte H'FF H'D11B
Timer R load register 1 TMRL1 W Byte H'FF H'D11C
Timer R load register 2 TMRL2 W Byte H'FF H'D11D
Timer R load register 3 TMRL3 W Byte H'FF H'D11E
Note: Memor ies of respective regist ers will be preserved even under the low power consum pt ion
mode. Nonet heles s, the CAPF f lag and SLW f lag of t he TMRM2 will be clear ed t o 0.
Rev. 2.0, 11/ 00, page 334 of 1037
16.2 Descripti on s of Respective Regi st ers
16.2.1 Timer R Mode Register 1 (TM RM1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
RLD
R/W
AC/BR
0
R/W
CLR2 RLCK PS21 PS20 RLD/CAP CPS
Bit :
Initial value :
R/W :
The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes
and to select the inputting clock for the TMRU-2. This is an 8-bit read/write register.
When reset, the TMRM1 is initialized to H'00.
Bit 7: Selecting Clearing/Not Clearing of TMRU-2 (CLR2)
This bit is used for selecting if the TMRU-2 counter reading is to be cleared or not as it is
captured.
Bit 7
CLR2 Description
0 TMRU-2 counter reading is not to be cleared as soon as it is capt ur ed. ( I nit ial value)
1 TMRU-2 counter reading is to be cleared as soon as it is captur ed
Bit 6: Selecting the Acceleration/Braking Processing (AC/BR)
This bit works to control occurrences of interrupt requests to detect completion of acceleration
or braking while the capstan motor is making intermittent revolutions.
For more information, see section 16.3.6, Acceleration and Braking of the Capstan Motor.
Bit 6
AC/BR Description
0 Acceleration (Init ial value)
1Braking
Rev. 2.0, 11/ 00, page 335 of 1037
Bit 5: Selection if Using the TMRU-2 for Reloading or Not Doing So (RLD)
This bit is used for selecting if the TMRU-2 reload function is to be turned on or not.
Bit 5
RLD Description
0 Not using the TM RU-2 as t he r eload tim er (Init ial value)
1 Using the TMRU-2 as the reload timer
Bit 4: Selection of the Reloading Timing for the TMRU-2 (RLCK)
This bit works to select if the TMRU-2 is reloading by the CFG or by underflowing of the
TMRU-2 counter. This choice is valid only when the bit 5 (RLD) is being set to 1.
Bit 4
RLCK Description
0 Reloading at the rising edge of t he CFG (Init ial value)
1 Reloading by underflowing of the TMRU-2
Bits 3 and 2: Selecting the Clock Source for the TMRU-2 (PS21 and PS20)
These bits work to select the inputting clock to the TMRU-2.
Bit 3 Bit 2
PS21 PS20 Description
0 Counting by underf lowing of the TM RU-1 ( I nit ial value)0
1 Counting by the PSS, φ/256
0 Counting by the PSS, φ/1281
1 Counting by the PSS, φ/64
Bit 1: Selection of the Operation Mode of the TMRU-1 (RLD/CAP)
This bit works to select if the operation mode of the TMRU-1 is reload timer mode or capture
timer mode.
Under the capture timer mode, reloading operation will not be made. Also, the counter reading
will be cleared as soon as capture has been made.
Bit 1
RLD/CAP Description
0 The TMRU-1 works as t he r eloading timer (Initial value)
1 The TMRU-1 works as t he capt ur e t im er
Rev. 2.0, 11/ 00, page 336 of 1037
Bit 0: Selection of the Capture Signals of the TMRU-1 (CPS)
In combination with the LAT bit (Bit 7) of the TMR2, this bit works to select the capture signals
of the TMRU-1. This bit becomes valid when the LAT bit is being set to 1. It will also become
valid when the RLD/CAP bit (Bit 1) is being set to 1. Nonetheless, it will be invalid when the
RLD/CAP bit (Bit 1) is being set to 0.
Bit 0
CPS Description
0 Capture signals at t he r ising edge of the CFG ( Initial value)
1 Capture signals at t he edge of the IRQ 3
16.2.2 Timer R Mode Register 2 (TM RM2)
0
0
1
0
R/(W)*
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/(W)*
R/WR/W
PS10
R/W
PS11
0
R/W
LAT PS31 PS30 CP/SLM CAPF SLW
Bit :
Initial value :
R/W :
The timer R mode register 2 (TMRM2) is an 8-bit read/write register which works to identify the
operati on m ode a nd t o cont rol the slow tra cki ng proc essing.
When reset, the TMRM2 is initialized to H'00.
Note: * T he CAPF bit a n d the SL W bi t , re sp ectively, works to latch the interrupt causes and
writing 0 only is valid. Consequently, when these bits are being set to 1, respective
interrupt requests will not be issued. Therefore, it is necessary to check these bits
during the course of the interrupt processing routine to have them cleared.
Also, priority is given to the set and, when an interrupt cause occur while the a
clearing command (BCLR, MOV, etc.) is being executed, the CAPF bi t and the SL W
bit will not be cleared respectively and it thus becomes necessary to pay attention to
the clearing timing.
Rev. 2.0, 11/ 00, page 337 of 1037
Bit 7: Selection of the Capture Signals of the TMRU-2 (LAT)
In combination with the CPS bit (Bit 0) of the TMRM1, this bit works to select the capture
signals of the T MRU-2.
TMRM2 TMRM1
Bit 7 Bit 0
LAT CPS Description
0*Captures when the TM RU-3 under f lows (Initial value)
0 Captures at the r ising edge of t he CFS1
1 Captures at the edge of t he IRQ3
Note: *Don't care.
Bits 6 and 5: Selecting the Clock Source for the TMRU-1 (PS11 and PS10)
These bits work to select the inputting clock to the TMRU-1.
Bit 6 Bit 5
PS11 PS10 Description
0 Counting at t he r ising edge of t he CFG ( I nit ial value)0
1 Counting by the PSS, φ/4
0 Counting by the PSS, φ/2561
1 Counting by the PSS, φ/512
Bits 4 and 3: Selecting the Clock Source for the TMRU-3 (PS31 and PS30)
These bits work to select the inputting clock to the TMRU-3.
Bit 4 Bit 3
PS31 PS30 Description
0 Counting at t he r ising edge of t he DVCTL from the dividing circuit.
(Init ial value)
0
1 Counting by the PSS, φ/4096
0 Counting by the PSS, φ/20481
1 Counting by the PSS, φ/1024
Rev. 2.0, 11/ 00, page 338 of 1037
Bit 2: Selection of Interrupt Causes (CP/SLM)
This bit works to select the interrupt causes for the TMRI3.
Bit 2
CP/SLM Description
0 M akes int er r upt requests upon t he capture signals of t he TM RU-2 valid (Init ial value)
1 M akes int er r upt r equest s upon ending of t he slow tr acking mono- m ult i valid
Bit 1: Capture Signal Flag (CAPF)
This is a flag being set out by the capture signal of the TMRU-2. Although both reading/writing
are possible, 0 only is valid for writing.
Also, priority is being given to the set and, when the "capture signal" and "writing 0" occur
simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued
and it is necessary to be attentive about this fact.
When t he CP/ SLM bi t (Bit 2) i s bei ng se t t o 1, t hi s CAPF bit shoul d a l ways be se t to 0.
The CAPF f l a g i s cleared to 0 under the low power consumption mode.
Bit 1
CAPF Description
0 [Clearing conditions] (Initial value)
When 0 is written after r eading 1
1 [Setting conditions]
At occurr ences of t he TMRU-2 capture signals while the CP/SLM bit is being set t o 0
Bit 0: Slow Tracking Mono-multi Fl ag (SLW)
This is a flag being set out when the slow tracking mono-multi processing ends. Although both
reading/writing are possible, 0 only is valid for writing.
Also, priorit y is bei ng gi ven t o t he set a nd, when "endi ng of t he slow tra c king m ono-m ult i
processing" and "writing 0" occur simultaneously, this flag bit remains being set to 1 and the
interrupt request will not be issued and it is necessary to be attentive about this fact.
When the CP/SLM bit (Bit 2) i s being set t o 0, thi s SLW bi t should a l ways be set t o 0.
The SLW flag is cleared to 0 under the low power consumption mode.
Bit 0
SLW Description
0 [Clearing conditions] (Initial value)
When 0 is written after r eading 1
1 [Setting conditions]
When the slow tracking mono- multi processing ends while t he CP/SLM bit is being set
to 1
Rev. 2.0, 11/ 00, page 339 of 1037
16. 2 .3 Time r R Co ntrol / St a tus Regi st e r ( T M RCS)
0
1
1——
——
1
2
0
R/(W)*
3
0
4
0
R/(W)*
5
0
6
0
7
R/(W)*
R/W
TMRI1E
R/W
TMRI2E
0
R/W
TMRI3E TMRI3 TMRI2 TMRI1
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer R control/status register (TMRCS) works to control the interrupts of the Timer R.
The TMRCS is an 8-bit read/write register. When reset, the TMRCS is initialized to H'03.
Bit 7: Enabling the TMRI3 Interrupt (TMRI3E)
This bit works to permit/prohibit occurrence of the TMRI3 interrupt when an interrupt cause
being selected by the CP/SLM bit of the TMRM2 has occurred, such as occurrences of the
TMRU-2 capture signals or when the slow tracking mono-multi processing ends, and the TMRI3
has been set to 1.
Bit 7
TMRI3E Description
0 Prohibits occurr ences of TMRI3 int er r upt s (Init ial value)
1 Permit s occur r ences of TMRI3 int er r upt s
Bit 6: Enabling the TMRI2 Interrupt (TMRI2E)
This bit works to permit/prohibit occurrence of the TMRI2 interrupt when the TMRI2 has been
set to 1 by issuance of t he unde rfl ow signal of t he TMRU-2 or by ending of t he slow trac ki ng
mono-multi processing.
Bit 6
TMRI2E Description
0 Prohibits occurr ences of TMRI2 int er r upt s (Init ial value)
1 Permit s occur r ences of TMRI2 int er r upt s
Rev. 2.0, 11/ 00, page 340 of 1037
Bit 5: Enabling the TMRI1 Interrupt (TMRI1E)
This bit works to permit/prohibit occurrence of the TMRI1 interrupt when the TMRI1 has been
set to 1 by issuance of t he unde rfl ow signal of t he TMRU-1.
Bit 5
TMRI1E Description
0 Prohibits occurr ences of TMRI1 int er r upt s (Init ial value)
1 Permit s occur r ences of TMRI1 int er r upt s
Bit 4 : T M RI3 Int e r rupt Re questi ng F l a g (T M RI3 )
This is the T MRI3 int errupt re questi ng fl ag.
It indicates occurrence of an interrupt cause being selected by the CP/SLM bit of the TMRM2,
such as occurrenc e s of the T MRU-2 capt ure signa l s or ending of t he slow trac ki ng mono-m ul ti
processing.
Bit 4
TMRI3 Description
0 [Clearing conditions] (Init ial value)
When 0 is written after r eading 1
1 [Sett ing conditions]
At occurr ence of t he inter rupt cause being selected by the CP/SLM bit of t he
TMRM2
Bit 3 : T M RI2 Int e r rupt Re questi ng F l a g (T M RI2 )
This is the T MRI2 int errupt re questi ng fl ag.
It indicates occurrences of the TMRU-2 underflow signals or ending of the acceleration/braking
processing of the capstan motor.
Bit 3
TMRI2 Description
0 [Clearing conditions] (Init ial value)
When 0 is written after r eading 1
1 [Sett ing conditions]
At occurr ences of t he TMRU-2 underflow signals or ending of the acceler at ion
/braking processing of t he capst an m ot or
Rev. 2.0, 11/ 00, page 341 of 1037
Bit 2 : T M RI1 Int e r rupt Re questi ng F l a g (T M RI1 )
This is the T MRI1 int errupt re questi ng fl ag.
It indicates occurrences of the TMRU-1 underflow signals.
Bit 2
TMRI1 Description
0 [Clearing conditions] (Init ial value)
When 0 is written after r eading 1.
1 [Sett ing conditions]
When the TM RU-1 under f lows.
Bits 1 and 0: Reserved
When they are read, 1 will always be readout. Writes are disabled.
16. 2 .4 Time r R Ca pture Regi st e r 1 ( TMRCP 1)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC17
R
TMRC16
R
TMRC15
R
TMRC14
R
TMRC13
R
TMRC12
R
TMRC11
R
TMRC10
Bit :
Initial value :
R/W :
The timer R capture register 1 (TMRCP1) works to store the capture data of the TMRU-1.
During the course of the capturing operation, the TMRU-1 counter readings are captured by the
TMRCP1 at the CFG edge or t he IRQ3 edge. T he ca pt uring ope ra ti on of t he T MRU-1 is being
performed using 16 bits, in combination with the capturing operation of the TMRU-2.
The TMRCP1 is an 8-bit read only register. When reset, the TMRCS is initialized to H'FF.
Notes: 1. W hen the TMRCP1 is readout while the capture signal is being received, the reading
data become unstable. Pay attention to the timing for reading out.
2. When a shift to the low power consumption mode is made while the capturing
operati ng i s in progress, t he c ount er re a ding be c ome s unstabl e. Afte r re turni ng t o the
active mode, always write "H'FF" into the TMRL1 to initialize the counter.
Rev. 2.0, 11/ 00, page 342 of 1037
16. 2 .5 Ti mer R Ca pt ur e Regi st e r 2 ( TMRCP 2)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC27
R
TMRC26
R
TMRC25
R
TMRC24
R
TMRC23
R
TMRC22
R
TMRC21
R
TMRC20
Bit :
Initial value :
R/W :
The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At
each CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter
readings are captured by the TMRCP2.
The TMRCP2 is an 8-bit read only register. When reset, the TMRCS will be initialized into
H'FF.
Notes: 1. W hen the TMRCP2 is readout while the capture signal is being received, the reading
data become unstable. Pay attention to the timing for reading out.
2. When a shift to the low power consumption mode is made, the counter reading
becomes unstable. After returning to the active mode, always write "H'FF" into the
TMRL2 to initialize the counter.
16.2.6 Timer R Load Register 1 (TMRL1)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR17
W
TMR16
W
TMR15
W
TMR14
W
TMR13
W
TMR12
W
TMR11
W
TMR10
Bit :
Initial value :
R/W :
The timer R load register 1 (TMRL1) is an 8-bit write only register which works to set the load
value of the TMRU-1.
When a load value is set to the TMRL1, the same value will be set to the TMRU-1 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows during the course of the reload timer operation, the TMRL1 value will be set to the
counter.
When reset, the TMRL1 is initialized to H'FF.
Rev. 2.0, 11/ 00, page 343 of 1037
16.2.7 Timer R Load Register 2 (TM RL2)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR27
W
TMR26
W
TMR25
W
TMR24
W
TMR23
W
TMR22
W
TMR21
W
TMR20
Bit :
Initial value :
R/W :
The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load
value of the TMRU-2.
When a load value is set to the TMRL2, the same value will be set to the TMRU-2 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows or a CFG edge is detected during the course of the reload timer operation, the
TMRL2 value will be set to the counter.
When reset, the TMRL2 is initialized to H'FF.
16.2.8 Timer R Load Register 3 (TMRL3)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR37
W
TMR36
W
TMR35
W
TMR34
W
TMR33
W
TMR32
W
TMR31
W
TMR30
Bit :
Initial value :
R/W :
The timer R load register 3 (TMRL3) is an 8-bit write only register which works to set the load
value of the TMRU-3.
When a load value is set to the TMRL3, the same value will be set to the TMRU-3 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows or a DVCTL edge is detected, the TMRL2 value will be set to the counter.
(Reloading will be made by the underflowing signals when the DVCTL signal is selected as the
clock source, and reloading will be made by the DVCTL signals when the dividing clock is
selected as the clock source.)
When reset, the TMRL3 is initialized to H'FF.
Rev. 2.0, 11/ 00, page 344 of 1037
16. 2 .9 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP11 bit is set to 1, the Timer R stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop
Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 3: Module Stop (MSTP11)
This bit works to designate the module stop mode for the Timer R.
MSTPCRH
Bit 3
MSTP11 Description
0 Cancels t he m odule st op m ode of the Timer R
1 Sets the module st op m ode of t he Tim er R (Initial value)
Rev. 2.0, 11/ 00, page 345 of 1037
16.3 Operation
16. 3 .1 Reloa d Time r Co unt e r E qui pped wit h Ca pturi ng Funct i o n T M RU- 1
The reload timer counter equipped with capturing function, TMRU-1, consists of an 8-bit down-
counter, a reloading register and a capture register.
The clock source can be selected from among the leading edge of the CFG signals and three
types of dividing clocks. It is also selectable whether using it as a reload counter or as a capture
counter. Even when the capturing function is selected, the counter readings can be updated by
writing the values into the reloading register.
When the counter underflows, the TMRI1 interrupt request will be issued.
The initial values of the TMRU-1 counter, reloading register and capturing register are all H'FF.
(1) Operation of the Reload Timer
When a value is written into to the reloading register, the same value will be written into the
counter simultaneously. Also, when the counter underflows, the reloading register value will
be reloaded to the counter. The TMRU-1 is a dividing circuit for the CFG. In combination
with the TMRU-2 and TMRU-3, it can also be used for the mode identification purpose.
(2) Capturing Operation
Capturing operation is carried out in combination with the TMRU-2 using the combined 16
bits. It can be so programmed that the counter may be cleared by the capture signal. The
CFG edges or IRQ3 edges are used as the capture signals. It is possible to issue the TMRI3
interrupt re quest by t he ca pt ure signa l .
In addition to the capturing function being worked out in combination with the TMRU-2, the
TMRU-1 can be used as a 16-bit CFG counter. Selecting the IRQ3 as the capture signal, the
CFG within the duration of the reel pulse being input into the
,54
pin can be c ounte d by
the TMRU-1.
Rev. 2.0, 11/ 00, page 346 of 1037
16. 3 .2 Rel o a d Time r Co unt e r E qui pped wit h Ca pturi ng Funct i o n T M RU- 2
The reload timer counter equipped with capturing function, TMRU-2, consists of an 8-bit down-
counter, a reloading register and a capture register.
The clock source can be selected from among the undedrflowing signal of the TMRU-1 and
three types of dividing clocks. Also, although the reloading function is workable during its
capturing operation, equipping or not of the reloading function is selectable. Even when
without-reloading-function is chosen, the counter reading can be updated by writing the values
to the reloading register.
When the counter underflows, the TMRI2 interrupt request will be issued.
The initial values of the TMRU-2 counter, reloading register and capturing register are all H'FF.
(1) Operation of the Reload Timer
When a value is written into to the reloading register, the same value will be written into the
counter, simultaneously. Also, when the counter underflows, the reloading register value
will be reloaded to the counter.
The TMRU-2 can make acceleration and braking work for the capstan motor using the reload
timer operation.
(2) Capturing Operation
Using the capture signals, the counter reading can be latched into the capturing register. As
the ca pt ure signa l , you ca n c hoose from a m ong edge s of the CFG, edge s of the IRQ3 or the
underflow signals of the T MRU-3. It i s possible to i ssue the TMRI3 int e rrupt re que st by the
capture signal.
The capturing function (stopping the reloading function) of the TMRU-2, in combination
with the TMRU-1 and TMRU-3, can also be used for the mode identification purpose.
16.3.3 Reload Counter Ti me r TM RU-3
The reload counter timer TMRU-3 consists of an 8-bit down-counter and a reloading register.
Its clock source can be selected from between the undedrflowing signal of the counter and the
edges of the DVCTL signals. (When the DVCTL signal is selected as the clock source,
reloading will be effected by the underflowing signals and when the dividing clock is selected as
the clock source, reloading will be effected by the DVCTL signals.) The reloading signal works
to reload the reloading register value into the counter. Also, when a value is written into to the
reloading register, the same value will be written into the counter, simultaneously.
The initial values of the counter and the reloading register are H'FF.
The underfl owing signa ls ca n be used as the c apt uri ng signal for t he T MRU-2.
The TMRU-3 can also be used as a dividing circuit for the DVCTL. Also, in combination with
the TMRU-1 and TMRU-2 (capt uri ng funct i on), the T MRU-3 can be used for t he mode
identification purpose. Since the divided signals of the DVCTL are being used as the clock
source, CT L signa l s (DVCTL) conformi ng t o the doubl e spee d c an be i nput when m a king
Rev. 2.0, 11/ 00, page 347 of 1037
searches. The se DVCTL signa ls ca n a lso be used for pha se c ontrol s of the ca psta n mot or.
Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the
edges of the DVCTL to provide the slow tracking mono-multi function.
16.3.4 Mode Identification
When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing
tapes, the T MRU-1 (CFG dividing circ ui t), T MRU-2 (capt uring func t ion/ wit hout re l oadi ng
function) and TMRU-3 (DVCTL dividing circuit) of the Timer R should be used.
The Timer R will become to the aforementioned status after a reset.
Under the aforementioned status, the divided CFG should be written into the reloading register
of the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU-
3. Whe n the T MRU-3 underflows, the count e r val ue of the T MRU-2 is capture d. Such
capturing register value represents the number of the CFG within the DVCTL cycle.
As aforementioned, the Timer R can work to count the number of the CFG corresponding to "n"
times of DVCTL's or to identify the mode being searched.
For exemplary settings for the register, see section 16.5.1, Mode Identification.
16.3.5 Reeling Controls
CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and
TMRU-2. By choosing the IRQ3 as the c a pture signa l, a nd by c ounti ng t he CFG within t he
duration of the reel pulse being input through the
,54
pin, reeling controls, etc. can be
effected.
For exemplary settings for the register, see section 16.5.2, Reeling Controls.
16.3.6 Acceleration and Braking Processes of the Capstan Motor
When making intermittent movements such as those for slow reproductions or for still
reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan
motor. The acceleration and braking processes will function to check if the revolution of a
capstan motor has reached the prescribed rate when accelerated or braked. For this purpose, the
TMRU-2 (reloading func t ion) should be used.
When making accelerations:
(1) Set the AC/BR bit of the TMRM1 to acceleration. (Set to 1). Also, use the rising edge of
the CFG as the reloading signal.
(2) Set the prescribed time on the CFG frequency to deem as the acceleration has been finished,
into the reloading register.
(3) The TMRU-2 will work to down-count the reloading data.
Rev. 2.0, 11/ 00, page 348 of 1037
(4) In case the acceleration has not been finished (in case the CFG signal is not input even when
the prescribed time has elapsed = underflowing of down-counting has occurred), such
underflowing works to set to CFG mask F/F (masking movement) and the reload timer will
be cleared by the CFG.
(5) When the acceleration has been finished (when the CFG signal is input before the prescribed
time has elapsed = reloading movement has been made before the down counter underflows),
an interrupt request will be issued because of the CFG.
When making breaking:
(1) Set the AC/BR bit of the TMRM1 to braking. (Clear to 0). Also, use the rising edge of the
CFG as the reloading signal.
(2) Set the prescribed time on the CFG frequency to deem as the braking has been finished, into
the reloading register.
(3) The TMRU-2 will work to down-count the reloading data.
(4) In case the bra king ha s not be en fi ni shed (when the CFG signal i s input be fore the pre scribe d
time has elapsed = reloading movement has been made before the down counter underflows),
the reload timer movement will continue.
(5) When the acceleration has been finished (when the CFG signal is not input even when the
prescribed time has elapsed = underflowing of down-counting has occurred), interrupt
request will be issued because of the underflowing signal.
The acceleration and braking processes should be employed when making special reproductions,
in combination with the slow tracking mono-multi function being outlined below.
For exemplary settings for the register, see section 16.5.4, Acceleration and Braking Processes
of the Capsta n Motor.
16.3.7 Slow Tracking Mono-multi Function
When performing slow reproductions or still reproductions, the braking timing for the capstan
motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi
function works to measure the time from the rising edge of the DVCTL signal down to the
desired point to issue the interrupt request. In actual programming, this interrupt should be used
to activate the brake of the capstan motor. The TMRU-3 should be used to perform time
measurements for the slow tracking mono-multi function. Also, the braking process can be
made using the TMRU-2. Figure 16.2 below shows the exemplary time series movements when
a slow reproduction is being performed.
For exemplary settings for the register, see section 16.5.3, Slow Tracking Mono-multi Function.
Rev. 2.0, 11/ 00, page 349 of 1037
HSW
FG acceleration detection
Compensation for vertical vibrations
(Supplementary V-pulse)
DVCTL Interrupt
Reloading
Reverse
rotation
Frame feeds
Compensation for
horizontal vibrations Compensation for
horizontal vibrations
Braking
process
Acceleration
process
Slow tracking
delay
C.Rotary
H.AmpSW
Accelerating the
capstan motor
Braking the
drum motor
Slow tracking
moto-multi
Braking the
capstan motor
Servo
Hi-Z
[Legend]
Hi-Z : High impedance state
In case of 4-head SP mode.
In case of 2-head application, H.AmpSW and
C.Rotary should be "Low".
FG stopping detection
Forward
rotation
Figure 16.2 Exemplary Time Series Movements when a Slow Reproduction
Is Being Performe d
Rev. 2.0, 11/ 00, page 350 of 1037
16.4 Interrupt Cause
The interrupt causes for the Timer R are 3-causes of the TMRI3 bit through TMRI1 bit of the
timer R control/status register (TMRCS).
(a) Int e rrupts bei ng c aused by t he underfl owing of t he T MRU-1 (TMRI1)
These interrupts will constitute the timing for reloading with the TMRU-1.
(b) Interrupts being caused by the underflowing of the TMRU-2 or by an end of the acceleration
or braking proce ss (TMRI2)
When interrupts occur at the reload timing of the TMRU-2, clear the AC/BR
(acceleration/braking) bit of the timer R mode register 1 (TMRM1) to 0.
(c) Int e rrupts bei ng c aused by t he ca pt ure signa l s of the T MRU-3 and by endi ng the slow
tracking mono-multi process (TMRI3)
Since these two interrupt causes are constituting the OR, it becomes necessary to determine
which inte rrupt ca use i s occurri ng using t he software .
Respective interrupt causes are being set to the CAPF flag o r the SL W fl a g o f the timer R
mode register 2 (TMRM2), have the software determine which.
Since t h e C APF flag a n d t h e SL W fl a g will not be cleared automatically, program the
software to clear them. (Writing 0 only is valid for these flags.) Unless these flags are
cleared, detection of the next cause becomes unworkable. Also, if the CP/SLM bit is
changed leaving these flags un-cleared as they are, these flags will get cleared.
Rev. 2.0, 11/ 00, page 351 of 1037
16.5 Exemplary S et t i n gs f or Resp ect i ve Fun ct ion s
16.5.1 Mode Identification
When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing
tapes, the T MRU-1 (CFG dividing circ ui t), T MRU-2 (capt uring func t ion/ wit hout re l oadi ng
function) and TMRU-3 (DVCTL dividing circuit) of the Timer R should be used.
The Timer R will become to the aforementioned status after a reset.
Under the aforementioned status, the divided CFG should be written into the reloading register
of the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU-
3. Whe n the T MRU-3 underflows, the count e r val ue of the T MRU-2 is capture d. Such
capturing register value represents the number of the CFG within the DVCTL cycle.
As aforementioned, the Timer R can work to count the number of the CFG corresponding to "n"
times of DVCTL's or to identify the mode being searched.
• Exemplary settings
(1) Setting the timer R mode register 1 (TMRM1)
CLR2 bit (Bit 7) = 1: Works to clear after making the TMRU-2 capture.
RLD bit (Bit 5) = 0: Sets the TMRU-3 without reloading function.
PS21 and PS20 (Bits 3 and 2) = (0 and 0): The unde rflowing signa l s of the T MRU-1 are
to be used as the c loc k source for the T MRU-2.
RLD/CAP bit (Bit 1) = 0: The TMRU-1 has been set to make the reload timer operation.
(2) Setting the timer R mode register 2 (TMRM2)
LAT bit (Bi t 7) = 0: T he unde rfl owing signal s of the TMRU-3 are t o be used as the
capture signa l for t he TMRU-2.
PS11 and PS10 (Bits 6 and 5) = (0 and 0): The leading edge of the CFG signal is to be
used as the cl oc k source for t he TMRU-1.
PS31 and PS30 (Bits 4 and 3) = (0 and 0): The leading edge of the DVCTL signal is to be
used as the cl oc k source for t he TMRU-3.
CP/SLM bit (Bit 2) = 0: The c apt ure signal i s to work to issue the T MRI3 inte rrupt
request.
(3) Setting the timer R load register 1 (TMRL1)
Set the di vi ding va l ue for t he CFG. The set va l ue should be c ome (n - 1) when di vide d by
"n".
(4) Setting the timer R load register 3 (TMRL3)
Set the di vi ding va l ue for t he DVCTL. The set val ue should bec om e (n - 1) when di vi ded
by "n".
Rev. 2.0, 11/ 00, page 352 of 1037
16.5.2 Reeling Controls
CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and
TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration
of the reel pulse being input through the
,54
pin, r eelin g con tr o ls , etc. can b e ef f ected .
• Exemplary settings
(1) Setting P13/
,54
pin as the
,54
pin
Set the PMR13 bit (Bit 3) of the port mode register 1 (PMR1) to 1. See section 22.2. 2,
Port Mode Register (PMR1).
(2) Setting the timer R mode register 1 (TMRM1)
CLR2 bit (Bit 7) = 1: Works to clear after making the TMRU-2 capture.
PS21 and PS20 (Bits 3 and 2) = (0 and 0): The unde rflowing signa l s of the T MRU-1 are
to be used as the c loc k source for the T MRU-2.
RLD/CAP bit (Bit 1) = 1: The TMRU-1 has been set to make the capturing operation.
CPS bit (Bit 0) = 1: T he e dge of the IRQ3 signal is to be used a s the c a pture signa l for t he
TMRU-1 and TMRU-2.
(3) Setting the timer R mode register 2 (TMRM2)
LAT bit (Bit 7) = 1: The edge of the IRQ3 signal is to be used as the capture signal for
the TMRU-1 and TMRU-2.
PS11 and PS10 (Bits 6 and 5) = (0 and 0): The ri sing edge of t he CFG signal i s to be used
as the cl oc k source for t he TMRU-1.
CP/SLM bit (Bit 2) = 0: The c apt ure signal i s to work to issue the T MRI3 inte rrupt
request.
16.5.3 Slow Tracking Mono-multi Function
When performing slow reproductions or still reproductions, the braking timing for the capstan
motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi
function works to measure the time from the leading edge of the DVCTL signal down to the
desired point to issue the interrupt request. In actual programming, this interrupt should be used
to activate the brake of the capstan motor. The TMRU-3 should be used to perform time
measurements for the slow tracking mono-multi function. Also, the braking process can be
made using the TMRU-2.
• Exemplary settings
(1) Setting the timer R mode register 2 (TMRM2)
PS31 and PS30 (Bits 4 and 3) = Other than (0, 0): T he di vi ding c l ock i s to be used as the
clock source for t he T MRU-3.
CP/SLM bit (Bit 2) = 1: The slow tracking delay signal is to work to issue the TMRI3
interrupt re quest.
Rev. 2.0, 11/ 00, page 353 of 1037
(2) Setting the timer R load register 3 (TMRL3)
Set the slow tracking delay value. When the delay count is "n", the set value should be
(n - 1).
Regarding the delaying duration, see figure 16.2 Exemplary time series movements
when a sl ow reproduction is being performed.
16.5.4 Acceleration and Braking Processes of the Capstan Motor
When making intermittent movements such as those for slow reproductions or for still
reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan
motor. The acceleration and braking processes will function to check if the revolution of a
capstan motor has reached the prescribed rate when accelerated or braked. For this purpose, the
TMRU-2 (reloading func t ion) should be used.
The acceleration and braking processes should be employed when making special reproductions,
in combination with the slow tracking mono-multi function.
• Exemplary settings for the acceleration process
(1) Setting the timer R mode register 1 (TMRM1)
AC/BR bit (Bit 6) = 1: Acceleration process
RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer.
RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.
PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): T he di vi ding c l ock i s to be used as the
clock source for t he T MRU-2.
(2) Setting the timer R load register 2 (TMRL2)
Set the count reading for the duration until the acceleration process finishes. When the
count is "n", the set val ue should be (n - 1).
Regarding the duration until the acceleration process finishes, see figure 16.2 Exemplary
time series movements when a slow reproduction is being performed.
• Exemplary settings for the braking process
(1) Setting the timer R mode register 1 (TMRM1)
AC/BR bit (Bit 6) = 0: Bra ki ng proce ss
RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer.
RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.
PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): T he di vi ding c l ock i s to be used as the
clock source for t he T MRU-2.
Rev. 2.0, 11/ 00, page 354 of 1037
(2) Setting the timer R load register 2 (TMRL2)
Set the count reading for the duration until the braking process finishes. When the count
is "n", the set va l ue should be (n - 1).
Regarding the duration until the braking process finishes, see figure 16.2 Exemplary time
series movements when a slow reproduction is being performed.
Rev. 2.0, 11/ 00, page 355 of 1037
Section 17 Timer X1
17.1 Overview
The Timer X1 is capable of outputting two different types of independent waveforms using the
free running counter (FRC) as the basic means and it is also applicable to measurements of the
durations of input pulses and the cycles external clocks.
17.1.1 Features
Listed below are the features of the Timer X1.
• Choices of 4 different types of counter inputting clocks are available for your selection.
You can select from among three different types of internal clocks (φ/4, φ/16 and φ/ 64) and
the DVCFG.
• Two independent out put c om pari ng func ti ons
Capable of out putt i ng two diffe re nt t ype s of indepe nde nt wave form s.
• Four independent input capturing functions
The rising edge or falling edge can be selected for use. The buffer operation can also be
designated.
• Counter clearing designation is workable.
The counter readings can be cleared by compare match A.
• Seven types of inte rrupt ca uses
Comparing match × 2 causes, input c a pture × 4 c auses and ove rfl ow × 1 cause are available
for use and they can make respective interrupt requests independently.
Rev. 2.0, 11/ 00, page 356 of 1037
17.1.2 Block Diagram
Figure 17.1 shows a block diagram of the Timer X1.
Internal data bus
[Legend]
TIER
ICRA
ICRB
ICRC
ICRD
TCRX
OCRB
Comparison circuit
FRC
Comparison circuit
OCRA
TOCR
TCSRX
TIER
Input
capture
control
Output comparing output
Interrupt
request 7
FTOA
FTOB
FTIA*
(HSW)
FTIB*
(VD)
FTIC*
(DVCTL)
FTID*
(NHSW)
(DVCFG)
/ 4
/ 16
/ 64
TCSRX
FRC
OCRA
OCRB
TCRX
TOCR
ICRA
ICRB
ICRC
ICRD
: Timer interrupt enabling register
: Timer control/status register X
: Free running counter
: Output comparing register A
: Output comparing register B
: Timer control register X
: Output comparing control register
: Input capture register A
: Input capture register B
: Input capture register C
: Input capture register D
Note: *stands for the external terminal.
( ) stands for the internal signal.
Figure 17. 1 Bl oc k Diagram of the Time r X1
Rev. 2.0, 11/ 00, page 357 of 1037
17.1.3 Pin Configuration
Table 17.1 shows the pin configuration of the Timer X1.
Table 17.1 Pin Configuration
Name Abbrev. I/O Function
Out put com par ing A output - pin FTOA O utput O ut put pin f or t he output com par ing A
Out put com par ing B output - pin FTOB O utput O ut put pin f or t he output com par ing B
Input capt ur e A input- pin FTI A Input Input- pin f or t he input capt ur e A
Input capt ur e B input- pin FTI B Input Input- pin f or t he input capt ur e B
Input capt ur e C input- pin FTIC Input Input- pin for the input capture C
Input capt ur e D input- pin FTID Input Input- pin for the input capture D
Rev. 2.0, 11/ 00, page 358 of 1037
17.1.4 Register Configuration
Table 17.2 shows the register configuration of the Timer X1.
Table 17.2 Register Configuration
Name Abbrev. R/W Ini tial Value Address*3
Timer int er r upt enabling regist er TIER R/W H'00 H'D100
Timer contr ol/ st at us r egister X TCSRX R/ ( W) *1H'00 H'D101
Free running count er H FRCH R/W H'00 H'D102
Free running count er L FRCL R/W H'00 H'D103
Out put com par ing regist er AH OCRAH R/W H'FF H'D104*2
Out put com par ing regist er AL OCRAL R/ W H'FF H'D105*2
Out put com par ing regist er BH OCRBH R/W H'FF H'D104*2
Out put com par ing regist er BL OCRBL R/ W H'FF H'D105*2
Timer cont r ol regist er X TCRX R/W H'00 H'D106
Timer out put com par ing cont r ol regist er TOCR R/W H'00 H'D107
Input capt ur e r egist er AH ICRAH R H'00 H'D108
Input capt ur e r egist er AL ICRAL R H'00 H'D109
Input capt ur e r egist er BH ICRBH R H'00 H'D10A
Input capt ur e r egist er BL ICRBL R H'00 H'D10B
Input capture r egis t er CH ICRCH R H'00 H'D10C
Input capture r egis t er CL ICRCL R H'00 H'D10D
Input capture r egis t er DH ICRDH R H'00 H'D10E
Input capture r egis t er DL ICRDL R H'00 H'D10F
Notes: 1. Only 0 can be writt en t o clear the flag for Bits 7 t o 1. Bit 0 is r eadable/wr itable.
2. The addresses of t he O CRA and OCRB are the sam e. Changeover between t hem
are to be made by use of t he TO CR bit and O CRS bit.
3. Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 359 of 1037
17.2 Descripti on s of Respective Regi st ers
17.2.1 Free Runni ng Count e r (F RC)
Free running count e r H (FRCH)
Free running count e r L (FRCL)
0
3
0
R/W
5
0
R/W
7
0
9
0
R/W
11
0
13
0
15
R/WR/WR/W
0
R/W R/W
1
0
2
0
R/W
4
0
R/W
6
0
8
0
R/W
10
0
12
0
14
FRC
FRCH FRCL
R/WR/WR/WR/W
0
R/W
0
Bit :
Initial value :
R/W :
The FRC is a 16-bit read/write up-counter which counts up by the inputting internal
clock/external clock. The inputting clock is to be selected from the CKS1 and CKS0 of the
TCRX.
By the setting of the CCLRA bit of the TCSRX, the FRC can be cleared by comparing match A.
When t h e FR C ov e r f l o ws (H'FFFF → H'0000), t he OVF of t he T C SRX will be set to 1.
At this time, when the OVIE of the TIER is being set to 1, an interrupt request will be issued to
the CPU.
Reading/ writ ing c a n be m a de from a nd to t he FRC through the CPU at 8-bi t or 16-bi t .
The FRC is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Rev. 2.0, 11/ 00, page 360 of 1037
17. 2 .2 Out put Co m paring Re g i st e r A and B ( O CRA a nd O CRB )
Output compa ri ng regi ste r AH and BH (OCRAH and OCRBH)
Output compa ri ng regi ste r AL and BL (OCRAL and OCRBL)
1
3
1
R/W
5
1
R/W
7
1
9
1
R/W
11
1
13
1
15
R/WR/WR/W
1
R/W R/W
1
1
2
1
R/W
4
1
R/W
6
1
8
1
R/W
10
1
12
1
14
OCRA, OCRB
OCRAH, OCRBH OCRAL, OCRBL
R/WR/WR/WR/W
1
R/W
0
Bit :
Initial value :
R/W :
The OCR consists of twin 8-bit read/write registers (OCRA and OCRB). The contents of the
OCR are always being compared with the FRC and, when the value of these two match, the
OCFA and OCRB of the TCSRX will be set to 1. At this time, if the OCIAE and OCIB of the
TIER are being set to 1, an interrupt request will be issued to the CPU.
When performing compare matching, if the OEA and OEB of the TOCR are being set to 1, the
level value having been set to the OLVLA and OLVLB of the TOCR will be output through the
FTOA and FTOB pins. After resetting, 0 will be output through the FTOA and FTOB pins until
the first compare matching occurs.
Reading/ writ ing c a n be m a de from a nd to t he OCR through the CPU at 8-bi t or 16-bi t .
The OCR is cleared to H'FFFF when reset or unde r t he st a ndby mode , watch mode, subsleep
mode, module stop mode or subactive mode.
Rev. 2.0, 11/ 00, page 361 of 1037
17. 2 .3 Input Capt ur e Regi st e r A T hr o ug h D (ICRA T hr o ug h ICRD)
Input capt ure regi ste r AH to DH (ICRAH to ICRDH)
Input capt ure regi ste r AL to DL (ICRAL t o ICRDL)
0
3
0
R
5
0
R
7
0
9
0
R
11
0
13
0
15
RRR
0
RR
1
0
2
0
R
4
0
R
6
0
8
0
R
10
0
12
0
14
ICRA, ICRB, ICRC, ICRD
ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL
RRRR
0
R
0
Bit :
Initial value :
R/W :
The ICR consists of four 16-bit re ad onl y re giste rs (ICRA through ICRD).
When the falling edge of the input capture input signal is detected, the value is transferred to the
ICRA through ICRD. At this time, the ICFA through ICFD of the TCSRX are set to 1
simultaneously. At this time, if the IDIAE through IDIDE of the TCRX are all being set to 1,
due interrupt request will be issued to the CPU. The edge of the input signal can be selected by
setting the IEDGA through IEDGD of t he T CRX.
Also, the ICRC and ICRD can be used as the buffer register, respectively, of the ICRA and
ICRB by setting the BUFEA and BUFEB of the TCRX to perform buffer operations. Figure
17.2 shows the connections necessary when using the ICRC as the buffer register of the ICRA.
(BUFE A = 1 )
When the ICRC is used as the buffer of the ICRA, by setting IEDGA ≠ IE DGC, both of t he
rising and falling edges can be designated for use. In case of IEDGA = I E DGC , either one of the
rising edge or the falling edge only is usable. Regarding selection of the input signal edge, see
table 17.3.
Note: Transference from the FRC to the ICR will be performed regardless of the value of the
ICF.
Rev. 2.0, 11/ 00, page 362 of 1037
Edge detection and
capture signal
generating circuit.
BUFEAIEDGA
FTIA
IEDGC
ICRC ICRA FRC
Figure 17. 2 Buffer O perati on (an example)
Tabl e 1 7 . 3 Input Signal Edge Selection when Making Buffer Operation
IEDG A IEDGC Sel ect i on of the Input Si gnal Edge
0 Captur es at t he r ising edge of the input captur e input A (Initial value)
0
1
0
Captur es at both rising and falling edges of t he input capture input A
1
1 Captur es at t he r ising edge of the input captur e input A
Reading c a n be m a de from t he ICR t hrough t he CPU at 8-bi t or 16-bit .
For stable input capturing operation, maintain the pulse duration of the input capture input
signals at 1.5 system clock (φ) or more in case of single edge capturing and at 2.5 system clock
(φ) or more i n ca se of bot h edge c apt uri ng.
The ICR is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Rev. 2.0, 11/ 00, page 363 of 1037
17.2.4 Timer Interr upt Enabling Register (TIER)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ICICE
R/W
ICIBE
0
R/W
ICIAE ICIDE OCIAE OCIBE OVIE ICSA
Bit :
Initial value :
R/W :
The TIER is an 8-bit read/write register which works to control permission/prohibition of
respective interrupt requests.
The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Bit 7 : E na bl i ng t he Input Capt ur e Inte r rupt A (ICIAE )
This bit works to permit/prohibit interrupt requests (ICIA) by the ICFA when the ICFA of the
TCSRX is being set to 1.
Bit 7
ICIAE Description
0 Prohibits inter r upt r equests (I CI A) by the ICFA (Initial value)
1 Permit s int er r upt r equest s ( I CI A) by t he ICFA
Bit 6 : E na bl i ng t he Input Capt ur e Inte r rupt B ( ICIB E)
This bit works to permit/prohibit interrupt requests (ICIB) by the ICFB when the ICFB of the
TCSRX is being set to 1.
Bit 6
ICIBE Description
0 Prohibits inter r upt r equests (I CI B) by the ICFB (Initial value)
1 Permit s int er r upt r equest s ( I CI B) by t he ICFB
Bit 5 : E na bl i ng t he Input Capt ur e Inte r rupt C (ICICE )
This bit works to permit/prohibit interrupt requests (ICIC) by the ICFC when the ICFC of the
TCSRX is being set to 1.
Bit 5
ICICE Description
0 Prohibits inter r upt r equests (I CI C) by t he ICFC (Initial value)
1 Permit s int er r upt r equest s ( I CI C) by t he ICFC
Rev. 2.0, 11/ 00, page 364 of 1037
Bit 4 : E na bl i ng t he Input Capt ur e Inte r rupt D (ICIDE )
This bit works to permit/prohibit interrupt requests (ICID) by the ICFD when the ICFD of the
TCSRX is being set to 1.
Bit 4
ICIDE Description
0 Prohibits inter r upt r equests (I CI D) by t he ICFD (Initial value)
1 Permit s int er r upt r equest s ( I CI D) by t he ICFD
Bit 3 : E na bl i ng t he O ut put Com pa r i ng Int e r rupt A ( O CIAE )
This bit works to permit/prohibit interrupt requests (OCIA) by the OCFA when the OCFA of the
TCSRX is being set to 1.
Bit 3
OCIAE Description
0 Prohibits inter r upt r equests (O CI A) by the OCFA (I nit ial value)
1 Permit s int er r upt r equest s ( O CI A) by the OCFA
Bit 2: Enabling the Output Compari ng Interrupt B (OCIBE)
This bit works to permit/prohibit interrupt requests (OCIB) by the OCFB when the OCFB of the
TCSRX is being set to 1.
Bit 2
OCIBE Description
0 Prohibits inter r upt r equests (O CI B) by the OCFB (I nit ial value)
1 Permit s int er r upt r equest s ( O CI B) by the OCFB
Bit 1: Enabling the Timer O ve rfl ow Interrupt (OVIE)
This bit works to permit/prohibit interrupt requests (FOVI) by t he OVF whe n t h e OVF o f the
TCSRX is being set to 1.
Bit 1
OVIE Description
0 Prohibits inter r upt r equests (FO VI ) by t he O VF (Init ial value)
1 Permit s int er r upt r equest s ( FO VI ) by t he O VF
Rev. 2.0, 11/ 00, page 365 of 1037
Bit 0: Selecting the Input Captur e A Si g na l s ( ICSA)
This bit works to select the input capture A signals.
Bit 0
ICSA Description
0 Selects the FTI A pin for inputting of t he input capt ur e A signals (Initial value)
1 Selects the HSW f or inputting of the input capt ur e A signals
Rev. 2.0, 11/ 00, page 366 of 1037
17. 2 .5 Ti mer Co nt r o l / St a tus Regi st e r X ( T CSRX)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/(W)*
ICFB
0
R/(W)*
ICFA
R/(W)*
ICFD
R/(W)*
ICFC
R/(W)*
OCFB
R/(W)*
OCFA CCLRA
R/(W)*
OVF
Note: * Only 0 can be written to clear the flag for Bits 7 to 1.
Bit :
Initial value :
R/W :
The TCSRX is an 8-bit register which works to select counter clearing timing and to control
respective interrupt requesting signals. The TCSRX is initialized to H'00 when reset or under
the standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
Meanwhile, as for the timing, see section 17.3, Operation.
The FTIA through FTID pins are for fi xe d input s inside the L SI under the l ow power
consumption mode excluding the sleep mode. Consequently, when such shifts as "active mode
→ low power consumption mode → active mode" are made, wrong edges may be detected
depending on the pin status or on the type of the detecting edge.
To avoid such error, clear the interrupt requesting flag once immediately after shifting to the
active mode from the low power consumption mode.
Bit 7 : Input Ca pture F l a g A (ICFA)
This is a status flag indicating the fact that the value of the FRC has been transferred to the
ICRA by the input c a pture signa ls.
When the BUFEA of the TCRX is being set to 1, the ICFA indicates the status that the FRC
value ha s bee n tra nsferre d to t he ICRA by the i nput ca pt ure signa l s and tha t the ICRA val ue
before being updated has been transferred to the ICRC.
This flag should be cleared by use of of the software. Such setting should only be made by use
of the hardware. It is not possible to make this setting using a software.
Bit 7
ICFA Description
0 [Clearing conditions] (Init ial value)
When 0 is written int o t he I CFA after r eading the ICFA under the set t ing of I CFA = 1
1 [Sett ing conditions]
When the value of the FRC has been transf er r ed t o t he ICRA by the input captur e
signals
Rev. 2.0, 11/ 00, page 367 of 1037
Bit 6 : Input Ca pture F l a g B ( ICF B )
This is a status flag indicating the fact that the value of the FRC has been transferred to the
ICRB by the input c apt ure signal s.
When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC
value ha s bee n tra nsferre d to t he ICRB by the i nput c a pture signa ls and t ha t t he ICRB val ue
before being updated has been transferred to the ICRC.
This flag should be cleared by use of the software. Such setting should only be made by use of
the hardware. It is not possible to make this setting using a software.
Bit 6
ICFB Description
0 [Clearing conditions] (Init ial value)
When 0 is written int o t he I CFB after r eading the ICFB under the set t ing of I CFB = 1
1 [Sett ing conditions]
When the value of the FRC has been transf er r ed t o t he ICRB by the input captur e
signals
Bit 5 : Input Ca pture F l a g C (ICFC)
This is a status flag indicating the fact that the value of the FRC has been transferred to the
ICRC by the input c apt ure signal s.
When an input capture signal occurs while the BUFEA of the TCRX is being set to 1, although
the ICFC will be set out, data transference to the ICRC will not be performed.
Therefore, in buffer operation, the ICFC can be used as an external interrupt by setting the
ICICE bit t o 1.
This flag should be cleared by use of the software. Such setting should only be made by use of
the hardware. It is not possible to make this setting using a software.
Bit 5
ICFC Description
0 [Clearing conditions] (Init ial value)
When 0 is written int o t he I CFC aft er reading the I CFC under t he setting of ICFC = 1
1 [Sett ing conditions]
When the input capt ur e signal has occurr ed
Rev. 2.0, 11/ 00, page 368 of 1037
Bit 4 : Input Ca pture F l a g D (ICFD)
This is a status flag indicating the fact that the value of the FRC has been transferred to the
ICRD by the input c a pture signa ls.
When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although
the ICFD will be set out, data transference to the ICRD will not be performed.
Therefore, in buffer operation, the ICFD can be used as an external interrupt by setting the
ICIDE bit to 1.
This flag should be cleared by use of the software. Such setting should only be made by use of
the hardware. It is not possible to make this setting using a software.
Bit 4
ICFD Description
0 [Clearing conditions] (Init ial value)
When 0 is written int o t he I CFD aft er reading the I CFD under t he setting of ICFD = 1
1 [Sett ing conditions]
When the input capt ur e signal has occurr ed
Bit 3: Output Comparing Flag A (OCFA)
This is a status flag indicating the fact that the FRC and the OCRA have come to a comparing
match.
This flag should be cleared by use of the software. Such setting should only be made by use of
the hardware. It is not possible to make this setting using a software.
Bit 3
OCFA Description
0 [Clearing conditions] (Init ial value)
When 0 is written int o t he O CFA after r eading the OCFA under the set t ing of O CFA
= 1
1 [Sett ing conditions]
When the FRC and the O CRA have come to t he com par ing m at ch
Rev. 2.0, 11/ 00, page 369 of 1037
Bit 2: Output Comparing Flag B (OCFB)
This is a status flag indicating the fact that the FRC and the OCRB have come to a comparing
match.
This flag should be cleared by use of the software. Such setting should only be made by use of
the hardware. It is not possible to make this setting using a software.
Bit 2
OCFB Description
0 [Clearing conditions] (Init ial value)
When 0 is written int o t he O CFB after r eading the OCFB under the set t ing of O CFB
= 1
1 [Sett ing conditions]
When the FRC and the O CRB have come to t he com par ing m at ch
Bit 1: Time O ve r F l ow (OVF)
This is a status flag indicating the fact that the FRC overflowed. (H'FFFF → H'0000).
This flag should be cleared by use of the software. Such setting should only be made by use of
the hardware. It is not possible to make this setting using a software.
Bit 1
OVF Description
0 [Clearing conditions] (Init ial value)
When 0 is written int o t he O VF af t er reading the O VF under t he setting of OVF = 1
1 [Sett ing conditions]
When the FRC value has become H'FFFF → H'0000
Bit 0 : Co unt e r Cle aring ( CCLRA)
This bit works to select if or not to clear the FRC by occurrence of comparing match A
(matching signal of the FRC and OCRA).
Bit 0
CCLRA Description
0 Prohibits clearing of t he FRC by occurr ence of comparing mat ch A (I nit ial value)
1 Permit s clearing of t he FRC by occurr ence of com par ing m at ch A
Rev. 2.0, 11/ 00, page 370 of 1037
17. 2 .6 Ti mer Co nt r o l Re g i st e r X (TCRX)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
IEDGB
0
R/W
IEDGA
R/W
IEDGD
R/W
IEDGC
R/W
BUFEB
R/W
BUFEA CKS0
R/W
CKS1
Bit :
Initial value :
R/W :
The TCRX is an 8-bit read/write register which works to select the input capture signal edge, to
designate the buffer operation and to select the inputting clock for the FRC.
The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Bit 7 : Input Ca pture Si g nal Edge Selection A (IEDGA)
This bit works to select the rising edge or falling edge of the input capture signal A (FTIA).
Bit 7
IEDGA Description
0 Captures the falling edge of the input capt ur e signal A (Init ial value)
1 Captures the rising edge of t he input capt ure signal A
Bit 6 : Input Ca pture Si g nal Edge Selection B (IEDGB)
This bit works to select the rising edge or falling edge of the input capture signal B (FTIB).
Bit 6
IEDGB Description
0 Captures the falling edge of the input capt ur e signal B (Init ial value)
1 Captures the rising edge of t he input capt ure signal B
Bit 5 : Input Ca pture Si g nal Edge Selection C (IEDGC)
This bit works to select the rising edge or falling edge of the input capture signal C (FTIC).
However, when the DVCTL has been selected as the signal for the input capture signal edge
selection C, this bit will not influence the operation.
Bit 5
IEDGC Description
0 Captures the falling edge of the input capt ur e signal C ( Initial value)
1 Captures the rising edge of t he input capt ure signal C
Rev. 2.0, 11/ 00, page 371 of 1037
Bit 4 : Input Ca pture Si g nal Edge Selection D (IEDGD)
This bit works to select the rising edge or falling edge of the input capture signal D (FTID).
Bit 4
IEDGD Description
0 Captures the falling edge of the input capt ur e signal D ( Initial value)
1 Captures the rising edge of t he input capt ure signal D
Bit 3: Buffer Enabling A (BUFEA)
This bit works to select if or not to use the ICRC as the buffer register for the ICRA.
Bit 3
BUFEA Description
0 Usin g the ICRC as the b u ffe r r eg is ter f or t h e ICRA (Init ia l v a lu e)
1 Not us ing the ICRC as the b u ff e r reg is ter for the ICRA
Bit 2: Buffer Enabling B (BUFEB)
This bit works to select if or not to use the ICRD as the buffer register for the ICRB.
Bit 2
BUFEB Description
0 Usin g the ICRD as the b u ffe r r eg is ter f or t h e ICRB (Init ia l v a lu e)
1 Not us ing the ICRD as the b u ff e r reg is ter for the ICRB
Bits 1 and 0: Clock Select (CKS1, 0)
These bits work to select the inputting clock to the FRC from among three types of internal
clocks and the DVCFG.
The DVCFG is the edge detecting pulse selected by the CFG dividing timer.
Bit 1 Bit 0
CKS1 CKS0 Description
0 0 Int er nal clock: Counts at φ/4 (Init ial value)
0 1 Internal clock: Counts at φ/16
1 0 Int er nal clock: Counts at φ/64
1 1 DVCFG: The edge det ect ing pulse selected by t he CFG dividing timer
Rev. 2.0, 11/ 00, page 372 of 1037
17.2.7 Timer Output Comparing Control Register (TOCR)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/W R/W
ICSC
0
R/W
ICSB
R/W
OSRS
R/W
ICSD
R/W
OEB
R/W
OEA OLVLB
R/W
OLVLA
Bit :
Initial value :
R/W :
The TOCR is an 8-bit read/write register which works to select input capture signals and output
comparing output level, to permit output comparing outputs and to control switching over of the
access of the OCRA and OCRB. See the section 17.2. 4 Timer Interrupt Enabling Register
(TIER) rega rdi ng the i nput c a pture i nputs A.
The TOCR is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Bit 7: Selecting the Input Captur e B Si g nals (ICSB )
This bit works to select the input capture B signals.
Bit 7
ICSB Description
0 Selects the FTI B pin for inputting of t he input capt ur e B signals (Initial value)
1 Selects the VD as the input capt ur e B signals
Bit 6: Selecting the Input Captur e C Si g na l s ( ICSC)
This bit works to select the input capture C signals. The DVCTL is the edge detecting pulse
selected by the CTL dividing timer.
Bit 6
ICSC Description
0 Selects the FTI C pin for input t ing of t he input capt ur e C signals ( I nit ial value)
1 Selects the DVCTL as the input capt ur e C signals
Bit 5: Selecting the Input Captur e D Si g na l s ( ICSD)
This bit works to select the input capture D signals.
Bit 5
ICSD Description
0 Selects the FTI D pin for input t ing of t he input capt ur e D signals ( I nit ial value)
1 Selects the NHSW as the input capt ur e D signals
Rev. 2.0, 11/ 00, page 373 of 1037
Bit 4: Selecting the Output Comparing Register (OCRS)
The addresses of the OCRA and OCRB are the same. The OCRS works to control which
register to choose when reading/writing this address. The choice will not influence the operation
of the OCRA and OCRB.
Bit 4
OCRS Description
0 Selects the O CRA register (Init ial value)
1 Selects the O CRB register
Bit 3: Enabling the Output A (OEA)
This bit works to cont rol the out put c om pari ng A signal s.
Bit 3
OEA Description
0 Prohibits t he out put com par ing A signal outputs (Initial value)
1 Permit s t he output com par ing A signal outputs
Bit 2: Enabling the Output B (OEB)
This bit works to cont rol the out put c om pari ng B signa ls.
Bit 2
OEB Description
0 Prohibits t he out put com par ing B signal outputs (Initial value)
1 Permit s t he output com par ing B signal outputs
Bit 1: Output Level A (OLVLA)
This bit works to select the output level to output through the FTOA pin by use of the comparing
match A (matching signal between the FRC and OCRA).
Bit 1
OLVLA Description
0 Lo w le v el (Init ia l v a lu e)
1 High le v el
Rev. 2.0, 11/ 00, page 374 of 1037
Bit 0: Output Level B (OLVLB)
This bit works to select the output level to output through the FTOB pin by use of the comparing
match B (matching signal between the FRC and OCRB).
Bit 0
OLVLB Description
0 Lo w le v el (Init ia l v a lu e)
1 High le v el
Rev. 2.0, 11/ 00, page 375 of 1037
17. 2 .8 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
0
MSTP15
R/W
MSTPCRH
6
0
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR consists of twin 8-bit read/write registers and it works to control the module stop
mode.
When the MSTP10 bit is set to 1, the Timer X1 stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop
Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 2: Module Stop (MSTP10)
This bit works to designate the module stop mode for the Timer X1.
MSTPCRH
Bit 2
MSTP10 Description
0 Cancels t he m odule st op m ode of the Timer X1
1 Sets the module st op m ode of t he Tim er X1 (I nit ial value)
Rev. 2.0, 11/ 00, page 376 of 1037
17.3 Operation
17.3.1 Operation of the Timer X1
(1) Output Comparing Operation
Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting
clock can be selected from among three different types of internal clocks or the external
clock by setting the CKS1 and CKS0 of the TCRX.
The cont e nts of the FRC are al ways bei ng com pa red wit h t he OCRA and OCRB and, when
the value of these two match, the level set by the the OLVLA and OLVLB of the TOCR is
output through t he FTOA pin and FTOB pin.
After resetting, 0 will be output through the FTOA and FTOB pins until the first compare
matching occurs.
Also, when the CCLRA of the TCSRX is being set to 1, the FRC will be cleared to H'0000
when the comparing match A occurs.
(2) Input Capturing Operation
Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting
clock can be selected from among three different types of internal clocks or the external
clock by setting the CKS1 and CKS0 of the TCRX.
The i nput s a re t ra nsfe rred t o t he IE DGA t hrough IE DGD of t he TCRX t hrough t he FT IA
through FTID pins and, at the same time, the ICFA through ICFD of the TCSRX are set to 1.
At this time, if the ICIAE through ICIED of the TIER are being set to 1, due interrupt request
will be issued to the CPU.
When the BUFEA and BUFEB of the T CRX are set t o 1, the ICRC a nd ICRD work as the
buffer register, respectively, of the ICRA and ICRB. When the edge selected by setting the
IEDGA through IE DGD of t he T CRX is i nput through t he FT IA a nd FT IB pi ns, t he val ue a t
the time of the FRC is transferred to the ICRA and ICRB and, at the same time, the values of
the ICRA and ICRB before updating are transferred to the ICRC and ICRD. At this time,
when the ICFA and ICFB are bei ng set to 1 a nd i f the ICIAE a nd ICIBE of t he TIE R a re
being set to 1, due interrupt request will be issued to the CPU.
Rev. 2.0, 11/ 00, page 377 of 1037
17.3.2 Counting Timing of the FRC
The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the
inputting clock can be selected from among three different types of clocks (φ/4, φ/16 a nd φ/64)
and t h e DVC FG.
(1) In Case of Internal Clock Operation
By setting the CKS1 and CKS0 bits of the TCRX, three types of internal clocks (φ/4, φ/16
and φ/64), generated by dividing the system clock (φ) can be selected. Figure 17.3 shows the
timing chart at this time.
FRC
Internal clock
FRC input
clock
NN-1 N+1
Figure 17. 3 Count Timing in Case of Internal Clock Operation
(2) In Case of DVCFG Clock Operation
By setting the CKS1 and CKS0 bits of the TCRX to 1, DVCFG clock input can be selected.
The DVCFG clock makes counting by use of the edge detecting pulse being selected by the
CFG dividing timer.
Figure 17.4 shows the timing chart at this time.
FRC
CFG
FRC input
clock
N N+1
DVCFG
Figure 17. 4 Count Timing in Case of CFG Clock Operati on
Rev. 2.0, 11/ 00, page 378 of 1037
17.3.3 Output Comparing Signal Outputting Timing
When a comparing match occurs, the output level having been set by the OLVL of the TOCR is
output through the output comparing signal outputting pins (FTOA and FTOB).
Figure 17.5 shows the timing chart in case of the output comparing signal outputting A.
FRC
OLVLA
FTOA
Output comparing
signal outputting
A pin
N
N
Clearing
*1
N
N
N+1N+1
Comparing match
signal
OCRA
Note: 1. Execution of the command is to be designated by the software.
Figure 17. 5 O utput Comparing Signal Outputti ng A Timing
17.3.4 FRC Cle ar ing Timi ng
The FRC can be cleared when the comparing match A occurs. Figure 17.6 shows the timing
chart when doing so.
FRC
Comparing match
A signal
N H' 0000
Figure17.6 FRC Clearing Timing by Occurrence of the Comparing Match A
Rev. 2.0, 11/ 00, page 379 of 1037
17. 3 .5 Input Capt ur e Signal Inputting T i m i ng
(1) Input Capture Signal Inputting Timing
As for the input capture signal inputting, rising or falling edge is selected by settings of the
IEDGA through IE DGD bi t s of t he T CRX.
Figure 17.7 shows the timing chart when the rising edge is selected (IEDGA t hrough IE DGD
= 1).
Input capture signal
inputting pin
Input capture signal
Fig ure 17.7 Input Capture Si gnal Inputti ng Ti ming (unde r nor mal state )
(2) Input Capture Signal Inputting Timing when Making Buffer Operation
Buffer operation can be made using the ICRA or ICRD as the buffer of the ICRA or ICRB.
Figure 17.8 shows the input capture signal inputting timing chart in case both of the rising
and falling edges are designated (IEDGA = 1 a n d IEDGC = 0 , o r IEDGA = 0 a n d IEDGC =
1), using the ICRC as the buffe r regi ste r for the ICRA (BUFEA = 1).
Input capture
signal
FTIA
FRC
ICRA
ICRC
n n+1 N
Mn
mM
n
M
N
n
Fi g ur e 1 7 . 8 Input Capt ur e Si gna l Input t i ng Timi ng Chart Unde r t he B uf fer Mode
(under normal state)
Rev. 2.0, 11/ 00, page 380 of 1037
Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up
corresponding to the designated edge change of respective input capture signals.
For example , when using t he ICRC a s the buffer re gi ster for t he ICRA, when a n edge c hange
having been designated by the IEDGC bit is detected with the input capture signals C and if the
ICIEC bit is duly set, an interrupt request will be issued.
However, in this case, the FRC value will not be transferred to the ICRC.
17. 3 .6 Input Capture Fla g (ICFA thr o ugh ICFD) Se t t i ng Up Timi ng
The input capture signal works to set the ICFA through ICFD to "1" and, simultaneously, the
FRC value is tra nsferre d to t he corre sponding ICRA through ICRD. Figure 17. 9 shows the
timing chart for the above.
Input capture
signal
ICFA to ICFD
ICRA to ICRD
FRC
N
N
Fi g ur e 1 7 . 9 ICF A t hr o ug h ICF D Se t t i ng Up Timi ng
Rev. 2.0, 11/ 00, page 381 of 1037
17.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing
The OCFA and OCFB are being set to 1 by the comparing match signal being output when the
values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the
last state of the value match (the timing of the FRC's updating the matching count reading).
After the values of the OCRA, OCRB and FRC match, up until the count up clock signal is
generated, the comparing match signal will not be issued. Figure 17.10 shows the OCFA and
OCFB setting timing chart.
Comparing match
signal
OCFA, OCFB
OCRA, OCRB
FRC N
N
N+1
Figure 17. 10 O CF Setti ng Up Timing
17.3.8 Overflow Flag (CVF) Setting Up Timing
The OVF i s se t to when t h e FR C o v e r flows (H'FFFF → H'0000). Figure 17.11 shows the timing
chart for t hi s case.
Overflowing
signal
FRC H'FFFF H'0000
OVF
Figure 17. 11 O VF Setti ng Up Timing
Rev. 2.0, 11/ 00, page 382 of 1037
17.4 Operation Mod e of t h e Ti m er X1
Table 17.4 indicated below shows the operation mode of the Timer X1.
Table 17.4 Operati on Mode of the Time r X1
Operation
mode Reset Active Sleep Watch Subactive Standby Subsleep Module
stop
FRC Reset Functions Functions Reset Reset Reset Reset Reset
OCRA, OCRB Reset Functions Functions Reset Reset Reset Reset Reset
ICRA to ICRD Reset Functions Functions Reset Reset Reset Reset Reset
TIER Reset Functions Functions Reset Reset Reset Reset Reset
TCRX Reset Functions Functions Reset Reset Reset Reset Reset
TOCR Reset Functions Functions Reset Reset Reset Reset Reset
TCSRX Reset Functions Functions Reset Reset Reset Reset Reset
Rev. 2.0, 11/ 00, page 383 of 1037
17.5 Interrupt Causes
Total seven interrupt causes exist with the Timer X1, namely, ICIA through ICID, OCIA, OCIB
and FOVI . Ta ble 1 7 . 5 g i v e n belo w l ists the conten t s o f respective interrupt causes. Respective
interrupt requests can be permitted or prohibited by setting of respective interrupt enabling bits
of the TIER. Also, independent vector addresses are being allocated to respective interrupt
causes.
Tabl e 1 7 . 5 Interrupt Causes of t he T i m e r X1
Abbreviations of the Int er r upt Causes Pr i or i ty Degree Content s
ICIA Inter r upt request by t he ICFA
ICIB Inter r upt request by t he ICFB
ICIC Int er r upt r equest by the ICFC
ICID Int er r upt r equest by the ICFD
OCIA Int er r upt r equest by the OCFA
OCIB Int er r upt r equest by the OCFB
FOVI Int er r upt r equest by the OVF
High
Low
Rev. 2.0, 11/ 00, page 384 of 1037
17.6 Exemplary Uses of t h e Ti m er X1
Figure 17.12 indicated below shows an example of outputting at optional phase difference of the
pulses of the 50% duty. For this setting, follow the procedures listed below.
(1) set the CCLRA bit of the TCSRX to "1".
(2) Each time a comparing match occurs, the OLVIA bit and the OLVLB bit are reversed by use
of the software.
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
Clearing the
counter
FRC
Figure 17.12 An Exemplary Pulse Outputting
Rev. 2.0, 11/ 00, page 385 of 1037
17.7 Precauti on s when Usin g t he Ti m er X1
Pay great attention to the fact that the following competitions and operations occur during
operation of the Timer X1.
17.7.1 Competition between Writing and Clearing with the FRC
When a counter clearing signal is issued under the T2 state where the FRC is under the writing
cycle, writing into the FRC will not be effected and the priority will be given to clearing of the
FRC.
Figure 17.13 shows the timing chart in this case.
Address FRC address
Internal writing
signal
Counter clearing
signal
FRC N H'0000
T1 T2
Writing cycle with the FRC
Figure 17.13 Competition between Writing and Clearing with the FRC
Rev. 2.0, 11/ 00, page 386 of 1037
17.7.2 Competition between Writi ng and Counti ng Up with the F RC
When a counting up cause occurs under the T2 state where the FRC is under the writing cycle,
the counting up will not be effected and the priority will be given to count writing.
Figure 17.14 shows the timing chart in this case.
Address FRC address
Internal writing
signal
Inputting clock
to the FRC
Writing data
FRC N M
T1 T2
Writing cycle with the FRC
Figure 17.14 Competition between Writing and Counting Up with the FRC
Rev. 2.0, 11/ 00, page 387 of 1037
17.7.3 Competition between Writi ng and Comparing Match with the OCR
When a comparing match occurs under the T2 state where the OCRA and OCRB are under the
writing cycle, the priority will be given to writing of the OCR and the comparing match signal
will be prohibited.
Figure 17.15 shows the timing chart in this case.
Address OCR address
Internal writing
signal
Comparing match
signal
FRC
Writing data
Will be prohibited
OCR N M
N N+1
T1 T2
Writing cycle with the OCR
Figure 17. 15 Competiti on between Wri ting and Comparing Match with the OCR
Rev. 2.0, 11/ 00, page 388 of 1037
17. 7 .4 Changi ng O v e r the Int e r na l Cloc ks a nd Count e r O pe r a t i o ns
Depending on the timing of changing over the internal clocks, the FRC may count up. Table
17.6 indicated below shows the relations between the timing of changing over the internal clocks
(Re-writing of t he CKS1 and CKS0) and the FRC operat i ons.
When using an internal clock, the counting clock is being generated detecting the falling edge of
the internal clock dividing the system clock (φ). For this reason, like Item No. 3 of table 17.6,
count clock signals are issued deeming the timing before the changeover as the falling edge to
have the FRC to c ount up.
Also, when changi ng over be t ween a n i nte rna l c l ock a nd t he e xt erna l cl oc k, the FRC ma y count
up.
Table 17.6 Changing Over the Internal Clocks and the FRC Operation
No.
Re-writing timing
for t he CKS1 and
CKS0 FRC oper ati on
1 Low → Low level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Re-writing of the CKS1 and CKS0
N N+1
2 Low → High leve l
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Re-writing of the CKS1 and CKS0
N N+1 N+2
Rev. 2.0, 11/ 00, page 389 of 1037
No.
Re-writing timing
for t he CKS1 and
CKS0 FRC oper ati on
3 High → Low level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Re-writing of the CKS1 and CKS0
N
*
N+1 N+2
4 High → High level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Re-writing of the CKS1 and CKS0
N N+1 N+2
Note: *The count clock signals ar e iss ued deem ing t he changeov er t im ing as t he f alling edge
to have t he FRC to count up.
Rev. 2.0, 11/ 00, page 390 of 1037
Rev. 2.0, 11/ 00, page 391 of 1037
Section 18 Watchdog Timer (WDT)
18.1 Overview
This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system
operation. The WDT outputs an overflow signal if a system crash prevents the CPU from
writing to the timer counter, allowing it to overflow. At the same time, the WDT can also
generate an internal reset signal or internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In
interval timer mode, an interval timer interrupt is generated each time the counter overflows.
18.1.1 Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
— WOVI interrupt generation in interval timer mode
• Internal reset or internal interrupt generated when the timer counter overflows
— Choice of internal reset or NMI interrupt generation in watchdog timer mode
• Choice of 8 counter input clocks
— Maximum WDT interval: system clock period × 131072 × 256
Rev. 2.0, 11/ 00, page 392 of 1037
18.1.2 Block Diagram
Figure 18.1 shows block dia gram of W DT.
Overflow
Interrupt
control
•
Reset
control
WOVI
(Interrupt request signal)
Internal reset signal*
WTCNT WTCSR
/ 2
/ 64
/ 128
/ 512
/ 2048
/ 8192
/ 32768
/ 131072
Clock Clock
select
Internal clock
source
Bus
interface
Module bus
WTCSR
WTCNT
Note: * The internal reset signal can be generated by means of a register setting.
: Timer control/status register
: Timer counter
Internal bus
WDT
[Legend]
Internal NMI
interrupt request signal
Figure 18. 1 Bl oc k Diagram of WDT
Rev. 2.0, 11/ 00, page 393 of 1037
18.1.3 Register Configuration
The WDT has two registers, as summarized in table 18.2. These registers control clock
selection, WDT mode switching, the reset signal, etc.
Table 18.2 WDT Registers
Address*1
Name Abbre v . R/W Ini tia l Val ue Write*2Read
Watchdog t im er
control/status r egister WTCSR R/ (W)*3H'00 H'FFBC H'FFBC
Watchdog timer count er WTCNT R/W H'00 H'FFBC H'FFBD
Syst e m contr ol regis t e r SYSCR R/W H'0 9 H'FFE8 H'FFE8
Notes: 1. Lower 16 bits of the addr ess.
2. For details of write oper at ions, see sect ion 18. 2. 4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the f lag.
Rev. 2.0, 11/ 00, page 394 of 1037
18.2 Register Descript ion s
18.2.1 Watchdog Timer Counter (WTCNT)
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit :
Initial value :
R/W :
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the
internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows
(change s from H'FF to H'00), t h e OVF fl a g i n W T C SR i s set t o 1.
WTCNT is initialized to H'00 by a reset, or when the TME bit is cleared to 0.
Note: * WTCNT is write-protected by a password to prevent accidental overwriting. For
details see section 18.2.4, Notes on Register Access.
18.2. 2 Watchdog Timer Contro l / Status Regi ste r (WTCSR)
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
RSTS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source
to be input to WTCNT, and the timer mode.
WTCSR is initialized to H'00 by a reset.
Note: * WTCSR is write-protected by a password to prevent accidental overwriting. For
details see section 18.2.4, Notes on Register Access.
Rev. 2.0, 11/ 00, page 395 of 1037
Bit 7: Over fl ow Flag (O VF)
A status flag that indicates that WTCNT has overflowed from H'FF to H'00.
Bit 7
OVF Description
0 [Clearing conditions] (Init ial value)
(1) W r it e 0 in t he TM E bit
(2) Read WTCSR when OVF = 1, then wr ite 0 in O VF
1 [Set t ing condition]
When WTCNT overflows (changes f r om H'FF to H'00)
When internal r eset r equest gener ation is selected in watchdog timer m ode, O VF is
cleared autom at ically by the inter nal r eset
Bit 6: Timer Mode Select (WT/
,7
,7
)
Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval
timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If
used as a watchdog timer, the WDT generates a reset or NMI interrupt when TCNT overflows.
Bit 6
WT/
,7
,7
Description
0 Int er val t imer m ode: Sends the CPU an interval timer int er r upt r equest (WO VI ) when
WTCNT ov e rf lo ws (Init ia l v a lu e)
1 Watchdog timer m ode: Sends t he CPU a reset or NMI int er r upt r equest when
WTCNT overflows
Bit 5: Timer Enable (TM E)
Selects whether WTCNT runs or is halted.
Bit 5
TME Description
0 WTCNT is initialized t o H'00 and halted (Initial value)
1 WTCNT counts
Bit 4: Reset Select (RSTS)
Reserved. Thi s bit should not be set to 1.
Rev. 2.0, 11/ 00, page 396 of 1037
Bit 3: Reset or NMI (RST/
10,
10,
)
Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in
watchdog timer mode.
Bit 3
RST/
1,0,
1,0,
Description
0 An NMI inter r upt request is gener at ed (Initial value)
1 An internal reset r equest is generat ed
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0)
These bits select an internal clock source, obtained by dividing the system clock (φ) for input to
WTCNT.
WDT i nput c l o c k selection
Bit 2 Bi t 1 Bit 0 Descript ion
CSK2 CSK1 CSK0 Cl oc k Over flow Per iod* (w hen φ = 10 MHz)
0φ/2 (Initial
value) 51.2 µs0
1φ/64 1.6 ms
0φ/128 3.3 m s
0
1
1φ/512 13.1 m s
0φ/2048 52. 4 m s0
1φ/8192 209. 7 m s
0φ/32768 838. 9 m s
1
1
1φ/131072 3. 36 s
Note: *The overf low period is the t ime f r om when WTCNT starts count ing up f r om H'00 until
overflow occurs.
Rev. 2.0, 11/ 00, page 397 of 1037
18. 2 .3 Syste m Co ntrol Re g i st e r (SYSCR)
7
—
0
—
6
—
0
—
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
—
1
—
2
NMIEG1
0
R/W
1
NMIEG0
0
R/W
Bit :
Initial value :
R/W :
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3 : E x ter nal Reset (XRST )
Indicates the reset source. When the watchdog timer is used, a reset can be generated by
watchdog timer overflow in addition to external reset input. XRST is a read-only bit. It is set to
1 by an external reset, and cleared to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 Reset is generat ed by wat chdog t im er over f low
1 Reset is generat ed by ext er nal r eset input (Init ial value)
18.2.4 Notes on Register Access
The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more
difficult to write to. The procedures for writing to and reading these registers are given below.
(1) Writing to WTCNT and WTCSR
These registers must be written to by a word transfer instruction. They cannot be written to
with byte transfer instructions.
Figure 18.2 shows the format of data written to WTCNT and WTCSR. WTCNT and
WTCSR both have the same write address. For a write to WTCNT, the upper byte of the
written word must contain H'5A and the lower byte must contain the write data. For a write
to WTCSR, the upper byte of the written word must contain H'A5 and the lower byte must
contain the write data. This transfers the write data from the lower byte to WTCNT or
WTCSR.
Rev. 2.0, 11/ 00, page 398 of 1037
<WTCNT write>
<WTCSR write>
Address : H'FFBC
Address : H'FFBC
H'5A Write data
15 8 7 0
0
H'A5 Write data
15 8 7 0
0
Figure 18. 2 F or mat of Data Writte n to WTCNT and WTCSR
(2) Reading WTCNT and WTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC
for WTCSR, a nd H'FFBD for WTCNT.
Rev. 2.0, 11/ 00, page 399 of 1037
18.3 Operation
18.3.1 Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/
,7
and TME bits in WTCSR to 1. Software
must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00)
before overflow occurs. This ensures that WTCNT does not overflow while the system is
operating normally. If WTCNT overflows without being rewritten because of a system crash or
other error, the chip is reset, or an NMI interrupt is generated, for 518 system clock periods (518
φ). This is illustrated in figure 18. 3.
An internal reset request from the watchdog timer and reset input from the
5(6
pin are ha ndl ed
via the same vector. The reset source can be identified from the value of the XRST bit in
SYSCR.
If a reset c a used by an i nput signal from the
5(6
pin and a re set ca used by W DT overfl ow occ ur
simultaneously, the
5(6
pin reset has priority, and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin
are handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt
request and a n NMI pin int errupt re quest m ust t here fore be a voi ded.
WTCNT value
H'00 Time
H'FF
WT/IT=1
TME=1 H'00 written
to WTCNT WT/IT=1
TME=1 H'00 written
to WTCNT
518 system clock period
Internal reset
signal
WT/IT
TME
Overflow
Internal reset
generated
WOVF=1*
: Timer mode select bit
: Timer enable bit
Note: * Cleared to 0 by an internal reset when WOVF is set to 1. XRST is cleared to 0.
Figure 18. 3 O per ation in Watchdog Timer M ode
Rev. 2.0, 11/ 00, page 400 of 1037
18.3.2 Inter val Time r Oper ati on
To use the WDT as an interval timer, clear the WT/
,7
bit in WTCSR to 0 and set the TME bit to
1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that
the WDT is operating as an interval timer, as shown in figure 18.4. This function can be used to
generate interrupt requests at regular intervals.
WTCNT value
H'00 Time
H'FF
WT/IT=0
TME=1 WOVI
Overflow Overflow Overflow Overflow
WOVI : Interval timer interrupt request generation
WOVI WOVI WOVI
Figure 18.4 Operation in Interval Timer Mode
Rev. 2.0, 11/ 00, page 401 of 1037
18.3.3 Timing of Setting of Ove r flow Fl ag (O VF)
The OVF bit i n WT C SR i s set t o 1 i f W T CNT ove rfl ows duri ng i nt e rva l timer operation. At the
same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 18.5.
If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the
OVF bit i n WTC SR i s se t to 1 a n d at the same time an NMI interrupt is requested.
CK
WTCNT H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 18. 5 Ti mi ng of OVF Setting
Rev. 2.0, 11/ 00, page 402 of 1037
18.4 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF fla g i s se t to 1 i n W T C SR . OVF
must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is
selected in watchdog timer mode, an overflow generates an NMI interrupt request.
18.5 Usage Notes
18.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a WTCNT write cycle, the
write takes priority and the timer counter is not incremented. Figure 18.6 shows this operation.
Internal address
Internal
Internal write
signal
WTCNT input
clock
WTCNT NM
T
1
T
2
WTCNT write cycle
Counter write data
Figure 18.6 Contention between WTCNT Write and Increment
Rev. 2.0, 11/ 00, page 403 of 1037
18. 5 .2 Changing Va l ue o f CK S2 to CK S0
If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur
in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)
before cha ngi ng the va lue of bi ts CKS2 to CKS0.
18.5.3 Switc hing between Watchdog Timer Mode and Interval Time r Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
Rev. 2.0, 11/ 00, page 404 of 1037
Rev. 2.0, 11/ 00, page 405 of 1037
Section 19 8-Bit PWM
19.1 Overview
The 8-bit PWM incorporates 4 channels of the duty control method. Its outputs can be used to
control a reel motor or loading motor.
19.1.1 Features
• Conversion period: 256-state
• Duty control me t hod
19.1.2 Block Diagram
Figure 19.1 shows a block di agra m of the 8-bi t PWM (1 cha nne l).
PWMn
(n=3 to 0)
2
0
2
7
OVF
Match signal
[Legend]
PWRn
PW8CR: 8-bit PWM data register n
: 8-bit PWM control register
PWMn
OVF : 8-bit PWM square-wave output pin n
: Overflow signal from FRC lower 8-bit
PWRn
Free-running counter (FRC)
Comparator
PW8CR
Polarity
specification
Internal data bus
R
S
Q
Figure 19. 1 Bl oc k Diagram of 8-Bit P WM
Rev. 2.0, 11/ 00, page 406 of 1037
19.1.3 Pin Configuration
Table 19.1 shows the 8-bit PWM pin configuration.
Table 19.1 Pin Configuration
Name Abbrev. I/O Function
8-bit PWM squar e- wave output pin
0PWM0 Out put 8-bit PWM squar e- wave output 0
8-bit PWM squar e- wave output pin
1PWM1 Out put 8-bit PWM squar e- wave output 1
8-bit PWM squar e- wave output pin
2PWM2 Out put 8-bit PWM squar e- wave output 2
8-bit PWM squar e- wave output pin
3PWM3 Out put 8-bit PWM squar e- wave output 3
19.1.4 Register Configuration
Table 19.2 shows the 8-bit PWM register configuration.
Table 19.2 8-Bit PWM Register s
Name Abbrev. R/W Si z e Ini t ial Value Address *
8-bit PWM dat a r egist er 0 PWR0 W Byte H'00 H'D126
8-bit PWM dat a r egist er 1 PWR1 W Byte H'00 H'D127
8-bit PWM dat a r egist er 2 PWR2 W Byte H'00 H'D128
8-bit PWM dat a r egist er 3 PWR3 W Byte H'00 H'D129
8-bit PWM cont r ol regist er PW8CR R/W Byt e H'F0 H'D12A
Port m ode r egist er 3 PM R3 R/W Byte H'00 H'FFD0
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 407 of 1037
19.2 Register Descript ion s
19.2.1 Bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)
(1) PWR0
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW04 PW03 PW02 PW01 PW00
0
W
PW07
WWW
PW06 PW05
Bit :
Initial value :
R/W :
(2) PWR1
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW14 PW13 PW12 PW11 PW10
0
W
PW17
WWW
PW16 PW15
Bit :
Initial value :
R/W :
(3) PWR2
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW24 PW23 PW22 PW21 PW20
0
W
PW27
WWW
PW26 PW25
Bit :
Initial value :
R/W :
(4) PWR3
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW34 PW33 PW32 PW31 PW30
0
W
PW37
WWW
PW36 PW35
Bit :
Initial value :
R/W :
8-bit PWM data registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) control the duty cycle at
8-bit PWM pins. The data written in PWR0, PWR1, PWR2 and PWR3 correspond to the high-
level width of one PWM output waveform cycle (256 states).
When data is set in PWR0, PWR1, PWR2 and PWR3, the contents of the data are latched in the
PWM waveform generators, updating the PWM waveform generation data.
PWR0, PWR1, PWR2 and PWR3 are write-only registers. When read, all bits are always read
as 1.
PWR0, PWR1, PWR2 and PWR3 are initialized to H'00 by a reset.
Rev. 2.0, 11/ 00, page 408 of 1037
19.2.2 8-bit PWM Control Register (PW8CR)
0
0
1
0
R/W
2
0
R/W
3
0
4567 ————
————
PWC3 PWC2 PWC1 PWC0
R/WR/W
1111
Bit :
Initial value :
R/W :
The 8-bit PWM control register (PW8CR) is an 8-bit readable/writable register that controls
PWM functions. PW8CR is initialized to H'00 by a reset.
Bits 7 to 4: Reserved
They are always read as 1. Writes are disabled.
Bits 3 to 0: Output Polarity Select (PWC3 to PWC0)
These bits select the output polarity of PWMn pin between positive or negative (reverse).
Bit n
PWCn Description
0 PWMn pin output has positive polarity (Initial value)
1 PWMn pin output has negative polarity
(n = 3 to 0)
Rev. 2.0, 11/ 00, page 409 of 1037
19.2.3 Port M ode Regi ster 3 (P M R3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR34 PMR33 PMR32 PMR31 PMR30
0
R/W
PMR37
R/W R/WR/W
PMR36 PMR35
Bit :
Initial value :
R/W :
The port mode register 3 (PMR3) controls function switching of each pin in the port 3.
Switching is specified for each bit.
The PMR3 is a 8-bit readable/writable register and is initialized to H'00 by a reset.
For bits other than 5 to 2, see section 11.5, Port 3.
Bits 5 to 2: P35/PWM 3 to P 32/P WM 0 Pi n Switching (PMR35 to PM R32)
These bits set whether the P3n/PWMn pin is used as I/O pin or it is used as 8-bit PWM output
PWMm p i n .
Bit n
PMR3n Description
0 P3n/PMWm pin functions as P3n I/O pin ( Initial value)
1 P3n/PMWm pin functions as PWM m out put pin
(n = 5 to 2, m = 3 to 0)
Rev. 2.0, 11/ 00, page 410 of 1037
19. 2 .4 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode.
When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle
and transits to the module stop mode. For details, see section 4.5, Module Stop Mode.
The MSTPCR is initialized to H'FFFF by a rese t .
Bit 4: M odule Stop (MSTP4)
This bit sets the module stop mode of the 8-bit PWM.
MSTPCRL
Bit 4
MSTP4 Description
0 8-bit PWM m odule st op m ode is r eleased
1 8-bit PWM m odule stop m ode is set (Initial value)
Rev. 2.0, 11/ 00, page 411 of 1037
19.3 8-Bit PWM O perat i on
The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width
determined by the data registers (PWR).
The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter.
Figure 19.2 shows the output waveform e xam pl e of 8-bi t PWM. T he pul se widt h (Twidt h) c an
be obtained by the following expression:
Twidth = (1/φ) × (PWR setting value)
T width
Pulse width
T width
Pulse cycle
(256 states)
T width
Pulse width
T width
Pulse cycle
(256 states)
H'00
PWRn setting
value
H'FFFRC lower
8-bit value
PWRn pin
output (Positive
polarity)
(n=3 to 0)
(Negative
polarity)
Figure 19. 2 8-bit P WM Output Waveform (Example)
Rev. 2.0, 11/ 00, page 412 of 1037
Rev. 2.0, 11/ 00, page 413 of 1037
Section 20 12-Bit PWM
20.1 Overview
The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the
drum and capstan motor controller.
20.1.1 Features
Two on-chip 12-bit PWM signal gene ra tors are provi ded t o c ontrol m otors. The se PWMs use
the pulse-pitch control method (periodically overriding part of the output). This reduces low-
frequency c om ponent s in t he pul se out put, e na bli ng a quic k re sponse without i nc rea sing t he
clock frequency. The pitch of the PWM signal is modified in response to error data
(representing lead or lag in relation to a preset speed and phase).
Rev. 2.0, 11/ 00, page 414 of 1037
20.1.2 Block Diagram
Figure 20.1 shows a block di agra m of the 12-bi t PWM (1 cha nne l). T he PWM signal i s
generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses
derived from the contents of a data register. Low-frequency components are reduced because
the two quantizing pulses have different frequencies. The error data is represented by an
unsigned 12-bit bi na ry numbe r.
Internal data bus
[Legend]
CAPPWM
or
DRMPWM
CAPPWM
/2
/4
/8
/16
/32
/64
/128
DRMPWM : Capstan mix pin
: Drum mix pin
PWM control register
Digital filter
circuit
Error data
PTON
PWM data register
Output control circuit
Pulse generator
Counter
· DFUCR
CP/DP
Figure 20. 1 Bl oc k Diagram of 12-Bit P WM (1 channel)
Rev. 2.0, 11/ 00, page 415 of 1037
20.1.3 Pin Configuration
Table 20.1 shows the 12-bit PWM pin configuration.
Table 20.1 Pin Configuration
Name Abbrev. I/O Function
Capstan m ix CAPPW M
Drum m ix DRMPW M
Out put 12-bit PWM squar e- wave out put
20.1.4 Register Configuration
Table 20.2 shows the 12-bit PWM register configuration.
Table 20.2 12-Bit PWM Register s
Name Abbrev. R/W Si z e Ini t ial Value Address *
CPWCR W Byte H'42 H'D07B
12-bit PWM cont r ol regist er
DPWCR W Byte H'42 H'D07A
CPWDR R/W Word H'F000 H'D07C12-bit PWM dat a r egist er
DPWDR R/W Word H'F000 H'D078
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 416 of 1037
20.2 Register Descript ion s
20.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR)
(1) CPWCR
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7CH/L CSF/DF CCK2 CCK1 CCK0
0
W
CPOL
WWW
CDC CHiZ
Bit :
Initial value :
R/W :
(2) DPWCR
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7DH/L DSF/DF DCK2 DCK1 DCK0
0
W
DPOL
WWW
DDC DHiZ
Bit :
Initial value :
R/W :
CPWCR is the PWM output c ont rol re gi ster for t he ca psta n mot or. DPWCR is the PWM output
control register for the drum motor. Both are 8-bit writable registers.
CPWCR and DPWCR are initialized to H'42 by a reset, or in sleep mode, standby mode, watch
mode, subactive mode, subsleep mode, or module stop mode of the servo circuit.
Bit 7: Polarity Invert (POL)
This bit can invert the polarity of the modulated PWM signal for noise suppression and other
purposes. This bit is invalid when fixed output is selected (when bit DC is set to 1).
Bit 7
POL Description
0 Out put with positive polarity (I nitial value)
1 Out put with inverted polarit y
Bit 6: Output Select (DC)
Selects either PWM modulated output, or fixed output controlled by the pin output bits (Bits 5
and 4).
Rev. 2.0, 11/ 00, page 417 of 1037
Bits 5 and 4: PWM Pin Output (HiZ, H/L)
Whe n bi t DC i s set t o 1, t h e 12-bi t PW M out put pi ns (CAPPW M, DRMPW M) out put a va l ue
determined by the HiZ and H/L bits. The output is not affected by bit POL.
In power-down modes, the 12-bit PWM circuit and pin statuses are retained. Before making a
transiti on t o a power-down mode , fi rst set bi t s 6 (DC), 5 (HiZ), a nd 4 (H/L) of t he 12-bit PWM
control registers (CPWCR and DPWCR) to select a fixed output level. Choose one of the
following settings:
Bit 6 Bit 5 Bit 4
DC HiZ H/L O utput s tat e
0 Low out put ( I nitial value)0
1 High output
1
1*High-impedance
0**Modulation signal out put
Note: *Don't care
Bit 3: Output Data Select (SF/DF)
Selects whether the data to be converted to PWM output is taken from the data register or from
the digital filter circuit.
Bit
SF/DF Description
0 Modulation by er r or dat a f r om the digital filter circ uit (I nit ial value)
1 Modulation by er r or dat a writ t en in t he dat a r egist er
Note: When PWM s output dat a f r om the digital filter circ uit, the data consist ing of t he speed and
phase filt ering resu lt s ar e m odulated by PWM s and output from t he CAPPW M and
DRMPWM pins. However, it is possible to output only dr um phase f ilter r esult s f r om
CAPPWM pin and only caps t an phas e f ilter result from DRMPWM pin, by DFUCR se t tings
of t he digital filter circuit . See t he sect ion 28. 11 Digital Filters.
Rev. 2.0, 11/ 00, page 418 of 1037
Bit 2 to 0: Carrier Frequency Select (CK2 to CK0)
Selects the carrier frequency of the PWM modulated signal. Do not set them to 111.
Bit 2 Bit 1 Bit 0
CK2 CK1 CK0 Description
0φ20
1φ4
0φ8 ( Initial va lu e)
0
1
1φ16
0φ320
1φ64
0φ128
1
1
1 (Do not set)
Rev. 2.0, 11/ 00, page 419 of 1037
20.2.2 12-Bit PWM Data Register s (CPWDR, DPWDR)
(1) CPWDR 1
0
R/W
CPWDR1
0
0
R/W
CPWDR0
3
0
R/W
CPWDR3
2
0
R/W
CPWDR2
5
0
R/W
CPWDR5
4
0
R/W
CPWDR4
7
0
R/W
CPWDR7
6
0
R/W
CPWDR6
9
0
R/W
CPWDR9
8
0
R/W
CPWDR8
11
0
R/W
CPWDR11
10
0
R/W
CPWDR10
12
1
13
1
14
1
15
————
————
1
Bit :
Initial value :
R/W :
(2) DPWDR
1
0
R/W
DPWDR1
0
0
R/W
DPWDR0
3
0
R/W
DPWDR3
2
0
R/W
DPWDR2
5
0
R/W
DPWDR5
4
0
R/W
DPWDR4
7
0
R/W
DPWDR7
6
0
R/W
DPWDR6
9
0
R/W
DPWDR9
8
0
R/W
DPWDR8
11
0
R/W
DPWDR11
10
0
R/W
DPWDR10
12
1
13
1
14
1
15
1
————
————
Bit :
Initial value :
R/W :
The 12-bit PWM data registers (CPWDR and DPWDR) are 12-bit readable/writable registers
in which the data to be converted to PWM output is written.
The data in these registers is converted to PWM output only when bit SF/DF of the
corresponding control register is set to 1. The error data from the digital filter circuit is
written in the data register, and then modulated by PWM. At this time, the error data from
the digital filter circuit can be monitored by reading the data register.
These registers can be accessed by word only, and cannot be accessed by byte. Byte access
gives unassured results.
CPWDR and DPWDR are initialized to H' F000 by a reset, or in sleep mode, standby mode,
watch mode, subactive mode, subsleep mode, or module stop mode of the servo circuit.
Rev. 2.0, 11/ 00, page 420 of 1037
20. 2 .3 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode.
When the MSTP1 bit is set to 1, the 12-bit PWM and Servo circuit, stops their operation upon
completion of the bus cycle and transits to the module stop mode. For details, see section 4.5,
Module Stop Mode.
The MSTPCR is initialized to H'FFFF by a rese t .
Bit 1: M odule Stop (MSTP1)
This bit set s the modul e stop mode of t he 12-bi t PWM. T his bit a lso cont rol s the m odul e stop
mode of the servo c irc ui t.
MSTPCRL
Bit 1
MSTP1 Description
0 Module stop m ode of the 12- bit PWM and servo circuit is r eleased
1 Module stop m ode of the 12- bit PWM and servo circuit is set (Initial value)
Rev. 2.0, 11/ 00, page 421 of 1037
20.3 Operation
20.3.1 Output Wavefor m
The PWM signal generator combines the error data with the output from an internal pulse
generator to produce a pulse-width modulated signal.
When Vcc/2 is set as the reference value, the following conditions apply:
• When the motor is running at the correct sped and phase, the PWM signal is output with a
50% duty cycle.
• When the motor is running behind the correct speed or phase, it is corrected by periodically
holding part of the PWM signal low. The part held low depends on the size of the error.
• When the motor is running ahead of the correct speed or phase, it is corrected by periodically
holding part of the PWM signal high. The part held high depends on the size of the error.
When the motor is running at the correct speed and phase, the error data is a 12-bit value
representing 1/2 (1000 0000 0000), and the PWM output has the same frequency as the selected
division cl oc k.
After the error data has been converted into a PWM signal, the PWM signal can be smoothed
into a DC voltage by an external low-pass filter (LPF). The smoothes error data can be used to
control t he mot or.
Figure 20.2 shows sample wave form out put s.
The 12-bit PWM pin out puts a l ow-le vel signa l upon re set , in power-down mode or a t m odul e-
stop.
Rev. 2.0, 11/ 00, page 422 of 1037
1
Counter
Pulse Generator
PWM data register
C10
C11
C12
C13
Corresponds to Pwr3=1
Corresponds to Pwr2=1
Corresponds to Pwr1=1
Corresponds to Pwr0=1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Pwr3 2 1 0 "L"
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12
Figure 20. 2 Sample Wave for m Output by 12-Bit PWM (4 Bits)
Rev. 2.0, 11/ 00, page 423 of 1037
Section 21 14-Bit PWM
21.1 Overview
The 14-bit PWM is a pulse division type PWM which can be used for V-synthesizer, etc.
21.1.1 Features
Features of the 14-bi t PWM are gi ven be l ow:
• Choice of two conversion periods
A conversion period of 32768/ φ with a minimum modulation width of 2/φ, or a conve rsion
period of 16384/φ with a minimum modulation width of 1/φ, can be selected.
• Pulse division met hod for l ess ripple
Rev. 2.0, 11/ 00, page 424 of 1037
21.1.2 Block Diagram
Figure 21.1 shows a block di agra m of the 14-bi t PWM.
[Legend]
PWCR
/4
/2
PWDRL
: PWM control register
: PWM data register L
PWDRU
PWM14
: PWM data register U
: PWM14 output pin
Internal data bus
PWCR
PWDRL
PWDRU
PWM waveform
generator PWM14
Figure 21. 1 Bl oc k Diagram of 14-Bit P WM
21.1.3 Pin Configuration
Table 21.1 shows the 14-bit PWM pin configuration.
Table 21.1 Pin Configuration
Name Abbrev. I/O Function
PWM 14-bit squar e- wave output pin PWM14*Out put 14-bit PWM square-wave output
Note: *This pin also functions as P40 general I/ O pin. When using t his pin, set t he pin
funct ion by the por t mode register 4 ( PM R4). For details, see sect ion 11. 6, Port 4.
Rev. 2.0, 11/ 00, page 425 of 1037
21.1.4 Register Configuration
Table 21.2 shows the 14-bit PWM register configuration.
Table 21.2 14-Bit PWM Register s
Name Abbrev. R/W Si z e Ini t ial Value Address *
PWM contr ol r egister PWCR R/W Byte H'FE H'D122
PWM data r egist er U PWDRU W Byte H'00 H'D121
PWM data r egist er L PWDRL W Byte H'00 H'D120
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 426 of 1037
21.2 Register Descript ion s
21.2.1 PWM Control Register (PWCR)
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7———————
——————— R/W
PWCR0
1
Bit :
Initial value :
R/W :
The PWM control register (PWCR) is an 8-bit read/write register that controls the 14-bit PWM
functions. PWCR is initialized to H'FE by a reset.
Bits 7 to 1: Reserved
They are always read as 1. Writes are disabled.
Bit 0: Clock Select (PWCR0)
Selects the clock supplied to the 14-bit PWM.
Bit 0
PWCR0 Description
0 The input clock is φ/2 (tφ = 2/ φ) (Initial v a lue )
The conversion period is 16384/φ, with a m inimum m odulat ion width of 1/ φ
1 The input clock is φ/4 (tφ = 4/ φ)
The conversion period is 32768/φ, with a m inimum m odulat ion width of 2/ φ
Note: t/φ: Period of PWM clock input
Rev. 2.0, 11/ 00, page 427 of 1037
21.2. 2 PWM Data Re gi ster s U and L (P WDRU, P WDRL)
(1) PWDRU
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7——
—— W
PWDRU0
W
PWDRU1
W
PWDRU2
W
PWDRU3
W
PWDRU4
W
PWDRU5
1
Bit :
Initial value :
R/W :
(2) PWDRL
0
0
1
0
2
0
3
0
4
0
5
0
67
W
PWDRL0
W
PWDRL1
W
PWDRL2
W
PWDRL3
W
PWDRL4
W
PWDRL5
0
W
PWDRL6
W
PWDRL7
0
Bit :
Initial value :
R/W :
PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN
waveform cycle.
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to
PWDRU and the lower 8 bits to PWDRL. The value written in PWDRU and PWDRL gives the
total high-level width of one PWM waveform cycle. Both PWDRU and PWDRL are accessible
by byte access only. Word access gives unassured results.
When 14-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM
waveform generator and the PWM waveform generation data is updated. When writing the 14-
bit data, follow these steps:
(1) Write the lower 8 bits to PWDRL.
(2) Write the upper 6 bits to PWDRU.
Write the data first to PWDRL and then to PWDRU.
PWDRU and PWDRL are write-only registers. When read, all bits always read 1.
PWDRU and PWDRL are initialized to H'C000 by a reset.
Rev. 2.0, 11/ 00, page 428 of 1037
21. 2 .3 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that
control t he modul e stop mode func ti ons.
When the MSTP5 bit is set to 1, the 14-bit PWM operation stops at the end of the bus cycle and
a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode.
MSTPCR is initialized to H'FFFF by a reset.
Bit 5: Module Stop (MSTP5)
Specifies the module stop mode of the 14-bit PWM.
MSTPCRL
Bit 5
MSTP5 Description
0 14-bit PWM m odule st op m ode is r eleased
1 14-bit PWM m odule st op m ode is set (Init ial value)
Rev. 2.0, 11/ 00, page 429 of 1037
21.3 14-Bit PWM Operation
When using the 14-bi t PWM, set the re gi sters in t hi s sequenc e:
(1) Set bit PMR40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for
PWM output.
(2) Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32768/φ (PWCR0 = 1) or 16384/φ (PW CR0 = 0).
(3) Set the output waveform data in PWM data registers U and L (PWDRU, PWDRL). Be sure
to write byte data first to PWDRL and then to PWDRU. When the data is written in
PWDRU, the contents of these registers are latched in the PWM waveform generator, and the
PWM waveform generation data is updated in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 21.2. The total high-level width
during this peri od (T H) corresponds to the data in PWDRU and PWDRL. This relation can be
expressed as follows:
TH = (data value in PWDRU and PWDRL + 64) × tφ/2
where tφ is the period of PWM clock input: 2/φ (bi t PWCR0 = 0) or 4/ φ (bi t PWCR0 = 1).
If the data value in PWDRU and PWDRL is from H'3FC0 to H'3FFF, th e PWM output st a y s
high.
When the data value is H' 0000, TH is calculated as follows:
TH = 64 × tφ/2 = 32 ⋅ tφ
t H64t H63t H3t H2t H1
T H = t H1 + t H2 + t H3 + ... + t H64
t f1 = t f2 = t f3 = ... = t f64
t f1 t f2 t f63 t f64
1 conversion period
Figure 21. 2 Wave for m Output by 14-Bit PWM
Rev. 2.0, 11/ 00, page 430 of 1037
Rev. 2.0, 11/ 00, page 431 of 1037
Section 22 Prescalar Unit
22.1 Overview
The prescalar unit (PSU) has a 18-bit fre e runni ng c ount e r (FRC) t ha t uses φ a s a cl oc k source
and a 5-bit counter that uses φW as a clock source.
22.1.1 Features
• Prescalar S (PSS):
Generates frequency division clocks that are input to peripheral functions.
• Prescalar W (PSW):
When a timer A is used as a clock time base, the PSW frequency-divides subclocks and
generates input clocks.
• Stable oscillation wait time count:
During the return from the low power consumption mode excluding the sleep mode, the FRC
counts the stable oscillation wait time.
• 8-bit PWM
The lower 8 bits of the FRC is used as 8-bit PWM cycle and duty cycle generation counters.
(Conversion cycle: 256 states)
• 8-bit input c a pture by
,&
pins
Catches the 8 bits of 215 to 28 of the FRC acc ordi ng to t he edge of t he
,&
pin for remot e
control receiving.
• Frequency division c l ock out put :
Can output the frequency division clock for the system clock or the frequency division clock
for the subcloc k from the fre quenc y di vision c l ock out put pin (T MOW).
Rev. 2.0, 11/ 00, page 432 of 1037
22.1.2 Block Diagram
Figure 22.1 shows a block diagram of the prescalar unit.
PWM3
ICR1
PCSR
18-bit free running counter (FRC)
w/128
Prescalar W
/131072 to /2
Prescalar S
Internal data bus
MSB LSB
w/4
w/8
w/16
w/32
/32 /16 /8 /4
Interrupt
request
5-bit counter
IC pin
Stable oscillation
wait time count output
2
12
2
15
2
8
2
17
2
7
2
8
TMOW
pin
MSB LSB
8 bits
6 bits 8 bits
PWM2
PWM1
PWM0
[Legend]
ICR1
PCSR : Input capture register 1
: Prescalar unit control/status register
IC
TMOW : Input capture input pin
: Frequency division clock output pin
Figure 22.1 Block Diagram of Prescalar Unit
Rev. 2.0, 11/ 00, page 433 of 1037
22.1.3 Pin Configuration
Table 22.1 shows the pin configuration of the prescalar unit.
Table 22.1 Pin Configuration
Name Abbrev. I/O Function
Input capt ur e input
,&
Input Prescalar unit input capt ur e input pin
Frequency division clock
output TMOW Output Prescalar unit fr equency division clock
output pin
22.1.4 Register Configuration
Table 22.2 shows the register configuration of the prescalar unit.
Table 22.2 Register Configuration
Name Abbrev. R/W Si z e Ini t ial Value Address *
Input capt ur e r egist er 1 ICR1 R Byte H'00 H'D12C
Prescalar unit
control/status r egister PCSR R/W Byte H'08 H'D12D
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 434 of 1037
22.2 Registers
22. 2 .1 Input Capture Regi st e r 1 ( ICR1)
0
0
1
0
R
2
0
R
3
0
4
0
R
0
R
56
0
7ICR14 ICR13 ICR12 ICR11 ICR10
0
R
ICR17
RRR
ICR16 ICR15
Bit :
Initial value :
R/W :
Input capture register 1 (ICR1) captures 8-bit data of 215 to 28 of the FRC ac cordi ng t o the e dge
of the
,&
pin.
ICR1 is an 8-bit read-only register. The write operation becomes invalid. The ICR1 values are
undefined until the first capture is generated after the mode has been set to the standby mode,
watch mode, subactive mode, and subsleeve mode. When reset, ICR1 is initialized to H'00.
22.2.2 Prescalar Unit Control/Status Register (PCSR)
0
0
1
0
R/W
2
0
R/W
3
—
—
1
4
0
R/W
5
0
6
0
7
R/WR/W
ICEG
R/W
ICIE
0
R/(W)*
ICIF NCon/off DCS2 DCS1 DCS0
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The prescalar unit control/status register (PCSR) controls the input capture function and selects
the freque nc y divi sion c loc k t hat i s output from t he T MOW pin.
PCSR is an 8-bit read/write enable register. When reset, PCSR is initialized to H'08.
Bit 7 : Input Ca pture Inte rr upt Fla g (ICIF)
Input capture interrupt request flag. This indicates that the input capture was performed
accordi ng t o the e dge of t he
,&
pin.
Bit 7
ICIF Description
0 [Clear condition] (Init ial value)
When 0 is written after 1 has been r ead
1 [Set condition]
When the input capture was perf or m ed according to the edge of the
,&
pin
Rev. 2.0, 11/ 00, page 435 of 1037
Bit 6 : Input Capture Int e rrupt E nable ( ICIE )
When ICIF was set to 1 by the input capture according to the edge of the
,&
pin, ICIE ena bl es
and disable s the gene ra ti on of a n input c apt ure int e rrupt.
Bit 6
ICIE Description
0 Disables the generation of an input capture inter r upt ( I nitial value)
1 Enables the generat ion of an input capt ur e int er r upt
Bit 5:
,&
,&
Pin Edge Select (ICEG)
ICEG selects the input edge sense of the
,&
pin.
Bit 5
ICEG Description
0 Detects t he f alling edge of t he
,&
pin input (Init ial value)
1 Detects t he r ising edge of t he
,&
pin input
Bit 4: Noise Cancel ON/OFF (NCon/off)
NCon/off selects enable/disable of the noise cancel function of the
,&
pin. For the noise c a nce l
function, see section 22.3, Noise Cancel Circuit.
Bit 4
NCon/off Description
0 Disables the noise cancel function of t he
,&
pin (In itial v a lue )
1 Enables the noise cancel function of the
,&
pin
Bit 3: Reseved Bit
When the bit is read, 1 is always read. The write operation is invalid.
Rev. 2.0, 11/ 00, page 436 of 1037
Bits 2 to 0: Frequency Division Clock Output Select (DCS2 to DCS0 )
DCS2 to DCS0 select eight types of frequency division clocks that are output from the TMOW
pin.
Bit 2 Bit 1 Bit 0
DCS2 DCS1 DCS0 Description
0 Out p uts PSS, φ/ 3 2 (In itial v alu e )0
1 Out p uts PSS, φ/16
0 Out p uts PSS, φ/8
0
1
1 Out p uts PSS, φ/4
0 Output s PSW, φW/320
1 Output s PSW, φW/16
0 Output s PSW, φW/8
1
1
1 Output s PSW, φW/4
Rev. 2.0, 11/ 00, page 437 of 1037
22.2.3 Port M ode Regi ster 1 (P M R1)
7
PMR17
0
R/W
6
PMR16
0
R/W
5
PMR15
0
R/W
4
PMR14
0
R/W
3
PMR13
0
R/W
0
PMR10
0
R/W
2
PMR12
0
R/W
1
PMR11
0
R/W
Bit :
Initial value :
R/W :
The port mode register 1 (PMR1) controls switching of each pin function of port 1. The
switching is specified in a unit of bit.
PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00.
Bit 7: P17/TM O W Pi n Switching (PMR17)
PMR17 sets whether the P17/TMOW pin i s used as a P17 I/O pin or a TMOW pin for di vi sion
clock out put .
Bit 7
PMR17 Description
0 The P17/TMOW pin funct ions as a P17 I/ O pin (Initial value)
1 The P17/TMOW pin funct ions as a TMOW pin for division clock output
Bit 6: P16/
,&
,&
Pi n Swi t c hing ( P M R1 6 )
PMR16 sets whether the P16/
,&
pin is used as a P16 I/O pin or an
,&
pin for the i nput ca pt ure
input of the prescalar unit.
Bit 6
PMR16 Description
0 The P16/
,&
pin functions as a P16 I/ O pin (I nit ial value)
1 The P16/
,&
pin functions as an
,&
input funct ion
22.3 Noise Cancel Circui t
The
,&
pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such
as remote control receiving. The noise cancel circuit samples the input values of the
,&
pin
twice at an interval of 256 states. If the input values are different, they are assumed to be noise.
The
,&
pin can specify enable/disable of the noise cancel function according to the bit 4
(NCon/off) of the prescalar unit control/status register (PCSR).
Rev. 2.0, 11/ 00, page 438 of 1037
22.4 Operation
22.4.1 Prescalar S (PSS)
The PSS i s a 17-bi t c ount e r t ha t use s t he sys tem clock (φ=fosc) as an input clock and generates
the freque nc y divi sion c loc ks (φ/131072 t o φ/ 2) of the pe riphe ra l func t ion. T he low-order 17 bi t s
of the 18-bi t free runni ng c ounte r (FRC) c orre spond to t he PSS. T he FRC is i ncremented by one
cl o c k . The PSS o u t p ut is sh a r e d b y the timer and serial communication interface (SCI), and the
frequency division ratio can independently be set by each built-in peripheral function.
When reset, the FRC is initialized to H'00000, and starts increment after reset has been released.
Because the system clock oscillator is stopped in standby mode, watch mode, subactive mode,
and subsleep mode, the PSS operation is also stopped. In this case, the FRC is also initialized to
H'00000.
The FRC cannot be read and written from the CPU.
Rev. 2.0, 11/ 00, page 439 of 1037
22.4.2 Prescalar W (PSW)
PSW is a counter that uses the subclock as an input clock. The PSW also generates the input
clock of the timer A. In this case, the timer A functions as a clock time base.
When reset, the PSW is initialized to H'00, and starts increment after reset has been released.
Even if the mode has been shifted to the standby mode *, watch mode *, subactive mode *, and
subsleep mode *, the PSW continues the operation as long as the clocks are supplied by the X1
and X2 pins.
The PSW can also be initialized to H'00 by setting the TMA3 and TMA2 bits of the timer mode
register A (TMA) to 11.
Note: * When the timer A is in module stop mode, the operation is stopped.
Figure 22.2 shows the supply of the clocks to the peripheral function by the PSS an d PSW .
/131072 to /2
Timer
SCI
OSC1 fosc
OSC2
w/128
w/4
wTimer A
Prescalar S
X1 (fx)
X2 CPU
ROM
RAM
TMOW pin
Peripheral register
I/O port
Medium
speed clock
frequency divider
Prescalar W
System clock
selection
Subclock
frequency
dividers
(1/2, 1/4, and 1/8)
Subclock
oscillator
System
clock
oscillator
System
clock
duty
correction
circuit
Fi g ur e 2 2 . 2 Cl o c k Supply
22.4.3 Stable Oscillation Wait Time Count
For the count of the stable oscillation stable wait time during the return from the low power
consumption mode excluding the sleep mode, see section 4, Power-Down State.
Rev. 2.0, 11/ 00, page 440 of 1037
22.4.4 8-Bit PWM
This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It
counts the cycle and the duty cycle at 27 to 20 of the FRC. It can be used for controlling reel
motors and loading motors. For details, see section 19, 8-Bit PWM.
22.4. 5 8-Bit Input Capture Usi ng
,&
,&
Pin
This function catches the 8-bit data of 215 to 28 of t he FRC acc ordi ng to t he edge of t he
,&
pin. It
can be used for remote control receiving.
For the edge of t he
,&
pin, the rising and falling edges can be selected.
The
,&
pin has a built-in noise cancel circuit. See section 22.3, Noise Cancel Circuit.
An interrupt request is generated due to the input capture using the
,&
pin.
Note: Rewriting the ICEG bit, NCon/off bit, or PMR16 bit is incorrectly recognized as edge
detection according to the combinations between the state and detection edge of the
,&
pin and the ICIF bit ma y be set a ft er up t o 384φ sec onds.
22. 4 .6 Fre que nc y Di v i sion Cl o c k O ut put
The freque nc y divi sion c loc k c an be out put from t he T MOW pin. For the freque nc y divi sion
clock, eight types of clocks can be selected according to the DCS2 to DCS0 bits in PCSR.
The clock in which the system clock was frequency-divided is output in active mode and sleep
mode and the clock in which the subclock was frequency-divided is output in active mode*,
sleep mode*, and subactive mode.
Note: * When the timer A is in module stop mode, no clock is output.
Rev. 2.0, 11/ 00, page 441 of 1037
Section 23 Serial Communication Interface 1 (SCI1)
23.1 Overview
The serial communication interface 1 (SCI1) can handle both asynchronous and clocked
synchronous serial communication. A function is also provided for serial communication
between processors (multiprocessor communication function).
23.1.1 Features
SCI1 features are listed below.
(1) Choice of asynchronous or clock synchronous serial communication mode
(a) Asynchronous mode
• Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character
Serial data communication can be carried out with standard asynchronous
communication chips such as a Universal Asynchronous Receiver/Transmitter
(UART) or Asynchronous Communication Interface Adapter (ACIA)
• A multiprocessor communication function is provided that enables serial data
communication with a number of processors
• Choice of 12 serial data transfer formats
Data length: 7 or 8 bits
Stop bit le ngt h: 1 or 2 bi t s
Parity: E ve n, odd, or none
Multiprocessor bit: 1 or 0
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the SI1 pin level directly in case of
a frami ng e rror
(b) Clock synchronous mode
• Serial data communication is synchronized with a clock
Serial data communication can be carried out with other chips that have a
synchronous communication function
• One serial data transfer format
Data length: 8 bits
• Receive error detection: Overrun errors detected
Rev. 2.0, 11/ 00, page 442 of 1037
(2) Full-duplex communication capability
• The transmitter and receiver are mutually independent, enabling transmission and
reception to be executed simultaneously
• Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
(3) Built-in baud rate generator allows any bit rate to be selected
(4) Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK1 pin
(5) Four interrupt source s
• Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive
error) that c an i ssue reque sts indepe nde ntl y
Rev. 2.0, 11/ 00, page 443 of 1037
23.1.2 Block Diagram
Figure 23.1 shows a block di agra m of the SCI1.
SI1
SO1
SCK1
Clock
External clock
/4
/16
/64
TEI
TXI
RXI
ERI
RSR
RDR1
TSR
TDR1
SMR1
SCR1
SSR1
SCMR1
BRR1
: Receive shift register
: Receive data register1
: Transmit shift register
: Transmit data register1
: Serial mode register1
: Serial control register1
: Serial status register1
: Serial interface mode register1
: Bit rate register1
SCMR1
SSR1
SCR1
SMR1
Transmission/
reception
control
Baud rate
generator
BRR1
Module data bus
Bus interface
Internal data bus
RDR1
TSRRSR
Parity gfeneration
Parity check
[Legend]
TDR1
Fi g ur e 2 3 . 1 B l o c k Di a g r a m o f SCI1
Rev. 2.0, 11/ 00, page 444 of 1037
23.1.3 Pin Configuration
Table 23.1 shows the serial pins used by the SCI1.
Tabl e 2 3 . 1 SCI P i ns
Channel Pin Name Symbol I/O Funct i on
Serial clock pin 1 SCK1 I/ O SCI1 clock input/out put
Receive data pin 1 SI1 I nput SCI1 receive data input
1
Transmit dat a pin 1 SO1 Out put SCI1 transm it dat a output
23.1.4 Register Configuration
The SCI1 has the internal registers shown in table 23. 2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the
transmitter/receiver.
Tabl e 2 3 . 2 SCI Re g i st e r s
Channel Nam e Abbrev. R/W I niti al Value Address*1
Serial mode register 1 SMR1 R/W H'00 H'D148
Bit rat e r egist er 1 BRR1 R/W H'FF H'D149
Serial control register 1 SCR1 R/ W H'00 H'D14A
Transmit dat a register 1 TDR1 R/W H'FF H'D14B
Serial status register 1 SSR1 R/(W) *2H'84 H'D14C
Receiv e da ta r e gis ter 1 RDR1 R H'00 H'D14 D
1
Serial interface m ode r egist er 1 SCMR1 R/W H'F2 H'D14E
MSTPCRH R/W H'FF H'FFECCommon M odule st op cont r ol register
MSTPCRL R/W H'FF H'FFED
Notes: 1. Lower 16 bits of the addr ess.
2. Only 0 can be written, t o clear f lags.
Rev. 2.0, 11/ 00, page 445 of 1037
23.2 Register Descript ion s
23.2.1 Receive Shift Register (RSR)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit :
R/W :
RSR is a register used to receive serial data.
The SCI1 sets serial data input from the SI1 pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to RDR1 automatically.
RSR cannot be directly read or written to by the CPU.
23.2.2 Receive Data Register (RDR1)
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit :
Initial value :
R/W :
RDR1 is a register that stores received serial data.
When the SCI1 has received one byte of serial data, it transfers the received serial data from
RSR to RDR1 where it is stored, and completes the receive operation. After this, RSR is
receive-enabled.
Since RSR and RDR1 function as a double buffer in this way, continuous receive operations can
be performe d.
RDR1 is a read-only register, and cannot be written to by the CPU.
RDR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Rev. 2.0, 11/ 00, page 446 of 1037
23. 2 .3 Tr ansm i t Shi f t Re g i st e r ( T SR)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit :
R/W :
TSR is a register used to transmit serial data.
To perform serial data transmission, the SCI1 first transfers transmit data from TDR1 to TSR,
then sends the data to the SO1 pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from TDR1 to
TSR, and transmission started, automatically. However, data transfer from TDR1 to TSR is not
performed i f t he T DRE bi t i n SSR1 is set to 1.
TSR cannot be directly read or written to by the CPU.
23.2.4 Transmit Data Regi ster (TDR1)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
TDR1 is an 8-bit register that stores data for serial transmission.
When the SCI1 detects that TSR is empty, it transfers the transmit data written in TDR1 to TSR
and starts serial transmission. Continuous serial transmission can be carried out by writing the
next transmit data to TDR1 during serial transmission of the data in TSR.
TDR1 can be read or written to by the CPU at all times.
TDR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Rev. 2.0, 11/ 00, page 447 of 1037
23.2.5 Serial Mode Register (SMR1)
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Bit :
Initial value :
R/W :
SMR1 is an 8-bit register used to set the SCI1's serial transfer format and select the baud rate
generat or c loc k source .
SMR1 can be read or written to by the CPU at all times.
SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7: Communication Mode (C/
$
$
)
Selects asynchronous mode or clock synchronous mode as the SCI1 operating mode.
Bit 7
C/
$
$
Description
0 Asynchronous mode (Init ial value)
1 Clock synchronous mode
Bit 6: Character Le ngth (CHR)
Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data
length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR Description
0 8-bit data (Init ia l v a lu e)
1 7-bit data*
Note: *When 7-bit dat a is selected, t he MSB (bit 7) of TDR1 is not t r ansm it t ed, and LSB-
first / M SB-f irs t selection is not available.
Rev. 2.0, 11/ 00, page 448 of 1037
Bit 5: Pari ty Enable (P E)
In asynchronous mode, selects whether or not parity bit addition is performed in transmission,
and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is
used, parity bit addition and checking is not performed, regardless of the PE bit setting.
Bit 5
PE Description
0 Parity bit addition and checking disabled (I nit ial value)
1 Parity bit addition and checking enabled*
Note: *When the PE bit is set to 1, t he par it y ( even or odd) specif ied by the O/
(
bit is added
to tr ansm it dat a bef ore tr ansm ission. In r eception, the par ity bit is checked for the
parity (even or odd) specif ied by the O/
(
bit.
Bit 4: Pari ty M ode (O/
(
(
)
Selects either even or odd parity for use in parity addition and checking.
The O/
(
bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checki ng, i n asynchronous mode . T he O/
(
bit setting is invalid in synchronous mode, when
parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor
format is used.
Bit 4
O/
(
(
Description
0 Even parity*1( Initial value)
1 Even parity*2
Notes: 1. When even parity is set, par ity bit addit ion is perfor m ed in t r ansm ission so that t he
tot al number of 1 bit s in the t r ansm it char act er plus t he par ity bit is even. In recept ion,
a check is perfor m ed t o see if t he t ot al number of 1 bits in the r eceive char act er plus
the parit y bit is even.
2. When odd parity is set, par ity bit addit ion is perf orm ed in t r ansm ission so that the tot al
number of 1 bit s in t he t r ansm it char act er plus t he par ity bit is odd. I n r ecept ion, a
check is perform ed to see if the t ot al number of 1 bits in the receive char act er plus the
parity bit is odd.
Rev. 2.0, 11/ 00, page 449 of 1037
Bit 3: Stop Bit Length (STOP)
Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only
valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since
stop bits are not a dded.
Bit 3
STOP Description
0 1 stop bit*1( I nit ial value)
1 2 stop bits *2
Notes: 1. In transm ission, a single 1 bit (st op bit) is added to the end of a transmit char act er
before it is sent .
2. In tr ansm ission, t wo 1 bits ( st op bit s) ar e added t o t he end of a tr ansm it char acter
before it is sent .
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2: Multiprocessor Mode (MP)
Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/
(
bit
parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid
in synchronous mode.
For details of the multiprocessor communication function, see section 23.3.3, Multiprocessor
Communication Function.
Bit 2
MP Description
0 Multiprocessor f unct ion disabled (Initial value)
1 Multiprocessor f or m at select ed
Rev. 2.0, 11/ 00, page 450 of 1037
Bits 1 and 0: Clock Select 1 and 0 (CKS1, CKS0)
These bits select the clock source for the baud rate generator. The clock source can be selected
from φ, φ/4, φ/16, a nd φ/64, according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 23.2.8, Bit Rate Register.
Bit 1 Bit 0
CKS1 CKS0 Description
0φ cloc k (I nitial v a lue )0
1φ/4 clock
0φ/16 clock1
1φ/64 clock
23.2.6 Serial Control Register (SCR1)
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit :
Initial value :
R/W :
SCR1 is a register that performs enabling or disabling of SCI1 transfer operations, serial clock
output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR1 can be read or written to by the CPU at all times.
SCR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7: Transmit Interrupt Enable (TIE)
Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit
data is transferred from TDR1 to TSR and the TDRE flag in SSR1 is set to 1.
Bit 7
TIE Description
0 Transm it- dat a-empt y inter rupt ( TXI) r equest disabled*(Init ial value)
1 Transm it- dat a-empt y inter rupt ( TXI) r equest enabled
Note: *TXI inter r upt r equest cancellation can be per f or m ed by r eading 1 f r om t he TDRE flag,
then clearing it t o 0, or clearing t he TI E bit to 0.
Rev. 2.0, 11/ 00, page 451 of 1037
Bit 6: Receive Interrupt Enable (RIE)
Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request generation when serial receive data is transferred from RSR to RDR1 and the RDRF flag
in SSR1 is set to 1.
Bit 6
RIE Description
0 Receive-data- f ull interr upt (RXI) r equest and r eceive- er r or interrupt ( ERI) r equest
disabled*(Initial value)
1 Receive-data- f ull interr upt (RXI) r equest and r eceive- er r or interrupt ( ERI) r equest
enabled
Note: *RXI and ERI interr upt r equest cancellation can be perfor m ed by r eading 1 f r om t he
RDRF, FER, PER, or ORER flag, t hen c lear ing t he flag to 0, or clear ing the RIE bit to
0.
Bit 5: Transmit Enable (TE)
Enables or disables the start of serial transmission by the SCI1.
Bit 5
TE Description
0 Transmission disabled*1(Initial value)
1 Transmission enabled*2
Notes: 1. The TDRE flag in SSR1 is fixed at 1.
2. In this stat e, serial transmission is start ed when transmit dat a is writt en t o TDR1 and
the TDRE flag in SSR1 is cleared t o 0.
SMR1 setting must be per formed to decide the tr ansm ission format bef or e set t ing t he
TE bit to 1.
Bit 4: Receive Enable (RE)
Enables or disables the start of serial reception by the SCI1.
Bit 4
RE Description
0 Reception disabled*1(Initial value)
1 Reception enabled*2
Notes: 1. Clear ing the RE bit to 0 does not affec t the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this st at e when a star t bit is detect ed in asynchronous
mode or ser ial clock input is detected in synchronous m ode.
SMR1 setting m ust be per f or m ed t o decide t he r ecept ion for m at befor e set t ing t he RE
bit to 1.
Rev. 2.0, 11/ 00, page 452 of 1037
Bit 3: Multiprocessor Interrupt Enable (MPIE)
Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in
asynchronous mode when receiving with the MP bit in SMR1 set to 1.
The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0 Multipr ocessor inter r upts disabled (normal r ecept ion perform ed) (I nitial value)
[Clearing conditions]
(1) W hen t he M PI E bit is cleared t o 0
(2) W hen dat a with M PB = 1 is received
1 Multiprocessor inter rupts enabled *
Receive interrupt ( RXI) r equest s , r eceive- er r or interrupt ( ERI) r equest s , and set t ing
of t he RDRF, FER, and ORER flags in SSR ar e dis abled unt il data with the
multiprocessor bit set t o 1 is received.
Note: *When receive dat a including MPB = 0 is received, receive dat a t r ansfer f r om RSR to
RDR1, r ec eiv e er r o r det ec tion, and setting of the RDRF, FER, and ORER flags in
SSR1, is not perf or m ed. W hen r eceive dat a with MPB = 1 is received, t he M PB bit in
SSR1 is set to 1, t he M PI E bit is cleared t o 0 automat ically, and gener at ion of RXI and
ERI interr upt s ( when t he TI E and RIE bits in SCR1 are set t o 1) and FER and ORER
flag sett ing is enabled.
Bit 2: Transmit End Interrupt Enable (TEIE)
Enables or disables transmit-end interrupt (TEI) request generation if there is no valid transmit
data in TDR1 when the MSB is transmitted.
Bit 2
TEIE Description
0 Transm it- end int er r upt ( TEI ) r equest disabled*(Initial value)
1 Transm it- end int er r upt ( TEI ) r equest enabled*
Note: *TEI cancellation can be perf or m ed by r eading 1 fr om the TDRE flag in SSR1, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit t o 0.
Bits 1 and 0: Clock Enable 1 and 0 (CKE1, CKE0)
These bits are used to select the SCI1 clock source and enable or disable clock output from the
SCK1 pin. The combination of the CKE1 and CKE0 bits determines whether the SCK1 pin
functions as an I/O port, the serial clock output pin, or the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
external clock operation (CKE1 = 1). Note that the SCI1's operating mode must be decided
using SMR1 before setting the CKE1 and CKE0 bits.
For details of clock source selection, see table 23.9 in section 23.3, Operation.
Rev. 2.0, 11/ 00, page 453 of 1037
Bit 1 Bit 0
CKE1 CKE0 Description
Asynchronous mode Internal clock/SCK1 pin f unct ions as I / O
port*1
0
Clock synchronous
mode Int er nal clock/SCK1 pin functions as serial
clock output*1
Asynchronous mode Internal clock/SCK1 pin f unct ions as clock
output*2
0
1
Clock synchronous
mode Int er nal clock/SCK1 pin functions as serial
clock output
Asynchronous mode Ext er nal clock/SCK1 pin functions as clock
input*3
0
Clock synchronous
mode Exter nal clock/SCK1 pin functions as serial
clock input
Asynchronous mode Ext er nal clock/SCK1 pin functions as clock
input*3
1
1
Clock synchronous
mode Exter nal clock/SCK1 pin functions as serial
clock input
Not es : 1. In itial v a lue
2. Output s a clock of t he sam e f r equency as the bit rat e.
3. Inputs a clock with a frequency 16 times the bit r at e.
23.2.7 Serial Status Register (SSR1)
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI1,
and multiprocessor bits.
SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 before ha nd. The T END flag a nd MPB flag a re re a d-only fl a gs and ca nnot be m odi fie d.
SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Rev. 2.0, 11/ 00, page 454 of 1037
Bit 7: Transmit Data Register Empty (TDRE)
Indicates that data has been transferred from TDR1 to TSR and the next serial data can be
written to TDR1.
Bit 7
TDRE Description
0 [Clearing conditions]
When 0 is written in TDRE after r eading TDRE = 1
1 [Sett ing conditions] (Initial value)
(1) W hen t he TE bit in SCR1 is 0
(2) W hen dat a is t r ansf er r ed from TDR1 to TSR and data can be written to TDR1
Bit 6: Receive Data Register Full (RDRF)
Indicates that the received data is stored in RDR1.
Bit 6
RDRF Description
0 [Clearing conditions] (Init ial value)
When 0 is wr it ten in RDRF after reading RDRF = 1
1 [Sett ing conditions]
When serial recept ion ends norm ally and receive dat a is tr ansf er r ed from RSR to
RDR1
Note: RDR1 and the RDRF flag are not affec t ed and r etain their previous values when an er r o r
is detected dur ing r ecept ion or when t he RE bit in SCR1 is clear ed t o 0.
If r ec e p tion o f t h e n e x t data is c omple ted wh ile the RDRF flag is s till se t t o 1 , an o v e rru n
err or will oc cu r and the rec eiv e dat a will be los t .
Rev. 2.0, 11/ 00, page 455 of 1037
Bit 5: Overrun Error (ORER)
Indicates that an overrun error occurred during reception, causing abnormal termination.
Bit 5
ORER Description
0 [Clearing conditions] (Init ial value)*1
When 0 is written in O RER after reading ORER = 1
1 [Sett ing conditions]
When the nex t s erial reception is com p let ed while RDRF = 1*2
Notes: 1. The ORER flag is not affected and r et ains its pr evious stat e when t he RE bit in SCR1
is cleared to 0.
2. The receive dat a prior t o t he overrun er r o r is retained in RDR1, and the data rece ived
subsequently is lost. Also, subsequent ser ial recept ion cannot be cont inued while the
ORER flag is set to 1. I n clock synchronous m ode, serial transm ission cannot be
continued, either .
Bit 4: Frami ng Err or (F ER)
Indicates that a framing error occurred during reception in asynchronous mode, causing
abnormal termination.
Bit 4
FER Description
0 [Clearing conditions] (Init ial value)*1
When 0 is writt en in FER aft er reading FER = 1
1 [Sett ing conditions]
When the SCI1 checks the st op bit at t he end of t he r eceive dat a when recept ion
ends, and t he st op bit is 0*2
Notes: 1. The FER flag is not af f ected and ret ains its previous stat e when t he RE bit in SCR1 is
cleared to 0.
2. In 2-stop- bit m ode, only the first st op bit is checked for a value of 1; the second st op
bit is n ot ch e c k e d . I f a fra ming e rro r oc c u rs, th e rece iv e d a ta is tr a n s fer red to RDR1
but t he RDRF f lag is not set . Als o, s ubsequent serial r ec ept ion c annot be c ont inued
while t he FER flag is set t o 1. I n clock synchronous m ode, ser ial tr ansm ission cannot
be continued, either .
Rev. 2.0, 11/ 00, page 456 of 1037
Bit 3: Pari ty Er ror (P ER)
Indicates that a parity error occurred during reception using parity addition in asynchronous
mode, causing abnormal termination.
Bit 4
PER Description
0 [Clearing conditions] (Init ial value)*1
When 0 is written in PER after r eading PER = 1
1 [Sett ing conditions]
When, in recept ion, t he num ber of 1 bits in the r eceive dat a plus the parity bit does
not mat c h t he par ity setting (even or odd) specified by t he O /
(
bit in SMR1*2
Notes: 1. The PER f lag is not af f ect ed and r et ains its previous st at e when the RE bit in SCR1 is
cleared to 0.
2. I f a pa rit y err o r o c c u rs, th e rece iv e da ta is tr an s fer red to RDR1 b ut t h e RDRF flag is
not set . Also, subsequent ser ial recept ion cannot be cont inued while the PER flag is
set to 1. In clock synchronous m ode, ser ial tr ansm ission cannot be cont inued, either .
Bit 2: Transmit End (TEND)
Indicates that there is no valid data in TDR1 when the last bit of the transmit character is sent,
and transmi ssion has bee n ende d.
The TE ND flag i s read-onl y a nd ca nnot be m odi fie d.
Bit 2
TEND Description
0 [Clearing conditions]
When 0 is written in TDRE after r eading TDRE = 1
1 [Sett ing conditions] (Initial value)
(1) W hen t he TE bit in SCR1 is 0
(2) W hen TDRE = 1 at tr ansm ission of the last bit of a 1- byt e ser ial tr ansm it
character
Rev. 2.0, 11/ 00, page 457 of 1037
Bit 1: Multiprocessor Bit (MPB)
When reception is performed using a multiprocessor format in asynchronous mode, MPB stores
the multiprocessor bit in the receive data.
MPB is a read-only bit , a nd ca nnot be m odi fie d.
Bit 1
MPB Description
0 [Clearing conditions] (Init ial value)*
When data with a 0 m ultipr ocessor bit is r eceived
1 [Sett ing conditions]
When data with a 1 m ultipr ocessor bit is r eceived
Note: *Retains its previous stat e when the RE bit in SCR1 is cleared t o 0 with mult iprocessor
format.
Bit 0: Multiproc e ssor Bit Transfer (M P BT)
When transmission is performed using a multiprocessor format in asynchronous mode, MPBT
stores the multiprocessor bit to be added to the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not
transmitting, and in synchronous mode.
Bit 0
MPBT Description
0 Data with a 0 multiprocessor bit is t r ansm itt ed (Initial value)
1 Data with a 1 multiprocessor bit is t r ansm itt ed
23.2.8 Bit Rate Register (BRR1)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
BRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR1.
BRR1 can be read or written to by the CPU at all times.
BRR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Table 23.3 shows sample BRR1 settings in asynchronous mode, and table 23. 4 shows sample
BRR1 settings in clock synchronous mode.
Rev. 2.0, 11/ 00, page 458 of 1037
Tabl e 2 3 . 3 BRR1 Se t t i ng s fo r Va r ious Bit Rat e s ( Asy nc hr o no us M o de )
Operat ing Frequency φ (MHz)
2 2.097152 2.4576 3
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 1 141 0.03 1 148 −0.04 1 174 −0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16
1200 0 51 0.16 0 54 −0.70 0 63 0.00 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16
4800 0 12 0.16 0 13 −2.48 0 15 0.00 0 19 −2.34
9600 06 −2.48 0 7 0.00 0 9 −2.34
19200 0 3 0.00 0 4 −2.34
31250 0 1 0.00 0 0 2 0.00
38400 0 1 0.00
Operat ing Frequency φ (MHz)
3.6864 4 4.9152 5
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 −0.25
150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16
300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16
600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 −1.36
9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
19200 0 5 0.00 0 7 0.00 0 7 1.73
31250 0 3 0.00 0 4 −1.70 0 4 0.00
38400 0 2 0.00 0 3 0.00 0 3 1.73
Rev. 2.0, 11/ 00, page 459 of 1037
Operat ing Frequency φ (MHz)
6 6.144 7.3728 8
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 106 −0.44 2 108 0.08 2 130 −0.07 2 141 0.03
150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16
300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16
600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16
1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16
2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16
4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16
9600 0 19 −2.34 0 19 0.00 0 23 0.00 0 25 0.16
19200 0 9 −2.34 0 9 0.00 0 11 0.00 0 12 0.16
31250 0 5 0.00 0 5 2.40 0 7 0.00
38400 0 4 −2.34 0 4 0.00 0 5 0.00
Operat ing Frequency φ (MHz)
9.8304 10
Bit Rate
(bits/s) n N Error
(%) n N Error
(%)
110 2 174 −0.26 2 177 −0.25
150 2 127 0.00 2 129 0.16
300 1 255 0.00 2 64 0.16
600 1 127 0.00 1 129 0.16
1200 0 255 0.00 1 64 0.16
2400 0 127 0.00 0 129 0.16
4800 0 63 0.00 0 64 0.16
9600 0 31 0.00 0 32 −1.36
19200 0 15 0.00 0 15 1.73
31250 0 9 −1.70 0 9 0.00
38400 0 7 0.00 0 7 1.73
Rev. 2.0, 11/ 00, page 460 of 1037
Tabl e 2 3 . 4 BRR1 Se t t i ng s fo r Va r ious Bit Rat e s ( Cl o c k Sy nc hronous Mode )
Operat ing Frequency φ (MHz)
24810
Bit
Rate
(bits/s) n N n N n N n N
110 3 70
250 2 124 2 249 3 124
500 1 249 2 124 1 249
1 k 1 124 1 249 2 124
2.5 k 0 199 1 99 1 199 1 249
5 k 0 99 0 199 1 99 1 124
10 k 0 49 0 99 0 199 0 249
25 k 0 19 0 39 0 79 0 99
50 k 0 9 0 19 0 39 0 49
100 k 0 4 0 9 0 19 0 24
250 k 0 1 0 3 0 7 0 9
500 k 0 0*010304
1 M 0 0*01
2.5 M 00*
5 M
Note: As far as possible, t he set ting should be made so that the error is no m or e t han 1% .
Legend:
Blank: Cannot be set .
—: Can be se t , but ther e will be a degr ee of err or .
*: Continuous tr ansf er is not possible.
Rev. 2.0, 11/ 00, page 461 of 1037
The BRR1 setting is found from the following equations.
• Asynchronous mode:
N= φ×106−1
64×22n−1×B
• Clock synchronous mode:
N= φ×106−1
8×22n−1×B
Where
B: Bit rate (bits/s)
N: BRR1 setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operat ing fre que ncy (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR1 Se t ti ng
n Clock CKS1 CKS0
0φ00
1φ/4 0 1
2φ/16 1 0
3φ/64 1 1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) = { φ × 106− 1 } × 100
(N+1) × B × 64 × 22n−1
Table 23.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 23.6
and 23.7 show the maximum bit rates with external clock input.
Rev. 2.0, 11/ 00, page 462 of 1037
Table 23.5 Maximum Bit Rate for Each Fr e quency (Asynchronous Mode)
φ (MHz) Maximum Bit Rate (bits/s) n N
2 62500 0 0
2.097152 65536 0 0
2.4576 76800 0 0
3 93750 0 0
3.6864 115200 0 0
4 125000 0 0
4.9152 153600 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
Rev. 2.0, 11/ 00, page 463 of 1037
Tabl e 2 3 . 6 M a ximum B i t Ra te wit h E xt e rnal Cl o c k Input ( Asynchr ono us M o de )
φ (MHz) External Input Clock (M Hz) Maxi m um Bit Rat e ( bi t s/s)
2 0.5000 31250
2.097152 0.5243 32768
2.4576 0.6144 38400
3 0.7500 46875
3.6864 0.9216 57600
4 1.0000 62500
4.9152 1.2288 76800
5 1.2500 78125
6 1.5000 83750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
Tabl e 2 3 . 7 M a ximum B i t Ra te wit h E xt e rnal Cl o c k Input ( Cl o c k Sy nc hr o no us M o de )
φ (MHz) External Input Clock (M Hz) Maxi m um Bit Rat e ( bi t s/s)
2 0.3333 333333.3
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
Rev. 2.0, 11/ 00, page 464 of 1037
23.2.9 Serial Interface Mode Register (SCMR1)
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Bit :
Initial value :
R/W :
SCMR1 is an 8-bit readable/writable register used to select SCI1 functions.
SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 to 4: Reserved
These bit s ca nnot be m odifi e d and a re al ways rea d as 1.
Bit 3: Data Transfer Direction (SDIR)
Selects the serial/parallel conversion format.
Bit 3
SDIR Description
0 TDR1 contents are t r ansm itted LSB-first (Initial value)
Receiv e d a ta is s tored in RDR1 LSB-f irst
1 TDR1 contents are t r ansm itted MSB-fir st
Receiv e d a ta is s tored in RDR1 M SB-f irst
Bit 2: Data Inver t (SINV)
Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the
parity bi t (s): pari t y bit i nversion re qui res inve rsion of t he O/
(
bit in SMR1.
Bit 2
SINV Description
0 TDR1 contents ar e t r ansm it t ed without m odif ication (Init ial value)
Receive dat a is s tored in RDR1 wit hout modificat ion
1 TDR1 contents ar e invert ed bef ore being transm it t ed
Receiv e d a ta is s tored in RDR1 in in v e rte d for m
Rev. 2.0, 11/ 00, page 465 of 1037
Bit 1: Reserved
This bit c a nnot be m odifi e d and i s al ways read a s 1.
Bit 0: Serial Communication Interface Mode Select (SMIF)
1 should not be written in this bit.
Bit 0
SMIF Description
0 Normal SCI mode (Init ial value)
1 Reserved mode
23. 2 .10 Modul e Sto p Cont r o l Regi st e r ( M ST P CR)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
MSTPCRH MSTPCRL
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Bit :
Initial value :
R/W :
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When bit MSTP8 is set to 1, SCI1 operation stops at the end of the bus cycle and a transition is
made to module stop mode. For details, see section 4.5, Module Stop Mode.
MSTPCR is initialized to H'FFFF by a reset.
Bit 0: Module Stop (MSTP8)
Specifies the SCI1 module stop mode.
MSTPCRH
Bit 0
MSTP8 Description
0 SCI1 module stop mode is cleared
1 SCI1 module stop mode is set (Initial value)
Rev. 2.0, 11/ 00, page 466 of 1037
23.3 Operation
23.3.1 Overview
The SCI1 can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or synchronous mode and the transmission format is made using
SMR1 as shown in table 23.8. The SCI1 clock is determined by a combination of the C/
$
bit in
SMR1 and the CKE1 and CKE0 bit s in SCR1, a s shown in tabl e 23. 9.
(1) Asynchronous Mode
• Data length: Choice of 7 or 8 bits
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
• Detection of framing, parity, and overrun errors, and breaks, during reception
• Choice of internal or external clock as SCI1 clock source
— When internal clock is selected:
The SCI1 operates on the baud rate generator clock and a clock with the same
frequency as the bit rate can be output
— When external clock is selected:
A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate
generat or i s not used)
(2) Clock Synchronous Mode
•Transfer format: Fixed 8-bit data
•Detection of overrun errors during reception
•Choice of internal or external clock as SCI1 clock source
— When internal clock is selected:
The SCI1 operates on the baud rate generator clock and a serial clock is output off-
chip
— When external clock is selected:
The built-in baud rate generator is not used, and the SCI1 operates on the input serial
clock
Rev. 2.0, 11/ 00, page 467 of 1037
Table 23.8 SMR1 Settings and Serial Transfer Format Selection
SMR1 Set t ings SCI1 Tr ansf er For mat
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3
C/
$
$
CHR MP PE STOP Mode Data
length Multiproc
-essor bit Parit
y bit St op bit
length
01 bit0
1
No
2 bits
01 bit
0
1
1
8-bit
data
Yes
2 bits
01 bit0
1
No
2 bits
01 bit
1
0
1
1
Asynchro-
nous mode
7-bit
data
No
Yes
2 bits
01 bit0
1
8-bit
data 2 bits
01 bit
0
1
1
1
Asynchro-
nous mode
(multi-
processor
format) 7-bit
data
Yes
2 bits
1 Clock
synchronous
mode
8-bit
data No
No
Tabl e 2 3 . 9 SM R1 and SCR1 Se t t i ng s and SCI1 Cl o c k So urce Selection
SMR1 SCR1 Set ti ng
Bit 7 Bit 1 Bi t 0 SCI 1 Tr ansf er Cl ock
C/
$
$
CKE1 CKE0 Mode Clock Source SCK1 Pin Funct i on
0 SCI1 does not use SCK1 pin0
1
Internal
Outputs clock with same frequency
as bit rate
0
0
1
1
Asynchronous
mode
External Inputs clock with fr equency of 16
times the bit rate
00
1
Inter nal O ut put s ser ial clock
0
1
1
1
Clock
synchronous
mode Exter nal Inputs ser ial clock
Rev. 2.0, 11/ 00, page 468 of 1037
23.3.2 Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of
communication. Serial communication is thus carried out with synchronization established on a
character-by-character basis.
Inside the SCI1, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 23.2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state
(high level). The SCI1 monitors the transmission line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally one or two st op bits (high level).
In asynchronous mode, the SCI1 performs synchronization at the falling edge of the start bit in
reception. The SCI1 samples the data on the 8th pulse of a clock with a frequency of 16 times
the length of one bit, so that the transfer data is latched at the center of each bit.
LSB
Start
bit
MSB
Idle state
(mark state)
Stop
bit(s)
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 1
Serial
data Parity
bit
1 bit 1 or 2 bits7 or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 23. 2 Data For mat i n Asynchronous Communication
(Example with 8-Bit Data, Par ity, Two Stop Bits)
Rev. 2.0, 11/ 00, page 469 of 1037
(1) Data Transfer Format
Table 23.10 shows the data transfer formats that can be used in asynchronous mode. Any of
12 transfer formats can be selected by settings in SMR1.
Table 23.10 Serial Transfer Formats (Asynchronous Mode)
PE
0
0
1
1
0
0
1
1
—
—
—
—
S 8-bit data
STOP
S 7-bit data
STOP
S 8-bit data
STOP STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
S 8-bit data
MPB STOP
S 8-bit data
MPB STOPSTOP
S 7-bit data
STOPMPB
S 7-bit data
STOPMPB STOP
S 7-bit data
STOPSTOP
CHR
0
0
0
0
1
1
1
1
0
0
1
1
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR1 Settings
123456789101112
Serial Transfer Format and Frame Length
STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
STOP
[Legend]
S
STOP
P
MPB
: Start bit
: Stop bit
: Parity bit
: Multiprocessor bit
Rev. 2.0, 11/ 00, page 470 of 1037
(2) Clock
Either an internal clock generated by the built-in baud rate generator or an external clock
input at the SCK1 pin can be selected as the SCI1's serial clock, according to the setting of
the C/
$
bit in SMR1 and the CKE1 and CKE0 bits in SCR1. For details of SCI1 clock
source selection, see table 23.9.
When an external clock is input at the SCK1 pin, the clock frequency should be 16 times the
bit rate used.
When the SCI1 is operated on an internal clock, the clock can be output from the SCK1 pin.
The frequency of the clock output in this case is equal to the bit rate, and the phase is such
that the rising edge of the clock is at the center of each transmit data bit, as shown in figure
23.3.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
Figure 23. 3 Rel ati on between Output Clock and Transfer Data Phase
(Async hr o no us M o de )
Rev. 2.0, 11/ 00, page 471 of 1037
(3) Data Transfer Operations
(a) SCI1 Initialization (Asynchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI1 as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE
bit to 0 doe s not c hange t he c ont ent s of the RDRF, PER, FER, a nd ORER fl ags, or the
content s of RDR1.
When an external clock is used the clock should not be stopped during operation,
including initialization, since operation is uncertain.
Figure 23.4 shows a sample SCI1 initialization flowchart.
Wait
<Initialization completed>
Start initialization
Set data transfer format
in SMR1 and SCMR1
[1]
Set CKE1 and CKE0 bits in SCR1
(TE, RE bits 0)
No
Yes
Set value in BRR1
Clear TE and RE bits in SCR1 to 0
[2]
[3]
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE,
and MPIE bits [4]
1-bit interval elapsed?
Set the clock selection in SCR1.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR1 settings are made.
Set the data transfer format in SMR1 and
SCMR1.
Write a value corresponding to the bit rate
to BRR1. This is not necessary if an
external clock is used.
Wait at least one bit interval, then set the
TE bit or RE bit in SCR1 to 1. Also set the
RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
[1]
[2]
[3]
[4]
Fi g ur e 2 3 . 4 Sa mple SCI Ini t i alization Flowchart
Rev. 2.0, 11/ 00, page 472 of 1037
(b) Serial Data Transmission (Asynchronous Mode)
Figure 23.5 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
No
< End >
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR1 [1]
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
No
Yes
No
Yes
Read TEND flag in SSR1
[3]
No
Yes
[4]
Clear PDR to 0
and set PCR to 1
Clear TE bit in SCR1 to 0
TDRE=1
All data transmitted?
TEND=1
Break output?
SCI1 initialization:
The SO1 pin is automatically designated as
the transmit data output pin.
SCI1 status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Serial transmission continuation procedure:
To continue serial transmission, read 1
from the TDRE flag to confirm that writing is
possible, then write data to TDR1, and then
clear the TDRE flag to 0.
Break output at the end of serial
transmission:
To output a break in serial transmission, set
PCR for the port corresponding to the SO1
pin to 1, clear PDR to 0, then clear the TE
bit in SCR1 to 0.
[1]
[2]
[3]
[4]
Figure 23.5 Sample Serial Transmission Flowchart
Rev. 2.0, 11/ 00, page 473 of 1037
In serial transmission, the SCI1 operates as described below.
[1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been
written to TDR1, and transfers the data from TDR1 to TSR.
[2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the SO1 pin in the following order.
[a] Start bit:
One 0-bit is output .
[b] Transmit data:
8-bit or 7-bit data is output in LSB-first order.
[c] Parity bit or multiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
[d] Stop bit(s):
One or two 1-bits (stop bits) are out put.
[e] Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
[3] The SCI1 checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR1 to TSR, the stop bit is
sent, and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then
the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR1 is set to
1 at this time, a TEI interrupt request is generated.
Figure 23.6 shows an example of the operation for transmission in asynchronous mode.
Rev. 2.0, 11/ 00, page 474 of 1037
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
Data
Start
bit
Parity
bit Stop
bit Start
bit
Data
Parity
bit Stop
bit
TXI interrupt
request
generated
Data written to TDR1 and
TDRE flag cleared to 0
in TXI interrupt handling
routine
TEI interrupt request
generated
Idle state
(mark state)
TXI interrupt request
generated
Figure 23. 6 Example of O perati on in Transmission in Async hronous Mode
(Example with 8-Bit Data, Par ity, O ne Stop Bit)
Rev. 2.0, 11/ 00, page 475 of 1037
(c) Serial Data Reception (Asynchronous Mode)
Figure 23.7 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
Yes
< End >
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR1 [4]
[5]
Clear RE bit in SCR1 to 0
Read ORER, PER,
FER flags in SSR1
Error handling
(Continued on next page)
[3]
Read receive data in RDR1, and clear
RDRF flag in SSR1 to 0
No
Yes
PER FER ORER=1
RDRF=1
All data received?
SCI1 initialization:
The SI1 pin is automatically designated as
the receive data input pin.
Receive error handling and break
detection:
If a receive error occurs, read the ORER,
PER, and FER flags in SSR1 to identify the
error. After performing the appropriate
error handling, ensure that the ORER,
PER, and FER flags are all cleared to 0.
Reception cannot be resumed if any of
these flags are set to 1. In the case of a
framing error, a break can be detected by
reading the value of the input port
corresponding to the SI1 pin.
SCI1 status check and receive data read:
Read SSR1 and check that RDRF = 1, then
read the receive data in RDR1 and clear
the RDRF flag to 0. Transition of the RDRF
flag from 0 to 1 can also be identified by an
RXI interrupt.
Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is received,
read the RDRF flag, read RDR1, and clear
the RDRF flag to 0.
[1]
[2][3]
[4]
[5]
Figure 23.7 Sample Serial Reception Data Flowchart (1)
Rev. 2.0, 11/ 00, page 476 of 1037
< End >
[3]
Error handling
Parity error handling
Yes
No
Clear ORER, PER, and FER
flags in SSR1 to 0
No
Yes
No
Yes
Framing error handling
No
Yes
Overrun error handling
ORER=1
FER=1
Break?
PER=1
Clear RE bit in SCR1 to 0
Figure 23.7 Sample Serial Reception Data Flowchart (2)
Rev. 2.0, 11/ 00, page 477 of 1037
In serial reception, the SCI1 operates as described below.
[1] The SCI1 monitors the transmission line, and if a 0 stop bit is detected, performs internal
synchronization and starts reception.
[2] The received data is stored in RSR in LSB-to-MSB order.
[3] The parity bit and stop bit are received.
After receiving these bits, the SCI1 carries out the following checks.
[a] Parity check:
The SCI1 checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set i n t he O/
(
bit in SMR1.
[b] Stop bit check:
The SCI1 chec ks whethe r the stop bi t i s 1.
If there are two stop bits, only the first is checked.
[c] Status check:
The SCI1 checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR1.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored
in RDR1.
If a receive error* is detected in the error check, the operation is as shown in table 23.11.
Note: * Subsequent receive operations cannot be performed when a receive error has
occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must
be cleared to 0.
[4] If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full
interrupt (RXI) request is generated.
Also, if the RIE bi t in SCR1 is set t o 1 when t he ORER, PER, or FER fl a g cha nge s to 1, a
receive-error interrupt (ERI) request is generated.
Table 23.11 Receive Errors and Conditions for Occurrence
Receive Err or Abbrev. O ccur r ence Condi t ion Data Tr ansf er
Over r un er r or O RER When the next dat a r ecept ion is
completed wh ile the RDRF flag
in SSR1 is set to 1
Receive data is not tr ansferr ed
from RSR to RDR1
Framing er r or FER When the st op bit is 0 Receive data is t r ansf er r ed
from RSR to RDR1
Parity error PER When t he r eceived data dif f er s
from the parity ( even or odd) set
in SMR1
Receive data is transf er r ed
from RSR to RDR1
Rev. 2.0, 11/ 00, page 478 of 1037
Figure 23.8 shows an example of the operation for reception in asynchronous mode.
RDRF
FER
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0
1 1
Data
Start
bit
Parity
bit Stop
bit Start
bit Data
Parity
bit Stop
bit
ERI interrupt request
generated by framing
error
Idle state
(mark state)
RDR1 data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
RXI interrupt
request
generation
Figur e 23. 8 Exampl e of SCI1 O per ati on in Reception
(Example with 8-Bit Data, Par ity, O ne Stop Bit)
23.3.3 Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using a
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in
asynchronous mode. Use of this function enables data transfer to be performed among a number
of processors sharing transmission lines.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is
used to differentiate between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as
data with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with
its own ID. The station whose ID matches then receives the data sent next. Stations whose ID
does not match continue to skip the data until data with a 1 multiprocessor bit is again received.
In this way, data communication is carried out among a number of processors.
Figure 23.9 shows an example of inter-processor communication using a multiprocessor format.
Rev. 2.0, 11/ 00, page 479 of 1037
(1) Data Transfer Format
There are four data transfer formats.
When a multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 23.10.
(2) Clock
See the section on asynchronous mode.
Transmitting
station
Receiving
station A
(ID=01)
Receiving
station B
(ID=02)
Receiving
station C
(ID=03)
Receiving
station D
(ID=04)
Serial communication line
Serial
data
ID transmission cycle:
receiving station
specification
Data transmission cycle:
data transmission to
receiving station
specified by ID
(MPB=1) (MPB=0)
H'01 H'AA
[Legend] MPB : Multiprocessor bit
Figure 23. 9 Example of Inter-P roc e ssor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
(3) Data Transfer Operations
(a) Multiprocessor Serial Data Transmission
Figure 23.10 shows a sample flowchart for multiprocessor serial data transmission.
The following procedure should be used for multiprocessor serial data transmission.
Rev. 2.0, 11/ 00, page 480 of 1037
No
< End >
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR1 [2]
Write transmit data to TDR1
and set MPBT bit in SSR1
No
Yes
No
Yes
Read TEND flag in SSR1
[3]
No
Yes
[4]
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR1 to 0
TDRE=1
Transmission end?
TEND=1
Break output?
Clear TDRE flag to 0
SCI1 initialization:
The SO1 pin is automatically designated as
the transmit data output pin.
SCI1 status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to
TDR1. Set the MPBT bit in SSR1 to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation procedure:
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR1,
and then clear the TDRE flag to 0.
Break output at the end of serial
transmission:
To output a break in serial transmission, set
the port PCR to 1, clear PDR to 0, then
clear the TE bit in SCR1 to 0.
[1]
[2]
[3]
[4]
Figure 23.10 Sample Multiprocessor Serial Transmission Flowchart
Rev. 2.0, 11/ 00, page 481 of 1037
In serial transmission, the SCI1 operates as described below.
[1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been
written to TDR1, and transfers the data from TDR1 to TSR.
[2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
The serial transmit data is sent from the SO2 pin in the following order.
[a] Start bit:
One 0-bit is output .
[b] Transmit data:
8-bit or 7-bit data is output in LSB-first order.
[c] Mult i proce ssor bit
One multiprocessor bit (MPBT value) is output.
[d] Stop bit(s):
One or two 1-bits (stop bits) are out put.
[e] Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
[3] The SCI1 checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then
the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR1 is set to
1 at this time, a transmit-end interrupt (TEI) request is generated.
Rev. 2.0, 11/ 00, page 482 of 1037
Figure 23.11 shows an example of SCI1 operation for transmission using a multiprocessor
format.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1Data Data
TXI interrupt
request
general
Data written to TDR1 and
TDRE flag cleared to 0
in TXI interrupt handling
routine
TEI interrupt
request
generated
Idle state
(mark state)
TXI interrupt request
generated
Start
bit
Multi-
processor
bit Stop
bit Start
bit
Stop
bit 1
Multi-
processor
bit
Fig ure 23.11 Example of SCI1 O per ati on i n Tr ansmissi on
(Example with 8-Bit Data, Multi proce ssor Bit, O ne Stop Bit)
(b) Multiprocessor Serial Data Reception
Figure 23.12 shows a sample flowchart for multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
Rev. 2.0, 11/ 00, page 483 of 1037
Yes
< End >
[1]
No
Initialization
Start reception
No
Yes
[4]
Clear RE bit in SCR1 to 0
Error handling
(Continued on
next page)
[5]
No
Yes
FER∨ORER=1
RDRF=1
All data received?
Set MPIE bit in SCR1 to 1 [2]
Read ORER and FER flags in SSR1
Read RDRF flag in SSR1 [3]
Read receive data in RDR1
No
Yes
This station's ID?
Read ORER and FER flags in SSR1
Yes
No
Read RDRF flag in SSR1
No
Yes
FER∨ORER=1
Read receive data in RDR1
RDRF=1
SCI1 initialization:
The SI1 pin is automatically designated as
the receive data input pin.
ID reception cycle:
Set the MPIE bit in SCR1 to 1.
SCI1 status check, ID reception and
comparison:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and compare it with this station's ID.
If the data is not this station's ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station's ID, clear the
RDRF flag to 0.
SCI1 status check and data reception:
Read SSR1 and check that the RDRF flag
is set to 1, then read the data in RDR1.
Receive error handling and break
detectioon:
If a receive error occurs, read the ORER
and FER flags in SSR1 to identify the error.
After performing the appropriate error
handling, ensure that the ORER and FER
flags are both cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can
be detected by reading the SI1 in value.
[1]
[2]
[3]
[4]
[5]
Figure 23.12 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 2.0, 11/ 00, page 484 of 1037
< End >
Error handling
Yes
No
Clear ORER, PER, and FER
flags in SSR1 to 0
No
Yes
No
Yes
Framing error handling
Overrun error handling
ORER=1
FER=1
Break?
Clear RE bit in SCR1 to 0
[5]
Figure 23.12 Sample Multiprocessor Serial Reception Flowchart (2)
Figure 23.13 shows an example of SCI1 operation for multiprocessor format reception.
Rev. 2.0, 11/ 00, page 485 of 1037
MPIE
RDR1
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
Data (ID1)
Start
bit
MPB
Stop
bit Start
bit
Data (Data 1) MPB
Stop
bit
RXI interrupt
request (multi-
processor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR1 data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station's
ID, MPIE bit is set
to 1 again
RXI interrupt request
is not generated, and
RDR1 retains its state
ID1
(a) Data does not match station's ID
MPIE
RDR1
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
Data (ID2)
Start
bit
MPB
Stop
bit Start
bit
Data (Data 2) MPB
Stop
bit
RXI interrupt
request (multi-
processor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR1 data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station's
ID, so reception continues,
and data is received in RXI
interrupt handling routine
MPIE bit set
to 1 again
ID2
(b) Data matches station's ID
Data2ID1
MPIE=0
MPIE=0
Fig ure 23.13 Example of SCI O per ati on i n Reception
(Example with 8-Bit Data, Multi proce ssor Bit, O ne Stop Bit)
Rev. 2.0, 11/ 00, page 486 of 1037
23. 3 .4 Ope ration i n Cl o c k Sy nc hrono us M o de
In clock synchronous mode, data is transmitted or received in synchronization with clock pulses,
making it suitable for high-speed serial communication.
Inside the SCI1, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 23.14 shows the general format for clock synchronous serial communication.
Don't
care
Don't
care
One unit of transfer data (character or frame)
Bit 0
Serial
data
Synchronous
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
**
Note: * High except in continuous transmit/reception
Figure 23. 14 Data For mat i n Clock Synchronous Communication
In clock synchronous serial communication, data on the transmission line is output from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the
serial clock.
In clock synchronous serial communication, one character consists of data output starting with
the LSB and ending with the MSB. After the MSB is output, the transmission line holds the
MSB state.
In clock synchronous mode, the SCI1 receives data in synchronization with the rising edge of the
serial clock.
(1) Data Transfer Format
A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
(2) Clock
Either an internal clock generated by the built-in baud rate generator or an external serial
clock input at the SCK1 pin can be selected, according to the setting of the C/
$
bit in SMR1
and the CKE1 and CKE0 bits in SCR1. For details on SCI clock source selection, see table
23.9.
When the SCI1 is operated on an internal clock, the serial clock is output from the SCK1 pin.
Rev. 2.0, 11/ 00, page 487 of 1037
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however,
the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To
perform receive operations in units of one character, select an external clock as the clock
source.
(3) Data Transfer Operations
(a) SCI1 Initialization (Synchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI1 as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE
bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the
content s of RDR1.
Figure 23.15 shows a sample SCI1 initialization flowchart.
Wait
<Transfer start>
Start initialization
Set data transfer format
in SMR1 and SCMR1
No
Yes
Set value in BRR1
Clear TE and RE bits in SCR1 to 0
[2]
[3]
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE, and MPIE
bits [4]
1-bit interval elapsed?
Set CKE1 and CKE0 bits in
SCR1 (TE, RE bits 0) [1]
Set the clock selection in SCR1. Be sure to
clear bits RIE, TIE, TEIE, and MPIE, TE
and RE, to 0.
Set the data transfer format in SMR1 and
SCMR1.
Write a value corresponding to the bit rate
to BRR1. This is not necessary if an
external clock is used.
Wait at least one bit interval, then set the
TE bit or RE bit in SCR1 to 1.
Also set the RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
[1]
[2]
[3]
[4]
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Fi g ur e 2 3 . 1 5 Sam pl e SCI Ini tialization Flowchart
Rev. 2.0, 11/ 00, page 488 of 1037
(b) Serial Data Transmission (Clock Synchronous Mode)
Figure 23.16 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
No
< End >
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR1 [2]
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
No
Yes
No
Yes
Read TEND flag in SSR1
[3]
Clear TE bit in
SCR1 to 0
TDRE=1
All data transmitted?
TEND=1
SCI1 initialization:
The SO1 pin is automatically designated as
the transmit data output pin.
SCI1 status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Serial transmission continuation procedure:
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR1,
and then clear the TDRE flag to 0.
[1]
[2]
[3]
Figure 23.16 Sample Serial Transmission Flowchart
Rev. 2.0, 11/ 00, page 489 of 1037
In serial transmission, the SCI1 operates as described below.
[1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been
written to TDR1, and transfers the data from TDR1 to TSR.
[2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is
generated.
When clock output mode has been set, the SCI1 outputs 8 serial clock pulses. When use of
an external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the SO1 pin starting with the LSB (bit 0) and ending
with the MSB (bit 7).
[3] The SCI1 checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR, and serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the MSB (bit 7) is sent, and
the SO1 pin maintains its state.
If the TEIE bit in SCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is
generated.
[4] After completion of serial transmission, the SCK1 pin is held in a constant state.
Figure 23.17 shows an example of SCI1 operation in transmission.
Transfer
direction
Bit 0
Serial
data
Synchronous
clock
1 frame
TDRE
TEND
Data written to TDR1
and TDRE flag cleared
to 0 in TXI interrupt
handling routine
TXI interrupt
request
generated
Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI interrupt
request
generated
TEI interrupt
request
generated
Fig ure 23.17 Example of SCI1 O per ati on i n Tr ansmissi on
Rev. 2.0, 11/ 00, page 490 of 1037
(c) Serial Data Reception (Clock Synchronous Mode)
Figure 23.18 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
When cha ngi ng the ope rat i ng mode from asynchronous to synchronous, be sure t o c hec k
that the ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor
receive operations will be possible.
Rev. 2.0, 11/ 00, page 491 of 1037
Yes
< End >
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR1 [4]
[5]
Clear RE bit in SCR1 to 0
Error handling
(Continued below)
[3]
Read receive data in RDR1,
and clear RDRF flag in SSR1 to 0
No
Yes
ORER=1
RDRF=1
All data received?
Read ORER flag in SSR1
< End >
Error handling
Clear ORER flag in
SSR1 to 0
Overrun error handling
[3]
SCI1 initialization:
The SI1 pin is automatically designated as
the receive data input pin.
Receive error handling:
IF a receive error occurs, read the ORER
flag in SSR1, and after performing the
appropriate error handling, clear the ORER
flag to 0. Transfer cannot be resumed if
the ORER flag is set to 1.
SCI1 status check and receive data read:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by and RXI interrupt.
Serial reception continuation procedure:
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
finish reading the RDRF flag, reading
RDR1, and clearing the RDRF flag to 0
[1]
[2][3]
[4]
Figure 23.18 Sample Serial Reception Flowchart
Rev. 2.0, 11/ 00, page 492 of 1037
In serial reception, the SCI1 operates as described below.
[1] The SCI1 performs internal initialization in synchronization with serial clock input or output.
[2] The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI1 checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR1.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR1. If a
receive error is detected in the error check, the operation is as shown in table 23.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in t he error c he ck.
[3] If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full
interrupt (RXI) request is generated.
Also, if the RIE bit in SCR1 is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
Figure 23.19 shows an example of SCI1 operation in reception.
Bit 7
Serial
data
Synchronous
clock
1 frame
RDRF
ORER
ERI interrupt request
generated by
overrun error
RXI interrupt
request
generated
RDR1 data read and
RDRF flag cleared to 0
in RXI interrupt
handling routine
RXI interrupt
request
generated
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figur e 23. 19 Exampl e of SCI1 O per ati on in Reception
(d) Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
Figure 23.20 shows a sample flowchart for simultaneous serial transmit and receive
operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
Rev. 2.0, 11/ 00, page 493 of 1037
Yes
< End >
[1]
No
Initialization
Start transfer
[5]
Error handling
[3]
Read receive data in RDR1, and
clear RDRF flag in SSR1 to 0
No
Yes
ORER=1
All data received?
[2]
Read TDRE flag in SSR1
No
Yes
TDRE=1
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
No
Yes
RDR=1
Read ORER flag in SSR1
[4]
Read RDRF flag in SSR1
Clear TE and RE
bits in SCR1 to 0
Note: When switching from transmit or receive operation
to simultaneous transmit and receive operations, first clear
the TE bit and RE bit to 0, then set both these bits to 1
simultaneously.
SCI1 initialization:
The SO1 pin is designated as the transmit
data output pin, and the SI1 pin is
designated as the receive data input pin,
enabling simultaneous transmit and receive
operations.
SCI1 status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1 can
also be identified by a TXI interrupt.
Receive error handling:
If a receive error occurs, read the ORER
flag in SSR1, and after performing the
appropriate error handling, clear the ORER
flag to 0. Transmission/reception cannot
be resumed if the ORER flag is set to 1.
SCI1 status check and receive data read:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by an RXI interrupt.
Serial transmission/reception continuation
procedure:
To continue serial transmission/reception,
before the MSB (bit 7) of the current frame
is received, finish reading the RDRF flag,
reading RDR1, and clearing the RDRF flag
to 0. Also before the MSB (bit 7) of the
current frame is transmitted, read 1 from
the TDRE flag to confirm that writing is
possible, then write data to TDR1 and clear
the TDRE flag to 0.
[1]
[2]
[3]
[4]
[5]
Figure 23.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Rev. 2.0, 11/ 00, page 494 of 1037
23.4 SCI1 Interrupt s
The SCI1 has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error
interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty
interrupt (TXI) request. Table 23.13 shows the interrupt sources and their relative priorities.
Individual i nte rrupt sources ca n be ena bl ed or di sabl ed wit h t he T IE , RIE, a nd T EIE bi ts in
SCR1. Each kind of interrupt request is sent to the interrupt controller independently.
When the TDRE flag in SSR1 is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR1 is set to 1, a TEI interrupt request is generated.
When the RDRF flag in SSR1 is set to 1, an RXI interrupt request is generated. When the
ORER, PER, or FER flag in SSR1 is set to 1, an ERI interrupt request is generated.
Tabl e 2 3 . 1 3 SCI1 Int errupt Sources
Channel I nterr upt Sour ce Description Priority*
ERI Interr upt by r eceive er r or ( O RER, FER, or PER)
RXI Inter rupt by r e c e ive d ata regis t e r f ull (RDRF)
TXI Int er r upt by tr ansm it data register em pty (TDRE)
1
TEI Int er r upt by tr ansm it end (TEND)
High
Low
The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance,
and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be
accepted in this case.
Rev. 2.0, 11/ 00, page 495 of 1037
23.5 Usage Not es
The foll owing poi nt s should be note d when using t he SCI1.
(1) Relation between Writes to TDR1 and the TDRE Flag
The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred
from TDR1 to TSR. When the SCI transfers data from TDR1 to TSR, the TDRE flag is set
to 1.
Data can be written to TDR1 regardless of the state of the TDRE flag. However, if new data
is written to TDR1 when the TDRE flag is cleared to 0, the data stored in TDR1 will be lost
since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE
flag is set to 1 before writing transmit data to TDR1.
(2) Operation when Multiple Receive Errors Occur Simultaneously
If a number of receive errors occur at the same time, the state of the status flags in SSR1 is as
shown in table 23.14. If there is an overrun error, data is not transferred from RSR to RDR1,
and the receive data is lost.
Table 23.14 State of SSR1 Status F l ags and Tr ansfe r of Receive Data
SSR1 Status Flags
RDRF ORER FER PER
Receive Data
Transfer
RSR → RDR1 Receive Err or s
1100×Over r un er r or
0010
{
Framing er r or
0001
{
Parity error
1110×Over r un er r or + f r aming error
1101×Overrun error + parity error
0011
{
Framing er r or + par ity er ror
1111×Over r un er r or + f r aming error + par it y er r or
Notes:
{
: Re c e iv e d a ta is tra n s fer red fr o m RSR to RDR1 .
×: Receiv e d a ta is n o t t r a n s fer red fro m RSR t o RDR1 .
(3) Break Detection and Processing
When a framing error (FER) is detected, a break can be detected by reading the SI1 pin value
directly. In a break, the input from the SI1 pin becomes all 0s, and so the FER flag is set,
and the pa ri ty e rror fl ag (PER) m a y al so be set .
Note that, since the SCI1 continues the receive operation after receiving a break, even if the
FER flag is cleared to 0, it will be set to 1 again.
(4) Sending a Brea k
The SO1 pin has a dual function as an I/O port whose direction (input or output) is
determined by PDR and PCR. This feature can be used to send a break.
Rev. 2.0, 11/ 00, page 496 of 1037
Between serial transmission initialization and setting of the TE bit to 1, the mark state is
replaced by the value of PDR (the pin does not function as the SO1 pin until the TE bit is set
to 1). Conseque ntl y, PCR and PDR for the port corre sponding t o the SO1 pin should first be
set to 1.
To send a break during serial transmission, first clear PDR to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the SO1 pin becomes an I/O port, and 0 is output from the SO1 pin.
(5) Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1,
even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
(6) Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI1 operates on a base clock with a frequency of 16 times the
transfer rate.
In reception, the SCI1 samples the falling edge of the start bit using the base clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the base clock. This is illustrated in figure 23.21.
Internal
base clock
16 clocks
8 clocks
Receive data
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Figure 23.21 Receive Data Sampling Timing in Asynchronous Mode
Rev. 2.0, 11/ 00, page 497 of 1037
Thus the receive margin in asynchronous mode is given by equation (1) below.
M = (0.5−1) − (L−0.5) F −D − 0. 5(1+F) × 100%
2N N …..(1)
Where M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1. 0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming valu e s o f F = 0 a n d D = 0 .5 i n e q u ation (1), a receive margin of 46. 875% is given by
equati on (2) be low.
When D = 0. 5 and F = 0,
M =(0.5−1) × 100%
2 × 16
=46.875% …..(2)
However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in
system design.
Rev. 2.0, 11/ 00, page 498 of 1037
Rev. 2.0, 11/ 00, page 499 of 1037
Section 24 Serial Communication Interface 2 (SCI2)
24.1 Overview
The serial communication interface 2 (SCI2) that has a 32-byte data buffer carries out clocked
synchronous serial transmission of 32 bytes by a single operation.
24.1.1 Features
SCI2 features are listed below.
• 32 bytes data transfer can be automatically carried out
• Choice of 7 internal clocks (φ/256, φ/64, φ/32, φ/16, φ/8, φ/4, and φ/2) and an external clock
as serial clock source
• Interrupt occurs when transmission has been completed or an error has occurred
• Data transfer at intervals of 1 byte can be set
Data transfer can be carried out at intervals of 1 byte. The interval can be selected from a
multiple of internal clock cycle by 56, 24, or 8 times
• Start of data transfer can be controlled by input of chip select
• Strobe pulse is output for each 1-byte transfer
Rev. 2.0, 11/ 00, page 500 of 1037
24.1.2 Block Diagram
Figure 24.1 shows a block di agra m of the SCI2.
[Legend]
STAR
/256, /64, /32,
/16, /8, /4, /2
EDAR
: Starting address register
: Ending address register
SCK2
STRB
: SCI2 clock input/output pin
: SCI2 strobe signal output pin
SCR2
SCSR2
: Serial control register 2
: Serial control status register
CS
SO2
: SCI2 chip select signal input pin
: SCI2 transmit data output pin
SI2 : SCI2 receive data input pin
Internal clock
SCK2
Interrupt request
SI2
SO2
CS
STRB
SCK2
Shift register
STAR
EDAR
SCR2
SCSR2
Data buffer
(32 bytes)
Interrupt
generation
circuit
Transmit/
receive
control
circuit
Internal data bus
Fi g ur e 2 4 . 1 B l o c k Di a g r a m o f SCI2
Rev. 2.0, 11/ 00, page 501 of 1037
24.1.3 Pin Configuration
Table 24.1 shows pin configuration of the SCI2.
Table 24.1 Pin Configuration
Name Abbrev. I/O Function
SCI2 Clock SCK2 I/O SCI2 clock input/output pin
SCI2 Data input SI2 Input SCI2 receive dat a input pin
SCI2 Data output SO2 Out put SCI2 tr ansm it dat a out put pin
SCI2 Strobe STRB O utput SCI2 st r obe signal output pin
SCI2 Chip s e le c t
&6
Input SCI2 chip select signal input pin
24.1.4 Register Configuration
Table 24.2 shows register configuration of the SCI2.
Table 24.2 Register Configuration
Name Abbrev. R/W I ni tial Value Address*
Start ing address register STAR R/W H'E0 H'D0E0
Ending address register EDAR R/W H'E0 H'D0E1
Serial control register 2 SCR2 R/W H'20 H'D0E2
Serial control stat us r egist er 2 SCSR2 R/W H'60 H'D0E3
Serial data buffer ( 32 bytes) R/W Undef ined H'D0C0 to H'D0DF
Note: *Lower 16 bits of t he addr ess. .
Rev. 2.0, 11/ 00, page 502 of 1037
24.2 Register Descript ion s
24.2.1 Starting Address Register (STAR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
56
1
7———
——— R/WR/W
STA4 STA3 STA2 STA1 STA0
11
Bit :
Initial value :
R/W :
The STAR is a readable/writable register that specifies the transfer starting address within the
address space (H'FFD0C0 to H'FFD0DF) to whi c h a 32-byt e data buffer is assigned. The 5 low-
order bits of the STAR corre spond to the 5 l ow-order bit s of the addre ss of 32-byte buffe r. The
range for executing continuous data transfer on STAR and EDAR is specified. When the value
of STAR is equal to that of EDAR, only one-byte transfer is carried out.
Since the 7 to 5 bits of the STAR are reserved, writes are disabled. When each bit is read, 1 is
read at all times.
The STAR is initialized to H'E0 by a reset.
24. 2 .2 Ending Addr e ss Re g i st e r (EDAR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
56
1
7———
——— R/WR/W
EDA4 EDA3 EDA2 EDA1 EDA0
11
Bit :
Initial value :
R/W :
The EDAR is a readable/writable register that specifies the transfer ending address within the
address space (H'FFD0C0 to H'FFD0DF) to whi c h 32-byt e data buffer is assigned. The 5 low-
order bits of EDAR correspond to t he 5 low-order bi t s of the a ddre ss of 32-byte buffer. T he
range for executing continuous data transfer is specified by the EDAR and the STAR. If the
value of the STAR is equal to that of the EDAR, only one-byte transfer is carried out.
Since the 7 to 5 bits of the EDAR are reserved, writes are disabled. When each bit is read, 1 is
read at all times.
The EDAR is initialized to H'E0 by a reset.
Rev. 2.0, 11/ 00, page 503 of 1037
24.2.3 Serial Control Register 2 (SCR2)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
—
—
67
R/WR/W
GAP1
0
R/W
ABTIE
R/W
TEIE GAP0 CKS2 CKS1 CKS0
01
Bit :
Initial value :
R/W :
The SCR 2 is a readable/writable register that enables or disables generation of SCI2 interrupt
and selects an data transfer interval and transfer clock when an internal clock is used.
The SCR2 is initialized to H'20 by a reset.
Bit 7: Transmit End Interrupt Enable (TEIE)
Enables or disables the occurrence of transmit-end interrupt when data transfer has been
completed and TEI of the SCR2 has been set to 1.
Bit 7
TEIE Description
0 Transm it- end int er r upt disabled ( I nitial value)
1 Transm it- end int er r upt enabled
Bit 6: Transmit Cutoff Interrupt (ABTIE)
Enables or disables the occurrence of transmit-cutoff interrupt when the
&6
pin has entered a
high leve l during t ra nsmission and ABT of t he SCRS2 has been set t o 1.
Bit 6
ABTIE Description
0 Transm it- cut off interrupt disabled (Initial value)
1 Transm it- cut off interrupt enabled
Bit 5: Reserved
When read, 1 is read at all times. Writes are disabled.
Rev. 2.0, 11/ 00, page 504 of 1037
Bits 4 and 3: Transmit Data Interval Select 1 and 0 (GAP1, GAP0)
When an internal clock is used, data can be transmitted at 1-byte intervals. During that time, the
SCK2 pin retains the high level. When data is transmitted without intervals, the STRB signal
retains the low level.
Bit 4 Bit 3
GAP1 GAP0 Description
0 0 Data t r ansm ission without intervals ( I nitial value)
0 1 Data inter vals: 8 clocks
1 0 Data inter vals: 24 clocks
1 1 Data inter vals: 56 clocks
Bits 2 to 0: Transfer Clock Select 2 to 0 (CKS2 to CKS0)
Selects transfer clock.
Bit 2 Bi t 1 Bi t 0 Transfer cl ock cycle
CKS2 CKS1 CKS0 SCK2
pin Clock
source Prescal er di vi sion
ratio φ = 10 M Hz φ = 5 MHz
000 φ/256 ( I nit ial value) 25. 6 µs 51.2 µs
001 φ/64 6.4 µs 12.8 µs
010 φ/32 3.2 µs6.4 µs
011 φ/16 1.6 µs3.2 µs
100 φ/8 0.8 µs1.6 µs
101 φ/4 0.4 µs0.8 µs
110
SCK2
output Prescaler
S
φ/2 0.4 µs
111SCK2
input External
clock
24.2.4 Serial Control Status Register 2 (SCSR2)
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/W
56 ——
——
7
R/WR/(W)*
SOL
R/(W)*
TEI ORER WT ABT STF
011
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The SCSR2 is an 8-bit register that indicates the SCI2's state of operation and error.
The SCSR2 is initialized to H'60 by a reset.
Rev. 2.0, 11/ 00, page 505 of 1037
Bit 7: Transmit End Interrupt Request Fl ag (TEI)
Indicates that data transmission or reception has been completed.
Bit 7
TEI Description
0 [Clearing condition] (Init ial value)
When 0 is written after r eading 1
1 [Set t ing condition]
When tr ansm ission or recept ion has been com pleted
Bits 6 and 5: Reserved
When each bit is read, 1 is read at all times. Writes are disabled.
Bit 4: Extension Data Bit (SOL)
The SOL sets the output level of the SO2 pin. When read, the output level of the SO2 pin is
read. Output of the SO2 pin after completion of transmission retains the value of final bit of
transfer data, but the output level of the SO2 pin can be changed by operating this bit before or
after transmission. However, setting of the SOL bit becomes invalid when the next transmission
is started. Therefore, if the output level of the SO2 pin is changed after completion of
transmission, write operation for SOL must be performed every time when transmission is
terminated. Since writing to this register during data transfer may cause malfunction, write
operati on m ust not be pe rforme d duri ng tra nsmi ssion.
Bit 4
SOL Description
Read The SO2 pin output is at a low level ( Initial value)0
Write The SO2 pin output is changed t o a low level
Read The SO2 pin output is at a high level1
Write The SO2 pin output is changed t o a high level
Rev. 2.0, 11/ 00, page 506 of 1037
Bit 3: Over r un Error F l ag (ORER)
The ORER indicates an occurrence of overrun error while an external clock is used. When
excessive pulses are overlapped with the normal transfer clock caused by external noise, etc.
during transmission, this bit is set to 1. At this time data transfer cannot be assured. When a
clock is input after completion of transmission, it is also found to be in the state of overrun and
this bit is set to 1. However, overrun is not detected when the
&6
pin is at a high level.
Bit 3
ORER Description
0 [Clearing condition] (Init ial value)
When 0 is written after r eading 1
1 [Set t ing condition]
When excessive pulses are overlapped with a normal tr ansf er clock while an
external clock is used, or when a clock is input after completion of tr ansm ission
Bit 2: Wait Fl ag (WT)
The WT indicates that read/ or write to serial data buffer (32 bytes) has been executed during
transmission and in the
&6
input standby mode. The instruction at that time is ignored and this
bit is set to 1.
Bit 2
WT Description
0 [Clearing condition] (Init ial value)
When 0 is written after r eading 1
1 [Set t ing condition]
When an instruct ion t o r ead/ wr ite to serial data buf f er ( 32 bit s) is direct ed dur ing
transm ission and in the
&6
input standby m ode
Bit 1: Abort Flag (ABT)
The ABT indicates that the
&6
pin has ente re d a hi gh l eve l during t ra nsmission. Whe n a high
level of the
&6
pin is detected during transfer, the transfer is immediately cut off, and this bit is
set to 1, and then the SCK2 and SO2 pins go into the high impedance state. At this time values
of internal registers other than SCSR2 and serial data buffer (32 bytes) are retained. Transfer
cannot be carried out while this bit is set to 0. Resume transfer after clearing to 0.
Bit 1
ABT Description
0 [Clearing condition] (Init ial value)
When 0 is written after r eading 1
1 [Set t ing condition]
During transf er and when
&6
pin has entered a high level
Rev. 2.0, 11/ 00, page 507 of 1037
Bit 0: Start Flag (STF)
The STF control s the start of t ransfer ope ra ti ons. W he n thi s bit is set t o 1 a nd PMR30 of PMR3
is 0, tra nsfer opera t ion of t he SCI2 is starte d. W hen PMR30 of PMR3 is 1, the l ow leve l of the
&6
pin is detected and transfer is started. This bit retains 1 during transfer and in the
&6
input
standby mode, and it is cleared to 0 after completion of transfer and when transfer is cut off by
the
&6
pin. Therefore, this bit can be used as a busy flag. When this bit is cleared to 0 during
transfer, the transfer is cut off and the SCI2 is initialized. At this time the contents of internal
registers other than the SCR2 and the serial data buffer (32 bytes) are retained.
Bit 0
STF Description
Read Transf er operations stops (Initial value)0
Write Transf er oper at ion discontinues and the SCI2 is initialized
Read During tr ansf er oper ation or in
&6
input standby m ode1
Write Transfer oper at ion star t s
24. 2 .5 Module St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode
control. When the MSTPCR is set to 1, the SCI2 stops at the end of bus cycle and a transition is
made to the module stop mode. For details, see section 4.5 Module Stop Mode.
The MSTPCR is initialized to H'FFFF by a rese t .
Bit 7: Module Stop (MSTP7)
Specifies the SCI2 module stop mode.
MSTPCRL
Bit 7
MSTP7 Description
0 SCI2 module stop m ode is cleared
1 SCI2 module stop m ode is set ( I nit ial value)
Rev. 2.0, 11/ 00, page 508 of 1037
24.3 Operation
The SCI2, comprising 32 bytes serial data buffer, can continuously transmit a maximum of 32
bytes data by a single operation, synchronized with clock pulse. Installation of a register enables
to select transmit, receive, or simultaneous transmit/receive. When transmit is set, the value of
serial data buffer is retained even after completion of transmission.
An internal or external clock can be selected as transfer clock. When an internal clock is
selected, data can be transmitted at 1-byte intervals. The strobe signal can also be output from
the STRB pin. When an external clock is selected, malfunction due to clock can be detected by
the overrun fl a g.
The start of transfer and its forced cutoff can be controlled by
&6
input. Forced c ut off ca n be
detected by the abort flag.
24.3.1 Clock
Selection of a transfer clock can be made from seven internal clocks and an external clock.
When an internal clock is selected, the SCK2 pin becomes a clock output pin.
24.3.2 Data Transfer F ormat
Figures 24.2 and 24.3 show transfer format of the SCI2.
LSB-first transfer that allows to transmit/receive from the lowest-order bit of data is performed.
Transmit data is output from the fall of the transfer clock to its next fall. Receive data is
collected at the rise of the transfer clock.
When an internal clock is selected as a transfer clock, data can be transferred at intervals of 1
byte. The SCK2 output is retained at a high level between transfer data. The strobe signal can
be output from t he STRB pi n.
Selection of interval of transfer data is set at GAP1 o r GAP0 .
Rev. 2.0, 11/ 00, page 509 of 1037
SO2/SI2
SCK2
Start of transfer
Bit 0
End of transfer
CS
STRB
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 24. 2 Tr ansfer F ormat (Tr ansfer Data without Intervals)
Rev. 2.0, 11/ 00, page 510 of 1037
SO2/SI2
SCK2
Start of transfer
8, 24, and 56 clocks
Bit 0
End of transfer
CS
STRB
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 24. 3 Tr ansfer F ormat (Tr ansfer Data with Intervals)
Rev. 2.0, 11/ 00, page 511 of 1037
24.3.3 Data Transfer Operati ons
(1) SCI2 Initialization
To carry out data transfer, first initialize the SCI2 using software. Initialization is performed
as described be l ow:
(1) Use PMR2, PMR3, STAR, E DAR and SCR2 to set the pi n and t ra nsmission mode whil e
STF of SC SR2 i s set t o 0.
(2) The SCI2 pin is also used as a port. Switching of a port is performed on PMR.
The SO2 pin allows to select CMOS out p u t o r NMOS o p e n dr a in ou t p u t o n PMR 2 .
Transfer clock and transfer data intervals can be set on SCR2.
(3) The starting and ending addresses in the transfer data area are set on STAR and EDAR.
If the value of the ending address is smaller than that of the starting address, transfer data
at H' FFD0DF a nd t he n re turn t o H' FFD0C0 so t ha t t ra nsfe r t o t h e e ndi ng a ddre ss c a n be
carrie d out as shows in figure 24. 4. If the va lue of t he sta rt ing a ddre ss is equal t o t hat of
the endi ng a ddress is equal , pe rform one -byt e t ra nsfer.
End
H' FFD0C0
Ending address
Starting address
H' FFD0DF
Start
Figure 24.4 If The Value of The Ending Address is Smaller Than That of
The Starting Address
Rev. 2.0, 11/ 00, page 512 of 1037
(2) Transmit Operations
Transmit operations are performed as described below:
(1) Set PMR26 and PMR27 of PMR2 to 1 a nd set t he m t o t he SO2 and SCK2 pins,
respectively.
Set the SO2 pin to t he open dra i n output using PMR20 of PMR2 and set them to t he
&6
and STRB pins, respectively, using PMR30 and PMR31 of PMR3, as necessary.
(2) Set the transfer clock and transfer data intervals (only when an internal clock is in
operation) by setting SCR2.
(3) Write transmit data to serial data buffer. In transmit operations, the contents of the data
buffer will be retained even after the end of transmission. When the same data is
transmitted again, it is not necessary to write data.
(4) Set STAR to the 5 l ow-order bi ts at t he t ra nsmission start i ng addre ss and EDAR to the 5
low-order bits at t he t ra nsmission endi ng a ddress.
(5) Set STF to 1. When PMR30 of PMR3 is set to 0, transmission is started by setting STF.
While PMR30 of PMR3 is set to 1, transmission is started when low level of the
&6
pin is
detected.
(6) After completion of transmission, TEI of SCSR2 is set to 1. STF is cleared to 0.
When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of
starting transmission. When transmission has been completed, synchronous clock is not output
until the next STF is set. During that time, the SO2 pin continues to output the value of final bit
of the immediately preceding data.
When an external clock is selected, data is transmitted, synchronized with the clock input from
the SCK2 pin. If the synchronous clock is continuously input after completion of transmission,
no transmission is performed as the overrun state has been found and then ORER of the SCSR2
is set to 1. The SO2 pin continues to retain the value of final bit of the preceding data.
However, if the
&6
of PMR3 is set to 1, overrun is not detected when the
&6
pin is at a hi gh
level.
The output value of the SO2 pin while transmission is being stopped can be changed by SOL of
SCSR2. Data buffer cannot be read or written from CPU during transmission or in the
&6
standby mode.
When a Read instruction has been executed, H'FF is read. Even if a Write instruction is
executed, buffer does not change. When a Read/Write instruction has been executed during
transmission or in the
&6
input standby m ode , WT of t he SCSR2 is set.
While PMR30 of PMR3 is set to 0, transmission is immediately cut off when a high level of the
&6
pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0.
The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may
not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to
0.
Rev. 2.0, 11/ 00, page 513 of 1037
(3) Receive Operations
Receive operations are performed as described below:
(1) Set PMR25 and PMR27 of PMR2 to 1 a nd set t he m t o t he SI2 and SCK2 pins,
respectively. Set them to the
&6
pin, using PMR30 of PMR3 as necessary.
(2) Set the transfer clock and transfer data intervals (only when an internal clock is in
operation) by setting SCR2.
(3) Set STAR to 5 low-order bits at the receive starting address and EDAR to 5 low-order
bits at the receive ending address. This enables to determine the area in the serial data
buffer where receive data is stored.
(4) Set STF to 1. When PMR30 of PMR3 is set to 0, reception is started by setting STF.
While PMR30 of PMR3 is set to 1, reception is started when low level of the
&6
pin is
detected.
(5) After completion of reception, TEI of SCSR2 is set to 1. STF is cleared to 0.
(6) Read the receive data stored from the serial data buffer.
When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of
starting reception. When reception has been completed, synchronous clock is not output until
the next STF is set.
When an external clock is selected, data is received, synchronized with the clock input from the
SCK2 pin. If the synchronous clock is continuously input after completion of reception, no
reception is performed as the overrun state has been found and then ORER of the SCSR2 is set
to 1. However, if the
&6
of PMR3 is set to 1, overrun is not detected when the
&6
pin is at a
high level.
Data buffer cannot be read or written from CPU during reception or in the
&6
standby mode.
When a Read instruction has been executed, H'FF is read. Even if a Write instruction is
executed, buffer does not change. When a Read/Write instruction has been executed during
reception or in the
&6
input standby m ode , WT of t he SCSR2 is set.
While
&6
of PMR3 is set to 1, transmission is immediately cut off when a high level of the
&6
pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0.
The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may
not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to
0.
Rev. 2.0, 11/ 00, page 514 of 1037
(4) Simultaneous Transmit/Receive Operations
Simultaneous transmit/receive operations are performed as described below:
(1) Set PMR25, PMR26 and PMR27 of PMR2 to 1 and set t hem t o the SI2, SO2 and SCK2
pins, respectively.
Set the SO2 pin to ope n dra in out put , using PMR20 of PMR2, and set the m t o t he
&6
and
STRB pins, respectively, using PMR30 and PMR31, as necessary.
(2) Set the transfer clock and transfer data intervals (only when an internal clock is in
operation) by setting SCR2.
(3) Write transmit data to serial data buffer. In the simultaneous transmit/receive operations,
the receive data is stored in the same address alternately with the transmit data.
(4) Set STAR to 5 low-order bit s at the t ransmi ssion start ing a ddre ss and EDAR to 5 low-
order bits at t he t ra nsmission endi ng a ddress.
(5) Set STF to 1. When PMR30 of PMR3 is set to 0, transmission is started by setting STF.
While PMR30 of PMR3 is set to 1, transmission is started when low level of the
&6
pin is
detected.
(6) After completion of transmission, TEI of SCSR2 is set to 1. STF is cleared to 0.
(7) Read the receive data stored from the serial data buffer.
When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of
starting transmission. When transmission has been completed, synchronous clock is not output
until the next STF is set. During that time, the SO2 pin continues to output the value of final bit
of the preceding data.
When an external clock is selected, data is transmitted, synchronized with the clock input from
the SCK2 pin. If the synchronous clock is continuously input after completion of transmission,
no transmission is performed as the overrun state has been found and then ORER of the SCSR2
is set to 1. The SO2 pin continues to retain the value of final bit of the preceding data.
However, if the CS of PMR3 is set to 1, overrun is not detected when the
&6
pin is at a hi gh
level.
The output value of the SO2 pin while transmission is being stopped can be changed by SOL of
SCSR2. Data buffer cannot be read or written from CPU during transmission or in the
&6
standby mode. When a Read instruction has been executed, H'FF is read. Even if a Write
instruction is executed, buffer does not change. When a Read/Write instruction has been
execut e d during t ra nsmission or in t he
&6
input standby m ode , WT of t he SCSR2 is set.
While the CS of PMR3 is set to 1, transmission is immediately cut off when a high level of the
&6
pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0.
The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may
not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to
0.
Rev. 2.0, 11/ 00, page 515 of 1037
24.4 Interrupt S ou rces
An interrupt source of the SCI2 is transmission cutoff by completion of transmission and the
&6
pin, t o which di ffe rent ve ct or a ddresses are a ssigned.
On completion of data transfer, TEI of SCSR2 is set to 1, and transfer-end interrupt request is
generated. This interrupt can specify enable/disable by setting TEIE of SCR2.
While PMR30 of PMR3 is set to 1, transfer is cut off when the
&6
pin ente rs a hi gh le ve l duri ng
data transfer, and ABT of SCSR2 is set to 1 and then transfer cutoff interrupt request is
generated.
This interrupt can specify enable/disable by setting ABTIE of SCR2. In the case of transfer
cutoff by the
&6
pin, overrun error, and read/write to serial data buffer during transfer and in the
&6
standby mode, ABT, ORER, and WT of the SCSR2 is set to 1, respectively. These bits
allow to determine error factors.
Rev. 2.0, 11/ 00, page 516 of 1037
Rev. 2.0, 11/ 00, page 517 of 1037
Section 25 I2C Bus In terface (IIC)
25.1 Overview
The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inte r-IC bus)
interface functions. The register configuration that controls the I 2C bus differs part l y from t he
Philips configuration, however.
Each I2C bus interface channel uses only one data line (SDA) and on e clo c k l ine ( SC L ) t o
transfer data, saving board and connector space.
25.1.1 Features
• Selection of addressing format or non-addressing format
— I2C bus format: addressing format with acknowledge bit, for master/slave operation
— Serial format: non-addressing format without acknowledge bit, for master operation only
• Conforms to Philips I2C bus interface (I2C bus format)
• Two ways of setting slave address (I 2C bus format)
• Start and stop conditions generated automatically in master mode (I2C bus format)
• Selection of acknowledge output levels when receiving (I2C bus format)
• Automatic loading of acknowledge bit when transmitting (I2C bus format)
• Wait function in master mode (I2C bus format)
— A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode (I2C bus format)
— A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three int e rrupt source s
— Data transfer end (including transmission mode transition with I2C bus format and address
reception after loss of master arbitration)
— Address match: when any slave address matches or the general call address is received in
slave receive mode (I2C bus format)
— Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (with SCL and SDA pin s)
— Two pins-P24/SCL a nd P23/ SDA- (normally CMOS pins) functi on a s NMOS-only
outputs when the bus drive function is selected.
Rev. 2.0, 11/ 00, page 518 of 1037
25.1.2 Block Diagram
Figure 25.1 shows a block di agra m of the I2C bus interface.
Figure 25.2 shows an example of I/O pin connections to external circuits. I/O pins are driven
only by NMOS and a ppa re ntl y fun c t ion a s NMOS ope n-drai n out put s. Howe ve r, a pplicable
voltages to input pins depend on the power (Vcc) voltage of this LSI.
SCL
PS
Noise
canceller
Bus state
decision
circuit
Output data
control
circuit
ICCR
Clock
control ICMR
ICSR
ICDRS
Address
comparator
Arbitration
decision
circuit
SAR, SARX
SDA
Noise
canceler
Interrupt
generator Interrupt
request
Internal data bus
[Legend]
ICCR
ICMR
ICSR
ICDR
SAR
SARX
PS
: I2C control register
: I2C mode register
: I2C status register
: I2C data register
: Slave address register
: Slave address register X
: Prescaler
ICDRR
ICDRT
Figure 25. 1 Bl oc k Diagram of I2C Bus Inter fa c e
Rev. 2.0, 11/ 00, page 519 of 1037
V
CC
SCL
in
SCL
out
SCL
SDA
in
SDA
out
(Master)
This chip
SDA
SCL
SDA
SCL
in
SCL
out
SCL
SDA
in
SDA
out
(Slave 1)
SDA
SCL
in
SCL
out
SCL
SDA
in
SDA
out
(Slave 2)
SDA
V
CC
Figure 25.2 I2C Bus Interface Connections (Example: This Chip as M aster)
25.1.3 Pin Configuration
Table 25.1 summarizes the input/output pins used by the I2C bus interface.
Table 25.1 I2C Bus Interfa c e Pins
Name Abbrev. I/O Function
Serial clock pin SCL I/O IIC serial clock input/out put
Serial data pin SDA I/ O II C serial data input / out put
Rev. 2.0, 11/ 00, page 520 of 1037
25.1.4 Register Configuration
Table 25.2 summarizes the registers of the I2C bus interface.
Table 25.2 Register Configuration
Name Abbrev. R/W I ni tial Value Address*1
I2C bus control regist er ICCR R/W H'01 H'D158
I2C bus status r egister I CSR R/W H'00 H'D159
I2C bus data register ICDR R/W — H'D15E*2
I2C bus mode register ICMR R/W H'00 H'D15F*2
Slave address register SAR R/ W H'00 H'D15F*2
Second slave address register SARX R/W H'01 H'D15E*2
Serial timer cont r ol r egister STCR R/W H'00 H'FFEE
MSTPCRH R/W H'FF H'FFECModule stop cont r ol register
MSTPCRL R/W H'FF H'FFED
Notes: 1. Lower 16 bits of the addr ess.
2. The register t hat can be wr itt en or r ead depends on the ICE bit in the I2C bus contr ol
register. The slave address register can be accessed when ICE = 0, and t he I2C bus
mode regist er can be accessed when ICE = 1.
Rev. 2.0, 11/ 00, page 521 of 1037
25.2 Register Descript ion s
25.2.1 I2C Bus Data Re gi ste r (ICDR)
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
Bit :
Initial value :
R/W :
ICDRR
7
ICDRR7
—
R
6
ICDRR6
—
R
5
ICDRR5
—
R
4
ICDRR4
—
R
3
ICDRR3
—
R
0
ICDRR0
—
R
2
ICDRR2
—
R
1
ICDRR1
—
R
Bit :
Initial value :
R/W :
ICDRS
7
ICDRS7
—
—
6
ICDRS6
—
—
5
ICDRS5
—
—
4
ICDRS4
—
—
3
ICDRS3
—
—
0
ICDRS0
—
—
2
ICDRS2
—
—
1
ICDRS1
—
—
Bit :
Initial value :
R/W :
ICDRT
7
ICDRT7
—
W
6
ICDRT6
—
W
5
ICDRT5
—
W
4
ICDRT4
—
W
3
ICDRT3
—
W
0
ICDRT0
—
W
2
ICDRT2
—
W
1
ICDRT1
—
W
Bit :
Initial value :
R/W :
TDRE, RDRF (Int e r na l f l a g )
—
RDRF
0
—
—
TDRE
0
—
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 522 of 1037
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read
or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF.
After transmission/reception of one frame of data using ICDRS, if the I2C bus is in transmit
mode and the next data is in ICDRT (the TDRE flag is 0), data is transferred automatically from
ICDRT to ICDRS. After transmission/reception of one frame of data using ICDRS, if the I2C
bus is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0), data is
transferred automatically from ICDRS to ICDRR.
Rev. 2.0, 11/ 00, page 523 of 1037
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the
LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS
= 1.
ICDR is assigned to the same address as SARX, and can be written and read only when the ICE
bit is set t o 1 i n ICCR.
The val ue of ICDR is undefine d a fte r a reset .
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
TDRE Description
0 The next t r ans m it dat a is in I CDR (ICDRT) , or t ransmiss ion cannot be start e d
[Clearing conditions] (Initial value)
(1)When t r ans m it data is wr it ten in ICDR (ICDRT) in trans m it mode (TRS = 1)
(2)W hen a st op condition is detect ed in the bus line stat e af t er a stop condition is
issued with the I2C bus format or serial format selected
(3)W hen a st op condit ion is detect ed with t he I2C bus format selected
(4)In receive mode ( TRS = 0)
(A 0 write t o TRS during tr ansf er is valid after r eception of a fr am e containing an
acknowledge bit)
1 Th e n e x t t r a n s mit da ta c an b e wr itt e n in ICDR ( ICDRT)
[Sett ing conditions]
(1)In tr ansm it m ode ( TRS = 1), when a star t condition is detected in t he bus line
state after a st ar t condit ion is issued in master m ode with the I2C bus format or
serial format selected
(2)When dat a is t r ans ferr ed from ICDRT to ICDRS
(Data trans f e r from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS
is empty)
(3)W hen a switch is made from r eceive mode ( TRS = 0) t o t r ansm it m ode ( TRS = 1)
aft er det ect ion of a start condition
RDRF Description
0 Th e d a ta in ICDR ( ICDRR) is in v a lid (Init ia l v a lu e)
[Clearing condition]
When ICDR (ICDRR) rec eive data is r ead in r ec eiv e m ode
1 Th e ICDR ( ICDRR) rece iv e da ta c an b e r e a d
[Sett ing condition]
When data is t ransf er red from I CDRS to I CDRR
(Data tra n sfer from ICDRS t o ICDRR in ca s e o f norma l ter mination with TRS = 0
and RDRF = 0)
Rev. 2.0, 11/ 00, page 524 of 1037
25. 2 .2 Slave Addr e ss Regi st e r ( SAR)
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Bit :
Initial value :
R/W :
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected),
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start
condition, the chip operates as the slave device specified by the master device. SAR is assigned
to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0
in ICCR.
SAR is initialized to H'00 by a reset.
Bit s 7 to 1 : Slav e Addr ess (SVA6 t o SVA0)
Set a uni que addre ss i n bi t s SVA6 to SVA0, diffe ri ng from t he a ddre sse s of ot her sl a ve de vices
connected to the I2C bus.
Rev. 2.0, 11/ 00, page 525 of 1037
Bit 0: Format Select (FS)
Used tog e t h e r wi th t h e FSX b i t in SARX to select the communication format.
•I2C bus format: addressing format with acknowledge bit
•Synchronous serial format: non-addressing format without acknowledge bit, for master
mode only
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode.
SAR
Bit 0
SARX
Bit 0
FS FSX Operat i ng Mode
0I
2C bus format
• SAR and SARX slave addresses recognized
0
1I
2C bus form at ( Init ia l v a lu e)
• SAR slave addr ess r ecognized
• SARX slave address ignored
0I
2C bus format
• SAR slave addr ess ignored
• SARX slave address r ecognized
1
1 Clock synchronous serial form at
• SAR and SARX slave addresses ignored
Rev. 2.0, 11/ 00, page 526 of 1037
25. 2 .3 Sec o nd Sl a v e Addr ess Reg i st e r (SARX)
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
Bit :
Initial value :
R/W :
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected),
if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start
condition, the chip operates as the slave device specified by the master device. SARX is
assigned to the same address as ICDR, and can be written and read only when the ICE bit is
cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bit s 7 to 1 : Sec ond Slave Address (SVAX6 t o SVAX0)
Set a uni que addre ss i n bi t s SVAX6 to SVAX0, diffe ri ng from t he a ddre sse s of ot her sl a ve
devices connected to the I2C bus.
Bit 0: Format Select X (FSX)
Used together with the FS bit in SAR to select the communication format.
• I2C bus format: addressing format with acknowledge bit
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
The FSX bi t also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in SAR.
Rev. 2.0, 11/00, page 527 of 1037
25.2.4 I2C Bus Mode Register (ICMR)
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
Bit :
Initial value :
R/W :
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency
and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written
and read onl y when t he ICE bi t i s set t o 1 in ICCR.
ICMR is initialized to H'00 by a reset.
Bit 7: MSB-First/LSB-First Select (MLS)
Selects whether data is transferred MSB-first or LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the
LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS
= 1.
Do not set this bit to 1 when the I2C bus format is used.
Bit 7
MLS Description
0 MSB-first (Initial v a lue )
1 LSB-first
Rev. 2.0, 11/ 00, page 528 of 1037
Bit 6: Wait Insertion Bit (WAIT)
Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master
mode with the I2C bus format. When WAIT is set to 1, after the fall of the clock for the final
data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is
transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively
with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of
the WAIT setting.
The setting of this bit is invalid in slave mode.
Bit 6
WAIT Description
0 Data and acknowledge bits transf er r ed consecut ively (Initial value)
1 Wait insert ed bet ween dat a and acknowledge bits
Rev. 2.0, 11/ 00, page 529 of 1037
Bits 5 to 3: Transfer Clock Select (CKS2 to CKS0)
These bits, together with the IICX bit in the STCR register, select the serial clock frequency in
master mode. They should be set according to the required transfer rate.
STCR
Bit 6 Bit 5 Bit 4 Bit 3 Transfer Rate
IICX CKS2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz
0φ/28 179 kHz 286 kHz 357 kHz0
1φ/40 125 kHz 200 kHz 250 kHz
0φ/48 104 kHz 167 kHz 208 kHz
0
1
1φ/64 78. 1 kHz 125 kHz 156 kHz
0φ/80 62. 5 kHz 100 kHz 125 kHz0
1φ/100 50.0 kHz 80.0 kHz 100 kHz
0φ/112 44.6 kHz 71.4 kHz 89.3 kHz
0
1
1
1φ/128 39.1 kHz 62.5 kHz 78.1 kHz
0φ/56 89. 3 kHz 143 kHz 179 kHz0
1φ/80 62. 5 kHz 100 kHz 125 kHz
0φ/96 52. 1 kHz 83. 3 kHz 104 kHz
0
1
1φ/128 39.1 kHz 62.5 kHz 78.1 kHz
0φ/160 31.3 kHz 50.0 kHz 62.5 kHz0
1φ/200 25.0 kHz 40.0 kHz 50.0 kHz
0φ/224 22.3 kHz 35.7 kHz 44.6 kHz
1
1
1
1φ/256 19.5 kHz 31.3 kHz 39.1 kHz
Rev. 2.0, 11/ 00, page 530 of 1037
Bits 2 to 0: Bit Counter (BC2 to BC0)
Bits BC2 to BC0 specify the number of bits to be transferred next. With the I2C bus forma t
(whe n t h e FS b i t in SAR or t h e FSX b i t in SAR X i s 0 ), t he data is transferred with one addition
acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer
frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while
the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
Bit 2 Bit 1 Bit 0 Bits/Frame
BC2 BC1 BC0 Synchr onous Ser i al Form a t I2C Bus For m a t
0 8 9 (Init ial value)0
11 2
02 3
0
1
13 4
04 50
15 6
06 7
1
1
17 8
Rev. 2.0, 11/ 00, page 531 of 1037
25.2.5 I2C Bus Co nt r o l Re g i st e r (ICCR)
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables
or disables interrupts, selects master or slave mode and transmission or reception, enables or
disables acknowledgement, confirms the I2C bus interface bus status, issues start/stop conditions,
and performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset.
Bit 7: I2C Bus Inte r f a c e E na bl e ( ICE )
Selects whether or not the I2C bus interface is to be used. When ICE is set to 1, port pins
functi on a s SCL a nd SDA i nput /out put pi ns a nd t ra nsfe r ope rations are enabled. When ICE is
cleared to 0, the I2C bus interface module is disabled, and the internal state is initialized.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers
can be accessed when ICE is 1.
Bit 7
ICE Description
0I
2C bus interface m odule disabled, with SCL and SDA signal pins set t o por t function
SAR and SARX can be accessed. The inter nal st at e of the I 2C bus inter f ace m odule
is initialize d . (Init ia l v a lu e)
1I
2C bus interface m odule enabled for t ransfer oper at ions ( pins SCL and SCA are
driving the bus)
ICMR and I CDR c an be acce ss ed
Bit 6: I2C Bus Inte r f a c e Int e rr upt E na bl e ( IE IC)
Enable s or disabl es int e rrupts from t he I2C bus interface to the CPU.
Bit 6
IEIC Description
0 Int er r upts disabled (Init ial value)
1 Int er r upts enabled
Rev. 2.0, 11/ 00, page 532 of 1037
Bit 5: Master/Slave Select (MST)
Bit 4: Transmit/Receive Select (TRS)
MST selects whether the I2C bus interface operates in master mode or slave mode.
TRS selects whether the I2C bus interface operates in transmit mode or receive mode.
In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0 ), ha r d wa r e a u t o matically selects transmit or receive mode according
to the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
Bit 5 Bit 4
MST TRS Description
0 Slave receive mode (Init ial value)0
1 Slave transmit m ode
0 Mast er r eceive mode1
1 Mast er t r ansm it m ode
Bit 5
MST Description
0 Slave mode (Init ial value)
[Clearing conditions]
(1)W hen 0 is written by soft war e
(2)W hen bus ar bitr ation is lost after transm ission is start ed in I2C bus format master
mode
1 Mast er m ode
[Sett ing conditions]
(1)W hen 1 is writt en by sof t war e ( in cases other than clearing condition 2)
(2)W hen 1 is written in MST aft er r eading M ST = 0 (in case of clearing condition 2)
Rev. 2.0, 11/ 00, page 533 of 1037
Bit 4
TRS Description
0 Receive mode (Init ial value)
[Clearing conditions]
(1)W hen 0 is written by soft war e ( in cases other than sett ing condition 3)
(2)W hen 0 is written in TRS after r eading TRS = 1 (in case of set ting condition 3)
(3)W hen bus ar bitr ation is lost after transm ission is start ed in I2C bus format master
mode
1 Transm it m ode
[Sett ing conditions]
(1)W hen 1 is writt en by sof t war e ( in cases other than clearing conditions 3)
(2)W hen 1 is written in TRS after r eading TRS = 0 (in case of clearing conditions 3)
(3)W hen a 1 is r eceived as the R/ W bit of the first fr am e in I 2C bus format slave
mode
Bit 3: Acknowledge Bit Judgement Selection (ACKE)
Specifies whether the value of the acknowledge bit returned from the receiving device when
using the I2C bus format is to be ignored and continuous transfer is performed, or transfer is to be
aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is
0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always
0.
When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data
transmission, rega rdl ess of the va l ue of t he ac knowle dge bi t . Whe n t he ACKE bit i s 1, t he
TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge
bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge
bit is 1.
Depending on the receiving device, the acknowledge bit may be significant, in indicating
completion of processing of the received data, for instance, or may be fixed at 1 and have no
significance.
Bit 3
ACKE Description
0 The value of the acknowledge bit is ignored, and continuous transfer is perf ormed
(Init ial value)
1 If t he acknowledge bit is 1, continuous transf er is interr upt ed
Rev. 2.0, 11/ 00, page 534 of 1037
Bit 2: Bus Busy (BBSY)
The BBSY flag can be read to check whether the I2C b u s (SC L , SDA) i s b u sy o r fr e e. In m aster
mode, this bit is also used to issue start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA wh ile SCL is high is recognized as a stop
condition, clearing BBSY to 0.
To issue a start c o n dition , u se a MOV in st r u ction to write 1 in BBSY and 0 in SCP. A
retransmit start condition is issued in the same way. To issue a stop condition, use a MOV
instruction to write 0 in BBSY and 0 in SCP.
It is not possible to write to BBSY in slave mode; the I2C bus interface must be set to master
transmit mode before issuing a start condition. MST and TRS should both be set to 1 before
writing 1 in BBSY and 0 in SCP.
Bit 2
BBSY Description
0 Bus is free (Init ial value)
[Clearing condition]
When a stop condition is detected
1 Bus is busy
[Sett ing condition]
When a star t condition is detect ed
Bit 1: I2C Bus Inte r f a c e Int e rr upt Request F lag ( IRIC)
Indicates that the I2C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at
the end of a data transfer, when a slave address or general call address is detected in slave
receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is
detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in
ICMR. See section 25.3.6, IRIC Setting Timing and SCL Control. The conditions under which
IRIC is set also differ depending on the setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
When the DTC is used, IRIC is cleared automatically and transfer can be performed
continuously wit hout CPU interve nt ion.
Rev. 2.0, 11/ 00, page 535 of 1037
Bit 1
IRIC Description
0 Waiting for transf er , or transf er in progr ess (Init ial value)
[Clearing condition]
(1)W hen 0 is written in IRIC after r eading IRI C = 1
1 Int er r upt request ed
[Sett ing conditions]
I2C bus format m aster mode
(1)W hen a st ar t condition is detect ed in t he bus line state af ter a st ar t condition is
issued
(when the TDRE flag is set to 1 because of first f r am e t r ansm ission)
(2)W hen a wait is insert ed bet ween t he dat a and acknowledge bit when WAIT = 1
(3)At t he end of data tr ansf er
(at t he r ise of t he 9t h t r ansm it clock pulse, and at t he fall of the 8th
transm it / r eceive clock pulse when a wait is inserted)
(4)W hen a slave address is received af t er bus ar bitr at ion is lost
(when the AL flag is set to 1)
(5)W hen 1 is r eceived as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
I2C bus format slave m ode
(1)When t he slave addr es s ( SVA, SVAX) m atches
(when the AAS and AASX flags are set to 1)
and at the end of data t r ansf er up t o t he subsequent r et r ansm ission star t
condition or stop condit ion detect ion
(when the TDRE or RDRF flag is s et to 1)
(2)W hen t he gener al call address is detected
(when FS = 0 and the ADZ flag is set to 1)
and at the end of data t r ansf er up t o t he subsequent r et r ansm ission star t
condition or stop condit ion detect ion
(when the TDRE or RDRF flag is s et to 1)
(3)W hen 1 is r eceived as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
(4)W hen a st op condit ion is detect ed
(when the STOP or ESTP flag is set to 1)
Synchronous serial form at
(1)At t he end of data tr ansf er
(when the TDRE or RDRF flag is s et to 1)
(2)W hen a st ar t condition is detect ed with ser ial form at select ed
When condit ions ar e occ ur ed s uch that the TDRE or RDRF f lag is s et to 1
Rev. 2.0, 11/ 00, page 536 of 1037
When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding fla g, c aut i on is nee de d at t he e nd of a tra nsfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
The IRTR flag (the DTC* start request flag) is not set at the end of a data transfer up to
detection of a retransmission start condition or stop condition after a slave address (SVA) or
general call address match in I2C bus format slave mode.
Even when the IRIC fl ag a nd IRT R fla g a re set , t he T DRE or RDRF inte rnal fl ag m a y not be set .
The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in
continuous transfer using the DTC*. The TDRE or RDRF flag is cleared, however, since the
specified number of ICDR reads or writes have been completed.
Table 25.3 shows the relationship between the flags and the transfer states.
Note: * This LSI does not incorporate DTC.
Rev. 2.0, 11/ 00, page 537 of 1037
Table 25.3 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State
1/01/0000000000Idle state (flag clearing
required)
11000000000Start condition
issuance
11100100000Start condition
established
11/0100000000/1Master mode wait
11/0100100000/1Master mode
transmit/receive end
0010001/011/01/00Arbitration lost
00100000100SAR match by first
frame in slave mode
00100000110General call address
match
00100010000SARX match
01/0100000000/1Slave mode
transmit/receive end
(except after SARX
match)
0
01/0
11
10
00
01
01
10
00
00
00
1Slave mode
transmit/receive end
(after SARX m atch)
01/001/01/0000000/1Stop condition detected
Bit 0: Start Condition/Stop Condition Pr ohibit (SCP)
Controls the issuing of start and stop conditions in master mode. To issue a start condition, write
1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop
condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is
not stored.
Bit 0
SCP Description
0 Wr it ing 0 issues a st art or s t op c ondit ion, in c om bination with t he BBSY flag
1 Reading always r et ur ns a value of 1 ( I nitial value)
Writing is ignored
Rev. 2.0, 11/ 00, page 538 of 1037
25.2.6 I2C Bus St a tus Regi st e r (ICSR)
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset.
Bit 7: Error Stop Condition Detection Flag (ESTP)
Indicates that a stop condition has been detected during frame transfer in I2C bus format slave
mode.
Bit 7
ESTP Description
0 No error st op condit ion (I nitial value)
[Clearing condition]
(1)W hen 0 is written in ESTP after r eading ESTP = 1
(2)W hen t he IRIC flag is cleared to 0
1
In I2C bus format slave mode
Error st op condit ion detect ed
[Sett ing condition]
• When a stop condition is detected during fr am e transf er
In ot her m odes
No meaning
Rev. 2.0, 11/ 00, page 539 of 1037
Bit 6: Normal Stop Condition Detection Flag (STOP)
Indicates that a stop condition has been detected after completion of frame transfer in I 2C bus
format slave mode.
Bit 6
STOP Description
0 No normal st op condition (Init ial value)
[Clearing condition]
(1)W hen 0 is written in STOP after reading STOP = 1
(2)W hen t he IRIC flag is cleared to 0
1
In I2C bus format slave mode
Error st op condit ion detect ed
[Sett ing condition]
• When a stop condition is detected aft er com plet ion of fram e t r ansf er
In ot her m odes
No meaning
Rev. 2.0, 11/ 00, page 540 of 1037
Bit 5: I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag
(IRTR)
Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is
completion of reception/transmission of one frame in continuous transmission/reception for
which DTC* activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1
at the same time.
IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared
automatically when the IRIC flag is cleared to 0.
Note: * This LSI does not incorporate DTC.
Bit 5
IRTR Description
0 Waiting for transf er , or transf er in progr ess (Init ial value)
[Clearing condition]
(1)When 0 is writt en in I RTR aft er reading IRTR = 1
(2)W hen t he IRIC flag is cleared to 0
1 Continuous transfer state
[Sett ing condition]
In I2C bus int er f ace slave mode
• When the TDRE or RDRF flag is s et to 1 when AASX = 1
In ot her m odes
• When the TDRE or RDRF flag is s et to 1
Rev. 2.0, 11/ 00, page 541 of 1037
Bit 4 : Sec ond Slave Address Recog ni t i o n F l a g (AASX)
In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start
condition matches bits SVAX6 to SVAX0 in SARX.
AASX is cleared by reading AASX afte r it h a s b e en se t to 1, t h e n writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX Description
0 Second slave address not recognized (Initial value)
[Clearing condition]
(1)When 0 is wr itten in AASX afte r r eading AASX = 1
(2)W hen a st ar t condition is detect ed
(3)In master mode
1 Second slave address recognized
[Sett ing condition]
• When the second slave address is detected in slave receive mode while FSX = 0
Bit 3: Arbitration Lost (AL)
This flag indicates that arbitration was lost in master mode. The I2C bus interface monitors the
bus. When two or more master devices attempt to seize the bus at nearly the same time, if the
I2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the
bus has been take n by a nothe r m aste r.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL Description
0 Bus arbitr at ion won (I nit ial value)
[Clearing conditions]
(1)When I CDR dat a is written (t r ans m it m ode) or r ead ( receive m ode)
(2)W hen 0 is written in AL after r eading AL = 1
1 Arbitration lost
[Sett ing conditions]
(1)If t he int er nal SDA and SDA pin disagree at t he r ise of SCL in master transm it
mode
(2)If t he int er nal SCL line is high at t he fall of SCL in master t r ansm it m ode
Rev. 2.0, 11/ 00, page 542 of 1037
Bit 2 : Slav e Addr ess Recogniti o n F l a g (AAS)
In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start
condition matches bits SVA6 to SVA0 in SAR, or i f t h e g e n e r a l call address (H'00) is detected.
AAS is cleared by reading AAS afte r it h a s b e en se t to 1, t h e n writing 0 in AAS. I n a d dition,
AAS is rese t a u t o matically by write access to ICDR in transmit mode, or read access to ICDR in
receive mode.
Bit 2
AAS Description
0 Slave address or general call address not r ecognized ( I nitial value)
[Clearing conditions]
(1)When I CDR dat a is written (t r ans m it m ode) or r ead ( receive m ode)
(2)When 0 is wr itten in AAS after reading AAS = 1
(3)I n m ast er m ode
1 Slave address or general call address recognized
[Sett ing condition]
• When the slave address or gener al call address is detected in slave receive mode
Bit 1: General Call Address Recognition Flag (ADZ)
In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start
condition is the general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition,
ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in
receive mode.
Bit 1
ADZ Description
0 Gener al call address not r ecognized (Initial value)
[Clearing conditions]
(1)When I CDR dat a is written (t r ans m it m ode) or r ead ( receive m ode)
(2)When 0 is writt en in ADZ aft er reading ADZ = 1
(3)I n m ast er m ode
1 Gener al call address recognized
[Sett ing condition]
•If t he gener al call address is detect ed when FSX = 0 or FS = 0 is selected in the
slave receive mode.
Rev. 2.0, 11/ 00, page 543 of 1037
Bit 0: Acknowledge Bit (ACKB)
Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns
acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been
received, the acknowledge data set in this bit is sent to the transmitting device.
When thi s bit is rea d, i n tra nsmi ssion (when TRS = 1), the va lue l oade d from the bus li ne
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
Bit 0
ACKB Description
0 Receive mode: 0 is output at acknowledge output t im ing (Initial value)
Transmit m ode: I ndicat es t hat the receiving device has acknowledged the data
(signal is 0)
1 Receive mode: 1 is output at acknowledge output t im ing
Transmit m ode: I ndicat es t hat the receiving device has not acknowledged the data
(signal is 1)
25.2.7 Serial/Timer Control Register (STCR)
7
—
0
—
6
IICX
0
R/W
5
IICRST
0
R/W
4
—
0
—
3
FLSHE
0
R/W
0
—
0
—
2
—
0
—
1
—
0
—
Bit :
Initial value :
R/W :
STCR is an 8-bit readable/writable register that controls the I2C bus interface operating mode.
STCR is initialized to H'00 by a reset.
Bit 7: Reserved
Bit 6: I2C Transfer Select (IICX)
This bit, together with bits CKS2 to CKS0 in ICMR of I2C, selects the transfer rate in master
mode. For details, see section 25.2.4, I2C Bus Mode Registe r (ICMR).
Rev. 2.0, 11/ 00, page 544 of 1037
Bit 5: I2C Controller Reset (IICRST)
This bit controls the initialization of the internal state of the I2C bus interface. When the I2C bus
interface operating mode is hung because of communications error, and the IICRST bit is then
set to 1, the I2C bus interface controller is initialized of the internal state, and this allows the
internal state of the I2C bus interface to be initialized without making port settings or initializing
registers.
For the detail, refer to section 25.3.9, Initialization of Internal State.
The initialization is continuous and the I2C bus interface cannot operate, when the IICST bit
remains set to 1. Therefore, be sure to clear the IICST bit after setting it.
Bit 5
IICRST Description
0I
2C bus in terf ac e c o ntr o lle r is n o t r es e t (Init ia l v a lu e)
1I
2C bus interface cont r oller is reset
Bits 3: Flash Memory Control Resister Enable (F LSHE)
This bit selects the control resister of the flash memory. For details, refer to section 7.3.4 or
8.5.5, Serial Timer Control Resister.
Bits 4 and 2 to 0: Reserved
Rev. 2.0, 11/ 00, page 545 of 1037
25. 2 .8 Mo dul e St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode cont rol .
When the corresponding bit in MSTPCR is set to 1, operation of the corresponding I2C module is
halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see
section 4.5, Module Stop Mode.
MSTPCR is initialized to H'FFFF by a reset. I t i s n o t i n itialized in standby mode.
MSTPCRL Bit 6: Module Stop (MSTP6)
Specifies I2C module stop mode.
MSTPCRL
Bit 6
MSTP6 Description
0I
2C module stop mode is cleared
1I
2C module stop mode is set ( I nit ial value) (Init ial value)
Rev. 2.0, 11/ 00, page 546 of 1037
25.3 Operation
25.3.1 I2C Bus Data Format
The I2C bus interface has serial and I2C bus formats.
The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figure
25.3. The first frame following a start condition always consists of 8 bits.
The serial format is a non-addressing format with no acknowledge bit. This is shown in figure
25.4.
Figure 25.5 shows the I2C bus timing.
The symbols used in figures 25.3 to 25.5 are explained in table 25. 4.
SASLA
7n
R/W DATA A
1
1m
111A/A
1P
1Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
S SLA
7n1 7
R/W A DATA
11
1m1
1A/A
1S
1SLA R/W
1
1m2
A
1DATA
n2 A/A
1P
1
Upper: Transfer bit count (n1 and N2 = 1 to 8)
Lower: Transfer frame count (m1 and m2 = 1 or above)
(a) FS = 0 or FSX = 0
(b) Start condition transmission, FS = 0 or FSX = 0
Figure 25.3 I2C Bus Data Formats (I2C Bus For mats)
S DATA
8n
DATA
1
1m
P
1Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
FS = 1 and FSX = 1
Figure 25.4 I2C Bus Data Format (Serial Format)
Rev. 2.0, 11/ 00, page 547 of 1037
SDA
SCL
S SLA R/W A
981-7 981-7 981-7
DATA A DATA A/A P
Figure 25.5 I2C B us T i m i ng
Table 25.4 I2C Bus Data Format Symbols
S Start condit ion. The master device drives SDA fr om high to low while SCL is hig
SLA Slave address, by which the master device selects a slave device
R/
:
Indicates t he direct ion of dat a transf er : f r om t he slave device to t he m ast er device
when R/
:
is 1, or f r om t he m ast er device t o t he slave device when R/
:
is 0
A Acknowledge. The r eceiving device (the slave in master t r ansm it m ode, or t he
master in mast er r eceive m ode) dr ives SDA low t o acknowledge a transfer
DATA Transfer r ed dat a. The bit length is set by bit s BC2 to BC0 in ICMR. The M SB-
first or LSB-first format is selected by bit MLS in ICMR
P Stop condition. The mast er device dr ives SDA from low to high while SCL is high
25.3.2 Master Transmit Operation
In I2C bus format master transmit mode, the master device outputs the transmit clock and
transmit data, and the slave device returns an acknowledge signal. The transmission procedure
and operations synchronize with the ICDR writing are described below.
[1] Set bit ICE i n ICCR to 1. Set bi ts MLS, W AIT, and CKS2 to CKS0 in ICMR, and bi t IICX
in STCR, according to the operating mode.
[2] Read the BBSY flag i n ICCR to c onfi rm t ha t t he bus is free.
[3] Set bits MST and TRS to 1 in ICCR to select master transmit mode.
[4] Write 1 to BBSY and 0 to SCP. This changes SDA from high t o l o w whe n SCL i s high, a n d
generates the start condition.
[5] Then IRIC and IRT R fl ags are set to 1. If t he IEIC bi t in ICCR ha s bee n set t o 1, a n int e rrupt
request is sent to the CPU.
[6] Write the data (slave address + R/
:
) to ICDR. After the start condition instruction has been
issued and the start conditon has been generated, write data to ICDR. If this procedure is not
followed, data may not be output correctly. With the I2C bus format (when the FS bit in SAR
or t h e FSX b i t in SAR X i s 0 ), t he fi r st f rame data following the start condition indicates the
7-bit slave address and transmit/receive direction. As indicating the end of the transfer, and
so the IRIC flag is cleared to 0. After writing ICDR, clear IRIC immediately not to execute
other interrupt handling routine. If one frame of data has been transmitted before the IRIC
Rev. 2.0, 11/ 00, page 548 of 1037
clearing, it can not be determine the end of transmission. The master device sequentially
sends the transmission clock and the data written to ICDR using the timing shown in figure
25.6. The selected slave device (i.e. the slave device with the matching slave address) drives
SDA low at t h e 9 t h t r a n smit clock pulse and returns an acknowledge signal.
[7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low
in synchronization with the internal clock until the next transmit data is written.
[8] Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device
has not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry
the transmit operation.
[9] Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag
is cleared to 0. After writing ICDR, clear IRIC immediately not to execute other interrupt
handling routine. The master device sequentially sends the transmission clock and the data
written to ICDR. Transmission of the next frame is performed in synchronization with the
internal clock.
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low
in synchronization with the internal clock until the next transmit data is written.
[11] Read the ACKB bit in ICSR and confirm ACKB is cleared to 0. When there is data to be
transmitted, go to the step [6] to continue next transmission. When the slave device has not
acknowledged (ACKB bit is set to 1), operate the step [12] to end transmission.
[12] Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from
low to high when SCL is high, and generates the stop condition.
Rev. 2.0, 11/ 00, page 549 of 1037
SDA
(master output)
SDA
(slave output)
21
R/
43658712
9
A
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6
IRIC
IRTR
ICDR
SCL
(master output)
Start condition
Geberation
Slave address Data 1
[9] ICDR write [9] IRIC clear
[6] ICDR write [6] IRIC clear
address + R/
[7]
[5]
Note: Data write
timing in ICDR
ICDR Writing
prohibited
[4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
ICDR Writing
enable
Data 1
User processing
These processes are executed continuously. These processes are executed continuously.
Figure 25. 6 Example of M aster Tr ansmit Mode O perati on Timi ng (MLS = WAIT = 0)
Rev. 2.0, 11/ 00, page 550 of 1037
25.3.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns
an acknowledge signal. The slave device transmits data. I2C bus interface module consists of
the data buffers of ICDRR and ICDRS, so data can be received continuously in master receive
mode. For this construction, when stop condition issuing timing delayed, it may occurs the
interna l cont e nti on be twee n stop c ondit i on issuance a nd SCL cl oc k output for ne xt da t a
receiving, and then the extra SCL clock would be outputted automatically or the SCL line would
be held t o l ow. And for I2C bus interface system, the acknowledge bit must be set to 1 at the last
data receiving, so the change timing of ACKB bit in ICSR should be controlled by software. To
take measures against these problems, the wait function should be used in master receive mode.
The reception procedure and operations with the wait function in master receive mode are
described be l ow.
[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the
WAIT bit in ICMR to 1. Also clear the ACKB bit in ICSR to 0 (acknowledge data setting).
[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. In order to detect wait
operation, set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC
immediately not to execute other interrupt handling routine. If one frame of data has been
received before the IRIC clearing, it can not be determine the end of reception.
[3] The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has
been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in
synchronization with the internal clock until the IRIC flag clearing. If the first frame is the
last receive data, execute step [10] to halt reception.
[4] Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock
and d rive s SDA at the 9 t h receive clock pulse to return an acknowledge signal.
[5] When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR
are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to
receive next data.
[6] Read ICDR.
[7] Clear the IRIC flag to detect next wait operation. From clearing of the IRIC flag to negation
of a wait as described in step [4] (and [9]) to clearing of the IRIC flag as described in steps
[5], [6], and [7], must be performed within the time taken to transfer one byte.
[8] The IRIC flags set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed
low in synchronization with the internal clock until the IRIC flag clearing. If this frame is
the last receive data, execute step [10] to halt reception.
[9] Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th
cl o c k a n d d r i v e s SDA a t t he 9t h receive clock pulse to return an acknowledge signal. Data
can be received continuously by repeating step [5] to [9].
Rev. 2.0, 11/ 00, page 551 of 1037
[10] Set the ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit
to 1 to switch from receive mode to transmit mode.
[11] Clear IRIC flag to 0 to release from the Wait State.
[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
receive clock pulse.
[13] Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the
IRIC flag to 0. Clearing of the IRIC flag should be after the WAIT = 0.
[14] Clear the BBSY bit and SCP bit to 0. This changes SDA from l ow t o high whe n SCL is
high, and generates the stop condition.
9
A Bit7
Master receive modeMaster transmit mode
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing [1] TRS cleared to 0
WAIT set to 1
ACKB cleared to 0
[2] ICDR read
(dummy read) [2] IRIC clearance [4] IRC clearance [6] ICDR read
(Data 1) [7] IRIC clearance
Bit6 Bit5 Bit4 Bit3 Bit7 Bit6 Bit5 Bit4 Bit3Bit2 Bit1 Bit0
1234 56 78
[3] [5]
A
912 345
Data 1 Data 2
Data 1
These processes are executed continuously. These processes are executed continuously.
Figure 25.7 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
Rev. 2.0, 11/ 00, page 552 of 1037
8
Bit0
Data 2
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing [9] IRIC clearance [6] ICDR read
(Data 2) [7] IRIC clearance [9] IRIC Clearance [6] ICDR read
(Data 3) [7] IRIC clearance
Bit7
[8] [5]
A
Bit6 Bit5 Bit4 Bit7 Bit6Bit3 Bit2 Bit1 Bit0
9123 45 67
[8] [5]
A
8912
Data 3 Data 4
Data 3Data 2Data 1
These processes are executed continuously. These processes are executed continuously.
Figure 25.8 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1) continued
Rev. 2.0, 11/ 00, page 553 of 1037
25.3.4 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The receive procedure and operations in slave
receive mode are described below.
[1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according
to the ope ra ti ng m ode.
[2] A start condition output by the master device sets the BBSY flag to 1 in ICCR.
[3] After the slave device detects the start condition, if the first frame matches its slave address,
it functions as the slave device designated as the master device. If the 8th bit data (R/
:
) is
0, TRS bit in ICCR remains 0 and executes slave receive operation.
[4] At the ninth clock pulse of the receive frame, the slave device drives SDA l ow to
acknowledge the transfer. At the same time, the IRIC flag is set to 1 in ICCR. If IEIC is 1 in
ICCR, a CPU inte rrupt i s reque sted. If t he RDRF interna l fla g i s 0, i t i s set t o 1 and
continuous reception is performed. If the RDRF internal flag is 1, the slave device holds
SCL low from the fall of the receive clock until it has read the data in ICDR.
[5] Read ICDR and clear IRIC to 0 in ICCR. At this time, the RDFR flag is cleared to 0.
Steps [4] and [5] can be repeated to receive data continuously. When a stop condition is
detected (a low-to-high transition of SDA wh ile SCL is high), the BBSY flag is cleared to 0 in
ICCR.
Rev. 2.0, 11/ 00, page 554 of 1037
SDA
(Master output)
SDA
(Slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(Master output)
Start condition
issurance
SCL
(Slave output)
Interrupt request
generated
Address + R/W
Address + R/W
[5] Read ICDR [5] Clear IRIC
User processing
Slave address Data 1
[4]
A
R/W
Figure 25.9 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (1)
Rev. 2.0, 11/ 00, page 555 of 1037
SDA
(Master output)
SDA
(Slave output)
214365879879
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(Master output)
SCL
(Slave output)
Interrupt
request
generated
Interrupt
request
generated
Data 2
Data 2
Data 1
Data 1
[5] Read ICDR [5] Clear IRIC
User processing
Data 2
Data 1 [4] [4]
A
A
Figure 25.10 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (2)
Rev. 2.0, 11/ 00, page 556 of 1037
25.3.5 Slave Transmit Oper ati on
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs
the transmit clock and returns an acknowledge signal. The transmit procedure and operations in
slave transmit mode are described below.
[1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according
to the ope ra ti ng m ode.
[2] After the slave device detects a start condition, if the first frame matches its slave address, at
the ninth clock pulse the slave device drives SDA l ow to acknowle dge t h e t ra n sfe r. At t h e
same time, the IRIC flag is set to 1 in ICCR, and if the IEIC bit in ICCR is set to 1 at this
time, an interrupt request is sent to the CPU. If the eighth data bit (R/
:
) is 1, the TRS bit is
set to 1 in ICCR, automatically causing a transition to slave transmit mode. The slave device
holds SCL low from the fall of the transmit clock until data is written in ICDR.
[3] Clear the IRIC flag to 0, then write data in ICDR. The written data is transferred to ICDRS,
and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. Clear IRIC to 0,
then write the next data in ICDR. The slave device outputs the written data serially in step
with the clock output by the master device, with the timing shown in figure 25.11.
[4] When one frame of data has been transmitted, at the rise of the ninth transmit clock pulse
IRIC is set to 1 in ICCR. If the TDRE internal flag is 1, the slave device holds SCL low
from the fall of the transmit clock until data is written in ICDR. The master device drives
SDA low a t t h e nint h c l oc k pul se t o a cknowl e dge t he d ata. The acknowledge signal is stored
in the ACKB bit in ICSR, and can be used to check whether the transfer was carried out
normally. If TDRE internal flag is set to 0, the data written in ICDR is transferred to ICDRS,
then transmission starts and TDRE internal flag and IRIC and IRTR flags are all set to 1
again.
[5] To continue transmitting, clear IRIC to 0, then write the next transmit data in ICDR.
Steps [4] and [5] can be repeated to transmit continuously. To end the transmission, write H'FF
in ICDR so t ha t t he SDA m a y be fre e d on t he sl a ve si de . W he n a st op c ond ition is detected (a
low-to-high transition of SDA while SCL is high), the BBSY flag will be cleared to 0 in ICCR.
Rev. 2.0, 11/ 00, page 557 of 1037
SDA
(Slave output)
SDA
(Master output)
SCL
(Slave output)
21 21436587998
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRT
TDRE
SCL
(Master output)
Interrupt
request
generated
Interrupt
request
generated
Interrupt
request
generated
Slave receive mode Slave transmit mode
Data 1 Data 2
[3] Clear IRIC [5] Clear IRIC[3] Write ICDR [3] Write ICDR [5] Write ICDR
User
processing
Data 1
Data 1 Data 2
Data 2
A
R/W
A
[3]
[2]
Figure 25. 11 Example of Ti ming in Slave Tr ansmit Mode (M LS = 0)
Rev. 2.0, 11/ 00, page 558 of 1037
25. 3 .6 IRIC Set ting Timi ng and SCL Co ntrol
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR,
the FS bi t in SAR , and the FSX b i t in SAR X. I f t h e T DR E o r RDR F i n t ernal f l ag i s se t t o 1 ,
SCL is automatically held low after one frame has been transferred; this timing is synchronized
with the internal clock. Figure 25.12 shows the IRIC set timing and SCL control.
Rev. 2.0, 11/ 00, page 559 of 1037
SCL
SDA
IRIC
User
processing Clear
IRIC Write to ICDR (transmit) or
read ICDR (receive)
1A87
1987
SCL
SDA
IRIC
User
processing Clear IRIC Write to ICDR (transmit) or
read ICDR (receive)
1A8
198
Clear IRIC
SCL
SDA
IRIC
User
processing Clear IRIC Write to ICDR (transmit) or
read ICDR (receive)
187
187
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I
2
C bus format, no wait)
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I
2
C bus format, wait inserted)
(c) When FS = 1 and FSX = 1 (synchronous serial format)
Fi g ur e 2 5 . 1 2 IRIC Se t ting T i m i ng and SCL Co ntrol
Rev. 2.0, 11/ 00, page 560 of 1037
25.3.7 Noise Canceler
The l ogi c l ev el s a t t he SCL a nd SDA pi ns a re route d t hrough noi se c a ncelers before being
latched internally. Figure 25.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless
the outputs of both latches agree. If they do not agree, the previous value is held.
SCL or SDA
input signal Internal SCL
or SDA signal
Sampling clock
Sampling
clock
System clock
period
C
Latch
QD
C
Latch
QD Match
detector
Figure 25.13 Block Diagram of Noise Canceler
25.3.8 Sample F lowcharts
Figures 25.14 to 25. 17 show sample flowcha rt s for using the I 2C bus interface in each mode.
Rev. 2.0, 11/ 00, page 561 of 1037
Start
Initialize
Read BBSY in ICCR
No BBSY = 0?
Yes
Set MST = 1 and
TRS = 1 in ICCR
Write BBSY = 1
and SCP = 0 in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
No
Yes
IRIC = 1?
Write transmit data in ICDR
Read ACKB in ICSR
ACKB = 0? No
Yes No
Yes
Transmit mode?
Write transmit data in ICDR
Read IRIC in ICCR
IRIC = 1?
No
Yes
Clear IRIC in ICCR
Read ACKB in ICSR
End of transmission
or ACKB = 1?
No
Yes
Write BBSY = 0
and SCP = 0 in ICCR
End
Master receive mode
Read IRIC in ICCR
No IRIC = 1?
Clear IRIC in ICCR
[1] Initialize
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte (slave
address + R/ ).
(After writing ICDR, clear IRIC
immediately)
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit, transferred from
slave device.
[10] Wait for 1 byte to be transmitted.
[11] Test for end of transfer
[12] Stop condition issuance
[9] Set transmit data for the second and
subsequent bytes.
(After writing ICDR, clear IRIC
immediately)
Figure 25. 14 F l owchart for M aster Transmit Mode (Example )
Rev. 2.0, 11/ 00, page 562 of 1037
Master receive mode
Read ICDR
Clear IRIC in ICCR
IRIC = 1?
Clear IRIC in ICCR
Read IRIC in ICCR
IRIC = 1?
Last receive ?
Yes Yes
No
No
No
Yes
Yes
Yes
No
Yes
Read ICDR
Read IRIC in ICCR
Read IRIC in ICCR
IRIC = 1?
Last receive ?
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
Set WAIT = 0 in ICMR
Read ICDR
Write BBSY = 0
and SCP = 0 in ICCR
End
No
IRIC = 1?
No
Set TRS = 0 in ICCR
Set WAIT = 1 in ICMR
Set ACKB = 0 in ICSR
Read IRIC in ICCR
[1] Select receive mode
[2] Start receiving. The first read is a dummy
read. After reading ICDR, please clear
IRIC immediately.
[3] Wait for 1 byte to be received.
(8th clock falling edge)
[4] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[5] Wait for 1 byte to be received.
(9th clock risig edge)
[6] Read the received data.
[7] Clear IRIC
[8] Wait for the next data to be received.
(8th clock falling edge)
[9] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[10] Set ACKB = 1 so as to return No
acknowledge, or set TRS = 1 so as not
to issue Extra clock.
[12] Wait for 1 byte to be received.
[14] Stop condition issuance.
[13] Set WAIT = 0.
Read ICDR.
Clear IRIC.
(Note: After setting WAIT = 0, IRIC
should be cleared to 0)
[11] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
Figure 25.15 Flowchart for Master Receive Mode (Example)
Rev. 2.0, 11/ 00, page 563 of 1037
Start
End
Initialize
Read IRIC flag in ICCR
Read AAS and ADZ flags in ICSR
Read TRS bit in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read ICDR
Read ICDR
Read ICDR
Set ACKB=0 in ICSR
General call address processing
*Description omitted
Set MST=0 and
TRS=0 in ICCR
IRIC=1?
No
Yes
Read IRIC flag in ICCR
Set ACKB=0 in ICSR
IRIC=1?
No
Yes
TRS=0?
IRIC=1?
No
No
Yes
Yes
Yes
AAS=1 and
ADZ=0?
[2]
[1]
[3]
[8]
[5]
[6]
[4]
[7]
Slave transmit mode
Last receive?
No
No
Yes
Select slave receive mode.
Wait for 1 byte to be received (slave
address)
Start receiving. The first read is a dummy
read.
Wait for the transfer to end.
Set acknowledge data for the last receive.
Start the last receive.
Wait for the transfer to end.
Read the last receive data.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Figure 25. 16 F l owchart for Slave Tr ansmit Mode (Example)
Rev. 2.0, 11/ 00, page 564 of 1037
End
Write transmit data in ICDR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read ACKB bit in ICSR
Set TRS=0 in ICCR
Read ICDR
Read IRIC flag in ICCR
IRIC=1?
Yes
Yes
No
No
[1]
[4]
[5]
[2]
[3]
Slave transmit mode
End of transmission
(ACKB=1)?
Clear IRIC in ICCR
Set transmit data for the second and
subsequent bytes.
Wait for 1 byte to be transmitted.
Test for end of transfer.
Select slave receive mode.
Dummy read (to release the SCL line).
[1]
[2]
[3]
[4]
[5]
Figure 25.17 Flowchart for Slave Receive Mode (Example)
Rev. 2.0, 11/ 00, page 565 of 1037
25.3.9 Initializ ati on of Internal State
This I2C is capable of forcibly initializing internal state of I2C if de adl oc k deve l ops during
communication.
The initialization is done by setting IICRST bit in STCR register, or clearing ICE bit.
For details, see section 25.2.7, Serial/Time control Register (STCR).
(1) Range of Initialization
The following is initialized by this function:
• Internal fl a gs of TDRE and RDRF
• Programmable logic controller for signal receiving and sending.
• Internal latches used for holding outputs from SCL and SDA pi n s (wait, clock, data output,
etc.).
The following is not initialized by this function:
• Register val ue s (ICDR, SAR, SARX, ICMR, ICCR, ICSR, and STCR).
• Internal latches employed for maintaining data read from the registers which is used for
setting or clearing flags on ICMR, ICCR, and ICSR registers.
• Values on the ICMR registe r bi t c ount ers (BC2 to BC0).
• Interrupt factors currently generated (interrupt factors transferred to the interrupt controller).
(2) Precautions on Initialization
• Interrupt flags and interrupt factors are not cleared by this function. Thus, you need to clear
them own as needed.
• Other register flags are not basically cleared, too. Thus, you need to clear them as needed.
• When this I2C is initialized with IICRST bit, write data specified by IICRST bit is
maintained. When clearing I2C, set IICRST bit once, then clear it using the MOV
instruction. The I2C cannot operate with the IICRST bit set to 1. Don't try to use bit
operati on i nstruct i ons such as BCLR.
• If you try to clear a flag while data sending or receiving is taking place, I2C m odul e stops
sending or receiving at that moment and frees the SCL and SDA pins. Wh e n r e su m i n g t h e
communication, initialize registers as needed so that the system communication capability
may function as intended.
Clear function of this module does not directly rewrite value of BBSY bit. However, depending
on state of SCL and SDA pi ns and t h e timing in which they are made free, BBSY bit can be
cleared. Other bits and flags can also be affected by status change.
Rev. 2.0, 11/ 00, page 566 of 1037
In order to avoid these troubles, the following procedures must be observed in initialization of
I2C.
(1) Implement initialization of internal state by setting IICRST bit or ICE bit.
(2) Execute the stop condition issue instruction (setting BBSY = 0 and SCP = 0 to write) and
wait for a duration equivalent to 2 clocks of the transfer rate.
(3) Execute initialization of internal state again by setting IICRST bit or ICE bit.
(4) Initialize each I2C register (re-setting).
Rev. 2.0, 11/ 00, page 567 of 1037
25.4 Usage Not es
(1) In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA ar e b oth l o w, the n i ssu e t h e
instruction that generates the stop condition.
(2) Either of the following two conditions will start the next transfer. Pay attention to these
conditi ons when rea ding or writ i ng to ICDR.
(a) Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
(b) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
(3) Table 25.5 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 25.5 I2C Bus Tim i ng ( SCL a nd SDA O ut put )
It em Symbol Out put Tim ing Unit Notes
SCL output cycle time tSCLO 28tcyc to 256tcyc ns
SCL output high pulse width tSCLHO 0.5tSCLO ns
SCL output low pulse width t SCLLO 0.5tSCLO ns
SDA output bus fr ee t im e t BUFO 0.5tSCLO-1tcyc ns
Start condit ion output hold t ime t STAHO 0.5tSCLO-1tcyc ns
Retransmission star t condit ion
output set up t ime tSTASO 1tSCLO ns
Stop condition output set up time tSTOSO 0.5tSCLO+2tcyc ns
Data output set up t ime ( m aster) 1tSCLLO-3tcyc ns
Data output set up time (slave)
tSDASO 1tSCLL - (6tcyc or 12tcyc*1)ns
Data output hold t ime tSDAHO 3tcyc ns
Figure 28.10
(reference)
Note: 1. 6tcyc when II CX is 0, 12tcyc when 1.
(4) SCL and SDA i nput i s sam pl e d i n sync hronization with the internal clock. The AC timing
therefore depends on the system clock cycle t cyc, as shown in table 29.6 in section 29,
Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not
be met with a system clock frequency of less than 5 MHz.
Rev. 2.0, 11/ 00, page 568 of 1037
(5) The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for
high-speed mode ). In m aste r m ode, t he I2C bus interface monitors the SCL line and
synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low
to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high
period of SCL is extended. The SCL rise time is determined by the pull-up resistance and
load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust
the pull-up resistance and load capacitance so that the SCL rise time does not exceed the
values given in table 25.6.
Table 25.6 Permissible SCL Rise Time (tsr) Values
Time Indication [ns]
IICX tcyc
Indication
I2C Bus
Specification
(Max.) φ = 5 MHz φ = 8 MHz φ = 10 MHz
Normal
mode 1000 ←937 75007.5t
cyc
High-speed
mode 300 ←←←
Normal
mode 1000 ←←←
1 17.5tcyc
High-speed
mode 300 ←←←
(6) The I2C bus interface specifications for the SCL and SDA rise an d f all times are under 1000
ns and 300 ns. The I2C bus interface SCL and SDA ou t p ut timing is prescribed by tScyc and
tcyc, as shown in table 25.5. However, because of the rise and fall times, the I2C bus interfac e
specifications may not be satisfied at the maximum transfer rate. Table 25.7 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance
of a stop condition and issuance of a start condition, or (b) to select devices whose input
timing permits this output timing for use as slave devices connected to the I2C bus.
tSCLLO in high-speed mode a nd tSTASO in standard mode fail to satisfy the I2C bus interfac e
specifications for worst-case calculations of tSr/tSf. Possible soluti ons that should be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting
devices whose input timing permits this output timing for use as slave devices connected to
the I2C bus.
Rev. 2.0, 11/ 00, page 569 of 1037
Table 25.7 I2C Bus Timi ng (with Maximum Influence of tSr/tSf)
Time Indication (at M aximum Transfer Rate) [ns]
Item tcyc
Indication
tSr/tSf
Influence
(Max.)
I2C Bus
Specification
(Min.) φ = 5 MHz φ = 8 MHz φ = 10 MHz
Normal mode −1000 4000 4000 ←←
tSCLHO 0.5tSCLO
(-tSr)High-speed
mode −300 600 950 ←←
Normal mode −250 4700 4750 ←←
tSCLLO 0.5tSCLO
(-tSf)High-speed
mode −250 1300 1000*1←←
Normal mode −1000 4700 3800*13875*13900*1
tBUFO 0.5tSCLO-1tcyc
(-tSr)High-speed
mode −300 1300 750*1825*1850*1
Normal mode −250 4000 4550 4625 4650tSTAHO 0.5tSCLO-1tcyc
(-tSf)High-speed
mode −250 600 800 875 900
Normal mode −1000 4700 9000 9000 9000tSTASO 1tSCLO
(-tSr)High-speed
mode −300 600 2200 2200 2200
Normal mode −1000 4000 4400 4250 4200tSTOSO 0.5tSCLO+2tcyc
(-tSr)High-speed
mode −300 600 1350 1200 1150
Normal mode −1000 250 3100 3325 3400tSDASO
(master) 1tSCLLO*3-3tcyc
(-tSr)High-speed
mode −300 100 400 625 700
Normal mode −1000 250 1300 2200 2500tSDASO
(slave) 1tSCLL*3-12tcyc*2
(-tSr)High-speed
mode −300 100 −1400*1−500*1−200*1
Normal mode 0 0 600 375 300tSDAHO 3tcyc High-speed
mode 00 ↑↑↑
Notes: 1. Does not meet t he I2C bus inter f ace specificat ion. Remedial action such as the
following is necessar y: ( a) secur e a st ar t / s t op condition issuance interval; ( b) adjust
the rise and f all times by means of a pull-up r esistor and capacit ive load; (c ) r educe
the tr ansfer rat e; (d) select slave devices whose input timing permit s t his output
timing.
The values in t he above t able will v ar y depending on t he s et tings of the II CX bit and
bits CKS0 to CKS2. Depending on the f r equency it m ay not be possible to achieve the
maximum t r ansf er r at e; t her efore, whether or not the I2C bus int er f ace specificat ions
are met m ust be det er m ined in accordance with the actual setting conditions.
2. Value when t he I I CX bit is set t o 1. When the II CX bit is cleared to 0, the value is (tSCLL
- 6tcyc).
3. Calculat ed using t he I 2C bus specificat ion values (st andar d m ode: 4700 ns min.; high-
speed mode: 1300 ns m in. ) .
Rev. 2.0, 11/ 00, page 570 of 1037
(7) Precautions on reading ICDR at the end of master receive mode
When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR
BBSY = 0 and SCP = 0. T hi s forc e s to move SDA from l ow t o hi gh le v e l whe n SCL is a t
high leve l , the re by gene ra ti ng t he stop c ondi ti on.
Now you can read received data from ICDR. If, however, any data is remaining on the
buffer, received data on ICDRS is not transferred to ICDR, thus you won't be able to read the
second byte data.
When it is required to read the second byte data, issue the stop condition from the master
receive state (TRS bit is 0).
Before reading data from ICDR register, make sure that BBSY bit on ICCR register is 0, stop
condition is generated and bus is made free.
If you try to read received data after the stop condition issue instruction (setting ICCR's
BBSY = 0 and SCP = 0 to write) has been executed but before the actual stop condition is
generated, clock may not be appropriately signaled when the next master sending mode is
turned on. Thus, reasonable care is needed for determining when to read the received data.
After the master receive is complete, if you want to re-write I2C control bit (such as clearing
MST bit) for switching the sending/receiving mode or modifying settings, it must be done
during period (a) indicated in figure 25.18 (after making sure ICCR register BBSY bit is
cleared to 0).
SDA
SCL
Internal clock
BBSY bit
Bit 0 A
(a)
89
Stop condition Start
condition
Start condition
is issued
Generation of the stop
condition is checked
(BBSY = 0 is set to read)
The stop condition
issue instruction
(BBSY = 0 and SCP = 0
set to write) is executed
Master receive mode
ICDR read
inhibit period
Figure 25.18 Precautions on Reading the Master Receive Data
Rev. 2.0, 11/ 00, page 571 of 1037
(8) Notes on Start Condition Issuance for Retransmission
Figure 25.19 shows the timing of s tart conditon is s uance for retrans mis s ion, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After start
condition iss uance is done and determined the s tart condition, wr ite the trans mit data to ICD R.
IRIC=1 ?
SCL=Low ?
IRIC=1 ?
Write transmit data to ICDR
Write BBSY=1,
SCP=0 (ICSR)
Clear IRIC in ICSR
Read SCL pin
Start condition
issuance? Other processing
No [1]
[2]
[3]
[4]
[5]
No
No
Yes
Yes
Yes
Yes
No
[1] Wait for end of 1-byte transfer
[2] Determine wheter SCL is low
[3] Issue restart condition instruction for transmission
[4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/ )
Note: Program so that processing instruction [3] to [5] is
executed continuously.
[5] ICDR write (next transmit data)
[4] IRIC determination
[2] Determination of SCL=Low
[1] IRIC determination
SCL
SDA ACK bit 7
9
IRIC
Start condition
(retransmission)
[3] Issue restart condition instruction
for retransmission
Fi g ur e 2 5 . 1 9 F l o wc ha r t a nd Timi ng o f St a r t Conditi o n Instruct i o n Issua nc e f o r
Retransmission
Rev. 2.0, 11/ 00, page 572 of 1037
(9) Notes on I2C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load
capacitance is large, or if there is a slave device of the type that drives SCL low to effect a
wait, issue the stop condition instruction after reading SCL and determining it to be low, as
shown below.
As waveform rise is late,
SCL is detected as low
9th clock
SCL
SDA
IRIC
High period secured
Stop condition
[2] Stop condition instruction issuance
[1] Determination of SCL=Low
VIH
Fi g ur e 2 5 . 2 0 Timi ng o f St o p Conditi o n Issuance
Rev. 2.0, 11/ 00, page 573 of 1037
Section 26 A/D Converter
26.1 Overview
This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12
analog input channels to be selected.
26.1.1 Features
A/D converter features are listed below.
• 10-bit resoluti on
• 12 input channe l s
• Sample and hold function
• Choice of software, hardware (internal signal) triggering or external triggering for A/D
conversion start .
• A/D conversion end interrupt request generation
Rev. 2.0, 11/ 00, page 574 of 1037
26.1.2 Block Diagram
Figure 26.1 shows a block di agra m of the A/D conve rte r.
/2
/4
ADTRG
Interrupt request
AN0 Vref
AVCC
AVSS
Reference Voltage
Sample-and-
hold circuit
Chopper type
comparator
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
ANA
ANB
DFG
ADTRG
(HSW timing generator)
Internal data bus
[Legend]
ADR
AHR : Software trigger A/D result register
: Hardware trigger A/D result register ADTRG, DFG
ADTRG : Hardware trigger
: A/D external trigger input
ADCR
ADCSR: A/D control register
: A/D control/status register
ADTSR: A/D trigger selection register
-
+
10-bit
D/A
Hardware
control
circuit
Control circuit
Analog multiplexer
Successive
approximation register
A
D
R
A
H
R
A
D
C
S
R
A
D
C
R
A
D
T
S
R
Figure 26. 1 Bl oc k Diagram of A/D Converter
Rev. 2.0, 11/ 00, page 575 of 1037
26.1.3 Pin Configuration
Table 26.1 summarizes the input pins used by the A/D converter.
Table 26.1 A/D Converter Pins
Name Abbrev. I/O Function
Analog power supply pin AVCC Input Analog block power supply
Analog ground pin AVSS Input Analog block gr ound and A/D conversion
refer ence voltage
Analog input pin 0 AN0 Input Analog input channel 0
Analog input pin 1 AN1 Input Analog input channel 1
Analog input pin 2 AN2 Input Analog input channel 2
Analog input pin 3 AN3 Input Analog input channel 3
Analog input pin 4 AN4 Input Analog input channel 4
Analog input pin 5 AN5 Input Analog input channel 5
Analog input pin 6 AN6 Input Analog input channel 6
Analog input pin 7 AN7 Input Analog input channel 7
Analog input pin 8 AN8 Input Analog input channel 8
Analog input pin 9 AN9 Input Analog input channel 9
Analog input pin A ANA Input Analog input channel A
Analog input pin B ANB Input Analog input channel B
A/D external t r igger input pin
$'75*
Input External t r igger input f or st ar ting A/D
conversion
Rev. 2.0, 11/ 00, page 576 of 1037
26.1.4 Register Configuration
Table 26.2 summarizes the registers of the A/D converter.
Table 26.2 A/D Converter Registers
Name Abbrev. R/W Size Init i al Value Address*2
Software trigger A/ D
result regist er H ADRH R Byte H'00 H'D130
Software trigger A/ D
result regist er L ADRL R Byte H'00 H'D131
Hardware tr igger A/ D
result regist er H AHRH R Byte H'00 H'D132
Hardware tr igger A/ D
result regist er L AHRL R Byte H'00 H'D133
A/D control r egister ADCR R/W Byte H'40 H'D134
A/D control/st atus
register ADCSR R (W )*1Byte H'01 H'D135
A/D trigger selection
register ADTSR R/W Byte H'FC H'D136
Port m ode r egist er 0 PMR0 R/W Byte H'00 H'FFCD
Notes: 1. Only 0 can be writt en in bits 7 and 6, t o clear t he f lag. Bits 3 t o 1 ar e r ead-only.
2. Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 577 of 1037
26.2 Register Descript ion s
26.2.1 Software-Triggered A/D Result Register (ADR)
ADRH ADRL
1 03254 ——————
——————
7
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
The software-t ri ggere d A/D result regi ste r (ADR) is a registe r t hat store s the re sult of an A/D
conversion start e d by software.
The A/D-converted data is 10-bit data. Upon completion of software-triggered A/D conversion,
the 10-bit result data is transferred to ADR and the data is retained until the next software-
triggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes
(bits 15 to 8) of ADR, and t he l ower 2 bi ts are store d in t he lower byt e s (bits 7 and 6). Bi t s 5 to
0 are always read as 0.
ADR can be read by the CPU at any time, but the ADR value during A/D conversion is not
fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred
via a temporary register (TEMP). For details, see section 26. 3, Interface to Bus Master.
ADR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop
mode, standby mode, watch mode, subactive mode and subsleep mode.
26.2.2 Hardware-Triggered A/D Result Register (AHR)
AHRH AHRL
1 03254 ——————
——————
7
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
The hardware-triggered A/D result register (AHR) is a register that stores the result of an A/D
conversion started by hardware (internal signal: ADTRG and DFG) or by ext erna l t ri gger i nput
(
$'75*
).
The A/D-converted data is 10-bit data. Upon completion of hardware- or external-triggered A/D
conversion, the 10-bit result data is transferred to AHR and the data is retained until the next
hardware- or external- triggered A/D conversion completion. The upper 8 bits of the data are
stored in the uppe r byte s (bit s 15 to 8) of AHR, and t he l ower 2 bi ts are store d in t he lower byt e s
(bits 7 and 6). Bits 5 to 0 are always read as 0.
Rev. 2.0, 11/ 00, page 578 of 1037
AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not
fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred
via a temporary register (TEMP). For details, see section 26. 3, Interface to Bus Master.
AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop
mode, standby mode, watch mode, subactive mode and subsleep mode.
Rev. 2.0, 11/ 00, page 579 of 1037
26. 2 .3 A/D Co ntrol Re g i st e r (ADCR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
—
—
1
7
R/WR/WR/W
HCH1
0
R/W
CK HCH0 SCH3 SCH2 SCH1 SCH0
Bit :
Initial value :
R/W :
ADCR is a register that sets A/D conversion speed and selects analog input channel. When
executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0.
ADCR is an 8-bit readable/writable register that is initialized to H'40 by a reset, and in module
stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Bit 7: Clock Select (CK)
Sets A/D conversion speed.
Bit 7
CK Description
0 Conversion frequency is 266 st at es (Init ial value)
1 Conversion frequency is 134 st at es
Note: A/D conversion st ar t s when 1 is writt en in SST, or when HST is set to 1. The conver sion
period is the tim e f r om when this st ar t flag is set until the f lag is cleared at the end of
conversion. Actual sample-and- hold t akes place (r epeat edly) dur ing the conver sion
frequency shown in figur e 26. 2.
Rev. 2.0, 11/ 00, page 580 of 1037
Conversion frequency
Note: IRQ sampling;
Conversion period (134 or 266 states)
Interrupt request flag
IRQ sampling
(CPU)
States
Instruction execution MOV.B
WRITE
Start flag
When conversion ends, the start flag is cleared and the interrupt request flag is
set. The CPU recognizes the interrupt in the last execution state of an instruction,
and executes interrupt exception handling after completing the instruction.
Figure 26.2 Internal Operation of A/D Converter
Bit 6: Reserved
This bit cannot be modified and always reads 1. Writes are disabled.
Bits 5 and 4: Hardware Channel Select (HCH1, HCH0)
These bits select the analog input channel that is converted by hardware triggering or triggering
by an external input. Only channels AN8 to ANB are available for hardware- or external-
triggere d c onversion.
Bit 5 Bit 4
HCH1 HCH0 Analog I nput Channel
0 AN8 (Init ial value)0
1AN9
0ANA1
1ANB
Rev. 2.0, 11/ 00, page 581 of 1037
Bits 3 to 0: Software Channel Select (SCH3 to SCH0)
These bits select the analog input channel that is converted by software triggering.
When channels AN0 to AN7 are used, appropriate pin settings must be made in port mode
register 0 (PMR0). For pin settings, see section 26.2.6, Port Mode Register 0 (PMR0).
Bit 3 Bit 2 Bit 1 Bit 0
SCH3 SCH2 SCH1 SCH0 Analog Input Channel
0 AN0 (Init ial value)0
1AN1
0AN2
0
1
1AN3
0AN40
1AN5
0AN6
0
1
1
1AN7
0AN80
1AN9
0ANA
0
1
1ANB
1
1**No channel select ed f or sof tware-t r iggered conver sion
Notes: 1. If conversion is star t ed by sof tware when SCH3 to SCH0 are set t o 11**, the
conversion result is undeter m ined. Hardware- or external-t r iggered conver sion,
however, will be per formed on the channel s elected by HCH1 and HCH0.
2. *: Don't care.
Rev. 2.0, 11/ 00, page 582 of 1037
26. 2 .4 A/D Co ntrol / St a tus Regi st e r ( ADCSR)
0
—
—
0
1
0
R
2
0
R
3
0
4
0
R/W
5
0
67
R/(W)*RR/W
ADIE
0
R/(W)*
SEND SST HST BUSY SCNLHEND
1
Bit :
Initial value :
R/W :
Note: * Only 0 can be written to bits 7 and 6, to clear the flag.
The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/ D
conversion, or check the status of the A/D converter.
A/D conversion starts when 1 is written in SST flag. A/D conversion can also start by setting
HST flag to 1 by hardware - or e xte rna l-t ri ggeri ng.
For ADTRG start by HSW timing generator in hardware triggering, see section 28.4, HSW
Timing Generator.
When conversion ends, the converted data is stored in the software-triggered A/D result register
(ADR) or hardware-triggered A/D result register (AHR), and the SST or HST bit is cleared to 0.
If software-triggering and hardware- or external-triggering are generated at the same time,
priority i s give n to ha rdware - or ext e rnal -t rigge ri ng.
ADCSR is an 8-bit register which is initialized to H'01 by a reset, and in module stop mode,
standby mode, watch mode, subactive mode and subsleep mode.
Bit 7: Software A/D End Flag (SEND)
Indicates the end of A/D conversion.
Bit 7
SEND Description
0 [Clearing Conditions] (Init ial value)
0 is written af t er r eading 1
1 [Set t ing Conditions]
Software- triggered A/ D conversion has ended
Bit 6: Hardware A/D End Flag (HEND)
Indicates that hardware- or external-triggered A/D conversion has ended.
Bit 6
HEND Description
0 [Clearing Conditions] (Init ial value)
0 is written af t er r eading
1 [Set t ing Conditions]
Hardware- or ext er nal-triggered A/D conversion has ended
Rev. 2.0, 11/ 00, page 583 of 1037
Bit 5 : A/D Inte rrupt E nable ( ADIE )
Selects enable or disable of interrupt (ADI) generation upon A/D conversion end.
Bit 5
ADIE Description
0 Int er r upt (ADI) upon A/D conver sion end is disabled (Initial value)
1 Int er r upt (ADI) upon A/D conver sion end is enabled
Bit 4: Software A/D Start Flag (SST)
Starts software-triggered A/D conversion and indicates or controls the end of conversion. This
bit remains 1 during software-triggered A/D conversion.
When 0 is written in this bit, software-triggered A/D conversion operation can forcibly be
aborted.
Bit 4
SST Description
Read: Indicates t hat sof tware-t r iggered A/ D conversion has ended or been st opped
(Init ial value)
0
Write: Sof t war e- t r igger ed A/D conver sion is abort ed
Read: Indicates t hat software- t r iggered A/ D conversion is in progress1
Write: St ar t s sof t ware- triggered A/D conversion
Bit 3: Hardware A/D Status Flag (HST)
Indicates the status of hardware- or external-triggered A/D conversion. When 0 is written in this
bit, A/D conversion i s abort ed re ga rdle ss of whether i t was hardware -t rigge re d or ext e rnal -
triggered.
Bit 3
HST Description
Read: Hardware- or external-t r igger ed A/ D conversion is not in progr ess(Initial
value)
0
Write: Har dware- or external-t r igger ed A/D conver sion is abort ed.
1 Hardware- or ext er nal-triggered A/D conversion is in progress.
Rev. 2.0, 11/ 00, page 584 of 1037
Bit 2 : B usy F l a g (B USY)
During hardware- or external-triggered A/D conversion, if software attempts to start A/D
conversion by writing to the SST bit, the SST bit is not modified and instead the BUSY fl a g i s
set to 1.
This flag is cleared when the hardware-triggered A/D result register (AHR) is read.
Bit 2
BUSY Description
0 No contention for A/ D conversion (Init ial value)
1 Indicates an at t em pt to execute sof t ware- t r iggered A/ D conversion while hardware-
or exter nal-t r igger ed A/D conversion was in progress
Bit 1: Software-Triggered Conversion Cancel Flag (SCNL)
Indicates that software-triggered A/D conversion was canceled by the start of hardware-triggered
A/D conversion.
This flag is cleared when A/D conversion is started by software.
Bit 1
SCNL Description
0 No contention for A/ D conversion (Init ial value)
1 Indicates t hat software- t r iggered A/ D conversion was canceled by the star t of
hardware- t r iggered A/ D conversion
Bit 0: Reserved
This bit cannot be modified and always reads 1. Writes are disabled.
Rev. 2.0, 11/ 00, page 585 of 1037
26.2.5 Trigger Select Register (ADTSR)
0123
0
4
R/W
567 ——————
——————
TRGS1
0
R/W
TRGS0
111111
Bit :
Initial value :
R/W :
The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start
factor.
ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module
stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Bits 7 to 2: Reserved
These bits are reserved and are always read as 1. Writes are disabled.
Bits 1 and 0: Trigger Select
These bits select hardware- or external-triggered A/D conversion start factor. Set these bits
when A/D conversion is not in progre ss.
Bit 1 Bit 0
TRGS1 TRGS0 Description
0 Hardware- or exter nal-t riggered A/D conversion is disabled
(Init ial value)
0
1 Hardware-t r iggered ( ADTRG) A/D conver sion is selected
0 Hardware-triggered ( DFG ) A/D conver sion is selected1
1 External- t r igger ed (
$'75*
) A/D conversion is selected
26.2.6 Port Mode Register 0 (P M R0)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR04 PMR03 PMR02 PMR01 PMR00
0
R/W
PMR07
R/WR/WR/W
PMR06 PMR05
Bit :
Initial value :
R/W :
Port mode register 0 (PMR0) controls switching of each pin function of port 0. Switching is
specified for each bit.
PMR0 is an 8-bit readable/writable register and is initialized to H'00 by a reset.
Bit 7 to 0: P07/AN7 to P00/AN0 pin switching (PMR07 to PMR00)
These bit s set t he P0n/ANn pin as the i nput pi n for P0n or as the ANn pin for A/D conversion
analog i nput cha nne l.
Rev. 2.0, 11/ 00, page 586 of 1037
Bit n
PMR0n Description
0 P0n/ANn funct ions as a general-pur pose input por t (Init ial value)
1 P0n/ANn funct ions as an analog input channel
(n = 7 to 0)
26. 2 .7 Module St o p Cont r o l Regi st e r ( M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
MSTPCR consists of 8-bit readable/writable registers and performs module stop mode control.
When the MSTP2 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop
Mode.
MSTPCR is initialized to H'FFFF by a reset
Bit 2: Module Stop (MSTP2)
Specifies the A/D converter module stop mode.
MSTPCRL
Bit 2
MSTP2 Description
0 A/D converter m odule st op m ode is cleared
1 A/D converter m odule st op m ode is set (Initial value)
Rev. 2.0, 11/ 00, page 587 of 1037
26.3 Interface t o Bus Mast er
ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte
is accessed via a temporary register (TEMP).
A data reading from ADR and AHR is performed as follows. When the upper byte is read, the
upper byte va l ue i s tra nsferred t o t he CPU and the l ower byte va lue i s transferre d t o TE MP.
Next, when the lower byte is read, the TEMP contents are transferred to the CPU.
When rea di ng ADR and AHR, always rea d the uppe r byte be fore t he lower byt e . It i s possible t o
read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 26.3 shows the data flow for ADR access. The data flow for AHR access is the same.
Bus master
(H'AA)
ADRH
(H'AA) ADRL
(H'40)
Lower byte read
Bus master
(H'40)
ADRH
(H'AA) ADRL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
Module data bus
Module data bus
Bus
interface
Bus
interface
Upper byte read
Fi g ur e 2 6 . 3 ADR Access Operation (Reading H'AA40)
Rev. 2.0, 11/ 00, page 588 of 1037
26.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution.
26.4.1 Software-Triggered A/ D Conversion
A/D conversion starts when software set s the software A/D start fl ag (SST bit ) t o 1. The SST bit
remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends.
Conversion can be software -tri gge red on a ny of t he 12 c ha nnel s provide d by ana l og input pi ns
AN0 to ANB. Bits SCH3 to SCH0 in ADCR select the analog input pin used for software-
triggered A/D conversion. Pins AN8 to ANB are also available for hardware- or external-
triggere d c onversion.
When conve rsion e nds, SEND flag i n ADCSR bit is set to 1. If ADIE bit i n ADCSR is also set
to 1, a n A/D conversion e nd i nte rrupt occ urs.
If the conversion time or input channel selection in ADCR needs to be changed during A/D
conversion, to avoid malfunctions, first clear the SST bit to 0 to halt A/D conversion.
If software writes 1 in the SST bit to start software-triggered conversion while hardware- or
externa l -tri gge red c onve rsion is in progre ss, the ha rdware- or e xt erna l -tri gge red c onve rsion has
priority and the software-triggered conversion is not executed. At this time, BUSY fla g i n
ADCSR i s se t t o 1 . Th e B USY f l a g i s cleared to 0 when the hardware-triggered A/D result
register (AHR) is read. If conversion is triggered by hardware while software-triggered
conversion is in progress, the software-triggered conversion is immediately canceled and the
SST flag is cleared to 0, and SCNL flag in ADCSR is set to 1. The SCNL flag is cleared when
software writes 1 in the SST bit to start conversion after the hardware-triggered conversion ends.
Rev. 2.0, 11/ 00, page 589 of 1037
26.4.2 Hardware- or External-Triggered A/D Conversion
The system contains the hardware trigger function that allows to turn on A/D conversion at a
specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) a n d the
incoming external trigger (
$'75*
). This function can be used to measure an analog signal that
varies in synchronization with an external signal at a fixed timing.
To execute hardware- or external-triggered A/D conversion, select appropriate start factor in
TRGS1 and TRGS0 bits in ADTSR. When the selected triggering occurs, HST flag in ADCSR
is set to 1 and A/D conversion starts. The HST flag remains 1 during A/D conversion, and is
automatically cleared to 0 when conversion ends. For ADTRG start by HSW timing generator
in hardware triggering, see section 28.4, HSW Timing Generator. Setting of the analog input
pins on four channel s from AN8 to ANB can be m odifi e d with t he hardware t rigge r or t he
incoming external trigger. Setting is done from HCH1 and HCH0 bits on ADCR. Pins AN8 to
ANB are also available for software-triggered conversion.
When conve rsion e nds, HEND flag i n ADCSR is set to 1. If ADIE bit in ADCSR is also set to
1, an A/D conve rsion end i nt errupt oc curs.
If the conversion time or input channel selection in ADCR needs to be changed during A/D
conversion, to avoid malfunctions, first clear the HST flag to 0 to halt A/D conversion.
If software writes 1 in the SST bit to start software-triggered conversion while hardware- or
externa l -tri gge red c onve rsion is in progre ss, the ha rdware- or e xt erna l -tri gge red c onve rsion has
priority and the software-triggered conversion is not executed. At this time, BUSY fla g i n
ADCSR i s se t t o 1 . Th e B USY f l a g i s cleared to 0 when the hardware-triggered A/D result
register (AHR) is read.
If conversion is triggered by hardware while software-triggered conversion is in progress, the
software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and
SCNL flag in ADCSR is set to 1 (the SCNL flag is cleared when software writes 1 in the SST bit
to start c onve rsion aft e r the ha rdware-t ri ggere d c onversion e nds). T he ana l og input c hanne l
changes automatically from the channel that was undergoing software-triggered conversion
(selected by bits SCH3 to SCH0 in ADCR) to the channel selected by bits HCH1 and HCH0 in
ADCR for hardware- or externa l -tri gge red c onve rsion. After t he hardware - or e xte rna l-t ri ggere d
conversion ends, the channel reverts to the channel selected by the software-triggered conversion
channel select bits in ADCR.
Hardware- or exte rna l-t ri ggere d c onversion ha s priori ty ove r software -tri gge red c onve rsion, so
the A/D i n t errupt -ha ndl i ng rout i ne shoul d c he c k t he SCNL a nd BUSY fl a gs whe n i t proc e sse s
the converted data.
Rev. 2.0, 11/ 00, page 590 of 1037
26.5 Interrupt S ou rces
When A/D conversion e nds, SEND or HEND flag in ADCSR is set to 1. T he A/D conve rsion
end inte rrupt ca n be ena bl ed or di sabl ed by ADIE bit i n ADCSR.
Figure 26.4 shows the bloc k dia gra m of A/D conve rsion e nd int e rrupt.
A/D conversion end
interrupt (ADI)
To interrupt controller
A/D control/status register (ADCSR)
SEND HEND ADIE
Fi g ur e 2 6 . 4 B l o c k Di a g r a m o f A/ D Co nver si o n End Int e rrupt
Rev. 2.0, 11/ 00, page 591 of 1037
Section 27 Address Trap Controller (ATC)
27.1 Overview
The address trap controller (ATC) is capable of generating interrupt by setting an address to
trap, when the address set appears during bus cycle.
27.1.1 Features
Address to trap can be set inde pe ndent l y at t hree poi nts.
27.1.2 Block Diagram
Figure 27.1 shows a block diagram of the address trap controller.
TRCR
TAR0 to 2
Interrupt request
Modules bus
Internal bus
TRCR TAR0 TAR1 TAR2
Trap condition comparator
Bus
interface
: Trap control register
: Trap address register 0 to 2
Figure 27. 1 Bl oc k Diagram of ATC
Rev. 2.0, 11/ 00, page 592 of 1037
27.1.3 Register Configuration
Table 27.1 Register List
Name Abbrev. R/W Ini tial Val ue Address *
Address tr ap cont r ol r egister ATCR R/W H'F8 H'FFB9
Trap address r egist er 0 TAR0 R/ W H'F00000 H'FFB0 to H'FFB2
Trap address r egist er 1 TAR1 R/ W H'F00000 H'FFB3 to H'FFB5
Trap address r egist er 2 TAR2 R/ W H'F00000 H'FFB6 to H'FFB8
Note: *Lower 16 bits of t he addr ess.
27.2 Register Descri pt i on s
27. 2 .1 Address Tr a p Co ntrol Re g i st e r (ATCR)
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
1
6
1
7
—————
————— R/W
TRC2 TRC1 TRC0
1
Bit :
Initial value :
R/W :
Bits 7 to 3: Reserved
When read, 1 is read at all times. Writes are disabled.
Bit 2: Trap Control 2 (TRC2)
Set s ON/ OFF o p e r ation of the address trap function 2.
Bit 2
TRC2 Description
0 Address tr ap f unct ion 2 disabled (Initial value)
1 Address tr ap function 2 enabled
Rev. 2.0, 11/ 00, page 593 of 1037
Bit 1: Trap Control 1 (TRC1)
Set s ON/ OFF o p e r ation of the address trap function 1.
Bit 1
TRC1 Description
0 Address tr ap f unct ion 1 disabled (Initial value)
1 Address tr ap function 1 enabled
Bit 0: Trap Control 0 (TRC0)
Set s ON/ OFF o p e r ation of the address trap function 0.
Bit 0
TRC0 Description
0 Address tr ap f unct ion 0 disabled (Initial value)
1 Address tr ap function 0 enabled
27.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0)
0
0
1
0
R/W
2
0
R/W
34567
R/W
A18 A17 A16
00
R/W
0
R/W R/W
A23 A22 A21
00
R/W R/W
A20 A19
0
0
1
0
R/W
2
0
R/W
34567
R/W
A10 A9 A8
00
R/W
0
R/W R/W
A15 A14 A13
00
R/W R/W
A12 A11
0
—
—
1
0
R/W
2
0
R/W
34567
A2 A1
00
R/W
0
R/W R/W
A7 A6 A5
00
R/W R/W
A4 A3
0
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C)(n = 2 to 0)
The TAR sets the address to trap. The function of the TAR2 to TAR0 is the same.
The TAR is initialized to H'00 by a reset.
Rev. 2.0, 11/ 00, page 594 of 1037
TARA bits 7 to 0: Addresses 23 to 16 (A23 to A16)
TARB bits 7 to 0: Addresses 15 to 8 (A15 to A8)
TARC bits 7 to 0: Addresses 7 to 1 (A7 to A1)
If the value installed in this register and internal address buses A23 to A1 match as a result of
compari son, a n i nte rrupt ion oc c urs.
For the address to trap, set to the address where the first byte of an instruction exists. In the case
of other addresses, it may not be considered that the condition has been satisfied.
Bit 0 of thi s regi ster i s fixe d at 0. T he a ddre ss to trap be c ome s an e ven a ddre ss.
The range whe r e c o m pa ri son is m a de i s H' 000000 to H' FFFFFE .
Rev. 2.0, 11/ 00, page 595 of 1037
27.3 Precaution s in Usage
Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur
after the trap instruction has been executed, depending on a combination of instructions
immediately preceding the setting up of the address trap.
If the instruction to trap immediately follows the branch instruction or the conditional branch
instruction, operation may differ, depending on whether the condition was satisfied or not, or the
address to be stacked may be located at the branch. Figures 27.2 to 27.22 show specific
operations.
For information as to where the next instruction prefetch occurs during the execution cycle of
the instruction, see appendix A.5 of this manual or section 2.7 Bus State during Execution of
Instruction of the H8S/2600, H8S/2000 Series Programming Manual. (R:W NEXT is the next
instruction prefetch.)
27.3.1 Basic Operations
After terminating the execution of the instruction being executed in the second state from the
trap address prefetch, the address trap interrupt exception handling is started.
(1) Figure 27.2 shows the operation when the instruction immediately preceding the trap address
is that of 3 states or more of the execution cycle and the next instruction prefetch occurs in
the state before the last 2 states. The address to be stacked is 0260.
Address bus
Interrupt
request
signal
MOV
execution
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Internal
opera-
tion
Data
read Start of exception
handling
Immediately
preceding
Instruction
Address
025E MOV.B @ER3+,R2L
0260 NOP
(ER3 = H'0000)
0262 NOP
0264 NOP
025E 0260 0000 0262
*
*
Trap setting address
The underlines address is the
one to be actually stacked.
Figure 27. 2 Basic O perati ons (1)
Note: In the figure a bove , t he NOP i nst ruction is used as the typical example of instruction
with execution cycle of 1 state. Other instructions with the execution cycle of 1 state
also appl y (E x. MOV. B, Rs, Rd).
Rev. 2.0, 11/ 00, page 596 of 1037
(2) Figure 27.3 shows the operation when the instruction immediately preceding the trap address
is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in
the second state from the last. The address to be stacked is 0268.
Address bus
Interrupt
request
signal
MOV
execution NOP
execution
Start of exception
handling
Immediately
preceding
instruction
Address
0266 MOV.B R2L, @0000
0268 NOP
026A NOP
026C NOP
*
0266 026A0268 0000 026C
Data
read
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Figure 27. 3 Basic O perati ons (2)
(3) Figure 27.4 shows the operation when the instruction immediately preceding the trap address
is that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to
be stacked is 025C.
Address bus
Interrupt
request
signal
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
Start of
exception
handling
Immediately
preceding
instruction
Address
0256 NOP
0258 NOP
025A NOP
025C NOP
025E NOP
*
0256 025C0258 025A 025E
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Figure 27. 4 Basic O perati ons (3)
Rev. 2.0, 11/ 00, page 597 of 1037
27.3.2 Enable
The address trap function becomes valid after executing one instruction following the setting of
the ena bl e bi t of the a ddress trap c ont rol re gi ster (T RCR) t o 1.
029C BSET #0, @TRCR
*029E MOV.W R0, R1
02A0 MOV.B R1L, R3H
02A2 NOP
02A4 CMP.W R0, R1
02A6 NOP
* Trap setting address
After executing the MOV instruction,
the address trap interrupt does not
arise, and the next instruction is
executed.
Figure 27. 5 Enable
27. 3 .3 Bcc Inst r uc t i o n
(1) When the condition is satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is satisfied
by the Bcc i nstruct i on and t he n branc he d, tra nsit ion i s ma de t o t he a ddre ss trap int e rrupt a ft er
executing the instruction at the branch. The address to be stacked is 02A8.
Address bus
Interrupt
request
signal
BEQ
execu-
tion
CMP
execu-
tion
029C 02A8029E 02A6 02AA
029C BEQ NEXT:8
029E NOP
02A0 NOP
02A2 NOP
02A4 NOP
02A6 CMP.W R0, R1
02A8 NOP
(NEXT = H'02A6)
*
Start of
exception
handling
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Fig ur e 27. 6 Whe n the Condi ti on i s Satisfi e d by Bc c Instr uc ti on (8-bi t Di spl ac e me nt)
Rev. 2.0, 11/ 00, page 598 of 1037
(2) When the condition is not satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not
satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address
trap interrupt after executing the trap address instruction and prefetching the next instruction.
The address to be stacked is 02A2.
Address bus
Interrupt
request
signal
029E 02A202A0 02A8 02A4
029E BEQ NEXT:8
02A0 NOP
02A2 NOP
02A4 NOP
02A6 NOP
02A8 CMP.W R0, R1
02AA NOP
(NEXT = H'02A8)
*
BEQ
execu-
tion
NOP
execu-
tion
Start of
exception
handling
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
NEXT:
Fig ur e 27. 7 Whe n the Condi ti on i s Not Satisfi e d by Bc c Instr uc ti on (8-bi t Di spl ac e me nt)
Rev. 2.0, 11/ 00, page 599 of 1037
(3) When condition is not satisfied by Bcc instruction (16-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not
satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address
trap interrupt after executing the trap address instruction (if the trap address instruction is
that of 2 states or more. If the instruction is that of 1 state, after executing two instructions).
The address to be stacked is 02C0.
Address bus
Interrupt
request
signal
Start of
exception handling
02B8 02C002BC 02BE 02C202BA
02B8 BEQ NEXT:16
02BC NOP
02BE NOP
02C0 NOP
02C2 NOP
02C4 NOP
(NEXT = H'02C4)
*
BEQ
execution NOP
execu-
tion
NOP
execu-
tion
Data
fetch Internal
opera-
tion
*
Trap setting address
The underlines address is the
one to be actually stacked.
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NEXT:
Fig ur e 27. 8 Whe n the Condi ti on i s Not Satisfi e d by Bc c Instr uc ti on (16-bi t Di spl ac e me nt)
Rev. 2.0, 11/ 00, page 600 of 1037
(4) When the condition is not satisfied by Bcc instruction (Trap address at branch)
When the trap address is at the branch of the Bcc instruction and the condition is not satisfied
by the Bcc instruction and thus it fails to branch, transition is made into the address trap
interrupt after executing the next instruction (if the next instruction is that of 2 states or
more. If the next instruction is that of 1 state, after executing two instructions). The address
to be stacked is 0262.
Address bus
Interrupt
request
signal
Start of
exception
handling
025C 02620266025E 0260 0264
025C BEQ NEXT:8
025E NOP
0260 NOP
0262 NOP
0264 NOP
0266 CMP.W R0, R1
0268 NOP
(NEXT = H'0266)
BEQ
execution NOP
execu-
tion
NOP
execu-
tion
*
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
NEXT:
Fi g ur e 2 7 . 9 W he n t he Co ndi t i o n i s No t Sa t i sf i e d by B c c Inst r ucti o n
(Trap Address at Branch)
Rev. 2.0, 11/ 00, page 601 of 1037
27. 3 .4 BSR Instr ucti o n
(1) BSR Instruction (8-bit displacement)
When the trap address is the next instruction to the BSR instruction and the addressing mode
is an 8-bit displacement, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02C2.
Address bus
Interrupt
request
signal
BSR execution
Stack
saving
0294 SP-402C20296 SP-2 02C4
0294 BSR @ER0
0296 NOP
0298 NOP
02C2 MOV.W R4, @OUT
02C4 NOP
: :
(@ER0 = H'02C2)
*
Start of
exception handling
BSR
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Fig ur e 27. 10 BSR Instr uc ti on (8-bi t Di spl ac e me nt)
Rev. 2.0, 11/ 00, page 602 of 1037
27. 3 .5 JSR Instr ucti o n
(1) JSR Instruction (Register indirect)
When the trap address is the next instruction to the JSR instruction and the addressing mode
is a register indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02C8.
Address bus
Interrupt
request
signal
JSRexecution
Stack
saving Start of
exception
handling
029A SP-402C8029C SP-2 02CA
029A JSR @ER0
029C NOP
029E NOP
02C8 MOV.W R4, @OUT
02CE NOP
: :
(@ER0 = H'02C8)
*
JSR
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Fi g ur e 2 7 . 1 1 JSR Inst r ucti o n ( Re g i st e r indirect)
(2) JSR Instruction (Memory indirect)
When the trap address is the next instruction to the JSR instruction and the addressing mode
is memory indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02EA.
Address bus
Interrupt
request
signal
JSR execution
Stack
saving
Start of
exception
handling
0294 SP-2 SP-4 02EA006C0296 006E 02EC
0294 JSR @@H'6C:8
0296 NOP
0298 NOP
02EA NOP
02EC NOP
: :
006C H'02EA
: :
*
Data
fetch
JSR
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Fi g ur e 2 7 . 1 2 JSR Inst r ucti o n ( M e m o r y Indirect)
Rev. 2.0, 11/ 00, page 603 of 1037
27. 3 .6 JMP Inst r uc t i o n
(1) JMP I n st r uction (Register indirect)
When the trap address is the next instruction to the JMP i nstruc t ion a nd t he a ddre ssing mode
is a register indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02AA.
Address bus
Interrupt
request
signal
JMP
execution MOV.L
execution
Data
fetch Start of
exception
handling
029A 02A8 02AA02A4029C 02A6 02AC
029A JMP @ER0
029C NOP
029E NOP
02A0 NOP
02A2 NOP
02A4 MOV.L #DATA, ER1
02AA NOP
(@ER0 = H'02A4)
*
JMP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
*Trap setting address
The underlines address is the
one to be actually stacked.
Fi g ur e 2 7 . 1 3 JMP Instruct i o n ( Re g i st e r Indirect)
(2) JMP I n st r uction (Memory indirect)
When the trap address is the next instruction to the JMP i nstruc t ion a nd t he a ddre ssing mode
is memory indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02E4.
Address bus
Interrupt
request
signal
JMP execution
Start of
exception
handling
0294 006C 02E4006C0296 006E 02E6
0294 JMP @@H'6C:8
0296 NOP
0298 NOP
02E4 NOP
02E6 NOP
: :
006C H'02E4
: :
*
Data
fetch Internal
opera-
tion
JMP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Fi g ur e 2 7 . 1 4 JMP Instruct i o n ( M e m o r y Indirect)
Rev. 2.0, 11/ 00, page 604 of 1037
27. 3 .7 RTS Instruc tion
When the trap address is the next instruction to the RTS instruction, transition is made to the
address trap interrupt after reading the CCR and PC from the stack and prefetching the
instruction at the return location. The address to be stacked is 0298.
Address bus
Break interrupt
request signal
RTS execution
Start of
exception
handling
02AC SP 0298SP02AE SP+2 029A
Stack
storing
0296 BSR SUB
0298 NOP
029A NOP
02AC RTS
02AE NOP
*
: :
Internal
opera-
tion
RTS
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Fi g ur e 2 7 . 1 5 RTS Inst r ucti o n
27.3. 8 SLEEP Instr ucti on
(1) SLEEP Instruction 1
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 2 states or more and prefetch does
not occur in the last state, the SLEEP instruction is not executed and transition is made to the
address trap interrupt without going into SLEEP mode. The address to be stacked is 0274.
Address bus
Interrupt
request
signal
Start of
exception
handling
0272 FFF90274 SP-4SP-20276
0272 MOV.B R2L, @FFF8
0274 SLEEP
0276 NOP
0278 NOP
: :
*
Data
write
MOV
execution SLEEP
cancel
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
* Trap setting address
The underlines address is the
one to be actually stacked.
Fig ure 27.16 SLEEP Instr uct i on (1)
Rev. 2.0, 11/ 00, page 605 of 1037
(2) SLEEP Instruction 2
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch
occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP
instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is
made to the exception handling. The address to be stacked is 0264.
Address bus
Interrupt
request
signal
Start of
exception
handling
0260 0262 SP-2 SP-40264
0260 NOP
0262 SLEEP
0264 NOP
0266 NOP
: :
*
NOP
execution SLEEP
execution SLEEP
mode
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Fig ure 27.17 SLEEP Instr uct i on (2)
(3) SLEEP Instruction 3
When the trap address is the next instruction to the SLEEP instruction, this puts in the
SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by
the address trap interrupt and transition is made to the exception handling. The address to be
stacked is 0282.
Address bus
Interrupt
request
signal
Start of
exception h
andling
0280 SP-2 SP-40282
027E NOP
0280 SLEEP
0282 NOP
0284 NOP
: :
*
SLEEP
execution SLEEP mode
SLEEP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
* Trap setting address
The underlines address is the
one to be actually stacked.
Fig ure 27.18 SLEEP Instr uct i on (3)
Rev. 2.0, 11/ 00, page 606 of 1037
(4) SLEEP Instruction 4 (Standby or Watch Mode Setting)
When the trap address is the SLEEP instruction and the instruction immediately preceding
the SLEEP instruction is that of 1 state or 2 states or more and prefetch occurs in the last
state, this puts in the standby (watch) mode after execution of the SLEEP instruction. After
that, if the standby (watch) mode is cancelled by the NMI interrupt, transition is made to
NMI interrupt following the CCR and PC (at the address of 0266) stack saving and vector
reading. However, i f t he a ddre ss trap int e rrupt a ri ses before sta rt ing e xe cut i on of the NMI
interrupt processing, transition is made to the address trap exception handling. The address
to be stacked is the starting address of the NMI interrupt processing.
Address bus
Interrupt
request
signal
Address trap
interruption
0262 0264 0266 SP-2SP-2
0262 NOP
0264 SLEEP
0266 NOP
* Trap setting address
*
SLEEP
execution
NMI
interrupt
Standby
mode
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
Fig ure 27.19 SLEEP Instr uct i on (4) (Standby or Watc h M ode Se tti ng)
Rev. 2.0, 11/ 00, page 607 of 1037
(5) SLEEP Instruction 5 (Standby or Watch Mode Setting)
When the trap address is the next instruction to the SLEEP instruction, this puts in the
standby (watch) mode after execution of the SLEEP instruction. After that, if the standby
(watch) mode is cancelled by the NMI interruption, transition is made to the NMI interrupt
following the CCR and PC (at the address of 0266) stack saving and vector reading.
However, if t he a ddre ss trap int e rrupt a ri ses before sta rt ing e xe cut i on of the NMI inte rrupt
processing, t ransit i on is ma de to t he addre ss trap e xce pt ion ha ndl ing. T he addre ss to be
stacked is the starting address of the NMI interrupt processing.
Address bus
Interrupt
request
signal
Address trap
interrupt
0280 0282 0284 SP-2SP-2
0280 NOP
0282 SLEEP
0284 NOP
* Trap setting address
*
SLEEP
execution
NMI
interruption
Standby
mode
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
Fig ure 27.20 SLEEP Instr uct i on (5) (Standby or Watc h M ode Se tti ng)
27.3.9 Competi ng Interrupt
(1) General Int e rrupt (Int e rrupt ot he r tha n NMI)
When the ATC interrupt request is made at the timing in (1) (A) against the general interrupt
request, the interruption appears to take place in the ATC at the timing earlier than usual,
because higher priority is assigned to the ATC interrupt processing (Simultaneous interrupt
with the general interrupt has no effect on processing). The address to be stacked is 029E.
For comparison, the c ase where t he t ra p addre ss is set at 02A0 if no gene ra l i nt errupt re quest
was made is shown in (2). The address to be stacked is 02A4.
Rev. 2.0, 11/ 00, page 608 of 1037
Address bus
General Interrupt
request signal
Interrupt
request signal
MOV execution
Data
write
Data
write
Start of general
interrupt processing
Range of start of ATC
interrupt processing
(1)
029C NOP
0296 MOV.B R2L, @Port
029A NOP
029E NOP
02A0 NOP
02A2 NOP
02A4 NOP
0296 Port 029E SP-2 SP-4
Vector Vector
0298
NOP
execu-
tion
NOP
execu-
tion
MOV execution
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
029A 029C 02A0
Address bus
Interrupt
request
signal
Data
read
Data
read
Start of ATC interrupt
processing
Set one of these to the
trap address
(2)
029C NOP
0296 MOV.B R2L, @Port
029A NOP
029E NOP
02A0 NOP Trap address
02A2 NOP
02A4 NOP
0296 Port 029E0298 02A0 02A2 02A4 SP-2029A 029C 02A6
(A)
MOV
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Address
to be
stacked
Figure 27.21 Competing Interrupt (General Interrupt)
Rev. 2.0, 11/ 00, page 609 of 1037
(2) In case of NMI
When the NMI interruption request is made at the timing in (1) (A) against the ATC
interrupt request, the interrupt appears to take place in NMI at the timing earlier than usual,
because higher priority is assigned to the NMI interrupt processing. The ATC interrupt
processing starts after fetching the instruction at the starting address of the NMI interrupt
processing. The address to be stacked is 02E0 for the NMI and 340 for the ATC.
When the ATC interrupt request is made at the timing in (2) (B) against the NMI interrupt
request, the ATC interrupt processing starts after fetching the instruction at the starting
address of the NMI interrupt processing. The address to be stacked is 02E6 for the NMI and
0340 for the ATC.
Rev. 2.0, 11/ 00, page 610 of 1037
Address bus
NMI interrupt
request signal
ATC interrupt
request signal
Start of ATC inter-
rupt processing
(1)
02E0 NOP
02DC NOP
02DE NOP
02E2 NOP
02E4 NOP
02E6 NOP
02E8 NOP
02DC SP-4 0340 SP-6 SP-8
VectorVector VectorVector
02DE
NMI vector
read
02E0 0342SP-202E2
(2) Set one of these to
the trap address
(1) Set to the trap address
*
NMI interrupt
processing Start of ATC interrupt processing
Address bus
NMI interrupt
request signal
ATC interrupt
request signal
Start of ATC
Interrupt processing
(2)
02DC 02E2 02E4 SP-4SP-2 0340
Vector Vector Vector
02DE 02E0 034202E6 02E8
(B)
(A)
NMI interrupt
processing
: :
0340 The starting address of NMI
interrupt
: :
NOP
execu-
tion
NOP
execu-
tion
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Fi g ur e 2 7 . 2 2 Com pe t i ng Int e r rupt ( In Case of NMI)
Rev. 2.0, 11/ 00, page 611 of 1037
Section 28 Servo Circuits
28.1 Overview
28.1.1 Functions
Servo circuits for a video cassette recorder are included on-chip.
The funct i ons of the servo c i rcui t s can be di vide d i nto four groups, as li ste d in t a ble 28. 1.
Table 28.1 Servo Circuit Functions
Group Function Description
CTL I/O am plifier Gain variable input amplifier
Out put am plifier with r ewrit e m ode
CFGDuty compensat ion
input Duty accuracy: 50±2%
(Zero cr oss t ype com par ator)
DFG, DPG
separation/ over lap input Ov er lap input available: Three- level input
method, DFG noise m ask f unct ion
Reference signal
generators V compensation, field detection, ext er nal signal
sync, V sync when in REC mode, REF30 signal
output t o out side
HSW timing generat or Head-switching signals, FIFO 20 st ages
Compatible with DFG counter soft-r eset
Four-head high- speed
switching circuit for
special playback
Chroma- r ot ar y/head-am plifier switching output
12-bit PWM Impr oved speed of car r ier frequency
Frequency division
circuit With CFG mask, no CFG f or phase or CTL
mask
(1) Input and output
circuits
Sync detection circuit Noise count, field discrimination, Hsync
compensation, Hsync detect ion noise mask
Drum speed er r or
detector Lock detector function, pause at the counter
overflow, R/W error latch register, limiter function
Drum phase er r or
detector Latch signal selectable, R/W error latc h r egister
Capstan speed err or
detector Lock detector function, pause at the counter
overflow, R/W error latch register, limiter function
Capstan phase err or
detector R/ W er r or lat ch r egister
(2) Error detectors
X-value adjustment and
tracking adjustm ent
circuit
(Separat e set t ing available)
(3) Phase and gain
compensation Digital filt er co mputat io n
circuit Computations per f or m ed aut om at ically by
hardware
Output gain variable: × 2 to × 64 (exponents of 2)
(Part ial write in Z-1 ( high- or der 8 bits ) available)
Additional V signal
circuit Valid when in special playback(4) Ot her circ uits
CTL circuit Duty discrimination circuit, CTL head R/W
control, compatible with wide aspect
Rev. 2.0, 11/ 00, page 612 of 1037
28.1.2 Block Diagram
Figure 28.1 shows a block di agra m of the servo c irc ui ts.
Rev. 2.0, 11/ 00, page 613 of 1037
4-head
special
playback
controller
- +
SV1(P82)
EXCAP(P81)
( )
SV2(P83)
( )
EXCTL(PS4)
)
+
+
+
+
+
- +
+ -
-
CTL
Head
CTL Amp
CTL
Head
CFG
CA P
PWM
DRM
PWM
DFG
DPG(PS3)
VIDEOFF
AUDIOFF
Vpulse
H.Amp SW(PS1)
C.ROTARY(PS0)
COMP(PS2)
Csync
EXTTRG/(P80)
OSCH
REC:ON
ADTRIG
(HSW)
Ep
PWM
Es
Es
Ep
REC
REC
PB.ASM
CTLFB
PB.CTL
PB.
ASM
(NTSC)
DVCTL
Gain control
by register
setting
REF30,REF30X,CREF,
CTLMONI,DVCFG,
DFG,DPG,DFG,etc
Internal signal
monitor
controller
(PAL)REF30X
REC-CTL
DutyI/O
(Duty deter-
minator) (Assemble
recording)
DVCFG
DVCFG2
Gain up.
XE:ON
VD
PR0 to 7/
(P60 to 67)
Sync
detector
REC-CTL
generator
VISS
circuit
Noise
Det.
A/D
converter
Timer X1
Timer L
Timer R
AN pins
PWM
X-value
adjustment
Gain up.
PR0 to 7/
(P60 to 67)
PPG0 to 7/
(P70 to 77)
PPG0 to 7/
(P70 to 77)
REF30P(PB:30Hz,REC:1/2VD)
CREF
Res
System
clock
Additional
V pulse
generator
Head-switch
timing
generator
Drum system
reference
signal
Capstan
system
reference
signal
Phase
error
detector
Phase
error
detector
Digital
filter
Digital
filter
Digital
filter
Digital
filter
Frequency
divider
Frequency
divider
Speed
error
detector
Speed
error
detector
Figure 28.1 Block Diagram of Servo Circuits
Rev. 2.0, 11/ 00, page 614 of 1037
28.2 Servo Port
28.2.1 Overview
This LSI is equipped with seventeen pins dedicated to servo module and twenty-five dual-
purpose pins used also for general-purpose port. It has also built-in input amplifier to amplify
CTL signals, CTL output amplifier, CTL Schmitt comparator, and CFG zero cross type
comparator. The CTL input amplifier allows gain adjustment by software. DFG a n d DPG
signals, which are the signals to control the drum, allow selection between separate or overlap
input.
SV1 and SV2 pins allow to output to monitor the inside signals of the servo section. The signals
to be output can be selected out of eight kinds of signals. See section 28.2.5 (4), Servo Monitor
Control Re gi st er (SVMCR).
28.2.2 Block Diagram
(1) DFG and DPG i nput c i rc ui t s
The DFG and DPG i nput pi ns ha ve on-c hi p Sc hmitt circuits. Figure 28.2 shows the input
ci r c u i t s o f DFG a n d DPG.
DPG SW
DFG
DPG
DFG
DPG
DPG SW
RES+LPM
Fi g ur e 2 8 . 2 Input Circuits of DFG and DPG
Rev. 2.0, 11/ 00, page 615 of 1037
(2) CFG Input Circuit
The CFG input pin has built-in an amplifier and a zero cross type comparator. Figure 28.3
shows the input circ ui t of CFG.
+
-
+
-
+
-
CFGCOMP
CFGCOMP
P250
REF
M250 S
R
F/F
O
stp
VREF
VREF
CFG
BIAS
CFG RES+ModuleSTOP
Fi g ur e 2 8 . 3 CF G Input Circuit
Rev. 2.0, 11/ 00, page 616 of 1037
(3) CTL Input Ci rc uit
The CTL input pin has built-in an amplifier. Figure 28.4 shows the input circuit of CTL.
-
+
+
-
CTLFB
CTLSMT(i)CTLFBCTLREF CTLBias
CTLGR0CTLGR3 to 1
AMPSHORT
(REC-CTL)
PB-CTL(+)
Note: Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i)
Note
PB-CTL(-)
AMPON
(PB-CTL)
- +
CTLAmp(o)CTL(+)CTL(
-
)
Fi g ur e 2 8 . 4 CT L Input Circuit
Rev. 2.0, 11/ 00, page 617 of 1037
28.2.3 Pin Configuration
Table 28.2 shows the pin configuration of the servo section. P6n, P7n, P80 to P38, and PS1 to
PS4 are general-purpose ports. As for P6, P7, and P8, see section 10, I/O Port.
Table 28.2 Pin Configuration
Name Abbrev. I/O Function
Servo Vcc pin SVCC Input Power source pin for servo section
Servo Vss pin SVSS Input Power source pin for servo section
Audio head switching pin Audio FF Output Audio head switching signal output
Video head switching pin Video FF Output Video head switching signal output
Capstan m i x pin CAPPWM Output 12-bit PWM square wave output
Drum mix pin DRMPWM Output 12-bit PWM square wave output
Additional V pulse pin Vpulse Output Additional V signal output
Color rotary signal output pin C.Rotary/PS0 Output, I/O Control signal output port for processing
color signals/general-purpose port
Head amplifier switching pin H.Amp. SW/
PS1 Output, I/O Pre-amplifier output selection signal
output/general-purpose port
Compare signal input pin COMP/PS2 Input, I/O Pre-amplifier output result signal
input/general-purpose port
CTL (+) I/O pin CTL (+) I/O CTL signal input/output
CTL (−) I/O pin CTL (-) I/O CTL signal input/output
CTL Bias input pin CTLBias Input CTL primary amplifier bias supply
CTL Amp (O) output pin CTLAMP (O) Output CTL amplifier output
CTL SMT (i) input pin CTLSMT (I) Input CTL Schmitt amplifier input
CTL FB input pin CTLFB Input CTL amplifier high-range characteristics
control
CTL REF output pin CTLREF Output CTL amplifier reference voltage output
Capstan FG amplifier input pin CFG Input CFG signal amplifier input
Drum FG input pin DFG Input DFG signal input
Drum PG input pin DPG/PS3 Input, I/O DPG signal input/general-purpose port
External CTL signal input pin EXCTL/PS4 Input, I/O External CTL signal input/general-purpose
port
Complex sync signal input pin Csync Input Complex sync signal input
External reference signal input
pin P80/EXTTRG I/O, input General-purpose port/external reference
signal input
External capstan signal input pin P81/EXCAP I/O, input General-purpose port/external capstan signal
input
Servo monitor signal output pin 1 P82/SV1 I/O, output General-purpose port/servo monitor signal
output
Servo monitor signal output pin 2 P83/SV2 I/O, output General-purpose port/servo monitor signal
output
PPG output pin P7n/PPGn I/O, output General-purpose port/PPG output
RTP output pin P6n/RPn I/O, output General-purpose port/RTP output
Rev. 2.0, 11/ 00, page 618 of 1037
28.2.4 Register Configuration
Table 28.3 shows the register configuration of the servo port section.
Table 28.3 Register Configuration
Name Abbrev. R/W Size Initi al Value Address
Servo port m ode r egist er SPMR R/W Byte H'40 H'FD0A0
Servo contr ol r egister SPCR W Byte H'E0 H'FD0A1
Servo data r egist er SPDR R/ W Byte H'E0 H'FD0A2
Servo monitor contr ol regist er SVMCR R/W Byt e H'C0 H'FD0A3
CTL gain control register CTLGR R/W Byte H'C0 H'FD0A4
28.2.5 Register Descriptions
(1) Servo Port Mode Register (SPMR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
—
—
7EXCTLON DPGSW COMP
H.Amp.SW
C.Rot
0
R/W
CTLSTOP
R/WR/W
CFGCOMP
1
Bit :
Initial value :
R/W :
A register to switch the servo port/general-purpose port, and the CFG input system.
SPMR is an 8-bi t re a d/ write register. Bit 6 is reserved; writing in it is invalid. If read is
attempted, an undetermined value is read out. It is initialized to H'40 by a reset or stand-by.
Bit 7: CTLSTOP Bit (CTLSTOP)
Controls whether the CTL circuits are operated or stopped.
Bit 7
CTLSTOP Description
0 CTL circuits operate (Initial value)
1 CTL circuits stop oper at ion
Bit 6: Reserved
This bit is reserved. It cannot be written or read. If read is attempted, an undetermined value is
read out.
Rev. 2.0, 11/ 00, page 619 of 1037
Bit 5 : CFG Input Sy st e m Swi t c hi ng B i t (CFGCOMP)
Selects whether the CFG input signal system is set to the zero cross type comparator system or
digital signal input system.
Bit 5
CFGCOMP Description
0 CFG signal input syst em is set t o t he zer o cr oss type compar at or syst em
(Init ial value)
1 CFG signal input syst em is set to the digital signal input system
Bit 4: EXCTL Pin Switching Bit (EXCTLON)
Selects whether the EXCTL/PS4 pin is used as the EXCTL input pin or PS4 (general-purpose
I/O pin).
Bit 4
EXCTLON Description
0 EXCTL/ PS4 pin funct ions as EXCTL input pin (Initial value)
1 EXCTL/ PS4 pin funct ions as PS4 I/O
Bit 3: DPG Pi n Switching Bit (DPGSW)
Selects the drum control system input signals (DFG, DPG) as sep a r ate or overlapped inputs.
Bit 3
DPGSW Description
0 Drum control system input s ar e separ at e inputs (Init ial value)
(DPG/PS3 pin funct ions as DPG input pin)
1 Drum control system input s ar e over lapped inputs
(DPG/PS3 pin functions as PS3 I/O pin)
Bit 2: COMP Pin Switching Pin (COMP)
Selects whether the COMP/PS2 pi n is use d a s the COMP i nput pi n or PS2 (gene ra l -purpose I/ O
pin).
Bit 2
COMP Description
0 COMP/PS2 pin functions as COMP input pin (Initial value)
1 COMP/PS2 pin functions as PS2 I/O pin
Rev. 2.0, 11/ 00, page 620 of 1037
Bit 1: H. Amp SW Pin Switching Bit (H.Amp.SW)
Selects whether the H.Amp SW/PS1 pin is used as the H.Amp SW output pin or PS1 (general-
purpose I/O pin).
Bit 1
H.Amp.SW Description
0 H.Amp SW/PS1 pin functions as H.Amp SW output pin ( I nitial value)
1 H.Amp SW/PS1 pin functions as PS1 I/O pin
Bit 0: C.Rotary Pi n Switching Bit (C.Rot)
Selects whether the C.Rotary/PS0 pin is used as the C.Rotary output pin or PS0 (general-purpose
I/O pin).
Bit 0
C.Rot Description
0 C.Rotary/PS0 pin functions as C.Rotar y out put pin (Initial value)
1 C.Rotary/PS0 pin functions as PS0 I/O pin
(2) Serv o Cont r o l Regi st e r ( SP CR)
0
0
1
0
W
2
0
W
3
0
4
0
W
567 ———
———
SPCR4 SPCR3 SPCR2 SPCR1 SPCR0
WW
111
Bit :
Initial value :
R/W :
Controls input and output of each pin (PS4 to PS0) for each bit when the servo port/general-
purpose port dual-purpose pi n i s used as the ge ne ral -purpose port . If SPCR is set to 1, the
corresponding PS4 to PS0 pins function as output pins; if cleared to 0, they function as input
pins. Settings of SPCR and SPDR are v alid if the corresponding pins are set to general-purpose
I/O b y SPMR.
SPCR is an 8-bit write-only register. If read is attempted, an undetermined value is read out.
Bits 7 to 5 are reserved bits. Writes are disabled.
SPCR is initialized to H'E0 by a reset or stand-by.
Bit n
SPCRn Description
0 PSn pin f unct ions as input (Init ial value)
1 PSn pin f unct ions as out put
Rev. 2.0, 11/ 00, page 621 of 1037
(3) Servo Data Register (SPDR)
0
0
1
0
2
0
3
0
4
0
567 ———
———
SPDR4 SPDR3 SPDR2 SPDR1 SPDR0
111R/WR/WR/W R/WR/W
Bit :
Initial value :
R/W :
Stores the data of each pin (PS4 to PS0) when the servo port/general-purpose dual-purpose pin is
used as general-purpose port. If the port is accessed for read when SPCR is 1 (output), the
SPDRn value is read directly. Accordingly, this register is not affected by the state of the pin. If
the port is accessed for read when SPCR is 0 (input), the state of the pin is read out.
SPDR is an 8-bi t re a d/ write register. Bits 7-5 are reserved. No write in it is valid. If read is
attempted, an undetermined value is read out.
SPCR is initialized to H'E0 by reset or stand-by.
Rev. 2.0, 11/ 00, page 622 of 1037
(4) Serv o M o ni t or Control Regi st e r ( SVM CR)
0
0
1
0
2
0
3
0
4
0
567 ——
——
SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0
11 R/WR/WR/W
0
SVMCR5
R/W R/WR/W
Bit :
Initial value :
R/W :
Selects the monitor signal output to the SV1 and SV2 pins when the P82/SV1 pin is used as the
SV1 monitor output pi n or when t he P83/SV2 pin is used as the SV2 monit or output pi n.
SVMCR is an 8-bit read/write register. Bits 7 and 6 are reserved. Writes are disabled. If read is
attempted, an undetermined value is read out. It is initialized to H'C0 by a reset or stand-by.
Bit 5 Bit 4 Bit 3
SVMCR5 SVMCR4 SVMCR3 Description
0 O ut put s REF30 signal to SV2 output pin (I nit ial value)0
1 O ut put s CAPREF30 signal t o SV2 output pin
0 O ut put s CREF signal to SV2 output pin
0
1
1 Outputs CTLMO NI signal to SV2 output pin
0 Outputs DVCFG signal to SV2 output pin0
1 Outputs CFG signal to SV2 output pin
0 Outputs DFG signal to SV2 output pin
1
1
1 Outputs DPG signal to SV2 output pin
Bit 2 Bit 1 Bit 0
SVMCR2 SVMCR1 SVMCR0 Description
0 O ut put s REF30 signal to SV1 output pin (I nit ial value)0
1 O ut put s CAPREF30 signal t o SV1 output pin
0 O ut put s CREF signal to SV1 output pin
0
1
1 Outputs CTLMO NI signal to SV1 output pin
0 Outputs DVCFG signal to SV1 output pin0
1 Outputs CFG signal to SV1 output pin
0 Outputs DFG signal to SV1 output pin
1
1
1 Outputs DPG signal to SV1 output pin
Rev. 2.0, 11/ 00, page 623 of 1037
(5) CTL Gain Control Register (CTLGR)
0
0
1
0
2
0
3
0
4
0
567 ——
——
CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0
11 R/WR/WR/W
0
CTLE/
R/W R/WR/W
Bit :
Initial value :
R/W :
Sets the CTLFB switch in the CTL amplifier circuit to on/off and CTL amplifier gain.
CTLGR is an 8-bit read/write register. Bits 7 and 6 are reserved. No write in it is valid. If read
is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset or stand-by.
Bit 7 to 6: Reserved
Reserved bits; writes are disabled. If read was attempted, an undetermined value is read out.
Bit 5: CTL Selection Bit (CTLE/
$
$
)
Controls whether the amplifier output or EXCTL is used as the CTLP signal supplied to the CTL
circuit.
Bit 5
CTLE/
$
$
Description
0 AMP output (Init ial value)
1 EXCTL
Bit 4: SW Bit of the Feedback Section of CTL Amplifier (CTLFB)
Turning on/off the SW of the feedback section allows adjustment of gain.
See figure 28. 4, CT L Input Ci rc uit .
Bit 4
CTLFB Description
0 Turns off CTLFB SW ( Initial value)
1 Turns on CTLFB SW
Rev. 2.0, 11/ 00, page 624 of 1037
Bits 3 to 0: CTL Amplifier Gain Setting Bits (CTLGR3 to 0)
Set the output gain of the CTL amplifier.
Bit 3 Bit 2 Bit 1 Bit 0
CTLGR3 CTLGR2 CTLGR1 CTLGR0 CTL Out put G ain
0 34.0 dB (Init ial value)0
1 36.5 dB
0 39.0 dB
0
1
1 41.5 dB
0 44.0 dB0
1 46.5 dB
0 49.0 dB
0
1
1
1 51.5 dB
0 54.0 dB0
1 56.5 dB
0 59.0 dB
0
1
1 61.5 dB
0 64.0 dB*
0
1 66.5 dB*
0 69.0 dB*
1
1
1
1 71.5 dB*
Note: *With a set t ing of 64. 0 dB or m ore, t he CTLAMP is in a very sensitive st at us. W hen
configuring the set board, be concer ned about count er measure against noise around
the cont r ol head signal input port. Also, thor oughly set the filter bet ween t he CTLAMP
and CTLSMT.
Rev. 2.0, 11/ 00, page 625 of 1037
28.2.6 DFG/DPG Input Signals
DFG and DPG si g n a l s allow either separate or overlapped input. If the latter was selected
(DPGSW = 1), ta ke c a r e i n t he i nput l e v e l s of DFG and DPG. Figure 28.5 shows DFG/DPG
input signal s.
DPG DPG Schmitt level
3.45/3.55
V
IL
/V
IH
DFG Schmitt level
1.85/1.95
V
IL
/V
IH
DFG
(1) DPG/DFG separate input (DPGSW=0)
DPG Schmitt level
DFG/DPG
(2) DPG/DFG overlapped input (DPGSW=1)
DFG Schmitt level
Figure 28.5 DFG/DPG Input Sig na l s
Rev. 2.0, 11/ 00, page 626 of 1037
28.3 Reference Signal Gen erat ors
28.3.1 Overview
The refe re nce signa l ge ne rat ors consist of RE F30 signal ge ne rat or a nd CREF signal ge nera t or,
and they create the reference signals (REF30 and CREF signals) used in phase comparison, etc.
The REF30 signal i s used to cont rol the pha se of the drum and c a pstan. T he CREF signal i s
used if the re fe renc e signal t o cont rol the pha se of the c apsta n c annot be shared wit h t he RE F30
signal in REC mode. Each signal generator consists of a 16-bit counter which has the servo
clock φ s/2 (or φ s/4) as its clock source, a reference period register and a comparator.
The val ue set i n t he re fe renc e peri od re giste r should be 1/2 of t he desire d re fere nc e signa l
period.
28.3.2 Block Diagram
Figure 28.6 shows the bloc k dia gra m of t he REF30 signal ge nera t or. Figure 28. 7 shows that of
the CREF signal ge nera t or.
Rev. 2.0, 11/ 00, page 627 of 1037
s = fosc/2
s/2
s/4
Dummy read
External
frequency
signal
(EXTTRG)
Field
detection
signal
WW WW
WW
PB REC
PB ,
ASM
REC/PB V noise detection signal
REF30
REF30P
Video FF
VD
Match
Mask Clear
WR/W W
Internal bus
R/W
Internal bus
Toggle
RCS
REF30 counter register (16 bit)
OD/EV VST
FDS VEG
Edge
detec-
tion
Edge
detec-
tion
VNA
R/W
*
TBC CVSREX
Reference period buffer 1 (16 bit)
Reference period register 1 (16 bit)
Comparator (16 bit)
Counter (16 bit)
Note:* The TBC bit is available only in the H8S/2194C Series.
Figure 28. 6 REF30 Signal G e nerator
Rev. 2.0, 11/ 00, page 628 of 1037
s/2
s/4
WW
CREF
DVCFG2
PB(ASM)
REC
Match
Clear
Counter clear
Toggle
Edge
detection
CRD
W
RCS
Reference period register 2 (16 bit)
Reference period buffer 2 (16 bit)
Comparator (16 bit)
Counter (16 bit)
Internal bus
S
R
Q
Dummy read
s = fosc/2
Figure 28. 7 Bl oc k Diagram of CREF Signal Gener ator
28.3.3 Register Configuration
Table 28.4 shows the register configuration of the reference signal generators.
Table 28.4 Register Configuration
Name Abbrev. R/W Si z e Ini t ial Value Address
Reference per iod mode
register RFM W Byte H'00 H'FD096
Refer ence period register 1 RFD W W or d H'FFFF H'FD090
Refer ence period register 2 CRF W Wor d H'FFFF H'FD092
REF30 counter regist er RFC R/ W Wor d H'0000 H'FD094
Reference per iod mode
register 2 RFM2 R/W Byte H'FE H'FD097
Rev. 2.0, 11/ 00, page 629 of 1037
28.3.4 Register Descriptions
(1) Reference Period Mode Register (RFM)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7REX CRD OD/EV VST VEG
0
W
RCS
WWW
VNA CVS
Bit :
Initial value :
R/W :
RFM is an 8-bit write-only register which determines the operational state of the reference signal
generators. If a read is attempted, an undetermined value is read out.
It is initialized to H'00 by a reset, stand-by or module stop.
RFM is accessible by byte access only. If accessed by a word, its operation is not assured.
Bit 7: Clock Source Selection Bit (RCS)
Selects the clock source supplied to the counter. (φs = fosc/2)
Bit 7
RCS Description
0φs/ 2 (Init ia l v a lu e)
1φs/4
Bit 6: Mode Selection Bit (VNA)
Selects whether the transition to free-run operation when the REF30 signals are being generated
in sync with the VD signals in REC mode is controlled automatically by the V noise detection
signal, which has been detected by the sync signal detection circuit, or is controlled manually by
software.
Bit 6
VNA Description
0 Manual mode (Init ial value)
1 Auto mode
Rev. 2.0, 11/ 00, page 630 of 1037
Bit 5: Manual Selection Bit (CVS)
Selects whether the REF30 signals are generated in sync with VD or operated free-run in manual
mod e ( VNA = 0 ) . ( No selection is reflected in PB mode, except in TBC mode.)
Bit 5
CVS Description
0 Sync with VD (Init ial value)
1 Free- r un oper at ion
Bit 4: External Signals Sync Selection Bit (REX)
Selects whether the REF30 signals are generated in sync with VD or in free-run or in sync with
the external signals. (Valid in both PB and REC modes.)
Bit 4
REX Description
0 VD signals or f r ee- r un (Initial value)
1 Sync with external signals
Bit 3: DVCFG2 Sync Selection Bit (CRD)
Selects whether the reset timing in the CREF signals generation is immediately after switching
from PB (ASM) mode t o RE C m ode or i s i n sync wit h t he DVCFG2 si gna l s immediately after
the switching.
Bit 3
CRD Description
0 On switching modes (Init ial value)
1 In sync with DVCFG2 signals
Bit 2: ODD/EVEN Edge Switching Selection Bit (OD/EV)
Selects whether REF30P signals are generated by ODD of the f ield signals or EVEN when in
REC mode.
Bit 2
OD/EV Description
0 Generated at the rising edge ( EVEN) of the field signals (Init ial value)
1 Generated at the falling edge (ODD) of the field signals
Rev. 2.0, 11/ 00, page 631 of 1037
Bit 1 : Vide o FF Co unt e r Set (VST )
Selects whether the REF30 counter register value is set on or off by the Video FF signal when
the drum pha se i s in FIX on in PB mode.
Bit 1
VST Description
0 Counter set off by Video FF signal (Initial value)
1 Counter set on by Video FF signal
Bit 0: Video FF Edge Selection Bit (VEG)
Selects the edge at which the REF30 counter is set (VST = 1) by the Video FF signal.
Bit 0
VEG Description
0 Set at t he r ising edge of Video FF signal ( I nit ial value)
1 Set at t he f alling edge of Video FF signal
Rev. 2.0, 11/ 00, page 632 of 1037
(2) Reference Period Register 1 (RFD)
15
1
REF15
W
14
1
REF14
W
13
1
REF13
W
12
1
REF12
W
11
1
REF11
W
10
1
REF10
W
9
1
REF9
W
8
1
REF8
W
7
1
REF7
W
6
1
REF6
W
5
1
REF5
W
4
1
REF4
W
3
1
REF3
W
2
1
REF2
W
1
1
REF1
W
0
1
REF0
W
Bit :
Initial value :
R/W :
The reference period register 1 (RFD) is a buffer register which generates the reference signals
for playback (REF30), VD compensation for recording and the reference signals for free-
running. It is a 16-bit write-only register accessible by a word only. If a read is attempted, an
undetermined value is read out.
The val ue set i n RFD should be 1/2 of t he de sire d refe re nce signa l pe ri od. Care i s require d when
VD is unstable, such as when the field is weak (Synchronization with VD cannot be acquired if a
value less than 1/2 is set when in REC). When data is written in RFD, it is stored in the buffer
once, and then fetched into RFD by a match signal of the comparator. (The data which
generates the reference signal is updated from time to time by the match signal.) An enforced
write, such as initial setting, etc., should be done by a dummy read of RFD.
If a byte-write in RFD is attempted, no operation is assured. RFD is initialized to H'FFFF by a
reset, stand-by, or m odul e stop.
Use bit 7 ( ASM) a n d b i t 6 (R E C / PB ) i n t h e C T L mode re g i st er ( CTLM) i n t h e C T L circ u i t to
switch between record and playback modes. Use bit 4 (CR/RF bit) in the capstan phase error
detection control register (CPGCR) to switch between REF30 and CREF for capstan phase
control.
Rev. 2.0, 11/ 00, page 633 of 1037
(3) Reference Period Register 2 (CRF)
15
1
CRF15
W
14
1
CRF14
W
13
1
CRF13
W
12
1
CRF12
W
11
1
CRF11
W
10
1
CRF10
W
9
1
CRF9
W
8
1
CRF8
W
7
1
CRF7
W
6
1
CRF6
W
5
1
CRF5
W
4
1
CRF4
W
3
1
CRF3
W
2
1
CRF2
W
1
1
CRF1
W
0
1
CRF0
W
Bit :
Initial value :
R/W :
The reference period register 2 (CRF) is a 16-bit write-only buffer register which generates the
reference signals to control the capstan phase (CREF). CRF is accessibly by a word only. If a
read is attempted, an undetermined value is read out. The value set in CRF should be 1/2 of the
desired refe re nce signa l pe ri od.
When data is written in CRF, it is stored in the buffer once, and then fetched into CRF by a
match signal of the comparator. (The data which generates the reference signal is updated from
time to time by the match signal.) An enforced write, such as initial setting, etc. , should be done
by a dummy re a d of CRF.
If a byte-write in CRF is attempted, no operation is assured. CRF is initialized to H'FFFF by a
reset, stand-by, or m odul e stop.
Use bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR) to switch
between REF30 and CREF for capstan phase control. (See section 28.9, Capstan Phase Error
Detector)
(4) RE F 3 0 Count e r Reg i st e r (RF C)
15
0
RFC15
14
0
RFC14
13
0
RFC13
12
0
RFC12
11
0
RFC11
10
0
RFC10
9
0
RFC9
8
0
RFC8
7
0
RFC7
6
0
RFC6
5
0
RFC5
4
0
RFC4
3
0
RFC3
2
0
RFC2
1
0
RFC1
0
0
RFC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit :
Initial value :
R/W :
The REF30 counter register (RFC) is a register which determines the initial value of the free-run
counter when it generates REF30 signals when in playback. When data is written in RFC, its
value is written in the counter by a match signal of the comparator. If bit 1 (VST) in RFM is set
to 1, t he c ount er i s set by t he Vide o FF signal when t he drum pha se is in FIX ON. The c ounte r
setting by the Video FF signal should be done by setting RFM's bit 1 (VST) and bit 0 (VEG).
Don't set the RFC value at a value greater than 1/2 of the reference period register 1 (RFD).
RFC is a read/write register. If a read is attempted, the value of the counter is read out. If a
byte-access is attempted, no operation is assured. RFC is initialized to H'0000 by a reset, stand-
by, or modul e stop.
Rev. 2.0, 11/ 00, page 634 of 1037
(5) Reference Period Mode Register 2 (RFM2)
0
0
1
1
2
1
3
1
4
1
567 ——————(TBC)
——————
(R/W)*
FDS
111 R/W
Bit :
Initial value :
R/W :
Note:* Writable only in the H8S/2194C Series.
RFM2 is an 8-bit read/write register which determines the operational state of the reference
signal generators. Bits 7 to 1 are reserved. If a read is attempted, an undetermined value is read
out.
It is initialized to H'FE by a reset, stand-by or module stop. RFM2 is a byte access-only register;
if accessed by a word, no operation is assured.
Bits 7: TBC Selection Bit (TBC)
Selects whether the reference signals are generated by VD or in free-run in PB mode.
Bit 7
TBC Description
0 Reference signals are generat ed by VD (This funct ion is eff ect ive only in the
H8S/2194C series)
1 Reference signals are gener at ed in f r ee- r un (Initial value)
Bits 6 to 1: Reserved
No write is valid. If a read is attempted, an undetermined value is read out.
Bit 0: Field Selection Bit (FDS)
Determines whether selection between ODD or EVEN is ma de for t he f ield signals when PB
mode was switched over to REC mode, or these signals are synchronized with VD signals within
phase error of 90° immediately after the switching over.
Bit 0
FDS Description
0 Generated by the VD signal of ODD or EVEN selec t ed ( I nitial value)
1 Gener at ed by the VD signal within m ode t r ansit ion phase err or of 90 °
Rev. 2.0, 11/ 00, page 635 of 1037
28.3.5 Description of Operation
(1) Operation of RE F30 Signal Genera t ors
The REF30 signal generators generate the reference signals required to control the phase of
the drum a nd c apsta n.
To generate REF30 signals, set the half-period value to the reference period register 1 (RFD)
corresponding to the 50% duty cycle. When in playback, REF30 signals are generated by
operati ng RE F30 signal ge ne rat or i n free -run. T he ge ne rat or ha s the e xt erna l signal
synchronization function built-in, and if bit 4 (REX) of the reference period mode register
(RFM) is set to 1, it generates REF30 signals from external signals (EXTTRG).
In record mode, the reference signals are generated from the VD signal generated in the sync
signal detection circuit. Any VD drop-out caused by weak field intensity, etc., is
compensated by a set value of RFD. To cope with the VD noises, the generator performs
automatically the VD masking for a time period about 75% of the RFD setting after REF30
signal was changed due to VD. In record mode, the generation of the reference signals either
by VD or free-run operation can be controlled automatically or by software, using the V
noise detection signal detected in the sync signal detection circuit. Select which is used by
setting bit 6 (VNA) or 5 ( C VS) o f RFM.
The phase of the toggle output of the REF30 signal is cleared to L level when the signal
mode t ra n si ts from PB t o RE C (ASM). Al so t he frame servo function can be set, allowing to
control the phase of REF30 signals with the field signal detected in the sync signal detection
circui t . Use bit 2 (OD/EV) of RFM for such control.
See section 28.13.5(2), CTL Mode Register (CTLM) as for switching over between PB,
ASM and R E C .
(2) Operation of t he Mask Circui t
The REF30 signal ge nera t ors have a t oggle m ask ci rc uit a nd count e r ma sk (count er set signa l
mask) circuit built-in. Each mask circuit masks irregular VD signals which may occur when
the VD signal is unstable because of weak field intensity, etc., in record mode.
The toggle mask and counter mask circuits mask the VD automatically for about 75% of
double the time period set in the reference period register 1 (RFD) after a VD signal was
detected (see figure 28.9). If a VD si gnal dropped out and V was compensated, the toggle
mask circ ui t be gi ns masking. T he count e r ma sk ci rcui t does not do so for about 25% of t he
time period. If a VD signal was detected during such time period, it does masking for about
75% of the time period. If not detected, it does for the same time period after V was
compensated (see figures 28.10 and 28. 11).
Rev. 2.0, 11/ 00, page 636 of 1037
(3) Timing of the REF30 Signal Generation
Figures 28.8, 28.9, 28.10, 28. 11 and 28. 12 show the timing of the generation of REF30 and
REF30P signals.
Counter set Counter set Counter set
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
REF30
REF30P
Figure 28. 8 REF30 Signals in Pl ayback Mode
Rev. 2.0, 11/ 00, page 637 of 1037
Sampling
Sampling
Sampling
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD
Toggle mask
Field signal
REF30P
HSW
Drum phase counter
T
About 75%
Masking
period
Masking
period
Figure 28.9 Generation of Reference Signal in Record Mode (Normal Operation)
Rev. 2.0, 11/ 00, page 638 of 1037
Sampling
Cleared Cleared Cleared
Drop-out of V
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD
Toggle mask
Field signal
REF30P
HSW
Drum phase counter
Sampling
TSampling
About 75% About 75% About 75%
About 75%
About
25%
Masking
period
Masking
period
Figure 28.10 Generation of Reference Signal in Record Mode (V Dropped Out)
Rev. 2.0, 11/ 00, page 639 of 1037
Sampling
Cleared Cleared Cleared
Dislocation of V
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD
Toggle mask
Field signal
REF30P
HSW
Drum phase counter
Sampling
TSampling
About 75%
About 75% About 75%
About 75%
Masking
period
Masking
period
Figure 28.11 Generation of Reference Signal in Record Mode (V Dislocated)
Rev. 2.0, 11/ 00, page 640 of 1037
Cleared Cleared
Reset
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
External sync
signal
REF30
REF30P
Figure 28. 12 G e nerati on of REF30 Signal by External Sync Signal
(4) CREF Signal Genera t or
The CREF signal generator generates a CREF signal which is the reference signal to control
the phase of the capstan.
To generate CREF signals, set the half-period value to the reference period register 2 (CRF).
If the set value matches the counter value, a toggle waveform is generated corresponding to
the 50% duty cycle, and a one-shot pulse signal is output at the rising edge of the waveform.
The counter of the CREF signal generator is initialized to H'0000 and the phase of the toggle
is cleared to L level at the mode transition of PB (ASM) to RE C . The timing of clearing is
selectable between immediately after the transition from PB (ASM) t o REC a n d the timing
of DVCFG2 aft e r the t ransit i on. Use bit 3 (CRD) of the re fere nc e pe ri od mode re giste r
(RFM) for the selection.
In the capstan phase error detection circuit, either the REF30 signal or CREF signal can be
selected for the reference signal. Use either of them according to the use of the system.
Use the CREF signal t o c ontrol t he pha se of t he c a pstan a t a pe ri od which i s diffe rent from
the period used to control the phase of the drum. As for the switching between REF30 and
CREF in the capstan phase control, see section 28.9.4(3) Capstan Phase Error Detection
Control Regi ste r (CPGCR).
Rev. 2.0, 11/ 00, page 641 of 1037
(5) Timing Chart of the CREF Signal Generation
Figures 28.13, 28.14 and 28. 15 show the generation of the CREF si gnal.
Cleared Cleared Cleared
Value set in reference
period register 2 (CRF)
Counter
Toggle signal
CREF
Figure 28. 13 G e nerati on of CREF Signal
Rev. 2.0, 11/ 00, page 642 of 1037
Cleared Cleared Cleared
Value set in reference
period register 2 (CRF)
Counter
Time period when CRF is set
RECPB(ASM)
Toggle signal
REC/PB
CREF
Fi g ur e 2 8 . 1 4 CREF Si gna l when PB i s Switc he d t o REC ( whe n CRD B i t = 0)
Rev. 2.0, 11/ 00, page 643 of 1037
Cleared Cleared Cleared
Value set in reference
period register 2 (CRF)
Counter
Time period when
CRF is set
Toggle signal
REC/PB
CREF
DVCFG2
RECPB(ASM)
Fi g ur e 2 8 . 1 5 CREF Si gna l when PB i s Switc he d t o REC ( whe n CRD B i t = 1)
Rev. 2.0, 11/ 00, page 644 of 1037
Figures 28.16 and 28.17 show REF30 (REF30P) when PB is switched to REC.
Cleared
Cleared
Cleared
Cleared Cleared
Value set in reference
period register 1 (RFD)
Selected VD*
(OD/EV=0)
* When in the field discrimination mode
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
Field signal
REC/PB
REF30P
About 75%
Masking
period
Masking
period
Figure 28.16 Generation of the Reference Signal when PB is Switched to REC (1)
Rev. 2.0, 11/ 00, page 645 of 1037
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
Field signal
REC/PB
REF30P
About
50%
Cleared
Cleared
Cleared Cleared
Masking
period
Masking
period
Figure 28.17 Generation of the Reference Signal when PB is Switched to REC (2)
Rev. 2.0, 11/ 00, page 646 of 1037
Figures 28.18, 28.19, 28.20 and 28. 21 show REF30 (REF30P) when PB is switched to REC
(whe r e FDS b i t = 1).
Cleared Cleared Cleared
Value set in reference
period register 1 (RFD)
FDS bit = "1"
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
Figure 28.18 Generation of the Reference Signal when PB is Switched to REC
where RFD Bit is 1 (1)
Rev. 2.0, 11/ 00, page 647 of 1037
Value set in reference
period register 1 (RFD)
FDS bit = "1"
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
25% 25% 25%
Figure 28.19 Generation of the Reference Signal when PB is Switched to REC
where RFD Bit is 1 (when VD Signal is Not Detected) (2)
Rev. 2.0, 11/ 00, page 648 of 1037
Cleared Cleared
Value set in reference
period register 1 (RFD)
FDS bit = "1"
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
Max. 25%
Figure 28.20 Generation of the Reference Signal when PB is Switched to REC
where RFD Bit is 1 (3)
Rev. 2.0, 11/ 00, page 649 of 1037
Cleared Cleared
Value set in reference
period register 1 (RFD)
FDS bit = "1"
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
Max. 25%
Figure 28.21 Generation of the Reference Signal when PB is Switched to REC
where RFD Bit is 1 (4)
Rev. 2.0, 11/ 00, page 650 of 1037
28.4 HSW (Head-switch) Timing Generator
28.4.1 Overview
The HSW timing generator consists of one 5-bit counter and one 16-bit counter, matching
cir cu i t , a nd t wo 31-bit 10-st a ge FIFOs.
The 5-bi t c ount e r c ount s t he DFG pul se s fol l o wi ng a DPG pul se . Each of them determines the
timing to reset the 16-bit timer for each field. The matching circuit compares the timing data in
the most significant 16 bits of FIFO with the 16-bit timer, and controls the output of pattern data
set in the least significant 15 bits of FIFO. The 16-bit timer is a timer clocked by a φ s/4 clock
source, and c a n be use d a s a PPG (Progr ammable Pattern Generator) as well as a free-running
counter (FRC). If used as a free-running counter, it is cleared by overflow (FRCOVF) of t h e
Prescaler unit. Accordingly, two free-running counter operate in sync.
28.4.2 Block Diagram
Figure 28.22 shows a block diagram of the HSW timing generator.
Rev. 2.0, 11/ 00, page 651 of 1037
RWW
R/WR/W
WR/WR/W
STRIG
IRRHSW2
ISEL2
AudioFF
VideoFF
HSW
NHSW
Mlevel
Vpulse
ADTRG
IRRHSW1
RVD PB
WR/W R/W
Cleared
Cleared
CLK
WR
,
NCDFG
FRCOVF
DPG
CKSL
VFF/NFF
Internal bus
W
• FPDRA • FPDRB
• FTPRA • FTPRB
W
ISEL1
OFG
FIFO output pattern
register 1 FIFO output pattern
register 2
SOFGLOP
R/WR/WRRWW
CLRA,BOVWA,BEMPA,BFLA,B
R/W R/W
HSM2
• HSM1
• HSLP
EDG
HSW loop stage
number setting
register
Internal bus
FGR20FF
FRTCCLR
Edge
detector
Control
circuit
FIFO 1
(31 bits 10 stages)
15 bits
P77 to 70
(PPG output)
FIFO timing pattern
register 1 FIFO timing pattern
register 2
16 bits
FIFO2
(31 bits 10 stages)
15 bits16 bits
FIFO output selector & output buffer
15 bits16 bits
• DFCRB
• DFCRA
• DFCRA • HSM2 • HSM2
Capture • HSM2
• DFCRA • DFCRA
DFG reference
register 1
Comparator
(5 bits) Comparator
(5 bits)
DFG reference
register 2
• DFCTR
Counter (5 bits)
Compare circuit (16 bits)
FTCTR (16 bits)
Timer counter (16 bits)
s/4 s/8
Figure 28. 22 Composition of the HSW Timing Ge ner ator
Rev. 2.0, 11/ 00, page 652 of 1037
28.4.3 Composition
The HSW timing generator is composed of the elements shown in table 28.5.
Table 28.5 Composition of the HSW Timing Generator
Element Function
HSW mode register 1 ( HSM1) Conf ir m at ion/ det er m inat ion of t his circ uits' operating
status
HSW mode register 2 ( HSM2) Conf ir m at ion/ det er m inat ion of t his circ uits' operating
status
HSW loop stage number set t ing register
(HSLP) Set t ing of num ber of loop st ages in loop mode
FIFO out put pat tern r egister 1 (FPDRA) Output pat tern dat a r egister of FI FO 1
FIFO out put pat tern r egister 2 (FPDRB) Output pat tern dat a r egister of FI FO 2
FIFO t im ing pattern r egist er 1 ( FTPRA) Output timing register of FI FO1
FIFO t im ing pattern r egist er 2 ( FTPRB) Output timing register of FI FO2
DFG ref er ence r egister 1 (DFCRA) Set t ing of r ef er ence DFG edge f or FI FO1
DFG ref er ence r egister 2 (DFCRB) Set t ing of r ef er ence DFG edge f or FI FO2
FIFO t imer capture r egister ( FTCTR) Capt ur e r egister of t imer counter
DFG ref er ence count r egist er ( DFCTR) DFG edge count
FIFO cont r ol circuit Controls FI FO st atus
DFG count compar e cir cuit (×2) Det ect ion of match bet ween DFCR and DFG counters
16-bit t imer counter 16-bit free- r un t imer counter
31-bit x 20 st age FI FO First I n Fir st Out dat a buf fer
31-bit FI FO data buff er Data storing buf f er for t he f ir st st age of FIFO
16-bit com par e circuit Detect ion of m at ch bet ween t imer counter and FI FO
data buf f er
FPDRA an d FPDRB a r e int erm e d iate buffers; an FTPRA and FTPRB write results in
simultaneous writing of all 31 bits to the FIFO. The FIFO has two 31-bit x 10-stage data
buffers, its operating status being controlled by HSM1 a n d HSM2. Data is stored in the 31-bit
data buffer. The values of FTPRA, FTPRB and the timer counter are compared, and if they
match, the 15-bit pattern data is output to each function. AudioFF, VideoFF and PPG (P70 t o
P77) are pin output s, ADTRG is the A/D conve rt er ha rdware start signa l, Vpulse a nd Mle vel
signals are the signals to generate the additional V pulses, and HSW and NHSW si g n a l s are t h e
same with VideoFF signals used for the phase control of the drum. In free-run mode (when FRT
bit of HSM2 = 1), t he 16-bi t timer counter is initialized when the prescaler unit overflows, or by
a signal indicating a match between DFCRA, DFCRB and the DFG c ount e r i n DFG refe re nc e
mode.
Rev. 2.0, 11/ 00, page 653 of 1037
28.4.4 Register Configuration
Table 28.6 shows the register configuration of the HSW timing generator.
Table 28.6 Register Configuration
Name Abbrev. R/W Siz e I nitial Value Address
HSW mode register 1 HSM1 R/W Byte H'30 H'FD060
HSW mode register 2 HSM2 R/W Byte H'00 H'FD061
HSW loop stage number set ting
register HSLP R/W Byte Undetermined H'FD062
FIFO out put pat tern r egister 1 FPDRA W Word Undeterm ined H'FD064
FIFO t iming pat t er n r egist er 1*FTPRA W Word Undetermined H'FD066
FIFO out put pat tern r egister 2 FPDRB W Word Undeterm ined H'FD068
FIFO t im ing pattern r egist er 2 FTPRB W Wor d Undeterm ined H'FD06A
DFG refer ence r egister 1*DFCRA W Byte Undetermined H'FD06C
DFG ref er ence r egister 2 DFCRB W Byte Undeterm ined H'FD06D
FIFO t imer capture r egister *FTCTR R Word H'0000 H'FD066
DFG refer ence count r egist er*DFCTR R Byte H'E0 H'FD06C
Note: *FTPRA and FTCTR, as well as DFCRA and DFCTR, are allocated to the same
addresses.
28.4.5 Register Descriptions
(1) HSW Mode Register 1 (H SM1)
0
0
1
0
R/W
2
0
R/(W)*
3
0
4
1
R
1
R
56
0
7EMPA OVWB OVWA CLRB CLRA
0
R
FLB
R/WR/(W)*
R
FLA EMPB
Bit :
Initial value :
R/W :
Note: * Only 0 can be written
HSM1 is a regi st e r whi c h c onfi rms a nd determines the operational state of the HSW timing
generator.
HSM1 is an 8-bi t re gi st e r. Bi t s 7 to 4 a re re a d-onl y bit s, a nd write is disabled. All the other bits
accept both read and write. It is initialized to H'30 by a reset or stand-by.
Rev. 2.0, 11/ 00, page 654 of 1037
Bit 7: FIFO2 F ull Fl ag (F LB)
When the FLB bit is 1, it indicates that the timing pattern data and the output pattern data of
FIFO2 are full. If a write is attempted in this state, the write operation becomes invalid, an
interrupt is generated, the OVWB flag (bit 3) is set to 1, and the write data is lost. Wait until
space becomes available in the FIFO2, then write again.
Bit 7
FLB Description
0 FIFO 2 is not f ull, and can accept dat a input (Initial value)
1 FIFO2 is full
Bit 6: FIFO1 F ull Fl ag (F LA)
When the FLA bit is 1, it indicates that the timing pattern data and the output pattern data of
FIFO1 are full. If a write is attempted in this state, the write operation becomes invalid, an
interrupt is generated, the OVWA flag (bit 2) is set to 1, and the write data is lost. Wait until
space becomes available in the FIFO1, then write again.
Bit 6
FLA Description
0 FIFO 1 is not f ull, and can accept dat a input (Initial value)
1 FIFO1 is full
Bit 5: FIFO2 Empty Fl ag (EM PB)
Indicates that FIFO2 has no data, or that all the data has been output in single mode.
Bit 5
EMPB Description
0 FIFO2 cont ains dat a
1 FIFO 2 cont ains no data ( I nit ial value)
Bit 4: FIFO1 Empty Fl ag (EM PA)
Indicates that FIFO1 has no data, or that all the data has been output in single mode.
Bit 4
EMPA Description
0 FIFO1 cont ains dat a
1 FIFO 1 cont ains no data ( I nit ial value)
Rev. 2.0, 11/ 00, page 655 of 1037
Bit 3: FIFO2 Overwrite Flag (OVWB)
If a write is attempted when the timing pattern data and the output pattern data of FIFO2 are full
(FLB bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWB flag is
set to 1, and the write data is lost. Wait until space becomes available in the FIFO2, then write
again.
Write 0 to clear the OVWB flag, because it is not cleared automatically.
Bit 3
OVWB Description
0 Normal operation (Init ial value)
1 Indicates that a writ e in FIFO2 was attempted when FIFO2 was full. Clear this f lag
by 0 writ in g
Bit 2: FIFO1 Overwrite Flag (OVWA)
If a write is attempted when the timing pattern data and the output pattern data of FIFO1 are full
(FLA bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWA flag is
set to 1, and the write data is lost. Wait until space becomes available in the FIFO1, then write
again.
Write 0 to clear the OVWA flag, because it is not cleared automatically.
Bit 2
OVWA Description
0 Normal operation (Init ial value)
1 Indicates that a writ e in FIFO1 was attempted when FIFO1 was full. Clear this f lag
by 0 writ in g
Bit 1: FIFO2 Pointer Clear (CLRB)
Clears the FIFO2 write position pointer. After 1 is written, the bit immediately reverts to 0.
Writing 0 in this bit has no effect.
Bit 1
CLRB Description
0 Normal operation (Init ial value)
1 Clears the FI FO 2 point er
Rev. 2.0, 11/ 00, page 656 of 1037
Bit 0: FIFO1 Pointer Clear (CLRA)
Clears the FIFO1 write position pointer. After 1 is written, the bit immediately reverts to 0.
Writing 0 in this bit has no effect.
Bit 0
CLRA Description
0 Normal operation (Init ial value)
1 Clears the FI FO 1 point er
Rev. 2.0, 11/ 00, page 657 of 1037
(2) HSW Mode Register 2 (H SM2)
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7EDG ISEL1 SOFG OFG VFF/NFF
0
R/W
FRT
WR/WR
FGR20FF LOP
Bit :
Initial value :
R/W :
HSM2 is a regi st e r whi c h c onfi rms a nd determines the operational state of the HSW timing
generator.
HSM2 is an 8-bit re gist e r. Bi t s 6 and 1 a re re a d-onl y bit s, and write is disabled. Bit 0 is a write-
only bit, and if a read is attempted, an undetermined value is read out. All the other bits accept
both read and write. It is initialized to H'00 by a reset or stand-by.
Bit 7: Free-run Bit (FRT)
Selects whether timing is matched to the DPG c ounte r a nd timer, or to free-running counter.
Bit 7
FRT Description
0 5-bit DFG count er + 16- bit t imer counter (Initial value)
1 16-bit FRC
Bit 6: FRG2 Clear Stop Bit (FGR2OFF)
Nullifies the clearing of the counter by the DFG re fe re nc e regi st e r 2. T he FIFO group, i nc l udi ng
both FIFO1 and FIFO2, is available.
Bit 6
FGR2OFF Description
0 Validates the clearing of t he 16- bit t im er count er by DFG refer ence r egister 2
(Init ial value)
1 Nullifies the clearing of the 16-bit timer counter by DFG reference regist er 2
Bit 5: Mode Selection Bit (LOP)
Selects the output mode of FIFO. If the loop mode is selected, LOB3 to LOB0 bits and LOA3 to
LOA0 bits become valid. If the LOP bit is rewritten, the pointer which counts the writing
position of FIFO is cleared. In this case, the ultimate output date is kept.
Bit 5
LOP Description
0 Single mode (Init ial value)
1 Loop mode
Rev. 2.0, 11/ 00, page 658 of 1037
Bit 4: DFG Edge Selection Bit (EDG)
Selects the edge by which to count DFG.
Bit 4
EDG Description
0 Counts by the r ising edge of DFG (I nitial value)
1 Counts by the falling edge of DFG
Bit 3: Interrupt Selection Bit (ISEL1)
Selects the factor which causes an interrupt. (IRRHSW1)
Bit 3
ISEL1 Description
0 Gener at es an int er r upt r equest by the r ising edge of t he STRIG signal of FI FO
(Init ial value)
1 Gener at es an int er r upt r equest by the m at c hing signal of FIFO
Bit 2: FIFO Output Group Selection Bit (SOFG)
Selects whether 20 stages of FIFO1 + FIFO2 or only 10 stages of FIFO1 are used.
If 20-stage output mode is used in single mode, data write in FIFO1 and FIFO2 is required.
Monitor t he out put FIFO group fla g (OFG) a nd c ont rol i t by soft wa re . Out put all the data of
FIFO2 after all the data of FIFO1 was output. Repeat this step again. If 10-stage output mode is
used, the data of FIFO2 is not reflected.
Rewr i ti ng t h e SOFG b i t 0 → 1 → 0 initializes the control signal of the FIFO output stage to the
FIFO1 si d e .
Bit 2
SOFG Description
0 20-st age output of FIFO1 + FI FO2 (I nitial value)
1 10-st age out put of FI FO 1 only
Bit 1: Output FIFO Group Flag (OFG)
Indicates the FIFO group which is outputting.
Bit 1
OFG Description
0 Patt er n is being output by FI FO1 ( I nitial value)
1 Patt er n is being output by FI FO2
Rev. 2.0, 11/ 00, page 659 of 1037
Bit 0: Output Switching Bit Between VideoFF and NarrowFF (VFF/NFF)
Switches the signal output to the VideoFF pin.
Bit 0
VFF/NFF Description
0 VideoFF output (Init ial value)
1 Narro wFF output
Rev. 2.0, 11/ 00, page 660 of 1037
(3) HSW Loop Stage Number Setting Register (H SLP)
0
*
1
*
R/W
2
*
R/W
3
*
4
*
R/W
5
*
6
*
7
R/W R/WR/W
LOB1
R/W
LOB2
*
R/W
LOB3 LOB0 LOA3 LOA2 LOA1 LOA0
Bit :
Initial value :
R/W :
Note: * Undetermined
HSLP sets the number of the loop stages when the HSW timing generator is in loop mode. It is
valid if bit 5 (LOP) of HSM2 is 1. Bi t s 7 t o 4 se t the n umbe r of FI FO2 sta ges. Bits 3 t o 0 se t the
number of FIFO1 stages.
HSLP is an 8-bit read/write register. It is not initialized by a reset, stand-by or module stop,
accordi ngl y be sure t o set the num ber of t he stage s when the loop m ode is used.
Rev. 2.0, 11/ 00, page 661 of 1037
Bits 7 to 4: FIFO2 Stage Number Setting Bits (LOB3 to LOB0)
Set the number of FIFO2's stages in loop mode. They are valid only if the loop mode is set
(LOP b i t of HSM2 is 1).
HSM2 HSLP
Bit 5 Bit 7 Bit 6 Bit 5 Bit 4
LOP LOB3 LOB2 LOB1 LOB0 Description
0****Single mode ( I nit ial value)
0 Only 0th st age of FI FO2 is output0
1 0th and 1st st ages of FIFO 2 ar e output
0 0th to 2nd st ages of FIFO 2 ar e output
0
1
1 0th to 3r d stages of FI FO 2 ar e output
0 0th to 4t h stages of FI FO2 are out put0
1 0th to 5t h stages of FI FO2 are out put
0 0th to 6t h stages of FI FO2 are out put
0
1
1
1 0th to 7t h stages of FI FO2 are out put
0 0th to 8t h stages of FI FO2 are out put
1
100
1 0th to 9t h stages of FI FO2 are out put
01
1
00
1
0
1
1
1
Setting prohibited
Note: *Don't care.
Rev. 2.0, 11/ 00, page 662 of 1037
Bits 3 to 0: FIFO1 Stage Number Setting Bits (LOA3 to LOA0)
Set the number of FIFO1's stages in loop mode. They are valid only if the loop mode is set
(LOP b i t of HSM2 is 1).
HSM2 HSLP
Bit 5 Bit 3 Bit 2 Bit 1 Bit 0
LOP LOA3 LOA2 LOA1 LOA0 Description
0****Single mode ( I nit ial value)
0 Only 0th st age of FI FO1 is output0
1 0th and 1st st ages of FIFO 1 ar e output
0 0th to 2nd st ages of FIFO 1 ar e output
0
1
1 0th to 3r d stages of FI FO 1 ar e output
0 0th to 4t h stages of FI FO1 are out put0
1 0th to 5t h stages of FI FO1 are out put
0 0th to 6t h stages of FI FO1 are out put
0
1
1
1 0th to 7t h stages of FI FO1 are out put
0 0th to 8t h stages of FI FO1 are out put
1
100
1 0th to 9t h stages of FI FO1 are out put
01
1
00
1
0
1
1
1
Setting prohibited
Note: *Don't care.
Rev. 2.0, 11/ 00, page 663 of 1037
(4) FIFO Out put P a tt e rn Re giste r 1 ( F P DRA)
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
—
—
NarrowFFA
VFFA AFFA VpulseA MlevelA
1WWW
ADTRGA STRIGA
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGA4 PPGA3 PPGA2 PPGA1 PPGA0
*
W
PPGA7
WWW
PPGA6 PPGA5
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Note: * Undetermined
FPDRA is a buffer re gi st e r for t he out put p attern register of FIFO1. When the timing pattern is
written in FTPRA the output pattern data written in FPDRA is written at the same time to the
position pointed by the buffer pointer of FIFO1. Be sure to write the output pattern data in
FPDRA before wr iting it in FTPRA.
FPDRA is a 16-bi t write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. No read is valid. If a read is attempted, an
undetermined value is read out. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to write data before use.
Bit 15: Reserved
It cannot be written in or read out.
Bit 14: A/D Trigger A Bit (ADTRGA)
A signal for starti ng t he A/D conve rt er ha rdware .
Bit 13: S-TRIGA Bit (STRIGA)
A signal for generating an interrupt by pattern data. When STRIGA is selected by ISEL, pattern
data changes from 0 to 1, and thus generates an interrupt.
Bit 12: NarrowFFA Bit (Narr owFF A)
Controls the Narrow Video Hea d.
Bit 11: VideoFFA Bit (VFF A)
Controls the Vide o Hea d.
Bit 10: AudioF F A Bit (AF F A)
Controls the Audio Hea d.
Bit 9 : Vpulse A Bit (VpulseA)
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
Rev. 2.0, 11/ 00, page 664 of 1037
Bit 8: MlevelA Bit (MlevelA)
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
Bits 7 to 0: PPG Output Signal A Bits (PPGA7 to PPGA0)
Used for timing control output of port 7 (PPG).
(5) FIFO Output Pattern Register 2 (FPDRB)
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
—
—
NarrowFFB
VFFB AFFB VpulseB MlevelB
1WWW
ADTRGB STRIGB
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGB4 PPGB3 PPGB2 PPGB1 PPGB0
*
W
PPGB7
WWW
PPGB6 PPGB5
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Note: * Undetermined
FPDRB is a buffer register for the output pattern register of FIFO2. When the timing pattern is
written in FTPRB the output pattern data written in FPDRB is written at the same time to the
position pointed by the buffer pointer of FIFO2. Be sure to write the output pattern data in
FPDRB before writing it in FTPRB.
FPDRB is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. No read is valid. If a read is attempted, an
undetermined value is read out. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to write data before use.
Bit 15: Reserved
It cannot be written in or read out.
Bit 14: A/D Trigger B Bi t (ADTRGB)
A signal for starti ng t he A/D conve rt er ha rdware .
Bit 13: S-TRIGB Bit (STRIGB)
A signal for generating an interrupt by pattern data. When STRIGB is selected by ISEL, pattern
data changes from 0 to 1, and thus generates an interrupt.
Bit 12: NarrowFFB Bi t (Narr owFFB)
Controls the Narrow Video Hea d.
Bit 11: VideoFFB Bi t (VFF B)
Controls the Vide o Hea d.
Rev. 2.0, 11/ 00, page 665 of 1037
Bit 10: AudioF F B Bi t (AF F B)
Controls the Audio Hea d.
Bit 9 : Vpulse B B i t ( Vpul se B )
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
Bit 8: MlevelB Bit (MlevelB)
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
Bits 7 to 0: PPG Output Signal B Bits (PPGB7 to PPGB0)
Used for timing control output of port 7 (PPG).
(6) FIFO Timi ng Patte rn Register 1 (F TPRA)
*
W
13
*
W
14
*
W
15
FTPRA15 FTPRA14 FTPRA13 FTPRA12 FTPRA11 FTPRA10 FTPRA9 FTPRA8 FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0
1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
Note: * Undetermined
FTPRA is a register to write the timing pattern data of FIFO1. The timing data written in
FTPRA is written at the same time to the position pointed by the buffer pointer of FIFO1
together with the buffer data of FPDRA.
FTPRA is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module
stop, accordingly be sure to write data before use.
Note: Its address is shared with the FIFO timer capture register (FTCTR). Accordingly, the
value of FTCTR is read out if a read is attempted.
Rev. 2.0, 11/ 00, page 666 of 1037
(7) FIFO Timi ng Patte rn Register 2 (F TPRB)
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8 FTPRB7 FTPRB6 FTPRB5 FTPRB4 FTPRB3 FTPRB2 FTPRB1 FTPRB0
Note: * Undetermined
FTPRB is a register to write the timing pattern data of FIFO2. The timing data written in
FTPRB is written at the same time to the position pointed by the buffer pointer of FIFO2
together with the buffer data of FPDRB.
FTPRB is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module
stop, accordingly be sure to write data before use.
(8) DFG Reference Register 1 (DFCRA)
0
*
1
*
W
2
*
W
3
*
4
*
W
0
W
56
0
7DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0
0
W
ISEL2
WWW
CCLR CKSL
Bit :
Initial value :
R/W :
Note: * Undetermined
DFCRA is a register which determines the operation of the HSW timing generator as well as the
starting point of the timing of FIFO1.
DFCRA is an 8-bit write-only register. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to write data before use.
Note: Its address is share d wi t h t he DFG re fe re nce c ount e r re gi ste r (DFCT R). Ac c ordi ngl y,
the value of DFCTR is read out in the low-order five bits if a read is attempted.
Bit 7: Interrupt Selection Bit (ISEL2)
Selects the factor which causes an interrupt. (IRRHSW2)
Bit 7
ISEL2 Description
0 Gener at es an int er r upt r equest by the clear signal of t he 16- bit t im er count er
(Init ial value)
1 Gener at es an int er r upt r equest by the VD signal in PB m ode
Rev. 2.0, 11/ 00, page 667 of 1037
Bit 6: DFG Counter Clear Bi t (CCLR)
Enforces clearing of the 5-bit counter which counts DFG by so ftwar e . W r it i ng 1 ret urns 0
immediately. Writing 0 causes no effect on operation.
Bit 6
CCLR Description
0 Normal operation (Init ial value)
1 Clears the 5- bit DFG count er
Bit 5: 16-bit Timer Counter Clock Source Selection Bit (CKSL)
Selects the clock source of the 16-bit timer counter.
Bit 5
CKSL Description
0φs/ 4 (Init ia l v a lu e)
1φs/8
Bit s 4 to 0 : FIF O 1 O ut put T i m i ng Se t t i ng Bits (DFCRA4 to DF CRA0 )
Determine the starting point of the timing of FIFO1. The initial value is undetermined. Be sure
to set a value after a reset or stand-by. It is valid only if bit 7 (FRT bit) of HSM2 is 0 .
(9) DFG Reference Register 2 (DFCRB)
0
*
1
*
W
2
*
W
3
*
4
*
W
56
1
7———
———
DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0
WW
11
Bit :
Initial value :
R/W :
Note: * Undetermined
DFCRB is a register which determines the starting point of the timing of FIFO2.
DFCRB is an 8-bit write-only register. If a read is attempted, an undetermined value is read out.
Bits 7 to 5 are reserved. No write is valid. If a read is attempted, 1 is read out. It is not
initialized by a reset or stand-by, accordingly be sure to write data before use.
Bits 4 to 0: FIFO2 Output Timing Setting Bits (DFCRB4 to DFCRB0)
Determine the starting of the FIFO2 output. The initial values are undetermined, accordingly be
sure to write values in the bits after a reset or stand-by.
It is valid only if bit 7 (FRT bit) of HSM2 i s 0.
Rev. 2.0, 11/ 00, page 668 of 1037
(10) FIFO Time r Capture Register (F TCTR)
0
R
13
0
R
14
0
R
15 1032547
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
RRRRRRR
12
000000
Bit :
Initial value :
R/W :
FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8 FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0
FTCTR is a register to display the count of the 16-bit timer counter.
FTCTR is a 16-bit read-only register. It stores the counter value if a VD signal was detected in
PB mode. Only a word access is accepted. If a byte access is attempted, resulting operation is
not assured. It is initialized to H'0000 by a reset or stand-by.
Note: Its address is shared with the FIFO timing pattern register 1 (FTPRA). Accordingly, if a
write is attempted, the value is written in FTPRA.
(11) DFG Reference Count Register (DFCTR)
0
0
1
0
R
2
0
R
3
0
4
0
R
56
1
7———
———
DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0
RR
11
Bit :
Initial value :
R/W :
DFCTR i s a re gi st e r t o c ount t he DFG pul se s.
DFCTR is an 8-bit read-only register. Bits 7 to 5 are reserved. If a read is attempted, 1 is read
out. It is initialized to H'E0 by a reset or stand-by.
Note: Its address is sha re d wi t h t h e DFG refe re nc e re gi st e r 1 (DFCRA). Ac c ordi ngl y, i f a
write is attempted, the value is written in DFCRA.
Bits 4 to 0: DFG Pulse Count Bits (DFCTR4 to DFCTR0)
Count the num be r of pul ses of DFG.
Rev. 2.0, 11/ 00, page 669 of 1037
28.4.6 Description of Operation
(a) 5-bit DFG c ount er
The 5-bit DFG c ount e r t a ke s c ount s by t he e dge s of DFG selected by the EDG bit of HSW
mode re gi st er 2. T he 5-bit DFG c ount e r i s cleared by the DPG' s r i se or wh e n 1 wa s wr itten
in the C C L R bit o f DFG refe r e n c e r e g i ster 1 .
(b) 16-bit Timer Counter
DFG refere nce m ode or free -run m ode ca n be selected for the 16-bit timer counter.
• DFG Refere n c e Mode
DFG ref e r e n c e m od e is ba se d o n the DFG si g n a l . W hen t h e DFG r e f e r e n c e re g i st ers 1
and 2 and t he 5-bi t DFG count e r va l ue match, the 16-bit timer counter is initialized, and
that point becomes the starting of the FIFO output.
In DFG refe r e n c e mo d e , th e FGR 2 OFF bit o f t h e HSW mod e r e g i st er 2 can b e u se d t o
select between using only the DFG r e f e r e n c e r e g i ster 1 t o se t the star t ing o f t h e FI FO
out p ut or using b o t h DFG refe r e n c e r e g i ster s 1 a n d 2 t o se t t he start i n g of t h e FI FO1 a n d
FIFO2 outputs, respectively. When using only the DFG ref e r e n c e r e g i ster 1 t o se t the
starting, continuous values should be set as the timing patterns for FIFO1 and FIFO2.
• Free-run Mode
Free-run mode is to operate together with the prescaler unit. An overflow of the 18-bit
free-running counter in the prescaler unit initializes the 16-bit timer counter, and that
point becomes the starting of the FIFO output.
(c) Matching Circuit
The matching circuit compares the timing pattern value of FIFO with the 16-bit timer
counter value, and if they match, it generates a trigger signal to output the pattern data for
the FIFO’s next stage.
(d) FIFO
FIFO generates the head-switching signal used in the VCR and the pattern data necessary for
servo control. Data is set in FIFO by the FIFO timing pattern registers 1 and 2 and the FIFO
output pattern registers 1 and 2.
FIFO has two modes, i. e. single mode and loop mode. In either mode, output of 20 stages of
FIFO1 + FIFO2 or output of only 10 stages of FIFO1 can be selected.
• Single Mode
In single mode, the output pattern data is output each time the timing data matches. The
data, once output, is lost, and the internal pointer is decremented by 1. When the last
data was output, it stops operation until data is written again. When it is used in the 20-
stage output mode, writing in FIFO1 and FIFO2 has to be controlled by software.
Rev. 2.0, 11/ 00, page 670 of 1037
• Loop Mode
In loop mode, the output pattern cycles repeatedly from stage 0 through the final stage
selected in the HSW loop number setting register. As in single mode, the output pattern
data is output each time the timing data matches. In loop mode, the FIFO data is
retained.
When loop mode is active, data can be rewritten for each FIFO group.
After confi rm i ng wi t h t he OFG bi t of t he HSW m ode re gi st e r 2 whi c h FIFO group i s
outputting, clear the FIFO group which is not outputting and write data for the entire
FIFO group. Writing has to be completed before the rewritten FIFO group starts
operation.
Partial rewriting in the FIFO is not possible, because the write pointer is outside the loop
stages.
Figures 28.23 and 28.24 show examples of the timing waveform and its operation of the
HSW timing generator.
Rev. 2.0, 11/ 00, page 671 of 1037
DPG
01
tA1
tA2 tB1
tA3 tA1
234567891011 012
V.FF
A.FF
Clear A
Clear B
Example of setting: DFCRA=H'02, DFCRB=H'08, HSLP=H'21, DFG falling edge
DFG
Figure 28. 23 Example of Ti ming Wavefor m of H SW (when DFG is 12 Shots)
Rev. 2.0, 11/ 00, page 672 of 1037
Output pattern data
s/4
WW
FTPRB
FIFO2
tB0 PB9
tB5 PB4
tB4 PB3
tB3 PB2
tB2 PB1
tB1 PB0
WW
FPDRA
Output select buffer Output select buffer
Comparator
FTPRA
FIFO1
tA0 PA9
tA5 PA4
tA4 PA3
tA3 PA2
tA2 PA1
tA1 PA0
Internal bus
FPDRB
Timer counter
Figure 28. 24 Example of O perati on of the HSW Timi ng Gener ator
Rev. 2.0, 11/ 00, page 673 of 1037
(1) Exampl e of opera t ion i n singl e m ode (20 stage s of FIFO used)
(a) Set t o single m ode (L OP = 0)
(b) Write the output pattern data (PA0) to FPDRA.
(c) Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This
initializes the output pattern data to PA0.
(d) Repeat the steps in the same way, until PA1, PA2, etc., are set.
(e) Write the output pattern data (PB0) to FPDRB.
(f) Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This
initializes the output pattern data to PB0.
(g) Repeat these steps in the same way, until PB1, PB2, etc., are set.
From (c), the pattern data of PA0 is output.
If tA1 matches with the timer counter, the pattern data of PA1 is output.
If tA2 matches with the timer counter, the pattern data of PA2 is output.
.
.
.
Rev. 2.0, 11/ 00, page 674 of 1037
After this sequence is repeated and all the pattern data set in FIFO1 is output, the pattern data of
FIFO2 is output. After the pattern data is output, the pointer is decremented by 1. Care is
required, however, because matching of tA0 is not detected until data is written in FIFO2.
Matching of tB0 also is not detected until data is written in FIFO1 again.
(2) Exampl e of opera t ion i n l oop mode
(a) Set t he num be r of loop sta ge s in the HSLP registe r (e. g. HSLP = H'44)
(b) Write the output pattern data (PA0) to FPDRA.
(c) Write the output timing (tA1) t o FTPRA. tA1 is written in FIFO1 together with PA0. This
initializes the output pattern data to PA0.
(d) Repeat the steps in the same way, until PA1, PA2, etc., are set.
(e) Write the output pattern data (PB0) to FPDRB.
(f) Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This
initializes the output pattern data to PB0.
(g) Repeat the steps in the same way, until PB1, PB2, etc., are set.
From (c), the pattern data PA0 is output.
If tA1 matches the timer counter, the pattern data PA1 is output.
If tA2 matches the timer counter, the pattern data PA2 is output.
.
.
.
If tA4 matches the timer counter, the pattern data PA4 is output.
If tA5 matches the timer counter, the pattern data PB0 is output.
If tB1 matches the timer counter, the pattern data PB1 is output.
.
.
.
If tB4 matches the timer counter, the pattern data PB4 is output.
If tB5 matches the timer counter, the pattern data PA0 is output.
.
.
.
Rev. 2.0, 11/ 00, page 675 of 1037
28.4.7 Interrupt
The HSW timing generator generates an interrupt under the following conditions.
(1) IRRHSW1 occurred when pattern data was written (OVWA, OVWB = 1) and FIFO was full
(FULL).
(2) IRRHSW1 occurred when matching was detected and the STRIG bit of FIFO was 1.
(3) IRRHSW1 occurred when the values of the 16-bit timer counter and 16-bit timing pattern
register matched.
(4) IRRHSW2 occurred when the 16-bit timer counter was cleared.
(5) IRRHSW2 occurred when a VD signal (capture signal of the timer capture register) was
received in PB mode.
(2) and (3), as well as (4) and (5), are switched over by ISEL1 and ISEL2.
Rev. 2.0, 11/ 00, page 676 of 1037
28.4.8 Cautions
(1) When bot h t he 5-bi t DFG c ounte r a nd 16-bi t timer counter are operating, the latter is not
cleared if input of DPG and DFG si gna l s is st oppe d. T h i s leads to free-running of the 16-bit
timer counter, and periodical detection of matching by the 16-bit timer counter. In such a
case, the period of the output from the HSW timing generator is independent from DPG or
DFG.
(2) Specify the mode setting bit (LOP) of the HSW mode register 2 (HSM2) immediately before
writing the FIFO data.
(3) Input the ri si ng e dge of DPG a nd DFG c ount e dge at di ffe re nt timings. If the same timing
was input , c ount i ng up of DFG and clearing of the 5-bit DFG c ount e r oc c urs si m ultaneously.
In this case, the latter will take precedence. This leads to the 5-bit DFG counte r ' s la g by 1.
Figure 28.25 shows the input timing of DPG an d DFG.
(4) If stop of the drum system is required when FIFO output is being used in the 20-stage output
mode, rewrite the SOFG bit o f HSM2 r e g i st er 0 → 1 → 0 by software, and initialize the
FIFO output stage to the FIFO1 side without fail. Also clear and rewrite the data of FIFO1
and FI FO2.
DPG
I ± T
P · FG
I > (1 state)
T
P · FG
DFG
Note: When the DFG counter takes count at the rising edges of DFG
Fi g ur e 2 8 . 2 5 Input T i m i ng o f DPG and DFG
Rev. 2.0, 11/ 00, page 677 of 1037
28.5 Four-head High-speed Switching Circuit f or Special P layback
28.5.1 Overview
This four-head high-speed switching circuit generates a color rotary signal (C.Rotary) and head-
amplifier switching signal (H.Amp SW) for use in four-head special playback.
A pre-am pl i fi e r out put c om pa ri son re sult si gna l i s input from th e COMP pi n. T he si gna l out put
at the C. Rot ary pi n i s a Chroma signa l proc e ssing control signa l. T he signal out put a t the
H.Amp SW pin is a pre-amplifier output select signal. To reduce the width of noise bars, the
C.Rotary and H.Amp SW signals are synchronized to the horizontal sync signal (OSCH). OSCH
is made by adding supplemented H, which has been separated from the Csync signal in the sync
signal detector circuit. For more details of OSCH, see section 28.15, Sync Signal Detector.
If the C. Rot a ry, H. Am p SW or COMP pi n doe s not requi re t hi s ci rc ui t t o c onfi gure a VCR
system, it can be used as an I/O port.
28.5.2 Block Diagram
Figure 28.26 shows the bloc k dia gra m of t hi s circ ui t.
WW
Synchronization
control
· CHCR
W
· CHCR
RTP0
H.Amp SW
C.Rotary
OSCH
(Synchronization)
COMP
Narrow.FF
Video.FF
W
· CHCR
Internal bus
Internal bus
HAHCRH
W
· CHCR
SIG3 to 0
HSWPOLV/N
Decoding circuit
Figure 28.26 Four-Head High-Speed Switching Circuit for Special Playback
Rev. 2.0, 11/ 00, page 678 of 1037
28.5.3 Pin Configuration
Table 28.7 summarizes the pin configuration of the high-speed switching circuit used in four-
head special playback. They can also be used as I/O ports when not in use. See section 28.2,
Servo Port.
Table 28.7 Pin Configuration
Name Abbrev. I/O Function
Compare input pin COM P Input Input of pr e- am plifier out put r esult signal
Color rotar y signal output
pin C.Rotary Output Out put of chr om a pr ocessing cont r ol
signal
Head-amplifier switching pin H.Am p SW Out put Out put of pre- am plifier out put select
signal
28.5.4 Register Description
(1) Regi st e r Co nf i g ur a tion
Table 28.8 shows the register configuration of the high-speed switching circuit used in four-
head special playback.
Table 28.8 Register Configuration
Name Abbrev. R/W Size Init i al Value Address
Special playback cont r ol
register CHCR W Byte H'00 H'FD06E
Rev. 2.0, 11/ 00, page 679 of 1037
(2) Special Playback Control Register (CHCR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HAH SIG3 SIG2 SIG1 SIG0
0
W
V/N
WWW
HSWPOL CRH
Bit :
Initial value :
R/W :
The special playback control register (CHCR) is an 8-bit write-only register. It cannot be read.
If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset,
stand-by or module stop.
Bit 7: HSW Signal Selection Bit (V/N)
Selects the HSW signal to be used at special playback.
Bit 7
V/N Description
0 Video FF signal output (Init ial value)
1 Narrow FF signal output
Bit 6: COMP Polarity Selection Bit (HSWPOL)
Selects the polarity of the COMP signa l.
Bit 6
HSWPOL Description
0 Pos itive (Init ia l v a lu e)
1 Negative
Bit 5: C.Rotary Synchronization Control Bit (CRH)
Synchronizes the C.Rotary signal with the OSCH signal.
Bit 5
CRH Description
0 Synchronous (Init ial value)
1 Asynchronous
Rev. 2.0, 11/ 00, page 680 of 1037
Bit 4: H. Amp SW Synchronization Control Bit (HAH)
Synchronizes the H.Amp SW signal with the OSCH signal.
Bit 4
HAH Description
0 Synchronous (Init ial value)
1 Asynchronous
Bits 3 to 0: Signal Control Bits (SIG3 to SIG0)
These bits, combined with the state of the COMP input pin, cont rol t he out put s at t he C. Rot a ry
and H.Amp SW pins.
Bit 3 Bit 2 Bit 1 Bit 0 Output Pins
SIG3 SIG 2 SI G1 SI G0 C.Rotary H. Am p SW
0**L L ( I nit ial value)
0HSW L0
1
+6:
H
0L HSW
0
1
1
1H
+6:
0 HSW EX-OR
COMP COMP0
1 HSW EX-NOR
COMP COMP
0 HSW E-OR RTP0 RTP0
1
1
1
*
HSW EX- NOR
RTP0 RTP0
Note: *Don't care.
Rev. 2.0, 11/ 00, page 681 of 1037
28.6 Drum Sp eed Error Det ect or
28.6.1 Overview
Drum speed error control operates so as to hold the drum at a constant revolution speed by
measuring the period of the DFG signa l . A di g ital counter detects the speed deviation from a
preset value. The speed error data is processed and added to phase error data in a digital filter.
This filter controls a pulse-width modulated (PWM) output, which controls the revolution speed
and phase of the drum .
The DFG i nput si gna l i s re shap ed in to a squa re wa ve by a resha pi ng c i rc ui t , a nd se nt t o t he
speed error detector as the DFG si g n a l .
The speed error detector uses the system clock to measure the period of the DFG si gn a l, a n d
detects the deviation from a preset data value. The preset data is the value that would result
from measuring the DFG signal pe ri od wi t h t he c l oc k si gna l i f t he drum m ot or wa s runni ng a t
the correct speed.
The error detector operates by latching a counter value when it detects an edge of the DFG
signal. The latched count provides 16 bits of speed error data for the digital filter to operate on.
The digital filter processes and adds the speed error data to phase error data from the drum phase
control system, then sends the result to the pulse-width modulator as drum error data.
28.6.2 Block Diagram
Figure 28.27 shows a block diagram of the drum speed error detector.
Rev. 2.0, 11/ 00, page 682 of 1037
WW R
UDF
OVF
Rock 2 up
Clear
Latch
Preset
· DFVCR
· DFRLOR
· DFVCR
· DFPR
· DFVCR
· DFVCR
· DFVCR
· DFUCR
· FGCR
· DFER
· DFRVCR
Error data
(16 bits)
To DFU
ADDFGN
NCDFG
· DFRUDR
Internal bus
W R/W
Internal bus
R/W WR/WR/W
R/W R/W (R)/W
Rock 1 up
S
RF/FQ
S
R
F/F
DFRCS1,0
DF-R/UNR
Lock counter
(2 bits)
Q
S
R
F/F
Q
Lock range
detector
Lock range data 1 (16bit)
DPCNT
Error data
limitter
control circuit
DFEFON
DFESS
DRF
Edge
detector
,
Error data (16bit)
Counter (16bit)
DFOVF
IRRDRM2
IRRDRM1
To DROCKON
DFU
Preset data
(16 bits) Lock range data 2
(16 bits)
DFCS1,0
s
s/2
s/4
s/8
Figure 28. 27 Bl oc k Diagram Of The Drum Speed Error Dete ctor
Rev. 2.0, 11/ 00, page 683 of 1037
28.6.3 Register Configuration
Table 28.9 shows the register configuration of the drum speed error detector.
Table 28.9 Register Configuration
Name Abbrev. R/W Size Init ial Value Address
Specified DFG speed
preset data register DFPR W Word H'0000 H'FD030
DFG speed err or dat a
register DFER R/W Word H'0000 H'FD032
DFG lo c k UPPER d a ta
register DFRUDR W Word H'7FFF H'FD034
DFG lo c k L OWER d a t a
register DFRLDR W Word H'8000 H'FD036
Drum speed er r or
detection cont r ol register DFVCR R/W Byte H'00 H'FD038
Rev. 2.0, 11/ 00, page 684 of 1037
28.6.4 Register Descriptions
(1) Specified DFG Speed Preset Data Register (DFPR)
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
The specified DFG speed pr e set data is set in DFPR . Whe n t h e d ata is written, a 16-bit preset
data is sent to the preset circuit. The preset data is referenced to H'8000*, and can be calculated
from the following equation.
φs/n
Specifi ed DFG speed preset data =H'8000− ( −2)
DFG f re quency
φ s: Servo clock fre que ncy (fosc/ 2) i n Hz
DFG fre q uenc y : In Hz
The constant 2 is the presetting interval (see Figure 28.28).
φ s/n Clock source of selected counter
DFPR is a 16-bi t wr ite-only register, and is accessible by word access only. Byte access gives
una ssu red r e su l t s. Re ads a r e d i sa b l ed. DFPR i s initialized to H'0000 by a reset, and in standby
mode and m odul e stop m ode .
Note: * The preset data value is calculated so that the counter will reach H'8000 when the
error is zero. When the counter value is latched as error data in the DFG speed error
data register (DFER), however, it is converted to a value referenced to H'0000.
Rev. 2.0, 11/ 00, page 685 of 1037
(2) DFG Speed Error Data Register (DFER)
0
R*/W
13
0
R*/W
14
0
R*/W
15 1032547
0
R*/W
6
0
R*/W
9
0
R*/W
8
0
R*/W
11
0
R*W
10
0
R*/W
0
R*/W R*/W R*/WR*/W R*/WR*/W R*/W
12
000000
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
DFER is a re gi st er t ha t st ore s 16-bit DFG spe e d e rror data. When the drum motor speed is
correct, the data latched in DFER is H'0000. Negative data will be latched if the speed is too
fast, and positive data if the speed is too slow. The DFER value is sent to the digital filter either
automatically or by software.
DFER is a 16-bit readable/writable register. DFER is accessible by word access only. Byte
access gives unassured results. DFER is initialized to H'0000 by a reset, and in standby mode
and module stop m ode.
Refer to the Note in 28.6.4 (1) Specified DFG Spe ed Prese t Data Register (DFPR).
(3) DFG Loc k UP P ER Data Re gi ste r (DF RUDR)
1
W
13
1
W
14
0
W
15 1032547
1
W
6
1
W
9
1
W
8
1
W
11
1
W
10
1
W
1
WWWWWWW
12
111111
Bit :
Initial value :
R/W :
DFRUDR is a re gi st e r use d t o se t t he l oc k ra nge on t he UPPE R si de whe n drum spe e d l oc k is
detected, and to set the limit value on the UPPER si d e wh e n t h e limiter function is in use. Set a
signed data to DFRUDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock
counter whic h ha s been set by DFRCS 1 and 0 bits of the DFVCR register count s down. If the
set value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the
computation of the digital filter in the drum phase system can be controlled automatically. Also,
if t he DFG spe e d e rror data is beyond the DFRUDR value while the limiter function is in use,
the DFRUDR value can be used as the data for computation by the digital filter.
DFRUDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined
value is read out. It is initialized to H'7FFF by a re se t, sta nd-by or modul e -st op.
Rev. 2.0, 11/ 00, page 686 of 1037
(4) DFG Lock LOWER Data Register (DFRLDR)
0
W
13
0
W
14
1
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
DFRLDR is a register used to set t he l oc k range on t he L OWE R side when drum spee d loc k i s
detected, and to set the limit value on LOWER side when the limiter function is in use. Set a
signed data to DFRLDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock
counter whic h ha s been set by t he DFRCS1 and DFRCS0 bits of the DFVCR register counts
down. If the set value of DFRCS1 and DFRCS0 matches the number of times of occurrence of
locking, the computation of the digital filter in the drum phase system can be controlled
automatically. Also, if the DFG speed e rror data is under the DFRLDR value when the limiter
function is in use, the DFRLDR value can be used as the data for computation by the digital
filter.
DFRLDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined
value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop.
(5) Drum Spe e d E r ror De t e cti o n Co ntrol Re g i st e r (DF VCR)
0
0
1
0
(R)
*2
/W
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*1
56
0
7DFRFON
DF-R/UNR
DPCNT DFRCS1 DFRCS0
0
R/W
DFCS1
(R)
*2
/WRR/W
DFCS0 DFOVF
Notes:
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
DFVCR controls the operation of drum speed error detection.
DFVCR is an 8-bit readable/writable register. Bit 3 accepts only read, and bit 5 accepts only
read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop.
Rev. 2.0, 11/ 00, page 687 of 1037
Bits 7 and 6: Clock Source Selection Bits (DFCS1, DFCS0)
DFCS1 and DFCS0 select the clock to be supplied to the counter. (φs = fosc/2)
Bit 7 Bit 6
DFCS1 DFCS0 Description
0φs (I n itial va lu e)0
1φs/2
0φs/41
1φs/8
Bit 5: Counter Overflow Flag (DFOVF)
The DFOVF fla g i n dicates the overflow of the 16-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
DFOVF Description
0 Norm al s tate (Init ia l v a lu e)
1 Indicates t hat over flow has occurred in the counter
Bit 4: Error Data Limit Function Selection Bit (DFRFON)
Makes the error data limit function valid. (Limit values are the values set in the lock range data
register (DFRUDR, DFRLDR)).
Bit 4
DFRFON Description
0 Limit func tion o ff (Init ia l v a lu e)
1 Limit f unct ion on
Bit 3 : Drum L ock Flag ( DF - R/ UNR)
Sets a flag i f a n underfl ow occ urred i n t he drum l ock c ount er.
Bit 3
DF-R/UNR Description
0 Indicates t hat the drum speed system is not locked (Initial value)
1 Indicates t hat the drum speed system is locked
Rev. 2.0, 11/ 00, page 688 of 1037
Bit 2: Drum Phase System Filter Computation Automatic Start Bit (DPCNT)
Sets on the filter computation of the phase system if an underflow occurred in the drum lock
counter.
Bit 2
DPCNT Description
0 Does not perform t he f ilter com put ation by detection of t he dr um lock (Initial value)
1 Sets on the filter comput at ion of t he phase syst em when drum lock is detected
Bit s 1 and 0 : Dr um Lo c k Co unt e r Sett i ng Bits (DFRCS1, DFRCS0)
Set the number of times where drum lock has been determined (DFG ha s b e e n d etected in the
range set by the lock range data register). It sets the drum lock flag if it detected the set number
of times of occurrence of drum lock. If an NCDFG sign a l is detected outside the lock range
after data is written in DFRCS1 and 0, data is stored in the lock counter.
Note: If DFRCS1 or DFRCS0 is read-accessed, the counter value is read out. If bit 3 (drum
lock flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed
system is locked. The drum look counter stops until lock is released after underflow.
Bit 1 Bit 0
DFRCS1 DFRCS0 Description
0 Underf low aft er lock was detected once (Initial value)0
1 Underf low aft er lock was detected twice
0 Underf low aft er lock was detected three t imes1
1 Underf low aft er lock was detected four t imes
Rev. 2.0, 11/ 00, page 689 of 1037
28.6.5 Description of Operation
The drum speed error detector detects the speed error based on the reference value set in the
DFG specified speed preset register (DFPR). T h e r e f e r e n c e va l u e set i n DFPR is preset in t h e
counte r by t h e NCDFG signa l , and c ount s down by t he s elected clock. The timing of the counter
presetting and the error data latching can be selected between the rising or falling edge of the
NCDFG sig n a l . Se e section 28.14.4, DFG Noise Re m ova l Circ ui t . T he e rror data detected is
sent to the digital filter circuit. The error data is signed binaries. It takes a positive number (+)
if the speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if
it correct (revolving at the specified speed). Figure 28.28 shows an example of operation to
detect the drum speed.
(a) Setting the error data limit
A limit can be set to the error data sent to the digital filter circuit using the DFG lock d a t a
register (DFRUDR, DFRLDR). Set the upper limit of the error data in DFRUDR and the
lower limit in DFRLDR, and write 1 in the DFRFON bit. If the e rror data is beyond the limit
range, the DFRLDR value is sent if a negative number is latched, or the DFRUDR value is
sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting
(DFRFON = 0) when you se t t he limit value. If the limit was set with the limit setting on
(DFRFON = 1 ), re su l t of c o m p utation is not assured.
(b) Lock detection
If an error data was detected within the lock range set in the lock data register, the drum lock
flag (DF-R/UNR) is set by the number of the times of occurrence of locking set by the
DFRCS1 and DFRCS0 bits, and an interrupt is requested (IRRDRM2) at the same time. The
number of the occurrence of locking (once to 4 times) can be specified when setting the flag.
Use th e DFRCS1 a nd DFRCS0 bi t s for t hi s purpose. Also, i f bi t 5 (DPHA bi t ) of t he drum
system digital filter control register (DFIC) is 0 (phased system digital filter computation off)
and the DPCNT bit is 1, turning on/off of the phase system digital filter computation can be
controlled automatically by the status of lock detection.
(c) Drum system speed error detection counter
The drum system speed error detection counter stops the counter and sets the overflow flag
(DFOVF) when t he ove rfl ow occ urre d. At t he same time, it generates an interrupt request
(IRRDRM1). Clear DFOVF by writing 0 after reading 1. If setting the flag and writing 0
take place simultaneously, the latter is nullified.
Rev. 2.0, 11/ 00, page 690 of 1037
(d) Interrupt re que st
IRRDRM1 is generated by the NCDFG sig nal latch and the overflow of the error detection
counter. IRRDRM2 is generated by detection of lock (after the detection of the number of
times of setting).
–value+value
Specified speed value
Latch data 0
(no error)
Preset value
Preset period
(2 counts)
Counter
NCDFG signal
Error data latch
signal (DFG )
Preset data
load
Figure 28. 28 Example of the O perati on of the Drum Speed Error Dete cti on
(Selection of the Rising Edge of DFG)
Rev. 2.0, 11/ 00, page 691 of 1037
28.6.6 fH Correction in Trick Play Mode
In trick play mode, the tape speed changes relative to the video head. This change alters the
horizontal sync signal (fH), causing skew. To correct the skew, the drum motor speed must be
shifted to a different speed in each trick play mode, so as to obtain the normal horizontal sync
frequency. To shift the drum motor speed, software should modify the value written in the DFG
preset data register in the speed error detector.
This fH correction can be expressed in terms of the basic frequency fF of the drum a s follows.
N0
fF = × fF0
N0+αH (1−n)
Legend:
n: Speed multiplier (FWD = positive, REV = negative)
αH: H al ignm e nt (1. 5H in sta nda rd mode , 0. 75H in 2x m ode, a nd 0. 5H in 3x m ode for
VHS and β systems; 1H for an 8-mm VCR)
N0: Standard H numbers within field
fF0: Field frequency
NTSC: N0 = 262. 5, fF0 = 59. 94
PAL: N0 = 312. 5, fF0 = 50.00
Rev. 2.0, 11/ 00, page 692 of 1037
28.7 Drum Ph ase Error Det ect or
28.7.1 Overview
Drum phase control must start operating after the drum motor is brought to the correct revolution
speed by the speed control system. Drum phase control works as follows in record and
playback.
Record: Phase is controlled so that the vertical blanking intervals of the recorded video signal
will line up along the bottom edge of the tape.
Playback: Phase is controlled so as to trace the recorded tracks accurately.
A digital counter detects the phase deviation from a preset value. The phase error data is
processed and added to speed error data in a digital filter. This filter controls a pulse-width
modulated (PWM) output, which controls the rotational phase and speed of the drum.
The DPG si gna l from th e drum m ot or i s resha pe d i nt o a rectangular pulse waveform by a
reshaping circuit, and sent to the phase error detector.
The phase error detector compares the phase of the DPG p ulse ( tackle pulse), which contains
video head phase information, with a reference signal. In the actual circuit, the comparison is
carried out by comparing the head-switching (HSW) signal, which is delayed by a counter that is
reset by DPG, with a r e f e r e n c e signal valu e . T he re f e r e n c e sign a l is th e R E F3 0 si g nal, which
differs betwee n re cord a nd pl ayba c k as foll ows.
Record: Vsync signal extracted from the video signal to be recorded (frame rate signal, actually
1/2 Vsync)
Playback: 30 Hz or 25 Hz signal divided from the system clock
28.7.2 Block Diagram
Figure 28.29 shows a block diagram of the drum phase error detector.
Rev. 2.0, 11/ 00, page 693 of 1037
R/W R/W R/W R/W R/W
R/W
REF30P
HSW
(Video FF)
NHSW
(Narrow FF)
·
DPGCR
·
DPGCR
·
DPGCR
·
DFUCR
·
DPGCR
·
DPPR1
·
DPPR2
R/(W)
S
R
F/F
Q
WW
Internal bus
Internal bus
OVF
LSBMSB
·
DPER1
·
DPER2
LSBMSB
DPOVF
DFEPS
HSWES
N/V
Latch
Preset
Error data (20 bits)
To DFU
Edge
detector
Sequence
controller
,
Error data
(16bit)
Error data
(4bit)
Preset data
(16bit)
Preset data
(4bit)
Counter (20bit)
IRRDRM3
DPCS1,0
s
s/2
s/4
s/8
s = fosc/2
Figure 28. 29 Bl oc k Diagram of Drum Phase Error Dete ctor
Rev. 2.0, 11/ 00, page 694 of 1037
28.7.3 Register Configuration
Table 28.10 shows the register configuration of the drum phase error detector.
Table 28.10 Register Configuration
Name Abbrev. R/W Size Init i al Value Address
Drum phase pr eset dat a
register 1 DPPR1 W Byte H'F0 H'FD03C
Drum phase pr eset dat a
register 2 DPPR2 W Word H'0000 H'FD03A
Drum phase er r or dat a
register 1 DPER1 R/W Byte H'F0 H'FD03D
Drum phase er r or dat a
register 2 DPER2 R/W Word H'0000 H'FD03E
Drum phase er r or
detection cont r ol register DPGCR R/W Byte H'07 H'FD039
Rev. 2.0, 11/ 00, page 695 of 1037
28.7.4 Register Descriptions
(1) Drum Phase Preset Data Registers (DPPR1, DPPR2)
DPPR1
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7————
———— WW
1
Bit :
Initial value :
R/W :
DPPR2
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
The 20-bit preset data that defines the specified drum phase is set in DPPR1 a nd DPPR2. The
20 bits are weighted as follows. Bit 3 of DPPR1 is the MSB, and bit 0 of DPPR2 is the LSB.
When data is written to DPPR2, the 20-bit preset data, including DPPR1, is loaded into the
preset circuit. Write to DPPR1 first, and DPPR2 next. The preset data is referenced to
H'80000*, and can be calculated from the following equation.
Target pha se diffe re nce = (refe re nce signa l fre que ncy/ 2) − 6. 5H
Drum phase preset data = H'80000 - (φs/n × targe t pha se di ffere nc e)
φs: Servo cl oc k freque nc y in Hz (fosc/ 2)
φs/n: Clock source of selected counter
DPPR2 is accessible by word access only. Byte access gives unassured results. Reads are
disabled. DPPR1 and DPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby
mode.
Note: * The preset data value is calculated so that the counter will reach H'80000 when the
error value is zero. When the counter value is latched as error data in the drum phase
error data registers (DPER1 and DPER2), however, it is converted to a value
referenc e d to H' 00000.
Rev. 2.0, 11/ 00, page 696 of 1037
(2) Drum Phase Error Data Registers (DPER1, DPER2)
DPER1
0
0
1
0
R*/W
2
0
R*/W
3
0
4
1
5
1
6
1
7————
———— R*/WR*/W
1
Bit :
Initial value :
R/W :
DPER2
0
R*/W
13
0
R*/W
14
0
R*/W
15 1032547
0
R*/W
6
0
R*/W
9
0
R*/W
8
0
R*/W
11
0
R*/W
10
0
R*/W
0
R*/W R*/W R*/WR*/W R*/WR*/W R*/W
12
000000
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
DPER1 and DPE R2 c onsi st of a 20-bi t DPG pha se e rror data register. The 20 bits are weighted
as follows. Bit 3 of DPER1 is the MSB, and bit 0 of DPER2 is the LSB. When the rotational
phase is correct, the data H'00000 is latched. Negative data will be latched if the drum leads the
correct phase, and positive data if it lags. Values in DPER1 and DPER 2 are transferred to the
digital filter circuit.
DPER1 and DPER2 are 20-bit readable/writable registers. When writing data to DPER1 and
DPER2, write to DPER1 first, and then write to DPER2. DPER2 is accessible by word access
only. Byte access gives unassured results. DPER1 and DPER2 are initialized to H'F0 and
H'0000 by a reset , and i n sta ndby mode .
See the note on the drum phase preset data registers (DPPR1 and DPPR2) in section 28.7.4 (1).
Rev. 2.0, 11/ 00, page 697 of 1037
(3) Drum Phase Error Detection Control Register (DPGCR)
0
1
12 ———
———
1
3
0
4
0
R/W R/W
5
0
6
0
7
R/(W)*
DPOVF
R/W
DPCS0
0
R/W
DPCS1 N/V HSWES
1
Bit :
Initial value :
R/W :
Note: * Only 0 can be written
DPGCR controls the operation of drum phase error detection.
DPGCR is an 8-bit readable/writable register. Bits 2 to 0 are reserved, bit 5 accepts only read
and 0 write.
It is initialized to H'07 by a reset or stand-by.
Bits 7 and 6: Clock Source Selection Bits (DPCS1, DPCS0)
Select the clock supplied to the counter. (φs = fosc/2)
Bit 7 Bit 6
DPCS1 DPCS0 Description
0φs (I n itial va lu e)0
1φs/2
0φs/31
1φs/4
Bit 5: Counter Overflow Flag (DPOVF)
The DPOVF fl ag i n dicates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
DPOVF Description
0 Norm al s tate (Init ia l v a lu e)
1 Indicates t hat an over flow has occurred in the counter
Rev. 2.0, 11/ 00, page 698 of 1037
Bit 4: Error Data Latch Signal Selection Bit (N/V)
Selects the latch signal of error data.
Bit 4
N/V Description
0 HSW (VideoFF) signal (Init ial value)
1 NHSW (NarrowFF) signal
Bit 3: Edge Selection Bit (HSWES)
Selects the edge of the error data latch signal (HSW or NHSW).
Bit 3
HSWES Description
0 Latches at t he rising edge (Init ial value)
1 Latches at t he falling edge
Bits 2 to 0: Reserved
No read or write is valid.
28.7.5 Description of Operation
The drum phase error detector detects the phase error based on the reference value set in the
drum phase preset data register 1 and 2 (DPPR1, DPPR2). T h e re fe re nc e va l ue s se t i n DPPR1
and DPPR2 are preset in the counter by the REF30P signal, and counted up by the clock
selected. The latch of the error data can be selected between the rising or falling edge of HSW
(NHSW). T he e rror data detected in the error data automatic transmission mode (DFEPS bit of
DFUCR = 0) is sent to the digital filter circuit automatically. In software transmission mode
(DFEPS bit of DFUCR = 1), the data written in DPER1 and DPER2 is sent to the digital filter
circuit. The error data is signed binary. It takes a positive number (+) if the phase is behind the
specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no
phase error (revolving at the specified phase). Figures 28.30 and 28.31 show examples of
operation to detect a drum phase error.
(a) Drum phase error detection counter
The drum phase error detection counter stops the counter when overflow or latch occurred.
At the same time, it generates an interrupt request (IRRDRM3), setting the overflow flag
(DPOVF) if overfl ow oc c urre d. Clear DPOVF by writing 0 after reading 1. If setting the
flag and writing 0 take place simultaneously, the latter is nullified.
(b) Interrupt re que st
IRRDRM3 is generated by the HSW (NHSW) signal latch and the overflow of the error
detection counter.
Rev. 2.0, 11/ 00, page 699 of 1037
Latch Latch
Preset value
Counter
HSW (NHSW)*
REF30P
Preset value
Preset
Note: * Edge selectable
Preset
Figure 28.30 Drum Phase Control in Playback Mode (HSW Rising Edge Selected)
Latch Latch
Preset value
Counter
HSW (NHSW)*
VD
REF30P
Preset value
Preset
Note: * Edge selectable
Preset
Reset Reset
Figure 28.31 Drum Phase Control in Record Mode (HSW Rising Edge Selected)
Rev. 2.0, 11/ 00, page 700 of 1037
28.7.6 Phase Comparison
The phase comparison circuit takes measures of the difference of time between the reference
signal and the comparing signal with a digital counter. The REF30 signal is used for the
refere nc e si gna l , a nd t he HSW si gna l (Vi de oFF) or HHSW si gna l (Na rrowFF) from th e HSW
timing generator is used for the comparing signal. In record mode, however, the phase of the
REF30 signal is the same as that of the vertical sync signal (Vsync) because the reference signal
generator (REF30 generator) is reset by the vertical sync signal (Vsync) in the video signals.
The error detection counter performs the data latching operation at the rising or falling edge of
the HSW signal. The digital filter circuit performs computation using this data as 20-bit phase
error data. After processing and adding the phase error data and the speed error data from the
drum speed control system, the digital filter circuit sends the data as the error data of the drum
system to the PWM modulation circuit.
Rev. 2.0, 11/ 00, page 701 of 1037
28.8 Capstan S peed Error Det ect or
28.8.1 Overview
Capstan speed control operates so as to hold the capstan motor at a constant revolution speed, by
measuring the period of the CFG signal. A digital counter detects the speed deviation from a
preset value. The speed error data is added to phase error data in a digital filter. This filter
controls a pulse-width modulated (PWM) output, which controls the revolution speed and phase
of the capstan motor.
The CFG input signal i s downloaded by t he com pa rat or c irc ui t, t he n reshape d i nto a square wave
by a reshaping circuit, divided by the CFG divider, and sent to the speed error detector as the
DVCFG sig n a l .
The speed error detector uses the system clock to measure the period of the DVCFG signal, and
detects the deviation from a preset data value. The preset data is the value that would result
from measuring the DVCFG signal period with the clock signal if the capstan motor was running
at the correct speed.
The error detector operates by latching a counter value when it detects an edge of the DVCFG
signal. The latched count provides 16 bits of speed error data for the digital filter to operate on.
The digital filter adds the speed error data to phase error data from the capstan phase control
system, then sends the result to the pulse-width modulator as capstan error data.
28.8.2 Block Diagram
Figure 28.32 shows a block diagram of the capstan speed error detector.
Rev. 2.0, 11/ 00, page 702 of 1037
WW R
UDF
OVF
Lock 2 up
Clear
Latch
Preset
· CFVCR
· CFRLDR
· CFVCR
· CFPR
· CFVCR
· CFVCR
· CFVCR
· CFUCR
· CFER
· CFRVCR
Error data
(16 bits)
To DFU
DVCFG
· CFRUDR
Internal bus
R/W
Internal bus
R/W WR/WR/W
R/W R/W (R)/W
Lock 1 up
S
RF/FQ
S
R
F/F
CFRCS1,0
CF-R/UNR
Lock counter
(2 bits)
Q
S
R
F/F
Q
Lock range
detector
Lock range data 2 (16 bits)
Lock range data 1 (16 bits)
CPCNT
Error data
limitter
control
circuit
CFRFON
CFESS
Error data
(16 bits)
Counter (16 bits)
CFOVF
IRRCAP2
IRRCAP1
CROCKON
To DFU
Preset data (16bit)
CFCS1,0
s
s/2
s/4
s/8
Figure 28. 32 Bl oc k Diagram of Capstan Spee d Err or Dete c tor
Rev. 2.0, 11/ 00, page 703 of 1037
28.8.3 Register Configuration
Table 28.11 shows the register configuration of the capstan speed error detector.
Table 28.11 Register Configuration
Name Abbrev. R/W Size Init ial Value Address
CFG speed preset dat a
register CFPR W Word H'0000 H'FD050
CFG speed err or dat a
register CFER R/W Word H'0000 H'FD052
CFG lo c k UPPER d a ta
register CFRUDR W Word H'7FFF H'FD054
CFG lo c k L OWER d a t a
register CFRLDR W Word H'8000 H'FD056
Capstan speed err or
detection cont r ol register CFVCR R/W Byte H'00 H'FD058
Rev. 2.0, 11/ 00, page 704 of 1037
28.8.4 Register Descriptions
(1) CFG Speed Preset Data Register (CFPR)
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
The 16-bit preset data that defines the specified CFG speed is set in CFPR. The preset data is
referenced to H'8000*, and can be calculated from the following equation.
φs/n
CFG speed preset data =H'8000 − ( − 2)
DVCFG frequency
φs: Servo c l ock fre que ncy i n Hz (fOSC/2)
DVCFG freque nc y: In Hz
The consta nt 2 is the pre set i nt erva l (see fi gure 28. 33).
φs/n: Clock source of the selected counter
CFPR is a 16-bit write-only register. CFPR is accessible by word access only. Byte access
gives unassured results. No read is valid. If a read is attempted, an undetermined value is read
out. CFPR is initialized to H'0000 by a reset, stand-by or module stop.
Note: * The preset data value is calculated so that the counter will reach H'8000 when the
error is zero. When the counter value is latched as error data in the CFG speed error
data register (CFER), however, it is converted to a value referenced to H'0000.
Rev. 2.0, 11/ 00, page 705 of 1037
(2) CFG Speed Error Data Register (CFER)
0
R*/W
13
0
R*/W
14
0
R*/W
15 1032547
0
R*/W
6
0
R*/W
9
0
R*/W
8
0
R*/W
11
0
R*/W
10
0
R*/W
0
R*/W R*/W R*/WR*/W R*/WR*/W R*/W
12
000000
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
CFER is a 16-bit data register. When the speed of the capstan motor is correct, the data latched
in CFER is H'0000. Negative data will be latched if the speed is too fast, and positive data if the
speed is too slow. The CFER value is sent to the digital filter either automatically or by
software.
CFER is a 16-bit readable/writable register. CFER is accessible by word access only. Byte
access gives unassured results. CFER is initialized to H'0000 by a reset, and in module stop
mode and sta ndby m ode.
See the note on the CFG speed preset data register (CFPR) in section 28.8.4 (1).
(3) CFG Loc k UP P ER Data Re gi ste r (CF RUDR)
1
W
13
1
W
14
0
W
15 1032547
1
W
6
1
W
9
1
W
8
1
W
11
1
W
10
1
W
1
WWWWWWW
12
111111
Bit :
Initial value :
R/W :
CFRUDR is a regi st er used t o se t the loc k range on the UPPER si d e wh e n c a p st an spee d loc k i s
detected, and to set the limit value on the UPPER si d e wh e n t h e limiter function is in use.
When lock is being detected, if the capstan speed is detected within the lock range, the lock
counter whic h ha s been set by t he CFRCS1 and CFRCS0 bits of the CFVCR registe r c ounts
down. If the set value of CFRCS1 and CFRCS0 matches the number of times of occurrence of
locking, the computation of the digital filter in the capstan phase system can be controlled
automatically. Also, if the CFG speed error data is beyond the CFRUDR value when the limiter
function is in use, the CFRUDR value can be used as the data for computation by the digital
filter.
CFRUDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. A read is invalid. If a read is attempted, an undetermined
value is read out. It is initialized to H'7FFF by a re se t, sta nd-by or modul e -st op.
Rev. 2.0, 11/ 00, page 706 of 1037
(4) CFG Lock LOWER Data Register (CFRLDR)
0
W
13
0
W
14
1
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
CFRLDR is a register used to set the lock range on the LOWER side when capstan speed lock is
detected, and to set the limit value on LOWER side when limiter function is in use.
When lock is being detected, if the drum speed is detected within the lock range, the lock
counter whic h ha s been set by t he CFRCS1 and CFRCS0 bits of the CFVCR registe r c ounts
down. If the set value of CFRCS1 and CFRCS0 matches the number of times of occurrence of
locking, the computation of the digital filter in the drum phase system can be controlled
automatically. Also, if the CFG speed error data is under the CFRLDR value when the limiter
function is in use, the CFRLDR value can be used as the data for computation by the digital
filter.
CFRLDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined
value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop.
(5) Ca pst an Speed E r ror De t e cti o n Co ntrol Re g i st e r (CF VCR)
0
0
1
0
(R)
*2
/W
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*1
56
0
7CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0
0
R/W
CFCS1
(R)
*2
/WRR/W
CFCS0 CFOVF
Notes:
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
CFVCR controls the operation of capstan speed error detection.
CFVCR is an 8-bit readable/writable register. Bit 3 accepts only read, and bit 5 accepts only
read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop.
Bits 7 and 6: Clock Source Selection Bits (CFCS1, CFCS0)
CFCS1 and CFCS0 select the clock to be supplied to the counter. (φs = fosc/2)
Bit 7 Bit 6
CFCS1 CFCS0 Description
0φs (I n itial va lu e)0
1φs/2
0φs/41
1φs/8
Rev. 2.0, 11/ 00, page 707 of 1037
Bit 5: Counter Overflow Flag (CFOVF)
The CFOVF flag i n d icates overflow of the 16-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
CFOVF Description
0 Norm al s tate (Init ia l v a lu e)
1 Indicates t hat an over flow has occurred in the counter
Bit 4: Error Data Limit Function Selection Bit (CFRFON)
Makes the error data limit function valid. (Limit values are the values set in the lock range data
register (CFRUDR, CFRLDR)).
Bit 4
CFRFON Description
0 Limit func tion o ff (Init ia l v a lu e)
1 Limit f unct ion on
Bit 3 : Ca pst an L o c k F lag (CF-R/ UNR)
Sets a flag i f a n underfl ow occ urred i n t he c a pstan l oc k count e r.
Bit 3
CF-R/UNR Description
0 Indicates t hat the capstan speed syst em is not locked (I nitial value)
1 Indicates t hat the capstan speed syst em is locked
Bit 2: Capstan Phase System Filter Computation Automatic Start Bit (CPCNT)
Sets on the filter computation of the phase system if an underflow occurred in the capstan lock
counter.
Bit 2
CPCNT Description
0 Does not perform t he f ilter com put ation by detection of t he capstan lock
(Init ial value)
1 Set on the filter comput at ion of t he phase syst em when capstan lock is detected
Rev. 2.0, 11/ 00, page 708 of 1037
Bit s 1 and 0 : Capst a n Lo c k Co unt e r Sett i ng Bits (CFRCS1, CFRCS0)
Sets the number of times where drum lock has been determined (DVCFG has been detected in
the range set by the lock range data register). It sets the capstan lock flag if it detected the set
number of times of occurrence of capstan lock. If a DVCFG signal is detected outside the lock
range after data is written in CFRCS1 and CFRCS0, data is stored in the lock counter.
Note: If CFRCS1 or CFRCS0 is read-accessed, the counter value is read out. If bit 3 (capstan
lock flag) is 1 and the capstan lock counter's value is 3, it indicates that the capstan
speed system is locked. The capstan look counter stops until lock is released after
underflow.
Bit 1 Bit 0
CFRCS1 CFRCS0 Description
0 Underf low aft er lock was detected once (Initial value)0
1 Underf low aft er lock was detected twice
0 Underf low aft er lock was detected three t imes1
1 Underf low aft er lock was detected four t imes
28.8.5 Description of Operation
The capstan speed error detector detects the speed error based on the reference value set in the
CFG speed preset register (CFPR). The reference value set in CFPR is preset in the counter by
the DVCFG signal, and counts down by the selected clock. The timing of the counter presetting
and the error data latching can be selected between the rising or falling edge of the DVCFG
signal. See section 28.14.3, CFG Frequency Divider. The error data detected is sent to the
digital filter circuit. The error data is signed binaries. It takes a positive number (+) if the speed
is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it had no
error (revolving at the specified speed). Figure 28.33 shows an example of operation to detect
the capstan speed.
(a) Setting the error data limit
A limit can be set to the error data sent to the digital filter circuit using the CFG lock data
register (CFRUDR, CFRLDR). Set the upper limit of the error data in CFRUDR and the
lower limit in CFRLDR, and write 1 in the CFRFON bit. If the e rror data is beyond the limit
range, the CFRLDR value is sent if a negative number is latched, or the CFRUDR value is
sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting
(CFRFON = 0) when you se t t he limit value. If the limit was set with the limit setting on
(CFRFON = 1), resul t o f c o m p utation is not assured.
Rev. 2.0, 11/ 00, page 709 of 1037
(b) Lock detection
If error data was detected within the lock range set in the lock data register, the capstan lock
flag (CF-R/UNR) is set by the number of the times of occurrence of locking set by the
CFRCS1 and CFRCS0 bits, and an interrupt is requested (IRRCAP2) at the same time. The
number of the occurrence of locking (once to 4 times) can be specified when setting the flag.
Use th e CFRCS1 a nd CFRCS0 bi t s for t hi s purpose. Also, i f bi t 5 (CPHA bi t ) of t he c a pst a n
system digital filter control register (CFIC) is 0 (phased system digital filter computation off)
and the DPCNT bit is 1, turning on/off of the phase system digital filter computation can be
controlled automatically by the status of lock detection.
(c) Capstan system speed error detection counter
The capstan system speed error detection counter stops the counter and sets the overflow flag
(CFOVF) when ove rflow oc c urre d. At t h e s ame time, it generates an interrupt request
(IRRCAP1). Clear CFOVF by writing 0 after reading 1. If setting the flag and writing 0
take place simultaneously, the latter is nullified.
(d) Interrupt re que st
IRRCAP1 is generated by the DVCFG signal latch and the overflow of the error detection
counter. IRRCAP2 is generated by detection of lock (after the detection of the number of
times of setting).
–value +value
Specified speed value
Latch data 0
(no error)
Preset value
Preset period
(2 counts)
Counter
Error data
latch signal
(DVCFG)
Preset data
load
Figure 28. 33 Example of the O perati on of the Capstan Spee d Error Dete cti on
Rev. 2.0, 11/ 00, page 710 of 1037
28.9 Capst an P hase Error Detector
28.9.1 Overview
The capstan phase control system is required to start operation after the capstan motor has
arrived at the specified speed under the control of the speed control system. The capstan phase
control system operates in the following way in record/playback mode.
In record mode: Controls the tape running so that it may run at a specified speed together with
the speed control system.
In playback mode: Controls the tape running so that the recorded track may be traced correctly.
Any error deviated from the reference phase is detected by the digital counter. This phase error
data and the speed error data is processed and added by the digital filter circuit to control the
PWM output. The phase and speed of the capstan, in turn, is controlled by this PWM output.
The cont rol signal of t he c a pstan pha se c ontrol i n REC m ode diffe rs from t hat i n PB mode. In
REC mode, the control is performed by the DVCFG2 signal which is generated by dividing the
frequencies of the reference signal (REF30P or CREF) and the CFG signal. In PB mode, it is
performed by di vi ded ri sing signa l (DVCTL) of t he refe re nce signa l (CAPREF30) and the
playbac k c ontrol pul se (PB-CTL).
The refe re nce signa l i n re cord a nd pl ayba c k mode s are as foll ows.
In record mode: 1/2 Vsync signal extracted from the video signal to be recorded
In playback mode: Signal generated by dividing the PB-CTL signal (DVCTL) at its rising edge
28.9.2 Block Diagram
Figure 28.34 shows the block diagram of the capstan phase error detector.
Rev. 2.0, 11/ 00, page 711 of 1037
R/W R/W R/W R/W R/W
R/W
CREF
REF30P
CAPREF30
RECREF
DVCFG2
DVCTL
· CPGCR
R/W
CR/RF
· CPGCR · DFUCR
· CPGCR
· CPPR1 · CPPR2
R/(W)
S
R
F/F
Q
WW
Internal bus
Internal bus
OVF
LSBMSB
· CPER1 · CPER2
LSBMSB
CPOVF
CFEPS
SELCFG2
R/W
· CTLM
R/P ASM
Latch
Preset
Error data (20 bits)
To DFU
Sequence
controller
Error data
(16 bit)
Error data
(4 bit)
Preset data
(16 bit)
Preset
PB: X value + TRK value = CAPREF30
REC: REF30P or CREF
Latch
PB : DVCTL
REC : DVCFG2Ê
Preset data
(4 bit)
Counter (20 bits)
IRRCAP3
CPCS1,0
s
s/2
s/4
s/8
s = fosc/2
Figure 28. 34 Bl oc k Diagram of Capstan Phase Error Detector
Rev. 2.0, 11/ 00, page 712 of 1037
28.9.3 Register Configuration
Table 28.12 shows the register configuration of the capstan phase error detector.
Table 28.12 Register Configuration
Name Abbrev. R/W Size Init i al Value Address*
Capstan phase preset
data regist er 1 CPPR1 W Byte H'F0 H'FD05C
Capstan phase preset
data regist er 2 CPPR2 W Word H'0000 H'FD05A
Capstan phase err or
data regist er 1 CPER1 R/W Byte H'F0 H'FD05D
Capstan phase err or
data regist er 2 CPER2 R/W Word H'0000 H'FD05E
Capstan phase err or
detection cont r ol register CPGCR R/W Byte H'07 H'FD059
Rev. 2.0, 11/ 00, page 713 of 1037
28.9.4 Register Descriptions
(1) Capstan Phase Preset Data Re gisters (CPPR1, CPPR2)
CPPR1
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7————
———— WW
1
Bit :
Initial value :
R/W :
CPPR2
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
The 20-bit preset data that defines the specified capstan phase is set in CPPR1 and CPPR2. The
20 bits are weighted as follows. Bit 3 of CPPR1 is the MSB. Bit 0 of CPPR2 is the LSB. When
CPPR2 is written to, the 20-bit preset data, including CPPR1, is loaded into the preset circuit.
Write to CPPR1 first, and CPPR2 next. The preset data is referenced to H'80000*, and can be
calculated from the following equation.
Target pha se diffe re nce = Rrefe re nce signa l fre que ncy/ 2
Capstan phase preset data = H'80000 − (φs/n × target pha se diffe re nce )
φs: Servo cl oc k freque nc y in Hz (fosc/ 2)
φs/n: Clock source of selected counter
CPPR2 is accessible by word access only. Byte access gives unassured results. Reads are
disabled. If read is attempted to CPPR1 or CPPR2, an undetermined value is read out. CPPR1
and CPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby mode.
Note: * The preset data value is calculated so that the counter will reach H'80000 when the
error is zero. When the counter value is latched as error data in the capstan phase
error data registers (CPER1 and CPER2), however, it is converted to a value
referenc e d to H' 00000.
Rev. 2.0, 11/ 00, page 714 of 1037
(2) Capstan Phase Err or Data Register s (CPER1, CPER2)
0
0
1
0
R*/W
2
0
R*/W
3
0
4
1
5
1
6
1
7————
———— R*/WR*/W
1
Bit :
Initial value :
R/W :
0
R*/W
13
0
R*/W
14
0
R*/W
15 1032547
0
R*/W
6
0
R*/W
9
0
R*/W
8
0
R*/W
11
0
R*/W
10
0
R*/W
0
R*/W R*/W R*/WR*/W R*/WR*/W R*/W
12
000000
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
CPER1 and CPER2 constitute a 20-bit capstan phase error data register. The 20 bits are
weighted as follows. Bit 3 of CPER1 is the MSB. Bit 0 of CPER2 is the LSB. When the
rotational phase is correct, the data H'00000 is latched. Negative data will be latched if the
phase leads the correct phase, and positive data if it lags. Values in CPER1 and CPER 2 are
transferred to the digital filter circuit.
CPER1 and CPER are 20-bit readable/writable registers. When writing data to CPER1 and
CPER2, write to CPER1 first, and then write to CPER2. CPER2 is accessible by word access
only. Byte access gives unassured results. CPER1 and CPER2 are initialized to H'F0 and
H'0000 by a reset , and i n sta ndby mode .
See the note on the capstan phase preset data registers (CPPR1 and CPPR2) in section 28.9. 4 (1).
Rev. 2.0, 11/ 00, page 715 of 1037
(3) Capstan Phase Error Detection Control Register (CPGCR)
0
1
12 ———
———
1
3
0
4
0
R/W
5
0
6
0
7
R/WR/(W)*
CPOVF
R/W
CPCS0
0
R/W
CPCS1 CR/RF SELCFG2
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
CPGCR controls the operation of capstan phase error detection.
CPGCR is an 8-bit readable/writable register. Bits 2 to 0 are reserved, bit 5 accepts only read
and 0 write.
It is initialized to H'07 by a reset or stand-by.
Bits 7 and 6: Clock Source Selection Bits (CPCS1, CPCS0)
Select the clock supplied to the counter. (φs = fosc/2)
Bit 7 Bit 6
CPCS1 CPCS0 Description
0φs (I n itial va lu e)0
1φs/2
0φs/41
1φs/8
Bit 5: Counter Overflow Flag (CPOVF)
CPOVF fl a g i n d icates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
CPOVF Description
0 Norm al s tate (Init ia l v a lu e)
1 Indicates t hat an over flow has occurred in the counter
Rev. 2.0, 11/ 00, page 716 of 1037
Bit 4: Preset Signal Selection Bit (CR/RF)
Selects the preset signal.
Bit 4
CR/RF Description
0 Presets REF30P signal (Initial value)
1 Presets CREF signal
Bit 3: Preset and Latch Signal Selection Bit (SELCFG2)
Selects the counter preset signal and the error data latch signal data in PB (ASM) mo d e .
Bit 3
SELCFG2 Description
0 Presets CAPREF30 signal; lat ches DVCTL signal (Initial value)
1 Presets REF30P (CREF) signal; latches DVCFG2 signal
Bits 2 to 0: Reserved
No read or write is valid.
28.9.5 Description of Operation
The capstan phase error detector detects the phase error based on the reference value set in the
capstan specified phase preset data register 1 and 2 (CPPR1, CPPR2). The reference values set
in CPPR1 and CPPR2 are preset in t he count e r by the RE F30P (CREF) signal or CAPREF30
signal, and counted up by the clock selected. The latching of the error data is performed by
DVCTL or DVCFG2 .
The error data detected in the error data automatic transmission mode (CFEPS bit of DFUCR =
0) is sent to the digital filter circuit automatically. In software transmission mode (CFEPS bit of
DFUCR = 1), the data written in CPER1 and CPER2 is sent to the digital filter circuit. The error
data is signed binary. It takes a positive number (+) if the phase is behind the specified phase, a
negative number (-) if in advance of the specified phase , or 0 if it had no phase error (revolving
at the specified phase). Figures 28.35 and 28.36 show examples of operation to detect a capstan
phase error.
(a) Capstan phase error detection counter
The capstan phase error detection counter stops the counter when overflow or latch occurred.
At the same time, it generates an interrupt request (IRRCAP3), setting the overflow flag
(CPOVF) if overfl ow oc c urre d. Clear CPOVF by writing 0 after reading 1. If setting the
flag and writing 0 take place simultaneously, the latter is nullified.
Rev. 2.0, 11/ 00, page 717 of 1037
(b) Interrupt re que st
IRRCAP3 is generated by the DVCTL or DVCFG2 signal latch and the overflow of the error
detection counter.
Latch Latch
Preset value
Counter
PB-CTL
CAPREF30
DVCTL
or
DVCFG2
Preset Preset
Figure 28.35 Capstan Phase Control in Playback Mode
Latch Latch
Preset value
Counter
DVCFG2
REF30P
or
CREF
Preset Preset
Figure 28.36 Capstan Phase Control in Record Mode
Rev. 2.0, 11/ 00, page 718 of 1037
28.10 X-Value and Tracking Adjustment Circuit
28.10.1 Overview
To maintain compatibility with other VCRs, an on-chip adjustment circuit adjusts the phase of
the refe re nce signa l (i nt erna l refe re nce signa l (RE F30) or ext erna l refe re nce signa l (E XCAP))
during playback. Because of manufacturing tolerances, the physical distance between the video
head and c ont rol he a d (the X-val ue: 79.244 m m) m a y vary from set to set , so when a
tape t ha t was rec orde d on a di ffe rent set is pla ye d bac k, t he pha se of t he re fe renc e signal m ay
need to be adjusted. The adjustment can be made by a register setting. The same setting can
adjust the rotational phase of the capstan motor to maintain positional alignment (tracking
alignm e nt) of t he vide o he ad wit h t he re c orded t ra cks in a ut otra c king, or when t ra cks tha t were
recorded with an EP head are traced by a wider head. These tracking adjustments can be made
by acquisit i on of the e nvel ope signal by t he A/D conve rt er.
28.10.2 Block Diagram
The adjustment circuit consists of a 10-bit counter clocked by the servo clock (φs or φs/2), a nd
two down-counters with load register. Individual setting of X-value adjustment can be made by
the X-value data register (XDR) and tracking adjustment by the TRK data register (TRDR). The
reference signal clears the 10-bit counter and sets the load register value in the down-counter
with two load registers. After the adjusted reference signal is generated, clock supply stops and
the circuit halts until the next reference signal is input. The REF30 signal can be divided (by 2
to 4) as necessary.
Figure 28.37 shows a block di agra m .
Rev. 2.0, 11/ 00, page 719 of 1037
R*/W
Note: * When DVREF1 and DVREF0 are read, values in the down counter (2 bits) are read out.
s = fosc/2
s
s /2
EXCAP
REF30P
· XTCR
W W
XCS · XTCR
W
AT/MU
ASM REC/PB
· XTCR
W
TRK/X
S
R
Q
S
RQ
Internal bus
Internal bus
DVREF1, 0
CAPRF
EXC/REF
WW
· XTCR
· XTCR
Down counter
Edge
selection
(2bit)
Counter
(10bit)
CAPREF30
REF30X
W
X-value data
register
· XDR
(12bit)
TRK value data
register
· TRDR
(12bit)
Down counter
(12bit)
(12bit)
Down counter
Figure 28.37 Block Diagram of X-Value Adjustment Circuit
Rev. 2.0, 11/ 00, page 720 of 1037
28.10.3 Register Descriptions
(1) Regi st e r Co nf i g ur a tion
Table 28.13 shows the register configuration of X-value adjustment and tracking adjustment
circuits.
Table 28.13 Register Configuration
Name Abbrev. R/W Size Init i al Value Address*
X-value and TRK-value
control regist er XTCR R/W Byte H'80 H'FD074
X-value data regist er XDR W W or d H'F000 H'FD070
TRK-value data register TRDR W Word H'F000 H'FD072
(2) X-value and TRK -value Control Regi ster (XTCR)
0
0
1
0
R/W
2
0
W
3
0
4
0
W
5
0
6
0
7
—
—R/WWW
AT/MU
W
CAPRF TRK/X EXC/REF XCS DVREF1 DVREF0
1
Bit :
Initial value :
R/W :
XTCR is an 8-bit register to determine the X-value and TRK-value adjustment circuits. Bits 6 to
2 are write-only bits. No read is valid. If a read is attempted, an undetermined value is read out.
Bits 1 and 0 are readable/writable bits. XTCR accepts only a byte access. If a word access is
attempted, operation is unassured.
It is initialized to H'80 by a reset, stand-by or module stop.
Bit 7: Reserved
No write is valid. If a read is attempted, an undetermined value is read out.
Bit 6: External Sync Signal Edge Selection Bit (CAPRF)
Selects the EXCAP edge when a selection is made to generate external sync signals.
Bit 6
CAPRF Description
0 Signal generated at the rising edge of EXCAP (Init ial value)
1 Signal generated at both edges of EXCAP
Rev. 2.0, 11/ 00, page 721 of 1037
Bit 5: Capstan Phase Correction Auto/Manual Selection Bit (AT/
08
08
)
Selects whether the generation of the correction reference signal (CAPREF30) for capstan phase
control is controlled automatically or manually depending on the status of the ASM and R E C /
3%
bits of the CTL mode register.
Bit 5
AT/
08
08
Description
0 Manual mode (Init ial value)
1 Auto mode
Bit 4: Capstan Phase Correction Register Selection Bit (TRK/
;
;
)
Determines the method to generate the CAPREF30 signal when the AT/
08
bit is 0.
Bit 4
TRK/
;
;
Description
0 Gener at es CAPREF30 only by t he set value of XDR ( I nitial value)
1 Gener at es CAPREF30 by the set values of XDR and TRDR
Bit 3: Reference Signal Selection Bit (EXC/REF)
Selects the reference signal to generate the correction reference signal (CAPREF30).
Bit 3
EXC/REF Description
0 Gener at es the signal based on REF30P (Init ial value)
1 Gener at es t he signal based on the ext er nal reference signal
Bit 2: Clock Source Selection Bit (XCS)
Selects the clock source to be supplied to the 10-bit counter.
Bit 2
XCS Description
0φs (Init ia l v a lu e)
1φs/2
Rev. 2.0, 11/ 00, page 722 of 1037
Bits 1 and 0: REF30P Division Ratio Selection Bits (DVREF1 , DVREF 0 )
Select the division value of REF30P. If it is read-accessed, the counter value is read out. (The
selected division value is set by the UDF of the c ount e r. )
Bit 1 Bit 0
DVREF1 DVREF0 Description
0 Division in 1 (Initial va lu e)0
1 Division in 2
0 Division in 31
1 Division in 4
(3) X-value Data Re gi ste r (XDR)
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
————
————
XD1 XD0XD3 XD2XD5 XD4XD7 XD6XD9 XD8
XD11 XD10
000000
Bit :
Initial value :
R/W :
The X-value data register (XDR) is a 16-bit write-only register. No read is valid. If a read is
attempted, an undefined value is read out. XDR accepts only a word-access. If a byte access is
attempted, operation is not assured.
Set X-value correction data to XDR, except a value which is beyond the cycle of the CTL pulse.
If AT/
08
= 0, TRK/
;
= 0 was set, CAPREF30 can be generated only by the setting of XDR.
Set an X-value and TRK correction value in PB mode, and an X-value in REC mode.
It is initialized to H'F000 by a reset, stand-by or module stop.
(4) TRK-value Data Re gi ste r (TRDR)
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
————
————
TRD1 TRD0TRD3 TRD2TRD5 TRD4TRD7 TRD6TRD9 TRD8
TRD11 TRD10
000000
Bit :
Initial value :
R/W :
The TRK-value data register (TRDR) is a 16-bit write-only register. No read is valid. If a read
is attempted, an undefined value is read out. TRDR accepts only a word-access. If a byte access
is attempted, operation is not assured.
Set a TRK-value correction data to TRDR, except a value which is beyond the cycle of the CTL
pulse. It is initialized to H'F000 by a reset, stand-by or module stop.
Rev. 2.0, 11/ 00, page 723 of 1037
28.11 Digital Filt ers
28.11.1 Overview
The digital filters required in servo control make extensive use of multiply-accumulate
operations on signed integers (error data) and coefficients. A filter computation circuit (digital
filter computation circuit) is provided in on-chip hardware to reduce the load on software, and to
improve processing efficiency. Figure 28.38 shows a block diagram of the digital filter
computation circuit configuration.
The filter computation circuit includes a high-speed 24-bit × 16-bit multiplier-accumulator, an
arithmetic buffer, and an I/O processor. The digital filter computations are carried out by the
high-speed multiplier-accumulator. The arithmetic buffer stores coefficients and gain constants
needed in the filter computations, which are referenced by the high-speed multiplier-
accumulator.
The I/O processor is activated by a frequency generator signal, and determines what operation is
carried out. When activated, it reads the speed error and phase error from the speed and phase
error detectors and sends them to the accumulator.
When the filter computation is completed, the I/O processor reads the result from the
accumulator and sends it to a 12-bit PWM. At this time, the accumulation result gain can be
controlled.
Rev. 2.0, 11/ 00, page 724 of 1037
28.11.2 Bl ock Diagram
Data bus
Accumulator
End
Start
Error latch signal
Error data
(from the error detector) Motor control data
(to PWM circuit)
Buffer/
register
select &
R/W
Address bus
Error check Accumulation
controller
LA (16 bits),
lower accumulator
UA (32 bits),
upper accumulator
MD (32 bits),
multiplied data
Data
shifter
Accumulation
sequence circuit
Buffer circuit
A, B, G, etc.
Write-only
Read-only
Accumu-
lator
Calculation
register
Coefficient
register
Constant
register
Sign
controller
Figure 28.38 Block Diagram of Digital Filter Circuit
Rev. 2.0, 11/ 00, page 725 of 1037
16
24 8
Z -1
-+
*
Usn-1 GKs
+
+
Ofs
+
-
+
+
24 8
Ws
24 8
VBs
14 4
24 8
XAs
24 8
XSn 24 8
VSn 24 8
DFUout 12
24 8
Es
Error detector
á Add 0s to 8 bits after the decimal point
á Add the same 8-bit value as MSB
Right-bit shift of the decimal point
along with Go PWM
Note: Go = 64, 32 are optional.
Go = 64, 32, 16, 8, 4, 2
24 8
Usn
16
DZs11 to 0
CZs11 to 0
DBs15 to 0
CBs15 to 0
16
DGKs15 to 0
CGKs15 to 0 DOfs15 to 0
COfs15 to 0
DFIC
CFIC
DFER15 to 0
CFER15 to 0
DAs15 to 0
CAs15 to 0
BsAs
GS KS Go
16
Es PWM
Digital filter
control
register
Speed
system
24 8
Z -1
-+
*
Upn-1 GKp
+
+
OfP
+
-
24 8
Tp
24 8
VBp
24 8
XAp
24 8
VPn
24 8
Y
Phase direct test output
* : See figure 28.42, Z
-1
initialization circuit.
12
24 8
Ep
Error detector
á Add 0s to 8 bits after the decimal point
á Add the same 8-bit value as MSB
PWM
Notes: 1.
24 8
Upn
DZp11 to 0
CZp11 to 0
DBp15 to 0
CBp15 to 0
16
16
DGKp15 to 0
CGKp15 to 0 DOfp15 to 0
COfp15 to 0
DPER19 to 0
CPER19 to 0
DAp15 to 0
CAp15 to 0
BPAP
GP KP
20
16 16
Ep PWM
PTON
Note 2
á DFUCR
á OPTION
CP/DP
Phase
system
Overflows during accumulation are ignored, and
values below the decimal point are always omitted.
2. Gain control is disabled during phase output.
Figure 28.39 Digital Filter Representation
Rev. 2.0, 11/ 00, page 726 of 1037
28.11.3 Ari thmetic Buffer
This buffer stores computational data used in the digital filters. See table 28.14. Write access is
limited to the gain and coefficient data (Z-1). Other data is used by hardware. None of the data
can be read.
Table 28.14 Arithmetic Buffer Register Configuration
Buffer Da ta Length
Arithmetic
Data Gain or
Coefficient Processing
Data
16 bits 16 bits 16 bits
Phase
system Ep
Upn
Upn-1 (Zp-1)
Vpn
Tp
Y
Ap
Bp
GKp
Ofp
Ap × Epn
Bp × Vpn
Speed
system Es
Xsn
Usn
Usn-1 (Z-1s)
Vsn
Ws
As
Bs
GKs
Ofs
As × Xsn
Bs × Vsn
Error
output PWM
Legend: Valid bit s ↑
Non-existent bits Decimal point
Rev. 2.0, 11/ 00, page 727 of 1037
28.11.4 Regi ster Configuration
Table 28.15 shows the register configuration of the digital filter computation circuit.
Table 28.15 Register Configuration
Name Abbrev. R/W Size Initi al Value Addr ess
Capstan phase gain
constant CGKp W Word Undetermined H'FD010
Capstan speed gain
constant CGKs W Word Undetermined H'FD012
Capstan phase coeff icient A CAp W Word Undeterm ined H'FD014
Capstan phase coeff icient B CBp W Word Undeterm ined H'FD016
Capstan speed coeff icient A CAs W Wor d Undeter m ined H'FD018
Capstan speed coeff icient B CBs W Wor d Undeter m ined H'FD01A
Capstan phase off set COf p W Wor d Undeter m ined H'FD01C
Capstan speed off set COf s W W or d Undeter m ined H'FD01E
Drum phase gain constant DGKp W W or d Undeter m ined H'FD000
Drum speed gain constant DGKs W Word Undeterm ined H'FD002
Drum phase coef f icient A DAp W Word Undetermined H'FD004
Drum phase coef f icient B DBp W Word Undetermined H'FD006
Drum speed coef f icient A DAs W Word Undeterm ined H'FD008
Drum speed coef f icient B DBs W Word Undeterm ined H'FD00A
Drum phase of f set DO f p W Wor d Undeter m ined H'FD00C
Drum speed of f set DO f s W W or d Undeter m ined H'FD00E
Drum system speed delay
init ializ a tion r e g is ter DZs W Word H'F000 H'FD020
Drum system phase delay
init ializ a tion r e g is ter DZp W Word H'F000 H'FD022
Capstan system speed
delay init ialization register CZs W Word H'F000 H'FD024
Capstan system phase
delay init ialization register CZp W Word H'F000 H'FD026
Drum system digital filter
control regist er DFIC R/W Byte H'80 H'FD028
Capstan system digital filter
control regist er CFIC R/W Byte H'80 H'FD029
Digit al filt er co ntr ol regis ter DFUCR R/W Byte H'C0 H'FD02 A
Rev. 2.0, 11/ 00, page 728 of 1037
28.11.5 Register Descriptions
(1) Gain Constants (DGKp, DGKs, CGKp, CGKs)
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
Note: * Initial value is uncertain.
These registers are 16-bit write-only buffers that set accumulation gain of the digital filter. They
cannot be read. They can be accessed by word access only. Accumulation gain can be set to
gain 1 value as the maximum value. Byte access gives unassured results. If read is attempted,
an undetermined value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before proce ssing start s.
In the digital filter, output gain and accumulation gain can be adjusted separately. Take output
gain into account when setting accumulation gain.
(2) Coefficients (DAp, DB p, DAs, DBs, CAp, CB p, CAs, CBs)
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
Note: * Initial value is uncertain.
These registers are 16-bit write-only buffers that determine the cutoff frequency f1 and f2. They
cannot be read. They can be accessed by word access only. Byte access gives unassured results.
If read is attempted, an undetermined value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before proce ssing start s.
In the digital filter, output gain and accumulation gain can be adjusted separately. Take output
gain into account when setting accumulation gain.
Rev. 2.0, 11/ 00, page 729 of 1037
(3) Offsets (DOfp, DOfs, COfp, COfs)
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
Note: * Initial value is uncertain.
These registers are 16-bit write-only buffers that set the offset level of digital filter output. They
cannot be read. They can be accessed by word access only. Byte access gives unassured results.
If read is attempted, an undetermined value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before proce ssing start s.
In this digital filter, output gain adjustment (×1, 2, 4, 8 ,16, 32, 64) a ft er offset a dding i s
enabled. Take output gain into account when setting accumulation gain.
(4) Delay Initializ ati on Registers (CZp, CZs, DZp, DZs)
131415 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
WWWWWWW
12
000000
1111 ————
Bit :
Initial value :
R/W :
The delay initialization register is a 16-bit write-only register. It accepts only a word-access. If
a byte access is attempted, operation is not assured. If a read is attempted, an undefined value is
read out. Bits 12 to 15 are reserved, and no write in them is valid.
It is initialized to H'F000 by a reset, stand-by or module stop. The MSB of 12-bit data (bit 11) is
a sign bit.
Loading to Z-1 is performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, C Z SON,
DZPON, DZSON). Wr iting in register is always available, but loading in Z-1 is not possible
when the digital filter is performing calculation processing in relation to such register. In such a
case, loading to Z-1 will be done the next time computation begins.
Rev. 2.0, 11/ 00, page 730 of 1037
(5) Drum System Digital Filter Control Register (DFIC)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
—
—R/WR/WR/(W)
DPHA
R/(W)*
DROV DZPON DZSON DSG2 DSG1 DSG0
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
DFIC is an 8-bit readable/writable register that controls the status of the drum system digital
filter and operating mode. It can be accessed by byte access only. Word access gives unassured
results.
Bit 7 is a reserved bit. Writes are disabled. If read is attempted, an undetermined value is read
out. DFIC is initialized to H'80 by a reset, and in standby mode and module stop mode.
Bit 7: Reserved
Reads and writes are both disabled.
Bit 6 : Drum Sy stem Rang e Ove r Fla g (DROV)
This flag is set to 1 when the result of a drum system filter computation exceeds 12 bits in width.
To clear this flag, write 0.
Bit 6
DROV Description
0 Indicates that t he f ilter com putation result did not exceed 12 bit s ( I nit ial value)
1 Indicates t hat the f ilter com putation result exceeded 12 bit s
Bit 5: Drum Phase System Filter Computation Start Bit (DPHA)
Starts or stops filter processing for the drum phase system.
Bit 5
DPHA Description
0 Phase system f ilter com put at ions are disabled
Phase computat ion result ( Y) is not added t o Es ( see f igur e 28. 39) ( I nit ial value)
1 Phase system f ilter com put at ions are enabled
Rev. 2.0, 11/ 00, page 731 of 1037
Bit 4: Drum Phase System Z-1 Initializ ation Bit (DZPO N)
Reflects the DZp value on Z-1 of the phase system when computation processing of the drum
phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to DZp.
Bit 4
DZPON Description
0 DZp value is not reflect ed on Z-1 of t he phase syst em (Init ial value)
1 DZp value is reflected on Z-1 of t he phase syst em
Bit 3 : Drum Spe ed System Z-1 Initializ ation Bit (DZSON)
Reflects the DZs value on Z-1 of the speed system when computation processing of the drum
speed system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to DZs.
Bit 3
DZSON Description
0 DZs value is not reflect ed on Z-1 of t he speed syst em ( I nit ial value)
1 DZs value is reflected on Z-1 of t he speed system
Bit s 2 to 0 : Drum Sy stem O ut put Gai n Co ntrol B i t s (DSG2, DSG1 , DSG0 )
Control the ga in out put to DRMPWM.
Bit 2 Bit 1 Bit 0
DSG2 DSG1 DSG0 Description
0× 1 (Init ia l v a lu e)0
1× 2
0× 4
0
1
1× 8
0× 160
1(× 32)*
0(× 64)*
1
1
1 Invalid (Do not set)
Note: *Setting opt ional
Rev. 2.0, 11/ 00, page 732 of 1037
(6) Capstan System Digital Filter Control Register (CFIC)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
—
—R/WR/WR/(W)
DPHA
R/(W)*
DROV DZPON DZSON DSG2 DSG1 DSG0
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
CFIC is an 8-bit readable/writable register that controls the status of the capstan system digital
filter and operating mode. It can be accessed by byte access only. Word access gives unassured
results.
Bit 7 is a reserved bit. Writes are disabled. If read is attempted, an undetermined value is read
out. CFIC is initialized to H'80 by a reset, and in standby mode and module stop mode.
Bit 7: Reserved
Reads and writes are both disabled.
Bit 6 : Ca pst an Sy st e m Rang e Ove r Flag ( CRO V)
This flag is set to 1 when the result of a capstan system filter computation exceeds 12 bits in
width. To clear this flag, write 0.
Bit 6
CROV Description
0 Indicates that t he f ilter com putation result did not exceed 12 bit s ( I nit ial value)
1 Indicates t hat the f ilter com putation result exceeded 12 bit s
Bit 5: Capstan Phase System Filter Start Bit (CPHA)
Starts or stops filter processing for the capstan phase system.
Bit 5
CPHA Description
0 Phase filter com putations are disabled
Phase computat ion result ( Y) is not added to Es (see f igure 28.39) (I nitial value)
1 Phase filter com putations are enabled
Rev. 2.0, 11/ 00, page 733 of 1037
Bit 4: Capstan Phase System Z-1 Initializati on Bit (CZPON)
Reflects the CZp value on Z-1 of the capstan phase system when computation processing of the
phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to CZp.
Bit 4
CZPON Description
0 CZp value is not reflect ed on Z-1 of t he phase syst em (Init ial value)
1 CZp value is reflected on Z-1 of t he phase syst em
Bit 3: Capstan Speed System Z-1 Initial iz ati on Bit (CZSON)
Reflects the CZs value on Z-1 of the capstan speed system when computation processing of the
speed system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to CZs.
Bit 3
CZSON Description
0 CZs value is not reflect ed on Z-1 of t he speed syst em ( I nit ial value)
1 CZs value is reflected on Z-1 of t he speed system
Bits 2 to 0: Capstan System Gain Control Bits (CSG2, CSG1, CSG0)
Control t he ga i n out put t o CAPPW M.
Bit 1 Bit 2 Bit 0
CSG2 CSG1 CSG0 Description
0× 1 (Init ia l v a lu e)0
1× 2
0× 4
0
1
1× 8
0× 160
1(× 32)*
0(× 64)*
1
1
1 Invalid (Do not set)
Note: *Setting opt ional
Rev. 2.0, 11/ 00, page 734 of 1037
(7) Digital Filter Control Register (DFUCR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
67 ——
—— R/WR/WR/W
PTON CP/DP CFEPS DFEPS CFESS DFESS
11
Bit :
Initial value :
R/W :
DFUCR is an 8-bit readable/writable register which controls the operation of the digital filter. It
accepts a byte-access only. If it was word-accessed, operation is not assured.
Bits 7 and 6 are reserved. No write in them is valid. It is initialized to H'00 by a reset, stand-by
or module stop.
Bits 7 and 6: Reserved
No read or write is valid. If a read is attempted, an undefined value is read out.
Bit 5: Phase System Computation Result PWM O utput Bit (PTON)
Outputs the computation results of only the phase system to PWM. (The computation results of
the drum phase system is output to the CAPPW M pin, and t h a t o f t h e c apst a n p hase sy stem is
output to t he DRMPWM pin.)
Bit 5
PTON Description
0 Out put s t he r esult s of or dinary com put at ion of t he f ilter t o PWM pin (Initial value)
1 Out put s t he com putation results of only t he phase syst em t o PWM pin
Bit 4: PWM Output Selection Bit (CP/
'3
'3
)
Selects whether the phase system computation results when PTON was set to 1 is output to the
drum or capstan. The PWM of the selected side outputs ordinary filter computation results
(speed system of MIX).
Bit 4
CP/
'3
'3
Description
0 Out puts the dr um phase syst em com putation result s ( CAPPWM ) (I nitial value)
1 Out put s the capstan phase syst em com put ation results (DRMPWM)
Rev. 2.0, 11/ 00, page 735 of 1037
Bit 3: Capstan Phase System Err or Data Transfer Bit (CFEP S)
Transfers the capstan phase system error data to the digital filter when the data write is enforced.
Bit 3
CFEPS Description
0 Error data is transferr ed by DVCFG2 signal latching (Init ial value)
1 Error data is transferr ed when the data is written
Bit 2: Drum Phase System Error Data Transfer Bit (DFEP S)
Transfers the drum phase system error data to the digital filter when the data write is enforced.
Bit 2
DFEPS Description
0 Error data is transferr ed by HSW (NHSW) signal latching (Initial value)
1 Error data is transferr ed when the data is written
Bit 1: Capstan Speed System Error Data Transfer Bi t (CFESS)
Transfers the capstan speed system error data to the digital filter when the data write is enforced.
Bit 1
CFESS Description
0 Error data is transferr ed by DVCFG signal latching ( I nit ial value)
1 Error data is transferr ed when the data is written
Bit 0: Drum Speed System Error Data Transfer Bit (DFESS)
Transfers the drum speed system error data to the digital filter when the data write is enforced.
Bit 0
DFESS Description
0 Err or data is t r ansferred by NCDFG s ignal lat ching (I nit ial value)
1 Error data is transferr ed when the data is written
Rev. 2.0, 11/ 00, page 736 of 1037
28.11.6 Filter Characteristics
(1) Lag-Lead Filter
A filter required for a servo loop is built in the hardware. This filter uses an IIR (Infinite
Impulse Response) type digital filter (another type of the digital filter is FIR, i.e. Finite
Impulse Response type). This digital filter circuit implements a lag-lead filter, as shown in
figure 28. 40.
R1
R2
C
+
INPUT OUTPUT
Figure 28.40 Lag-lead Filter
The transfer function G (S) is expressed by the following equation.
S
1+
2πf2
Transfer function G (S) =
S
1+
2πf1
f1=1/2πC ( R1 +R2)
f2=1/2πCR2
Rev. 2.0, 11/ 00, page 737 of 1037
(2) Frequency Characteristics
The computation circuit repeats computation of the function, which is obtained by s-z
conversion according to bi-linear approximation of the transfer function on the s-plane.
Figure 28.41 shows the frequency characteristics of the lag-lead filter.
f1
0
f2 Frequency (Hz)
20log(f1/f2)
gain(dB)phase(deg)
Figure 28.41 Frequency Characteristics of the Lag-Lead Filter
The pulse transfer function G(Z) is obtained by the bi-linear approximation of the transfer
function G (S).
In the transfer G (S),
2 1−Z-1
S= ⋅
Ts 1+Z-1
Where, assumed that Z-1 = e-jωTs,
2 1+AZ-1
G (Z) = G ⋅ ⋅
Ts 1+BZ-1
1 1 1
Ts+ Ts − Ts −
πf2 πf2 πf1
G (Z) = A = B =
1 1 1
Ts+ Ts+ Ts+
πf1 πf2 πf1
Ts: Sampling cycle (sec)
Rev. 2.0, 11/ 00, page 738 of 1037
28.11.7 O perati ons in Case of Transient Response
In case of transient response when the motor is activated, the digital filter computation circuit
must prevent computation due to a large error. The convergence of the computations becomes
slow and servo retraction becomes deteriorating if a large error is input to the filter circuit when
it is performing repeated computations. To prevent them from occurring, operate the filter (set
constants A and B) after pulling in the speed and phase within a certain range of error, initialize
Z-1 (set initial values in CZp, CZs, DZp, DZs)(see section 28.11.8, Initialization of Z-1), or use
the error data limit function (see section regarding the error detector).
28.11.8 Initializati on of Z-1
Z-1 can be initialized by its delay initialization register (CZp, CZs, DZp, DZs). Loading to Z-1 is
performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, C Z SON, DZPON,
DZSON). W r iting in register is always available, but loading in Z-1 is not possible when the
digital filter is performing calculation processing in relation to such register. In such a case,
loading to Z-1 will be done the next time computation begins. Figure 28.42 shows the
initialization circuit of Z-1.
The delay initialization register sets 12-bit data. The MSB (bit 11) is a signed bit. Z-1 has 24 bit s
for integers and 8 bits for decimals. Accordingly, the same value as the signed bits should be set
in the 13 bits on the MSB side of Z-1, and 0 in the entire decimal section.
Example: Value set for the delay initialization register Value set for Z-1
MSB
0MSB
Set here the value in the
signed bits Fixed
1 0000000000 1111111111111 00000000000 00000000
Rev. 2.0, 11/ 00, page 739 of 1037
WW
Internal bus
Z
-1
initiali-
zation bit
DZSON
DZPON
CZSON
CZSON
W
16 16
12
24 8
W
Delay initialization
register
Z
-1
USn
-+
Res
Note: MSB of 12-bit data to be written in the delay initialization register is a sign bit.
Usn-1
+
+
Xn Vn
DBs15 to 0
DBp15 to 0
CBs15 to 0
CBp15 to 0
DZs11 to 0
DZp11 to 0
CZs11 to 0
CZp11 to 0
DAs15 to 0
DAp15 to 0
CAs15 to 0
CAp15 to 0
AB
Figure 28. 42 Z-1 Initialization Circuit
Rev. 2.0, 11/ 00, page 740 of 1037
28.12 Additional V Signal Generator
28.12.1 Overview
The circuit described in this section outputs an additional vertical sync signal to take the place of
Vsync in special playback. It is activated at both edges of the HSW signal output by the head-
switch timing generator. The head-switch timing generator also outputs a Vpulse signal
containing the additional vertical sync pulse itself, and an Mlevel signal that defines the width of
the additional vertical sync signal including the equalizing pulses.
The additional V signal is output at a three-level output pin (Vpulse).
Figure 28.43 shows the additional V signal control circuit.
Csync
Additional V pulse
OSCH
Vpulse signal
Mlevel signal
Sync detector
HSW timing
generator
Additional V
pulse generator
Fi g ur e 2 8 . 4 3 Addi t i o nal V P ul se Co nt r o l Circuit
(a) HSW timing generator
This circuit generates signals that are synchronized with head switching. It should be
programmed to generate the Mlevel and Vpulse signals at edges of the HSW signal
(VideoFF). For details, see section 28.4, HSW (Head-switch) Timing Generator.
(b) Sync detector
This circuit detects pulses of the width specified by VTR or HTR from the signal input at the
Csync pin and generates an internal horizontal sync signal (OSCH). The sync detector has
an interpolation function, so OSCH has a regular period even if there are horizontal sync
dropouts in the signal received at the pin. For details, see section 28.15, Sync Signal
Detector.
Rev. 2.0, 11/ 00, page 741 of 1037
28.12.2 P in Configuration
Table 28.16 summarizes the pin configuration of the additional V signal.
Table 28.16 Pin Configuration
Name Abbrev. I/O Function
Additional V pulse pin Vpulse Out put Out put of additional V signal synchronized to
VideoFF
28.12.3 Register Configuration
Table 28.17 summarizes the register that controls the additional V signal.
Table 28.17 Register Configuration
Name Abbrev. R/W Size Init i al Value Address
Additional V control register ADDVR R/W Byte H'E0 H'FD06F
28.12.4 Register Description
Additi ona l V Cont rol Re gi st e r (ADDVR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
1
67 ———
——— R/WR/W
HMSK HiZ CUT VPON POL
11
Bit :
Initial value :
R/W :
ADDVR is an 8-bi t re a d a b le/writable register. It is initialized to H'E0 by a reset, and in standby
mode.
Bits 7 to 5: Reserved
Writes are disabled. If a read is attempted, an undefined value is read out.
Bit 4: OSCH Mask Bit (HMSK)
Masks the OSCH signal in the additional V pulse.
Rev. 2.0, 11/ 00, page 742 of 1037
Bit 4
HMSK Description
0 OSCH is added in (Init ial value)
1 OSCH is not added in
Bit 3: High Impedance Bit (Hi Z)
Set to 1 when the intermediate level is generated by an external circuit.
Bit 3
HiZ Description
0 Vpulse is a three-level output pin (Init ial value)
1 Vpulse is a three-state out put pin ( high, low, or high- impedance)
Bit s 2 to 0 : Additi o na l V O ut put Cont r o l B i t ( CUT, VP O N, POL)
These bits control the output at the additional V pin.
Bit 2 Bit 1 Bit 0
CUT VPON POL Description
0*Low lev e l (Initial v alu e )
0 Negative polarity (see f igur e 28. 46)
0
1
1 Positive polarity (see f igure 28. 45)
0 Inter m ediat e level (high impedance if HiZ bit = 1)1*
1 High le v el
Note: *Don't care.
Rev. 2.0, 11/ 00, page 743 of 1037
28. 1 2 . 5 Additi ona l V Pul se Si g na l
Figure 28.44 shows the additional V pulse signal. The Mlevel and Vpulse signals are generated
by the head-switch timing generator. The OSCH signal is combined with these to produce
equalizing pulses. The polarity can be selected by the POL bit in the additional V register
(ADDVR). Th e Vpul se pi n out put s a l ow l e ve l by a re set , a nd i n st a ndby m ode and m odul e st op
mode.
R/WR/W
· ADDVR · ADDVR
R/W
Internal bus
R/W R/W
CUTVPON HMSK POL HiZ STBY
V
CC
V
CC
V
SS
V
SS
Rs
Rs
Vpulse pin
OSCH
Vpulse
Mlevel
[Legend]
STBY : Power-down mode signal
Vpulse, Mlevel : Signal from the HSW timing generator
Rs : Voltage division resistance (20 k : Reference value)
Fi g ur e 2 8 . 4 4 Addi t i o nal V P i n
Rev. 2.0, 11/ 00, page 744 of 1037
(a) Additional V pulses when sync signal is not detected
With additional V pulses, the pulse signal (OSCH) detected by the sync detector is
superimposed on the Vpulse and Mlevel signals generated by the head-switch timing
generat or. If t here i s a lot of noi se in t he input sync signa l (Csync), or a pul se is mi ssing,
OSCH will be a complementary pulse, and therefore an H pulse of the period set in HRTR
and HPWR will be superimposed. In this case, there may be slight timing drift compared
with the normal sync signal, depending on the HRTR and FPWR setting, with resultant
discontinuity.
If no sync signal is input, the additional V pulse is generated as a complementary pulse. Set
the sync detector registers and activate the sync detector by manipulating the SYCT bit in the
sync signal control register (SYNCR). See section 28.15.7, Sync Signal Detector Activation.
Figures 28.45 and 28.46 show the additional V pulse timing charts.
HSW signal edge
OSCH
VPON=1, CUT=0, POL=1
Additional
V pulse
Vpulse
signal
Mlevel
signal
Fi g ur e 2 8 . 4 5 Addi t i o nal V P ul se W he n Posi t i v e P o l a r ity is Specified
Rev. 2.0, 11/ 00, page 745 of 1037
HSW signal edge
OSCH
VPON=1, CUT=0, POL=0
Additional
V pulse
Vpulse
signal
Mlevel
signal
Fig ure 28.46 Additi onal V P ulse Whe n Negati ve P ol ar i ty i s Specified
Rev. 2.0, 11/ 00, page 746 of 1037
28.13 CTL Circuit
28.13.1 Overview
The CTL circuit includes a Schmitt amplifier that amplifies and reshapes the CTL input, then
outputs it as the PB-CTL signal to the servo, linear time counter, and other circuits.
The PB-CTL signal is also sent to a duty discriminator in the CTL circuit that detects and
records VISS, ASM, a nd VASS m a rks. A RE C-CT L a m pl i fi e r i s i nc l ude d i n t he re c ord c i rc ui t s.
Detection and recording whether the CTL pulse pattern is long or short can also be enabled to
correspond to the wide-aspect.
The following operating modes can be selected by settings in the CTL mode register:
• Duty discrimination
VISS detect, ASM detect, VASS detect, L/S bit pattern detect
• CTL record
VISS record, ASM rec ord, VASS re c ord, L / S bit pattern detect
• Rewrite
Trapez oi d waveform ge nera t or
Rev. 2.0, 11/ 00, page 747 of 1037
28.13.2 Bl ock Diagram
Figure 28.47 shows a block di agra m of the CT L c i rcui t .
+ -
PB-CTL
FW/RV
CTL(-)CTL(+)
Schmitt
amplifier
CTL mode
CTL
detector
Duty des-
criminator
Bit pattern
register
VISS detect
VISS
control circuit
VISS write
Duty I/O flag
Write control
circuit
REC-
CTL amplifier
Internal bus
REF30X
IRRCTL
Figure 28.47 Block Diagram of CTL Circuit
Rev. 2.0, 11/ 00, page 748 of 1037
28.13.3 P in Configuration
Table 28.18 summarizes the pin configuration of the CTL circuit.
Table 28.18 Pin Configuration
Name Abbrev. I/O Function
CTL (+) I/O pin CTL (+) I / O CTL signal input/output
CTL (–) I/O pin CTL (–) I/O CTL signal input/out put
CTL Bias input pin CTL Bias I nput CTL primary amplifier bias supply
CTL Amp (O) out put pin CTLAmp ( O ) Output CTL amplifier output
CTL SMT (i) input pin CTLSMT (i) Input CTL Schm itt amplifier input
CTL FB input pin CTL FB Input CTL amplifier high-r ange char act er ist ics
control
CTL REF output pin CTL REF O utput CTL amplifier r ef er ence volt age out put
28.13.4 Register Configuration
Table 28.19 shows the register configuration of the CTL circuit.
Table 28.19 Register Configuration
Name Abbrev. R/W Si z e Ini t ial Value Address
CTL control register CTCR R/W Byte H'30 H'FD080
CTL mode register CTLM R/ W Byte H'00 H'FD081
REC-CTL duty data
register 1 RCDR1 W Word H'F000 H'FD082
REC-CTL duty data
register 2 RCDR2 W Word H'F000 H'FD084
REC-CTL duty data
register 3 RCDR3 W Word H'F000 H'FD086
REC-CTL duty data
register 4 RCDR4 W Word H'F000 H'FD088
REC-CTL duty data
register 5 RCDR5 W Word H'F000 H'FD08A
Duty I/O register DI/O R/W Byte H'F1 H'FD08C
Bit patt er n r egister BTPR R/W Byte H'FF H'FD08D
Rev. 2.0, 11/ 00, page 749 of 1037
28.13.5 Register Descriptions
(1) CT L Cont r o l Regi st e r ( CT CR)
0
0
1
0
R
2
0
W
3
0
4
1
W
5
1
6
0
7
WW W
FSLB
W
FSLC
0
W
NT/PL FSLA CCS LCTL UNCTL SLWM
Bit :
Initial value :
R/W :
The CTL control register (CTCR) controls PB-CTL rewrite and sets the slow mode. When a
CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register
(CTLGR) in the PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1. It is automatically cleared
to 0 when a CTL pulse is detected.
CTCR is an 8-bit readable/writable register. However, bit 1 is read-only, and the rest is write-
only.
CTCR is initialized to H'30 by a reset, and in standby and module stop mode.
Bit 7: NTSC/PAL Selection Bit (NT/PL)
Selects the period of the rewrite circuit.
Bit 7
NT/PL Description
0 NTSC mode (fr am e r ate: 30 Hz) (Initial value)
1 PAL mode (f r am e r ate: 25 Hz)
Bits 6 to 4: Frequency Selection Bits (FSLA, FSLB, FSLC)
These bits select the operating frequency of the CTL rewrite circuit. They should be set
accordi ng t o fosc.
Bit 6 Bit 5 Bit 4
FSLC FSLB FSLA Description
0 Reserved (do not set )0
1 Reserved (do not set )
0 fosc = 8 MHz
0
1
1 fo s c = 10 MHz (Initial va lu e)
1**Reser ved ( do not set)
Note: *Don't care.
Rev. 2.0, 11/ 00, page 750 of 1037
Bits 3: Clock Source Selection Bit (CCS)
Selects clock source of CTL.
Bit 3
CCS Description
0φs (Init ia l v a lu e)
1φs/2
Bit 2: Long CTL Bit (LCTL)
Sets the long CTL detection mode.
Bit 2
LCTL Description
0 Clock source (CCS) operates at t he set t ing value (Initial value)
1 Clock source (CCS) operates f or f ur t her 8- division after oper at ing at the sett ing
value
Bit 1 : CT L Unde t e c t e d B i t ( UNCTL )
Indicates the CTL pulse detection status at the CTL input amplifier sensitivity set at the CTL
gain cont rol regi ste r (CTL GR).
Bit 1
UNCTL Description
0 Detec ted (Init ia l v a lu e)
1 Undetected
Bit 0: Mode Selection Bit (SLWM)
Selects CTL mode.
Bit 0
SLWM Description
0 Normal mode (Init ial value)
1 Slow mode
Rev. 2.0, 11/ 00, page 751 of 1037
(2) CTL Mode Register (CTLM)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
FW/RV
R/W
REC/PB
0
R/W
ASM MD4 MD3 MD2 MD1 MD0
Bit :
Initial value :
R/W :
The CTL mode register (CTLM) is an 8-bit readable/writable register that controls the operating
state of the CTL circuit. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one
cycle (φ) later.
CTLM is initialized to H'00 by a reset, and in standby mode and module stop mode. When CTL
is being stopped, only bits 7, 6 and 5 operate.
Note: Do not set any value other than the setting value for each mode (see table 28.20, CTL
Mode Functions).
Bits 7 and 6: Record/Playback Mode Bits (ASM, REC/PB)
These bits switch between record and playback. Combined with bits 4 to 0 (MD4 to MD0), they
support th e VISS, VASS, a nd ASM m a rk fun ctions.
Bit 7 Bit 6
ASM REC/
3%
3%
Description
0 Playback mode (Initial value)0
1 Record m ode
0 Assemble mode1
1 I nvalid (do not set )
Bit 5: Direction Bit (FW/RV)
Selects the direction in playback. Clear this bit to 0 during record. Figure 28.48 shows the PB-
CTL signal i n forward and re ve rse.
Bit 5
FW/RV Description
0 FORWARD (Initial value)
1 REVERSE
Rev. 2.0, 11/ 00, page 752 of 1037
CTL input
PB-CTL
FWD
REV
Figure 28. 48 Internal P B-CTL Signal in For ward and Reverse
Bits 4 to 0: CTL Mode Selection Bits (MD4 to MD0)
These bits select the detect, record, and rewrite modes for VISS, VASS, and ASM mar k s. I f 1 is
written in bits MD3 and MD2, they will be cleared to 0 one cycle (φ) later.
The 5 bits from MD4 to MD0 are used in combination with bits 7 and 6 (ASM and RE C /
3%
).
Table 28. 20 de scribe s the mode s.
Table 28.20 CTL Mode Functions
Bit
ASM REC
/
3%
3%
FW/
RV MD4 MD3 MD2 MD1 MD0 Mode Description
000/100000VASS
detect
(duty
detect)
PB-CTL dut y di scrimin ation
(Initial value)
•Duty I/O flag is set to 1 if duty ≥
44% is detected
•Duty I/O flag is cleared to 0 if d u ty
< 44% is detected
•Interrupt request is generated
when one CTL pulse has been
detected
01000000VASS
record •If 0 is written in the duty I/O flag,
REC-CTL is generated and
recorded with the duty cycle set
by register RCDR2 or RCDR3
•If 1 is written in the duty I/O flag,
REC-CTL is generated and
recorded with the duty cycle set
by register RCDR4 or RCDR5
00010010VASS
rewrite Same as above (VASS record;
trapezoid waveform circuit
operation)
Rev. 2.0, 11/ 00, page 753 of 1037
Bit
ASM REC
/
3%
3%
FW/
RV MD4 MD3 MD2 MD1 MD0 Mode Description
000/101001VISS
detect
(index
detect)
•The duty I/O flag is set to 1 at the
point of write access to register
CTLM
•The 1 pulses recognized by the
duty discrimination circuit are
counted in the VISS control
circuit
•The duty I/O flag is cleared to 0,
indicating VISS detection, when
the value set at VCTR register is
repeatedly detected
•An interrupt request is generated
when VISS is detected
01000101VISS
record
(index
record)
•64 pulse data with 0 pulse data at
both edges are written (index
record)
•The index bit string is written
through the duty I/O flag
•An interrupt request is generated
at the end of VISS recording
00000101VISS
rewrite Same as above (VISS record;
trapezoid waveform circuit
operation)
00010000VISS
initialize VISS write is forcibly aborted
100/100000ASM
mark
detect
ASM mark detection
•The duty I/O flag is cleared to 0
when PB-CTL duty ≥ 66% is
detected
•An interrupt request is generated
when an ASM mark is detected
01010000ASM
mark
record
•An ASM mark is recorded by
writing 0 in the duty I/O flag
•An interrupt is requested for
every one CTL pulse
•REC-CTL is generated and
recorded with the duty cycle set
by reg ister RCDR3
Rev. 2.0, 11/ 00, page 754 of 1037
(3) REC-CTL Duty Data Registe r 1 (RCDR1)
131415 103254769811 10
CMT11
W
12
1111
————
———— 0
CMT10
W
0
CMT13
W
0
CMT12
W
0
CMT15
W
0
CMT14
W
0
CMT17
W
0
CMT16
W
0
CMT19
W
0
CMT18
W
0
CMT1B
W
0
CMT1A
W
0
Bit :
Initial value :
R/W :
RCDR1 is a register that sets the REC-CTL rising timing. This setting is valid only for
recording and rewriting, and is not used in detection.
RCDR1 is a 12-bit write-only register, and can be accessed by word access only. Byte access
gives unassured results. If read is attempted, an undetermined value is read out. Bits 15 to 12
are reserved and are not affected by write access.
RCDR1 is initialized to H'F000 by a reset, and in standby mode, module stop mode and CTL
stop mode.
The value to set in RCDR1 can be calculated from the transition timing T1 and the servo clock
frequency φs by the equation given below. See figure 28.60, REC-CTL Signal Generation
Timing. Any transition timing can be set. However, the timing should be selected with
attention to playback tracking compensation and the latch timing for phase control.
RCDR1 = T1 × φs/64
φs is the servo cl ock fre que ncy (= fOSC/2) in Hz, and T1 is the set timing (s).
Note: 0 ca nnot be set t o RCDR1. Set a va l ue 1 or a bove .
Rev. 2.0, 11/ 00, page 755 of 1037
(4) REC-CTL Duty Data Registe r 2 (RCDR2)
1111
131415 103254769811 10
CMT21
W
12
————
———— 0
CMT20
W
0
CMT23
W
0
CMT22
W
0
CMT25
W
0
CMT24
W
0
CMT27
W
0
CMT26
W
0
CMT29
W
0
CMT28
W
0
CMT2B
W
0
CMT2A
W
0
Bit :
Initial value :
R/W :
RCDR2 is a register that sets 1 pulse (short) falling timing of REC-CTL at recording and
rewriting, and detects long/short pulses at detecting.
RCDR2 is a 12-bit write-only register, and can be accessed by word access only. Byte access
gives unassured results. If read is attempted, an undetermined value is read out. Bits 15 to 12
are reserved and are not affected by write access.
RCDR2 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL
stop mode.
At recording, the value to set in RCDR2 can be calculated from the transition timing T2 and the
servo clock fre que ncy φs by the e qua ti on gi ven be l ow, a nd the set val ue should be 25% of t he
duty obtained by the equation. See figure 28.60, REC-CTL Signal Generation Timing.
RCDR2 = T2 × φ s/6 4
φs is the servo cl ock fre que ncy (= fOSC/2) in Hz, and T2 is the set timing (s).
At bit pattern detection, set the 1 pulse long/short threshold value at FWD. See figure 28.56,
Duty Discriminator.
RCDR2 = T2' × φ s/ 6 4
φs is the servo cl ock fre que ncy (= fOSC/2) in Hz, a nd T2' i s the 1 pulse l ong/ short thre shold va lue
at FW D ( s) .
Rev. 2.0, 11/ 00, page 756 of 1037
(5) REC-CTL Duty Data Registe r 3 (RCDR3)
1111
131415 103254769811 10
CMT31
W
12
————
———— 0
CMT30
W
0
CMT33
W
0
CMT32
W
0
CMT35
W
0
CMT34
W
0
CMT37
W
0
CMT36
W
0
CMT39
W
0
CMT38
W
0
CMT3B
W
0
CMT3A
W
0
Bit :
Initial value :
R/W :
RCDR3 is a register that sets 1 pulse (long) and assemble mark falling timing of REC-CTL at
recording and rewriting, and detects long/short pulses at detecting.
RCDR3 is a 12-bit write-only register, and can be accessed by word access only. Byte access
gives unassured results. If read is attempted, an undetermined value is read out. Bits 15 to 12
are reserved and are not affected by write access.
RCDR3 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL
stop mode.
At recording, the value to set in RCDR3 can be calculated from the transition timing T3 and the
servo clock fre que ncy φs by the e qua ti on gi ven be l ow. T he set va lue should be 30% of the dut y
when the RCDR3 is used for REC-CTL 1 pul se (long), a nd 67 t o 70% when used for assembl e
mark. The set value must not exceed the value of REF30X. See figure 28.60, REC-CTL Signal
Generation Timing.
RCDR3 = T3 × φs/64
φs is the servo cl ock fre que ncy (= fOSC/2) in Hz, and T3 is the set timing (s).
At bit pattern detection, set the 0 pulse long/short threshold value at FWD. See figure 28.56,
Duty Discriminator.
RCDR3 = T3' × φs/64
φs is the servo cl ock fre que ncy (= fOSC/2) in Hz, a nd T3' i s the 0 pulse l ong/ short thre shold va lue
at FW D ( s) .
Rev. 2.0, 11/ 00, page 757 of 1037
(6) REC-CTL Duty Data Registe r 4 (RCDR4)
1111
131415 103254769811 10
CMT41
W
12
————
———— 0
CMT40
W
0
CMT43
W
0
CMT42
W
0
CMT45
W
0
CMT44
W
0
CMT47
W
0
CMT46
W
0
CMT49
W
0
CMT48
W
0
CMT4B
W
0
CMT4A
W
0
Bit :
Initial value :
R/W :
RCDR4 sets the timing of falling edge of the 0 pulse (short) of REC-CTL in record or rewrite
mode. In detection mode, it is used to detect the long/short pulse.
RCDR4 is a 12-bit write-only register. It accepts only a word-access. If a byte access is
attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits
15 to 12 are reserved, and no write in them is valid.
It is initialized to H'F000 by a reset, stand-by, module stop or CTL stop.
In record mode, set a value with the 57.5% duty cycle obtained from the transition timing T4
corresponding to t he servo cl oc k freque nc y φs according to the following equation. See figure
28.60, REC-CTL Signal Generation Timing.
RCDR4 = T4 × φ s/6 4
φ is the servo c loc k fre quenc y (= f OSC/2) in Hz, and T4 is the set timing (s).
At bit pattern detection, set the 0 pulse long/short threshold value at REV. See figure 28.56,
Duty Discriminator.
RCDR4 = H'FFF − (T4' × φ s/80)
φs is the servo cl ock fre que ncy (= fOSC/2) in Hz, a nd T4' i s the 0 pulse l ong/ short thre shold va lue
at REV (s).
Rev. 2.0, 11/ 00, page 758 of 1037
(7) REC-CTL Duty Data Registe r 5 (RCDR5)
1111
131415 103254769811 10
CMT51
W
12
————
———— 0
CMT50
W
0
CMT53
W
0
CMT52
W
0
CMT55
W
0
CMT54
W
0
CMT57
W
0
CMT56
W
0
CMT59
W
0
CMT58
W
0
CMT5B
W
0
CMT5A
W
0
Bit :
Initial value :
R/W :
RCDR5 sets the timing of falling edge of the 0 pulse (long) of REC-CTL in record or rewrite
mode. In detection mode, it is used to detect the long/short pulse.
RCDR5 is a 12-bit write-only register. It accepts only a word-access. If a byte access is
attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits
15 to 12 are reserved, and no write in them is valid.
It is initialized to H'F000 by a reset, stand-by, module stop or CTL stop.
In record mode, set a value with the 62.5% duty cycle obtained from the transition timing T5
corresponding to t he servo cl oc k freque nc y φs according to the following equation. See figure
28.60, REC-CTL Signal Generation Timing.
RCDR5 = T5 × φ s/6 4
φ is the servo c loc k fre quenc y (= f OSC/2) in Hz, and T5 is the set timing (s).
At bit pattern detection, set the 1 pulse long/short threshold value at REV. See figure 28.56,
Duty Discriminator.
RCDR5 = H'FFF − (T5' × φ s/80)
φs is the servo cl ock fre que ncy (= fOSC/2) in Hz, a nd T5' i s the 1 pulse l ong/ short thre shold va lue
at REV (s).
Rev. 2.0, 11/ 00, page 759 of 1037
(8) Duty I/ O Regi ster (DI/O)
0
1
1
0
R/(W)*
2
0
W
3
0
4
—
—
5
1
67
R/WWW
VCTR0
1
W
VCTR1
1
W
VCTR2 BPON BPS BPF DI/O
1
Note: * Only 0 can be written.
Bit :
Initial value :
R/W :
The duty I/O register is an 8-bit register that confirms and determines the operating status of the
CTL circuit.
It is initialized to H'F1 by a reset, and in standby mode, module stop mode, and CTL stop mode.
Bit s 7 , 6 , and 5 : VISS Int e r rupt Se t ting B i t s (VCT R2 , VCT R1 , VCT R0 )
Combination of VCTR2, VCTR1 and VCTR0 sets number of 1 pulse detection in VISS
detection mode. Detecting the set number of pulse detection is considered as VISS detection,
and an interrupt request is generated.
Note: When changing the detection pulse number during VISS detection, initialize VISS first,
then resume the VISS detection setting.
Bit 7 Bit 6 Bit 5
VCTR2 VCTR1 VCTR0 Number of 1-pulse for Det ection
020
1 4 (SYNC mark)
06
0
1
1 8 (mark A, short)
0 12 (mar k A, long)0
116
0 24 (mark B)
1
1
132
Bit 4: Reserved
Writes are disabled. When read, undefined values are obtained.
Rev. 2.0, 11/ 00, page 760 of 1037
Bit 3: Bit Pattern Detection ON/OFF Bit (BPON)
Determines ON or OFF of bit p attern detection.
Note: When writi ng 1 t o t he BPON bi t , be sure t o se t a ppropriate data to RCDR2 to RCDR5
beforehand.
Bit 3
BPON Description
0 Bit patt er n detection OFF (Init ial value)
1 Bit patt er n detection ON
Bit 2: Bit Patte r n Detecti on Start Bit (BP S)
Starts 8-bit bit pattern detection. When 1 is written to this bit, it returns to 0 after one cycle.
Writing 0 to this bit does not affect operation.
Bit 2
BPS Description
0 Normal stat us (Init ial value)
1 Start s 8- bit bit pat t er n det ect ion
Bit 1: Bit Patte r n Detecti on Fl ag (BPF )
Sets the flag every time 8-bit PB-CTL is detected in PB or ASM mo d e . T o clear the flag, write
0 after reading 1.
Bit 1
BPF Description
0 Bit patt e r n (8- b it) is no t de tected (I n itial va lu e)
1 Bit pattern (8-bit) is detected
Bit 0: Duty I/O Register (DI/O)
This flag ha s diffe rent func ti ons for rec ord and pl a ybac k.
In VISS detect mode, VASS detect mode, and ASM ma r k d etect mode, this flag indicates the
detection result.
In VISS record or rewrite mode, this flag controls the write control circuit so as to write an index
code, opera t ing a c cordi ng t o a c ont rol signa l from t he VISS control ci rc uit .
In VASS record or re wr ite mode and ASM m a rk re c ord mode , t hi s fl ag is use d for write control,
one CTL pulse at a time.
This bit can always be written to, but this does not affect the write control circuit in modes other
than VISS record or rewrite, and ASM re c ord.
Rev. 2.0, 11/ 00, page 761 of 1037
VISS Detect Mode and VASS Detect Mode:
The du ty I/O flag ind icates th e r es u lt o f d u ty discrimination . The d u ty I/ O f lag is 1 wh en the d u ty
cycle of the PB-CTL signal is equal to or above 44% (a 0 pulse in the CTL signal). The duty I/O flag
is 0 when the duty cycle of the PB-CTL signal is below 43% (a 1 pulse in the CTL signal).
ASM Mark Detect Mode:
The duty I/O flag indicates the result of duty discrimination. The duty I/O flag is 0 when the
duty cycle of the PB-CTL signal is equal to or above 66% (when an ASM mark is detected).
The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is below 65% (when an ASM
mark is not detected).
VISS Record Mode and VISS Rewrite Mode:
The duty I/O flag operates according to a control signal from the VISS control circuit, and
controls the write control circuit so as to write an index code. The write timing is set in the
REC-CTL duty data registers (RCDR1 to RCDR5). For VISS recording, registers RCDR1 to
RCDR5 are set with reference to REF30X. For VISS rewrite, registers RCDR2 to RCDR5 are
set with reference to the low-to-high transition of the previously recorded CTL signal, and the
write is carried out through the trapezoid waveform generator.
Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0 pulse
(short) in RCDR4, and for a 0 pulse (l ong) i n RCDR5.
While an index code is being written, the value of the bit being written can be read by reading
the duty I/O flag. If the CTL signal currently being written is a 0 pulse, the duty I/O flag will
read 1. If the CTL signal currently being written is a 1 pulse, the duty I/O flag will read 0.
VASS Record Mode a nd VASS Re wr ite Mode:
The duty I/O flag is used for write control, one CTL pulse at a time. The write timing is set in
the REC-CTL duty data registers (RCDR1 to RCDR5). For VASS recordi ng, re gi st e rs RCDR1
to R C DR5 a r e set wi t h r e f e r e n c e to REF30X. For VASS rewrite, registers RCDR2 to RCDR5
are set with reference to the low-to-high transition of the previously recorded CTL signal, and
the write is carried out through the trapezoid waveform generator.
Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0 pulse
(short) in RCDR4, and for a 0 pulse (l ong) i n RCDR5.
If 0 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle set in RCDR2
and RCDR3, referenced to the immediately following REF30X. If 1 is written in the duty I/O
flag, a CTL pulse will be written with a duty cycle set in RCDR4 and RCDR5, referenced to the
immediately following REF30X.
ASM Record Mode :
The duty I/O flag is used for write control, one CTL pulse at a time. The write timing is set in
the REC-CTL duty data registers (RCDR1 and RCDR3). If 0 is written in the duty I/O flag, a
CTL pulse will be written with a duty cycle of 67% to 70% as set in RCDR3, referenced to the
immediately following REF30X.
Rev. 2.0, 11/ 00, page 762 of 1037
(9) Bit Patter n Register (BTPR)
0
1
1
1
R/W*
2
1
R/W*
3
1
45
1
67
R/W*
R/W*
R/W*
LSP5
1
R/W*
LSP4
1
R/W*
LSP6
1
R/W*
LSP7 LSP3 LSP2 LSP1 LSP0
Note: * Write is prohibited when bit pattern detection is selected.
Bit :
Initial value :
R/W :
The bit pattern register (BTPR) is an 8-bit shift register which detects and records the bit pattern
of the CTL pulses. If a CTL pulse is detected in PB or ASM mode , the r e g i st er i s sh i f t e d
leftward at the rising edge of PB-CTL, and reflects the determined result of long/short on bit 0
(long pulse = 1, short pul se = 0).
If t h e B PON bit i s se t to 1 i n PB mode, t h e r e g i st er st art s detection of bit pattern immediately
after the CTL pulse. To exit the bit pattern detection, set the BPON bit a t 0 .
If 1 was written in the BPS bit when the bit pattern is being detected, the BPF bit is set at 1 when
an 8-bit bit pattern was detected. If continuous detection of 8-bits is required, write 0 in the BPF
bit, and then write 1 in the BPS bit.
At the time of VISS detection, the bit pattern detection is disabled. Set the BPON bi t to 0 a t the
time of VISS detection.
In REC mode, the register records the long/short in the bit pattern set in BTPR. The pulse in
record mode is determined always by bit 7 (LSP7) of BTPR. BTPR records one pulse, shifts
leftward, and stores the data of bit 7 to bit 0.
BTPR is initialized to H'FF by a reset, stand-by, module stop, or CTL stop.
Rev. 2.0, 11/ 00, page 763 of 1037
28.13.6 Operation
(a) CTL circuit operation
As shown in figure 28.49, the CTL discrimination/record circuit is composed of a 16-bit
up/down counter a nd 12-bi t re gi sters (×5).
In playbac k (PB) mode , the 16-bi t up/ down count er c ount s on a φs/4 c loc k when t he PB-CTL
pulse is high, and on a φs/5 c l ock when l ow. In re c ord (REC) or slow mode , t his count e r
counts up on a φs/8 c loc k when t he pul se i s high, and on a φs/4 clock when low.
This counte r a lways count s up in re cord a nd slow mode s.
In playback or slow mode, it is cleared on the rise of a PB-CTL signal. In record mode, it is
cleared on the rise of an REF30X signal.
s/4
(s/8)
s/5
( s/4)
REC-CTL (L0)
RCDR5
REC-CTL (S0)
RCDR4
REC-CTL (L1and ASM)
RCDR3
REC-CTL (S1)
RCDR2
REC-CTL
Match
detection
Match
detection
Match
detection
Match
detection
Match
detection
RCDR1
12-bit register
UDF:
DOWN
UDF
Upper 12 bits
UP
UP/DOWN counter (16 bits) Duty
detection
Counter clear signal
REF30X (REC)
PB-CTL (PB, ASM)
UP/DOWN control signal
REC: UP
PB, ASM:
UP when PB-CTL is high
Down when PB-CTL is low
Underflows when PB-CTL
duty is 43% or less
Figure 28.49 CTL Discrimination/Record Circuit
(b) CTL mode register (CTLM) switchover timing
CTLM is enabled immediately after data is written to the register. Care must be taken with
changes in the operating state.
Capstan phase c ont rol i s perform ed by t he VD sync REF30X (X-value + tra c king va l ue) a nd
PB-CTL i n ASM m o de, a n d b y t h e R E F3 0X o r CR E F and C FG d i v i si o n si g nal ( DVC FG2) i n
REC mode. If t he CAPREF30 signal to be used for c apsta n pha se cont rol is al ways
generated by XDR, the value of XDR must be overwritten when switching between PB and
REC modes. Figures 28.50 and 28.51 show examples of switchover timing of CTLM and
XDR.
Rev. 2.0, 11/ 00, page 764 of 1037
VD
DVCFG2
REF30X
16bit
UP/DOWN
counter
HSW
CTL
Tx
Latch Preset
The X-value is updated by REF30P. Modification of XDR must be performed
before REF30P in the cycle in which the X-value is changed.
X-value
X-value
after
change
RCDR3RCDR1 RCDR2
REF30P
Ta
PB-CTL
Tb
1 pulseUDF
0 pulse 0 pulse
CDIVR2
Register write
Ta is the interval calculated from RDCR3.
Tb is the interval in which switchover is performed
from ASM mode to REC mode.
Tx is the cycle in which the REF30X period is
shortened due to the change of XDR.
1 pulse
X-value (XDR) is
rewritten in this
cycle
RCDR1
Capstan phase control
ASM mode, PB mode : REF30X-PB-CTL
REC mode : REF30P-DVCFG2
/4 /5 /4
REC-CTL
Figure 28. 50 Example of CTLM Switchover Timi ng
(When Phase Control is Performed by REF30P and DVCFG2 in REC Mode)
Rev. 2.0, 11/ 00, page 765 of 1037
VD
CREF
REF30X
16bit
UP/DOWN
counter
HSW
CTL
Tx
Latch Preset
The X-value is updated by REF30P. Modification of XDR must be performed
before REF30P in the cycle in which the X-value is changed.
X value
X-value after
change
RCDR3RCDR1 RCDR2
REF30P
Ta
PB-CTL
Tb
1 pulse0 pulse 0 pulse
ASM-REC
switchover
Ta is the interval calculated from RDCR3.
Tb is the interval in which switchover is
performed from ASM mode to REC mode.
Tx is the cycle in which the REF30X period
is shortened due to the change of XDR.
With CREF and DVCFG2
phase alignment, the
frequency need not be 25 Hz
or 30 Hz.
1 pulse
X-value (XDR) is
rewritten in this
cycle
DVCFG2
RCDR1
Capstan phase control
ASM mode, PB mode: REF30X-PB-CTL
Capstan phase control
REC mode : REF30P-DVCFG2
/4 /5 /4
REC-CTL
CDIVR2
Register write
UDF
Figure 28. 51 Example of CTLM Switchover Timi ng
(When Phase Control is Performed by CREF and DVCFG2 in REC Mode)
Rev. 2.0, 11/ 00, page 766 of 1037
28. 1 3 . 7 CTL Input Se c t i o n
The CTL input section consists of an input amplifier whose gain can be controlled by register
setting and a Schmitt amplifier. Figure 28.52 shows a block diagram of the CTL input section.
A trivial CTL pulse signal is received from the CTL head, amplified by the input amplifier,
reshaped into a square wave by the Schmitt amplifier, and sent to the servo circuits and timer L
as the PB-CTL signa l . Control t he CT L input a mpl i fie r ga in by bi t s 3 to 0 in t he CTL ga in
control re gi ster (CT L GR) of the servo port .
–
+
+
–
CTLFB
CTLSMT(i)CTLFBCTLREF CTLBias
CTLGR0CTLGR3 to 1
AMPSHORT
(REC-CTL)
PB-CTL(+)
Note : Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i).
Note
PB-CTL(-)
AMPON
(PB-CTL)
– +
CTLAmp(o)CTL(+)CTL(-)
Fi g ur e 2 8 . 5 2 Bloc k Diagram o f CTL Input Se c t i o n
Rev. 2.0, 11/ 00, page 767 of 1037
(1) CTL Detector
If the CTL detector fails to detect a CTL pulse, it sets bit 1 of the CTL control register
(CTCR) to high indicating that the pulse has not been detected. If a CTL pulse is detected
after that, the bit is automatically cleared to 0. Duration used for determining detection or
non-detection of the pulse depends on magnitude of phase shift of the last detected pulse
from the reference phase (phase difference between REF30 and CTL signal). Typically,
detection or non-detection is determined within 3 to 4 cycles of the reference period.
If settings of the CTL gain control register are maintained in a table format, you can refer to
it when the CTL detector failed to detect CTL pulses. From the table, you can control input
sensitivity of the CTL according to the state of the UNCTL bit, thereby selecting an optimum
CTL amplifier gain depending on the state of the pulse recorded.
Figure 28.53 illustrates the concept of gain control for detecting the CTL input pulse.
*
V+TH (fixed)
*
V-TH (fixed)
Note: *CTL input sensitivity is variable depending on CTL
gain control register (CTLGR) setting.
Fi g ur e 2 8 . 5 3 CTL Input P ul se G ain Control
Rev. 2.0, 11/ 00, page 768 of 1037
(2) PB-CTL Waveform Shaper in Slow Mode Operation
If bit 0 in the CTL control register (CTCR) is set to slow mode, slow reset function is
activated. In slow mode, if the falling edge is not detected within the specified time from
rising edge detection, PB-CTL is forcibly shut down (slow reset).
The time TFS (s) until the signal falls is the following interval after the rising edge of the
internal CTL signal is detected:
TFS = 16384 × 4φ s(φs = f OSC/2)
When fOSC = 10 MHz, TFS = 13. 1 m s.
Figure 28.54 shows the PB-CTL wave form i n slow mode .
CTL waveform
Internal CTL signal
1 frame 1 frame 1 frame
Slow tracking delaySlow tracking delaySlow tracking delay
Accelera-
tion Accelera-
tion Accelera-
tion
Decelera-
tion Decelera-
tion
Slow reset
Stop Stop
CTLP CTLP CTLP
Figure 28. 54 P B-CTL Wavefor m in Slow Mode Oper ati on
Rev. 2.0, 11/ 00, page 769 of 1037
28.13.8 Duty Discriminator
The duty discriminator circuit measures the period of the control signal recorded on the tape
(PB-CTL signal) and discriminates its duty cycle. In VISS or VASS detection, the duty I/O flag
is set or cleared according to the result of duty discrimination. The duty I/O flag is set to 1 when
the duty cycle of the PB-CTL signal is equal to or above 44%, and is cleared to 0 when the duty
cycle is below 43%.
In ASM detection, an ASM mark i s rec ognized (and the duty I/O flag is cleared to 0) when the
duty cycle is equal to or above 66%. When the duty cycle is below 65%, no ASM ma rk i s
recognized and the duty I/O flag is set to 1.
The detection direction can be switched between forward and reverse by bit 5 (FW/RV) in the
CTL mode re giste r.
A long or short pulse can be detected by comparing the REC-CTL duty data register (RCDR2 to
RCDR5) and UP/DOWN counter. Long or short pulse is discriminated at PB-CTL signal
falling. Discrimination result is stored in bit 0 (LSP0) of the bit pattern register (BTPR). At the
same time, BTPR is shifted to the left. LSP0 indicates 0 when a short pulse is detected, and 1
when a long pulse is detected.
Set the threshold value of a long/short pulse in RCDR2 to RCDR5. See (4), Detection of the
Long/Short Pulse.
Figure 28.55 shows the duty cycle of the PB-CTL signal.
Rev. 2.0, 11/ 00, page 770 of 1037
Input signal
Short 1 pulse
25±0.5%
PB-CTL
Input signal
Long 1 pulse
30±0.5%
PB-CTL
Input signal
Short 0 pulse
57.5±0.5%
62.5±0.5%
PB-CTL
Input signal
Long 0 pulse
PB-CTL
Input signal
ASM Mark
67 to 70%
PB-CTL
Figure 28. 55 P B-CTL Signal Duty Cycle
Rev. 2.0, 11/ 00, page 771 of 1037
Figure 28.56 shows the duty discrimination circuit. A 44% duty cycle is discriminated by
counting wit h t he 16-bi t up/down count e r, using a φs/ 4 cl oc k for the up-c ount a nd a φs/5 clock
for the down-count. An up-count i s performe d when t he PB-CTL signa l i s high, a nd a down-
count when low. Long or short pulse is discriminated by comparing with RCDR2 to RCDR5.
Counter
PB-CTL
1 pulse
PB-CTL
PB-CTL
s/4 s/5
Counter
PB-CTL
0 pulse
s/4
s/5
Counter
FWD
PB-CTL
Short pulse
(0 pulse)
s/4
s/5
RCDR3
RCDR2
0 pulse L/S threshold value
1 pulse L/S threshold value
Counter
REV
PB-CTL
Long pulse
(1 pulse)
s/5
s/4
RCDR4
RCDR5
0 pulse L/S threshold value
1 pulse L/S threshold value
UP/DOWN
Comparison of upper
12-bit
UP/DOWN counter (16 bits)
* RCDR2or4 (12bit)
* FWD : Discriminated by RCDR2 and RCDR3
REV : Discriminated by RCDR4 and RCDR5
* RCDR3or5 (12bit)
0/1
discrimination
UDF
Clear
R
SQ
s/4
s/5
L/S
discrimination
Figure 28.56 Duty Discriminator
Rev. 2.0, 11/ 00, page 772 of 1037
(1) VISS (Index) Detect/Record Mode
VISS detection is carried out by the VISS control circuit, which counts 1 pulses in the PB-
CTL signal. If the pulse count detects any value set in the VISS interrupt setting bits (bits 5,
6 and 7 in the duty I/O register), an interrupt request is generated and the duty I/O flag is
cleared to 0.
At VISS record or rewrite, INDEX code is automatically written. INDEX code is composed
of continuous 62-bit data with 0 pulse data at both edges.
Examples of bit strings and the duty I/O flag at VISS detection/record are illustrated in figure
28.57.
0Tape direction
Duty I/O flag
(a) VISS detection (INDEX: Thirty-two 1 pulse setting)
1111
61±3 bits
Thirty-two 1 pulses
detected
IRRCTL
63±3 bits
Start
11110
0Tape direction
Duty I/O flag
(b) VISS record
1111
62 bits
IRRCTL
64 bits
Start
11110
1 2 3 62 63 64
Fig ure 28.57 Example s of VISS Bit Str i ngs and Duty I/ O F la g
Rev. 2.0, 11/ 00, page 773 of 1037
(2) VASS Detect Mode
VASS detection is carried out by the duty discriminator. Software can detect index
sequences by reading the duty I/O flag at each CTL pulse.
At each CTL pulse, the duty discriminator sends the result of duty discrimination to the duty
I/O flag, and simultaneously generates an interrupt request. The duty I/O flag is cleared to 0
if the CTL pulse is a 1 (duty cycle below 43%), and is set to 1 if the CTL pulse is a 0 (duty
cycle equal to or above 44%).
The duty I/O flag is modified at each CTL pulse. It should be read by the interrupt-handling
routi ne withi n t h e p e r i o d o f t h e PB -C T L sig n a l . T h e VASS detection format is illustrated in
figure 28. 58.
1
Tape direction Written three times
1111111111
M
S
BL
S
BL
S
B
M
S
BM
S
BL
S
BL
S
B
M
S
B
ThousandsHeader (11 bits) Hundreds
Data (16 bits: 4 digits of 4-bit BCD)
Tens Ones
Fi g ur e 2 8 . 5 8 VASS (Index) F o r m at
(3) Assemb l e (ASM) Mark Detect Mode
ASM ma r k d etection is carried out by the duty discriminator. If the duty discriminator
detects that the duty cycle of the PB-CTL signal is 66% or higher, it generates an interrupt
request, and simultaneously clears the duty I/O flag to 0.
The duty I/O flag is updated at every CTL pulse. It should be read by the interrupt-handling
routine within the period of the PB-CTL signal.
Rev. 2.0, 11/ 00, page 774 of 1037
(4) Detection of the Long/Short Pulse
The Long/Short pulse is detected in PB mode by the L/S determination based on the
compari son of the REC-CT L duty re gi sters (RCDR2 to RCDR5) with the up/ down counte r
and the results of the duty I/O flag. The results of the determination are stored in bit 0
(LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting BTPR
leftward at the same time.
RCDR2 to RCDR5 set the L/S thresholds for each of FWD/REV. Set to RCDR2 a threshold
of 1 pulse L/S for FWD, t o RCDR3 a thre shold of 0 pul se L/ S for FWD, to RCDR4 a
threshold of 0 pulse L / S for REV, a nd to RCDR5 a t hre shold of 1 pulse L / S for REV. Figure
28.59 shows the detection of the Long/Short pulse.
Also, the bit pattern of eight bits can be detected by BTPR. Check that an 8-bit detection has
been done by bi t 1 (BPF bit) of the dut y I/O regi ste r, and t he n rea d BT PR.
Bit pattern register (8-bit)
UP/DOWN counter (16-bit)
RCDR2 (12bit)
High-order 12-bit data
L/S is determined at the rising edge of PB-CTL.
After the determination, the bit pattern register is
shifted leftward, and the results of the determination
are stored in the LSB.
RCDR3 (12bit)
Internal bus
LSB
FW/RV DI/O
Shift leftwardBTPR
R
R
SQ
RCDR4 (12bit)
RCDR5 (12bit) R
SQ
s/4
Figure 28.59 Detection of Long/Short Pulse
Rev. 2.0, 11/ 00, page 775 of 1037
28.13.9 CTL Output Section
An on-chip control head amplifier is provided for writing the REC-CTL signal generated by the
write control circuit onto the tape.
The write control circuit controls the duty cycle of the REC-CTL signal in the writing of VISS
and VASS se q u e n c e s and ASM m a r k s a n d the r e wr i tin g of VI SS a n d VASS sequenc e s. T h e
duty cycle of the REC-CTL signal is set in REC-CTL duty data registers 1 to 5 (RCDR1 to
RCDR5). Times calculated in terms of φs (= fOSC/2) should be converted to appropriate data to
be set i n t h ese re gi st e rs. In VISS or VASS m ode , se t RCDR2 for a dut y c ycle of 25%±0.5%,
RCDR3 for a duty cycle of 30%±0.5%, RCDR4 for a duty cycle of 57.5±0.5%, a nd RCDR5 for
a duty cycle of 62.5±0.5%. When 1 is written in the duty I/O flag, the REC-CTL signal will be
written on the tape with a 25%±0.5% duty cycle when 0 is written in bit 7 (LSP7) in the bit
pattern register (BTPR) and with a 30±0.5% duty cycle when 1 is written. Table 28.21 shows
the relationship between the REC-CTL duty register and CTL outputs.
In ASM m a r k wr ite mode, set RCDR3 for a duty cycle of 67% to 70%. An ASM ma r k will be
written when 0 is written in the duty I/O flag.
An interrupt request is generated at the rise of the reference signal after one CTL pulse has been
written. The reference signal is derived from the output signal (REF30X) of the X-value
adjustment circuit, and has a period of one frame.
Figure 28.60 shows the timings that generate the REC-CTL signal.
Table 28.21 REC-CTL Duty Register and CTL Outputs
MODE D/IO LSP7 Pulse RCDR Duty
0 S1 RCDR2 25±0.5%
0
1 L1 RCDR3 30±0.5%
0 S0 RCDR4 57.5±0.5%
VISS and VASS
modes
1
1 L0 RCDR5 65.5±0.5%
ASM m o de 0 *RCDR3 6 7 to 70 %
Note: *Don't care.
Rev. 2.0, 11/ 00, page 776 of 1037
W
Internal bus
RCDR2or4
(12bit)
W
RCDR1
(12bit)
UP/DOWN counter (12 bits)
Counter
REF30X
REC-CTL
Counter
reset
Match detection
Match detection
End of writing of one CTL
pulse (except VISS) IRRCTL
RCDR2 (VISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse, or ASM)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
RCDR1
Clear
Upper 12 bits
REC-CTL 0 pulse fall
timing
REC-CTL rise timing REC-CTL 1 pulse,
ASM fall timing
RESET
REF30X W
RCDR3or5
(12bit)
s/4
Compare Compare Compare
Figure 28. 60 REC-CTL Signal Generati on Timi ng
Rev. 2.0, 11/ 00, page 777 of 1037
The 16-bit c ounte r i n the RE C-CTL c irc ui t c ont inue s count ing on a c loc k de rive d by di vidi ng
the system clock φs (= fOSC/2) by 4. The counter is cleared on the rise of REF30X in record
mode, and on the rise of PB-CTL in rewrite mode. The REC-CTL match detection is carried out
by comparing the counter value with each RCDR value.
RCDR1 to RCDR5 can be written to by software at all times. If RCDR is changed before the
respective match detection is performed, match detection is performed using the new value. The
value changed after match detection becomes valid on the rise of REF30X following the change.
Figure 28.61 shows an example of RCDR change timing.
REF30X
REC-CTL RCDR1 RCDR2 RCDR1
1 pulse (Short) 0 pulse (Short) Rewritten 0 pulse
(Short)
RCDR1 RCDR1
Counter RCDR4
RCDR2
RCDR1
RCDR4 RCDR4
RCDR4
Interval in which
RCDR4 can be
written to
Fig ure 28.61 Example of RCDR Change Ti mi ng (Exampl e Showi ng RCDR4)
Rev. 2.0, 11/ 00, page 778 of 1037
28.13.10 Trapezoid Waveform Circuit
In rewriting, the trapezoid waveform circuit leaves the rising edge of the already-recorded PB-
CTL signal intact, but changes the duty cycle.
In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle
for a rewrite is set in the REC-CTL duty data registers (RCDR2 to RCDR5). Time values T2 to
T5 are referenced to the rise of PB-CTL.
Figure 28.62 shows the rewrite waveform.
W
Internal bus
RCDR3or5
(12bit)
W
Not used when
rewriting
RCDR2or4
(12bit)
UP/DOWN counter (16 bits)
Clear
Upper 12 bits
REC-CTL 0 pulse
fall timing
REC-CTL 1 pulse
fall timing
RESET
PB-CTL W
T
2
to T
5
Eliminated
pulse
High-impedance
interval
End of writing of one
CTL pulse (except
VISS) IRRCTL
RCDR1
(12bit)
s/4
Compare Compare
RCDR2 (VISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
PB-CTL
REC-CTL when
rewriting
New pulse
Fi g ur e 2 8 . 6 2 Re l a t i o nshi p be t we en REC- CTL a nd RCDR2 t o RCDR5 when Rewrit i ng
Rev. 2.0, 11/ 00, page 779 of 1037
28.13.11 Note on CTL Inte rr upt
Followi n g a r e se t, t h e C T L cir c u i t is in t h e VASS d etect (duty detect) mode.
Depending on the CTL pin states, a false PB-CTL input pulse may be recognized and an
interrupt request generated. If the interrupt request will be enabled, first clear the CTL interrupt
request fla g.
Rev. 2.0, 11/ 00, page 780 of 1037
28.14 Frequency Dividers
28.14.1 Overview
On-chip frequenc y di vide rs are provide d for t he pul se signa l pi c ked up from t he c ont rol t ra ck
during playback (PB-CTL signal), and the pulse signal received from the capstan motor (CFG
signal). An on-chip noise canceller is provided for the drum motor pulse signal (DFG sign a l ) .
The CTL frequency divider generates a CTL divided control signal (DVCTL) from the PB-CTL
signal, for use in c a pstan pha se c ontrol duri ng high-spee d sea rch, for e xa mpl e . The CFG
frequency divider generates two divided signals (DVCFG for speed control and DVCFG2 for
phase c ont rol ) from t he CFG si gna l . T he DFG noi se c a n celler is a circuit which considers a
signal less than 2φ as noise and masks it.
28.14.2 CTL Frequency Divider
(1) Block Diagra m
Figure 28.63 shows a block di agra m of the CT L fre que ncy di vi der.
EXCTL
PB-CTL , DVCTL
UDF
R/W W
(8bit)
R/W Internal bus
CEX
CTL division register
Down counter (8 bits)
CEG
Edge
detector
· CTVC · CTLR
· CTVC
Figure 28. 63 CTL Fr e quency Divider
(2) Register Configuration
• Register configuration
Table 28.22 shows the register configuration of the CTL dividers.
Table 28.22 Register Configuration
Name Abbrev. R/W Size Init i al Value Address
DVCTL control register CTVC R/W Byte Undefined H'FD098
CTL division r egister CTLR W Byt e H'00 H'FD099
Rev. 2.0, 11/ 00, page 781 of 1037
• DVCTL control register (CTVC)
0
*
1
*
R
2
*
R
345 ———
———
67
R
CFG HSW
0
W
0
W
CEX CEG CTL
111
Bit :
Initial value :
R/W :
Note: * Initial value is uncertain.
The DVCTL cont rol regi ste r (CTVC) is a re gi ster c onsisti ng of the e xte rna l i nput signal
selection bit and the flags which show the CFG, HSW and CTL levels.
Note: It has an undetermined value by a reset or stand-by.
Bit 7: DVCTL Signal Generation Selection Bit (CEX)
Selects whether the PB-CTL signal or the external input signal is used to generate the DVCTL
signal.
Bit 7
CEX Description
0 Gener at es DVCTL signal with PB-CTL signal (Initial value)
1 Gener at es DVCTL signal with ext er nal input signal
Bit 6: External Sync Signal Edge Selection Bit (CEG)
Selects the edge of the external signal at which the frequency division is made when the external
signal was selected to generate the DVCTL signal.
Bit 6
CEG Description
0 Rising edge (I nit ial value)
1 Falling edge
Bits 5 to 3: Reserved
No write in them is valid. If a read is attempted, an undetermined value is read out.
Bit 2: CFG Fl ag (CFG )
Shows the CFG level.
Bit 2
CFG Description
0 CFG is a t Low lev e l (Init ia l v alu e )
1 CFG is a t High lev e l
Rev. 2.0, 11/ 00, page 782 of 1037
Bit 1: HSW Flag (H SW)
Shows the level of the HSW signal selected by the VFF/ NFF b i t o f t h e HSW mod e r e g i st er 2
(HSM2).
Bit 1
HSW Description
0 HSW is at Lo w lev e l (Init ia l v a lu e)
1 HSW is at High lev e l
Bit 0: CTL Flag (CTL)
Shows the CTL level.
Bit 0
CTL Description
0 REC or PB-CTL is at Low le v e l (Init ia l v alu e )
1 REC or PB-CTL is at High level
• CTL frequency division register (CTLR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7CTL4 CTL3 CTL2 CTL1 CTL0
0
W
CTL7
WWW
CTL6 CTL5
Bit :
Initial value :
R/W :
The CTL fre quenc y di vision re gi ster (CT L R) is an 8-bi t write -onl y regi ste r to set t he fre que ncy
dividing value (N-1 if divided by N) for PB-CTL. If a read is attempted, an undetermined value
is read out.
PB-CTL is divide d by N at it s rising e dge. If t he regi ste r val ue was 0, no di vision ope ra ti on i s
performed, and the DVCTL signal with the same cycle with PB-CTL is output. It is initialized
to H'00 by a re set or sta nd-by.
Rev. 2.0, 11/ 00, page 783 of 1037
(3) Operation
During playbac k, c ontrol pul ses recorde d on t he t a pe a re pic ke d up by the c ontrol he ad a nd
input to the CTL pin. The control pulse signal is amplified by a Schmitt amplifier, reshaped,
then input t o the CT L fre que ncy di vi der a s the PB-CTL signa l .
This circ ui t i s em ploye d when t he c ont rol pul se (PB-CTL signal ) i s used for phase cont rol of
the capstan motor. The divided signal is sent as the DVCTL signal to the capstan phase
system in the servo circuits, and the Timer R.
The CTL frequency divider is an 8-bit reload timer consisting of a reload register and a
down-counter. Frequency division is obtained by setting frequency-division data in bits 7 to
0 in the CTL frequency division register (CTLR), which is the reload register. When a
frequency-division value is written in this reload register, it is also written into the down-
counter. The down-counter is decremented on rising edges of the PB-CTL signal.
Figure 28.64 shows exampl es of the PB-CTL signal a nd DVCTL waveform s.
CTL input signal
CTLR : CTL frequency division register
PB-CTL or external
sync signal
CTLR=00
CTLR=01
CTLR=02
Figure 28. 64 CTL Fr e quency Division Waveforms
Rev. 2.0, 11/ 00, page 784 of 1037
28.14.3 CFG Fr e quency Divider
(1) Block Diagra m
Figure 28.65 shows a block diagram of the 7-bit CFG frequency divider and its mask timer.
WR/WW
R/W
WWWR
R/W
Internal bus
CMN
CRF
UDF
UDF
UDF
CFG DVCFG
DVCFG2
,
MCGin
Internal bus
CFG
clock
select
CTMR(6bit)
CDIVR2(7bit)
DVTRG
PB(ASM) REC
s = fosc/2
s/1024
s/512
s/256
s/128
Down counter (7 bits)
Down counter (7 bits)
Down counter (6 bits)
CDIVR(7bit)
CMK
S
R
Edge
select
· CDVC
· CDVC · CDVC
· CDVC
· CDVC
Figure 28.65 CFG Frequency Divider
Rev. 2.0, 11/ 00, page 785 of 1037
(2) Register Descri pt ions
• Register configuration
Table 28.23 shows the register configuration of the CFG frequency divider.
Table 28.23 Register Configuration
Name Abbrev. R/W Size Init ial Value Address
DVCFG control register CDVC R/W Byte H'60 F'FD09A
CFG frequency division
register 1 CDIVR1 W Byte H'80 H'FD09B
CFG frequency division
register 2 CDIVR2 W Byte H'80 H'FD09C
DVCFG mask p eriod
register CTMR W Byte H'FF H'FD09D
•DVCFG c o nt r o l r egi st e r (CDVC)
0
0
1
0
W
2
0
W
34
0
W
5
1
6
—
—
1
7
WR
CMK CMN
W
DVTRG
0
R/W*
MCGin CRF CPS1 CPS0
0
Note: * Only 0 can be written.
Bit :
Initial value :
R/W :
CDVC is an 8-bit registe r t o cont rol the c apsta n fre quenc y di vision c i rcui t .
It is initialized to H'60 by a reset, stand-by or module stop.
Bit 7: Mask CFG Flag (M CGi n)
MCGin is a flag to indicate occurrence of a frequency division signal during the mask timer's
mask period. To clear it, write 0. To clear it by software, write 0 after reading 1. Also, setting
has the highest priority in this flag. If a condition setting the flag and 0 write occurs
simultaneously, the latter is nullified.
Bit 7
MCGin Description
0 CFG is in normal oper at ion (Init ial value)
1 Shows that DVCFG was detected dur ing masking (r unaway detected)
Bit 6: Reserved
No write in it is valid. If a read is attempted, 1 is read out.
Rev. 2.0, 11/ 00, page 786 of 1037
Bit 5: CFG Mask Status Bit (CMK)
Indicates the status of the mask. It is initialized to 1 by a reset, stand-by or module stop.
Bit 5
CMK Description
0 Indicates t hat the capstan m ask t imer has r eleased masking
1 Indicates t hat the capstan m ask t imer is curr ent ly m asking (I nit ial value)
Bit 4: CFG Mask Selection Bit (CMN)
Selects the turning ON/OFF of the m a sk function.
Bit 4
CMN Description
0 Capstan mask t imer f unct ion O N ( I nitial value)
1 Capstan mask t imer f unct ion O FF
Bit 3: PB (ASM) → REC Transition Timing Sync ON/OFF Selection Bit (DVTRG)
Selects the ON/OFF o f t h e timing sync of the transition from PB (ASM) to REC when t h e
DVCFG2 signal is generated.
Bit 3
DVTRG Description
0 PB ( ASM ) → REC transition timing sync ON (Init ial value)
1 PB ( ASM ) → REC transition timing sync OFF
Bit 2: CFG Frequency Division Edge Selection Bit (CRF)
Selects the edge of the CFG signal to be divided.
Bit 2
CRF Description
0 Perfor m s f r equency division at the r ising edge of CFG ( I nit ial value)
1 Perfor m s f r equency division at both edges of CFG
Rev. 2.0, 11/ 00, page 787 of 1037
Bits 1 and 0: CFG Mask Timer Clock Selection Bits (CPS1, CPS0)
Selects the clock source for the CFG mask timer. (φs = fosc/2)
Bit 1 Bit 0
CPS1 CPS0 Description
0φs/1024 (Init ial value)0
1φs/512
0φs/2561
1φs/128
Rev. 2.0, 11/ 00, page 788 of 1037
• CFG f r eque nc y di v i si o n r egi st e r 1 ( CDIVR1)
0
0
1
0
W
2
0
W
34
0
W
5
0
67
—
—WW
CDV15 CDV14
0
W
CDV16
0
W
CDV13 CDV12 CDV11 CDV10
1
Bit :
Initial value :
R/W :
The CFG frequency division register 1 (CDIVR1) is an 8-bit write-only register to set the
CFG division value (N-1 for N division). If a read is attempted, an undetermined value is
read out. Bi t 7 is reserve d.
The frequency division value is written in the reload register and the down counter at the
same time.
CFG's frequency is divi ded by N at i ts rising e dge or both e dge s. If t he re gi ster va l ue was
0, no division operation is performed, and the DVCFG signal with the same input cycle
with the CFG signal i s output . The DVCFG signal is sent to t he c a pstan spee d e rror
detector. It is initialized to H'80 by a reset or stand-by together with the capstan
frequency di vi sion regi ste r and t he down counte r.
• CFG f r eque nc y di v i si o n r egi st e r 2 ( CDIVR2)
0
0
1
0
W
2
0
W
34
0
W
5
0
67
—
—WW
CDV25 CDV24
0
W
CDV26
0
W
CDV23 CDV22 CDV21 CDV20
1
Bit :
Initial value :
R/W :
The CFG frequency division register 2 (CDIVR2) is an 8-bit write-only register to set the
CFG division value (N-1 for N division). If a read is attempted, an undetermined value is
read out. Bi t 7 is reserve d.
The frequency division value is written in the reload register and the down counter at the
same time.
CFG's frequency is divi ded by N at i ts rising e dge or both e dge s. If t he re gi ster va l ue was
0, no division operation is performed, and the DVCFG signal with the same input cycle
with the CFG signal i s output . The DVCFG2 signal is sent to t he c a pstan spee d e rror
detector and the Timer L.
The DVCFG2 circuit has no mask timer function.
The frequency division counter for the DVCFG2 signal starts its division operation at the
point data was written in CDIVR2. If synchronization is required for phase matching, for
exampl e , do it by writ ing i n CDIVR2. If the DVTRG bit of t he CDVC registe r was 0, t he
register synchronizes with the switching timing from PB (ASM) t o REC.
It is initialized to H'80 by a reset or stand-by together with the capstan frequency division
register a nd t he down count e r.
Rev. 2.0, 11/ 00, page 789 of 1037
• DVCFG mask period register (CTMR)
0
1
1
1
W
2
1
W
34
1
W
5
1
67 ——
—— WW
CPM5 CPM4
1
W
CPM3 CPM2 CPM1 CPM0
11
Bit :
Initial value :
R/W :
The DVCFG mask period registe r (CT MR) is an 8-bit writ e-onl y re giste r. If a rea d i s
attempted, an undetermined value is read out. CTMR is a reload register for the mask
timer (down counter). Set in it the mask period of CFG. The mask period is determined
by the clock specified by bits 1 and 0 of CDVC and the set value (N-1). If data is written
in CTMR, it is written also in the mask timer at the same time.
It is initialized to H'FF by a reset, stand-by or module stop.
Mask period = N × clock cycle
(3) Operation
• Frequency divide r
The CFG pulses output from t he ca psta n mot or a re sent t o int e rnal c irc ui try a s the CFG
signal via the zero-cross type comparator. The CFG signal, shaped into a rectangular
waveform by a re shapi ng ci rc uit , i s divide d by t he CFG frequenc y di vide rs, a nd used i n
servo control. The rising edge or both edges of the CFG signal can be selected for the
frequency di vi der.
The CFG frequency dividers comprises a 7-bit frequency divider with a mask timer for
capstan spee d c ontrol (DVCFG signal genera tor) a nd a 7-bit fre quenc y di vide r for c apsta n
phase control (DVCFG2 signal genera tor).
The DVCFG signal generat or c onsists of a 7-bit re loa d re giste r (CFG frequenc y divi sion
register1: CDIVR1), a 7-bit down-counter, and a 6-bit mask timer (with settable mask
interval). Frequency division is performed by setting the frequency-division value in 7-
bit CDIVR1. When the frequency-division value is written in CDIVR1, it is also written
in the down-count e r. After fre que ncy di vi sion of a CFG signal for whic h t he e dge has
been selected, the signal is sent via the mask timer to the capstan speed error detector as
the DVCFG si g n a l .
The DVCFG2 signal generat or c onsists of a 7-bit re loa d re giste r (CFG frequenc y divi sion
register 2: CDIVR2) and a 7-bi t down-count e r. The 7-bi t fre que ncy di vi der doe s not ha ve
a mask timer. Frequency division is performed by setting the frequency-division value in
CDIVR2. When the frequency-division value is written in CDIVR2, it is also written in
the down-counte r. Afte r freque nc y divi sion of a CFG signal for which t he edge ha s been
selected, the signal is sent to the capstan speed error detector and the Timer L as the
DVCFG2 signal. Frequency division starts when the frequency-division value is written.
Rev. 2.0, 11/ 00, page 790 of 1037
When the DVTRG bit in the CDVC register is set to 0, reloading is executed with the
switchover timing from PB (ASM) m o d e t o R E C m o de. T o switch from REF30 to
CREF, change the settings of bit 4 (CR/RF bit) in the capstan phase error detection
control register (CPGCR). If synchronization is necessary for phase control, this can be
provided by writing the frequency-divisi on value in CDIVR2.
The down-counters are decremented on rising edges of the CFG signal when the CRF bit
is 0 in the DVCFG control regi ste r (CDVC), and on bot h edge s when the CRF bit i s 1.
Figure 28.66 shows exampl es of CFG frequency di vi sion waveform s.
CFG
CRF bit=1
CDIVR=00
CRF bit=0
CDIVR=00
CRF bit=0
CDIVR=01
CRF bit=0
CDIVR=02
Figure 28. 66 F r equency Division Wavefor ms
Rev. 2.0, 11/ 00, page 791 of 1037
• Mask timer
The capstan mask timer is a 6-bit reload timer that uses a prescaled clock as a clock
source.
The mask timer is used for masking the DVCFG signal intended for controlling the
capstan speeds.
The capstan mask timer prevents edge detection to be carried out for an unnecessarily
long duration by masking the edge detection for a certain period. The above trouble can
result from abnormal revolution (runout) of the capstan motor because its revolution has
to cover a wide range speeds from the slow/still up to the high speed search.
The capstan mask timer is started by output of a pulse edge in the divided CFG signal
(DVCFG). While the timer is running, a mask signal disables the output of further
DVCFG pulses. The m ask signal i s shown in Figure 28.67.
The mask timer status can be recognized by reading the CMK flag in the DVCFG control
register (CDVC).
Mask
DVCFG
Mask timer
underflow
Figure 28. 67 M ask Signal
Rev. 2.0, 11/ 00, page 792 of 1037
Figures 28.68 and 28.69 show examples of CFG mask timer operations.
CFG (racing)
Edge detect
Cleared by writing 0
after reading 1
Capstan motor
mask timer Mask interval Mask interval
DVCFG
MCGin flag
Figure 28. 68 CFG M ask Timer O per ation (When Capstan Motor is Racing)
CFG
Edge detect
Capstan motor
mask timer Mask interval Mask interval
Figure 28. 69 CFG M ask Timer O per ation (When Capstan Motor is Operating Normally)
Rev. 2.0, 11/ 00, page 793 of 1037
28.14.4 DFG Noise Removal Circuit
(1) Block Diagra m
Figure 28. 70 shows t he bl oc k di agra m of t he DFG noi se rem ova l c i rc ui t.
Edge
detection
Delay circuit
DFG SQ
R
NCDFG
delay = 2
Edge
detection
Figure 28.70 DFG Noise Removal Circuit
(2) Register Descri pt ions
• Register configuration
Table 28.24 shows the register configuration of the DFG m ask c irc u i t .
Table 28.24 Register Configuration
Name Abbrev. R/W Size Init ial Value Address
FG cont r ol regist er FGCR W Byte H'FE H'FD09E
•FG Control Register (FGCR)
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7
———————
——————— W
DRF
1
Bit :
Initial value :
R/W :
Selects the edge of the DFG noise re m ova l si gna l (NCDFG) t o be se nt t o t he drum spe e d e rror
detector. If a read is attempted, an undetermined value is read out. Bits 7 to 1 are reserved. No
write in them is valid.
It is initialized to H'FE by a reset, stand-by or module stop.
The edge selection circuit is located in the drum speed error detector, and outputs the register
output to the drum speed error detector.
Bits 7 to 1: Reserved
No write in them is valid. If a read is attempted, an undetermined value is read out.
Rev. 2.0, 11/ 00, page 794 of 1037
Bit 0: DFG Edge Selection Bit (DRF)
Selects the edge of the NCDFG signal use d i n t he drum spe ed e rror detector.
Bit 0
DRF Description
0 Selects t he rising edge of NCDFG signal (I nit ial value)
1 Selects t he falling edge of NCDFG signal
(3) Description of Operation
The DFG no i se r e moval cir c u i ts ge n e r ates a signal (NCDFG signa l) wi t h a d elay circuit as a
result of removing noise (signal fluctuation smaller than 2 φ) from t h e DFG si gna l . T h e
resulted NCDFG si g n a l is be h i n d the time when the DFG signa l wa s d etected by 2 φ. Figure
28. 7 1 sho ws t h e NC DFG si g n a l .
DFG
NCDFG
Noise
2 2 2 = fosc
Figure 28. 71 NCDFG signal
Rev. 2.0, 11/ 00, page 795 of 1037
28.15 Sync Signal Detector
28.15.1 Overview
This block performs detection of the horizontal sync signal (Hsync) and vertical sync signal
(Vsync) from the composite sync signal (Csync), noise counting, and field detection.
It detects the horizontal and vertical sync signals by setting threshold in the register and based on
the servo cl oc k (φs = fosc/2). Noise masking is possible during the detection of the horizontal
sync signals, and if any Hsync is missing, it can be supplemented. Also, if total volume of the
noise detected in one frame of Csync amounted over a specified volume, the detector generates a
noise detection interrupt.
Note: This circuit detects a pulse with a specific width set by the threshold register. It does not
classify or restore the sync signal to a formal one.
Rev. 2.0, 11/ 00, page 796 of 1037
28.15.2 Bl ock Diagram
Figure 28.72 shows the block diagram of the sync signal detector.
W
H threshold
register
W
V threshold
register
(6bit) (4bit)
· HTR
· VTR
WW
H supplement
start time
register Supplemented
H pulse width
register
(8bit) (4bit)
· HPWR
· HRTR
WW
(6bit) (8bit)
· NDR
R/W R/WR/(W) R
NOIS
H counter (8-bit)
Noise detector
Supplement control &
noise mask control circuit
Up/Down
counter (6-bit)
SEPH
Selection of
polarity Noise detection
window
Noise detection interrupt
VD interrupt
Csync
Sync signal detector
H reload counter (8-bit)
Field detector
Noise counter (10-bit)
Toggle
circuit
Clear
FLD SYCT
VD(SEPV)
FILED
NOISE
IRRSNC
OSCH
NIS/VD
· SYNCR
· NWR
Internal bus
s = fosc/2
s/2
Noise detection
window
register Noise
detection
register
Figure 28. 72 Bl oc k Diagram of the Sync Signal Detector
Rev. 2.0, 11/ 00, page 797 of 1037
28.15.3 P in Configuration
Table 28.25 shows the pin configuration of the sync signal detector.
Table 28.25 Pin Configuration
Name Abbrev. I/O Function
Composite sync signal input pin Csync Input Composite sync signal input
28.15.4 Register Configuration
Table 28.26 shows the register configuration of the sync signal detector.
Table 28.26 Register Configuration
Name Abbrev. R/W Size Init ial Value Address
Vertical sync signal
threshold regist er VTR W Byte H'C0 H'FD0B0
Horizontal sync signal
threshold regist er HTR W Byte H'F0 H'FD0B1
H supplement star t t ime
setting r egister HRTR W Byte H'00 H'FD0B2
Supplemented H pulse
width setting register HPWR W Byte H'F0 H'FD0B3
Noise detection window
setting r egister NWR W Byte H'C0 H'FD0B4
Noise detector register NDR W Byte H'00 H'FD0B5
Sync signal control
register SYNCR R/W Byte H'F8 H'FD0B6
Rev. 2.0, 11/ 00, page 798 of 1037
28.15.5 Register Descriptions
(1) Vertical Sync Signal Threshold Register (VTR)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7——
—— WWW
VTR5 VTR4 VTR3 VTR2 VTR1 VTR0
1
Bit :
Initial value :
R/ W :
Sets the threshold for the vertical sync signal when the signal is detected from the composite
sync signal. The t hreshold i s set by bi ts 5 to 0 (VTR5 t o VTR0). Bi ts 7 and 6 a re reserve d.
VTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'C0 by a reset, stand-by or module stop.
Rev. 2.0, 11/ 00, page 799 of 1037
(2) Horizontal Sync Signal Threshold Register (HTR)
0
0
1
0
W
2
0
W
3
0
456
1
7————
———— WW
HTR3 HTR2 HTR1 HTR0
111
Bit :
Initial value :
R/W :
Sets the threshold for the horizontal sync signal when the signal is detected from the
composite sync signal. The threshold is set by bits 3 to 0 (HTR3 to HTR0). Bits 7 and 4 are
reserved.
HTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'F0 by a reset, stand-by or module stop.
Figure 28.73 shows threshold and separated sync signals.
[Legend]
TH
Hpuls
TH
SEPV
Hpuls : Cycle of the horizontal sync signal (NTSC: 63.6, PAL: 64 [ s])
: Pulse width of the horizontal sync signal (NTSC, PAL: 4.7 [ s])
VVTH
HVTH : Value set as the threshold of the vertical sync signal
: Value set as the threshold of the horizontal sync signal
SEPV
SEPH : Detected vertical sync signal
: Detected horizontal sync signal (before supplement)
TH
SEPH
Csync
H'00
Counter value
1/2 Hpuls
VD interrupt
Hpuls
VVTH
HVTH
Fi g ur e 2 8 . 7 3 Thre shold and Se pa r a ted Sync Si g na l s
Rev. 2.0, 11/ 00, page 800 of 1037
• Example
The set values to detect the vertical and horizontal sync signals (SEPV and SEPH) from
Csync are required to meet the following conditions. Assumed t h a t t he set va l u e s in t h e
VTHR r e g i ste r were VVT H and HVTH,
(VVTH-1) × 2/φs > Hpuls
(HVTH-2) × 2/φs ≤ Hpuls/2 < (HVTH-1) ) × 2/φs
Where, Hpuls is pulse widt h (µs) of the horizontal sync signal, and φs is servo clock
(fosc/2).
Thus, if φs = 5 MHz, NTSC system is used,
(VVTH-1) × 0.4µs > 4.7µs
∴VVTH ≥ H'D
(HVTH-2) × 0.4µs ≤ 2.35µs < (HVTH-1) × 0.4µs
∴HVTH ≥ H'7
Note: This circuits detects the pulse with the width set in the VTHR register. If a noise pulse
with the width greater than the set value was input, the circuit regards that it detected a
sync signal.
Rev. 2.0, 11/ 00, page 801 of 1037
(3) H Suppleme nt Sta r t T i m e Se t t i ng Re g i st e r ( H RT R)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HRTR4 HRTR3 HRTR2 HRTR1 HRTR0
0
W
HRTR7
WWW
HRTR6 HRTR5
Bit :
Initial value :
R/W :
Sets the timing to generate a supplementary pulse if a drop-out of a pulse of the horizontal
sync signal occ urre d.
HRTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'00 by a reset, stand-by or module stop.
((Value of HRTR7 to HRTR0) + 1) × 2/ φs = T H
where, TH is the cycle of the horizontal sync signal (µs), and φs is the servo c loc k (fosc/ 2).
Whether the horizontal sync signal exists or not is determined one clock before the
supplementary pulse is generated. Accordingly, set to HRTR7 to HRTR0 a value obtained
from the equation shown above plus one.
Also, HRTR7 to HRTR0 set the noise mask period. If the horizontal sync signal had the
normal pulses, it is masked in the mask period.
The start a nd end of t he ma sk peri od are c omput e d frm t he rising e dge of OSCH and SEPH,
respectively. See figure 28.75.
(4) Supplem e nt e d H Pulse Width Se t ting Re g i st e r ( H PWR)
0
0
1
0
W
2
0
W
3
0
456
1
7————
———— WW
HPWR3 HPWR2 HPWR1 HPWR0
111
Bit :
Initial value :
R/W :
HPWR sets the pulse width of the supplemented pulse which is generated if a drop-out of a
pulse of the horizontal sync signal occurs. Bits 7 to 4 are reserved.
HRWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'F0 by a reset or stand-by.
((Value of HPWR3 to HPWR0) + 1) × 2/φs = Hpul se
Where, Hpuls is the pulse width of the horizontal sync signal (µs), and φs is the servo cloc k
(fosc/2).
Rev. 2.0, 11/ 00, page 802 of 1037
(5) No i se Det e cti o n Window Se t t i ng Re g i st e r ( NW R)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7——
—— WWW
NWR5 NWR4 NWR3 NWR2 NWR1 NWR0
1
Bit :
Initial value :
R/W :
NWR sets the period (window) when the drop-out of the pulse of the horizontal sync signal is
detected and the noise is counted. Set the timing of the noise detection window in bits 5 to 0.
Bits 7 and 6 are re served.
NWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'C0 by a reset, stand-by or module stop.
Set the value of the noise detection window timing according to the following equation.
((Value of NWR5 to NWR0) + 1) × 2/ φs = 1/4 × TH
Where, TH is the pulse width of the horizontal sync signal (µs), a nd φs is the servo c loc k
(fosc/2).
It is recommended that this timing value is set at about 1/4 of the cycle of the horizontal sync
signal.
(6) No i se Det e cti o n Re g i st e r ( NDR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7NDR4 NDR3 NDR2 NDR1 NDR0
0
W
NDR7
WWW
NDR6 NDR5
Bit :
Initial value :
R/W :
NDR sets the noise detection level when the noise of the horizontal sync signal is detected
(when NWR is set). Set the noise detection level in bits 7 to 0.
NDR is an 8-bit write-only register. No read is valid. If a read is attempted, an
undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop.
The noise detector takes counts of the drop-outs of the horizontal sync signals and the noises
within the pulses, and if they amount to a count greater than four times of the value set in
NDR7 to NDR0, the detector sets the NOIS flag in the sync signal control register (SYNCR).
Set the noise detection level at 1/4 of the noise counts in one frame.
The noise counter is cleared whenever Vsync was detected twice.
See section 28.15.6, Noise Detection, for the details of the noise detection window and the
noise detection level.
Rev. 2.0, 11/ 00, page 803 of 1037
(7) Sy nc Signal Control Regi st e r ( SYNCR)
0
0
1
0
R
2
0
R/(W)*
3
1
456
1
7————
———— R/WR/W
NIS/VD NOIS FLD SYCT
111
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
SYNCR controls the noise detection, field detection, polarity of the sync signal input, etc.
SYNCR is an 8-bit register. It is initialized to H'F8 by a reset, stand-by or module stop. Bits
7 to 4 are reserved. No write is valid. Bit 1 is valid for read only.
Bits 7 to 4: Reserved
Writes are disabled. If a read is attempted, an undetermined value is read out.
Bit 3: Interrupt Selection Bit (NIS/VD)
Selects whether an interrupt request is generated when a noise level was detected or when the
VD signal was detected.
Bit 3
NIS/VD Description
0 Int er r upt at t he noise level
1 Int er r upt at VD (Init ial value)
Bit 2: Noise Detecti on Fl ag (NOIS)
NOIS is a status flag indicating that the noise counts reached at more than four times of the
value set in NDR. The flag is cleared only by writing 0 after reading 1. Care is required
because it is not cleared automatically.
Bit 2
NOIS Description
0 Noise count is smaller than four t imes of the value set in NDR ( I nitial value)
1 Noise count is equal to or gr eat er t han f our t im es of t he value set in NDR
Rev. 2.0, 11/ 00, page 804 of 1037
Bit 1: Field Detection Flag (FLD)
Indicates whether the field currently being scanned is even or odd. See figure 28.74.
Bit 1
FLD Description
0 Odd f ield (Initial value)
1 Even field
Bit 0: Sync Signal Polarity Selection Bit (SYCT)
Selects the polarity of the sync signal (Csync) to be input.
Bit 0
SYCT Description Polarity
0(Init ial value) Positive
1Negative
Rev. 2.0, 11/ 00, page 805 of 1037
Field detection
flag (FLD)
SEPV
Noise detection
window
Composite sync
signal
(Csync)
Even field
(a) Even field (EVEN)
Field detection
flag (FLD)
SEPV
Noise detection
window
Composite sync
signal
(Csync)
Odd field
(b) Odd field (ODD)
Figure 28.74 Field Detection
Rev. 2.0, 11/ 00, page 806 of 1037
28.15.6 Noise Dete cti on
If drop-out of a pulse of the horizontal sync signal occurred, set a supplemented pulse at the
timing set in HPWR and with the set pulse width.
Set the noise detection window with HWR of about 1/4 of the horizontal sync signal, and the
pulse with equal High and Low periods will be obtained.
(1) Example of Setting
Assumed t ha t a supplemented pulse is set when fosc = 10MHz under the conditions φs =
5MHz, NT SC : T H = 6 3 . 6 ( µs) and Hpuls = 4.7 (µs), the set values of the supplemented pulse
timing (HRTR7-0), supplemented pulse width (HPWR3-0) and noise detection window
timing (NWR5-0) are expressed by the following equations.
(Value of HRTR7-0) × 2/φs = TH
((Value of HPWR3-0) + 1) × 2/φs = Hpuls
((Value of NWR5-0) + 1) × 2/φs = 1/ 4 × TH
Where, TH is the cycle of the horizontal sync signal (µs), Hpuls is the pulse widt h of t he
horizontal sync signal (µs) and φs is the servo c loc k (Hz) (fosc/ 2).
Accordingly,
(Value of HRTR7 to HRTR0) × 0. 4 (µs) = 63. 6 (µs)
∴HRTR7-0=H'9F
((Value of HPWR3 to HPWR0) + 1) × 0. 4 (µs) = 4.7 (µs)
∴HRTR3-0=H'B
((Value of NWR5 to NWR0) + 1) × 0. 4 (µs) = 16 (µs)
∴NWR5-0=H'27
Also, the noise mask period is computed as follows.
((Value of HRTR7 to HRTR0) + 1) − 24) × 2/ φs = 54 (µs)
Where, 24 i s a c onstant re quire d for a struct ura l re a son.
Figure 28.75 shows the set pe riod for HRTR, HPWR and NWR.
Rev. 2.0, 11/ 00, page 807 of 1037
[Legend]
SEPH
Noise detection
window
Noise mask for
OSCH
OSCH
Noise mask for
H counter
H reload
counter
H counter
SEPH
c
OSCH : Horizontal sync signal after detection
: Horizontal sync signal after supplement
a
b : Value set for the noise detection window (NWR5 to NWR0)
: Value set for the pulse width of the horizontal sync signal (NPWR3 to NPWR0)
c
a, b, c : Value set for supplement timing (HRTR7 to HRTR0)
: Complements of 1 of a,b,c, respectively
H ' E 8
TH
:Complement of 2 of multiplier 24 in the equation for the noise mask period
(The noise mask period ends 24 counts before the overflow of H reload counter.)
: Cycle of the horizontal sync signal
(NTSC:63.6 [ms], PAL:64[ms])
TM : Timing at which the noise mask period ends.
Drop-out of the horizontal
sync signal Ignore signal during noise
mask period.
TH
a
b
H'00
OVF
H'E8
c
a
Mask
period
Period determined
by NWR5 to NWR0
Mask
period
TM
Mask
period Mask
period
Mask
period Mask
period Mask
period Mask
period
TH
Don't mask
immediately
after
supplement
period deter-
mined
by a and a
Period determined
by HRTR7 to HRTR0
period determined
by c and H'E8
Period determined
by HPWR3 to HPER0
period
determined
by b
Do mask also im-
mediately after
supplement.
Figure 28.75 Set Period for HRTR, HPWR and NWR
Rev. 2.0, 11/ 00, page 808 of 1037
(2) Operation to Detect Noise
The noise detector considers an irregular pulse of the composite sync signal (Csync) and a
chip of a pulse of the horizontal sync signal within a frame as noise. The noise counter takes
counts of the irregular pulses during the High period of the noise detection window and the
chips and drop-outs of the horizontal sync signal pulses during the Low period. Also, it
counts more than one irregular pulses as one. The noise counter is cleared at every frame
(Vsync is detected twice).
The equivalent pulse contained in 9H of the vertical sync signal is counted also as an
irregula r pul se.
It sets the noise detection flag (NOIS) in the sync signal control register (SYNCR) at 1 if the
count of the i rregul a r pulses + t he count of t he pul se c hips and drop-out s of the horiz ont al
sync signal > 4 × (va l ue of NDR7 to NDR0).
See section 28.15.5 (7), Sync Signal Control Register (SYNCR) for the NOIS bit.
Figure 28.76 shows the operation of the noise detection.
Csync
Noise detection
window
Noise detection
flag (NOIS)
Noise counter
Noise detection
level
Noise detection
flag is set.
NOIS : Bit 2 of the sync signal control register (SYNCR)
Noise
Figure 28.76 Operation of the Noise Detection
Rev. 2.0, 11/ 00, page 809 of 1037
28.15.7 Sync Signal Detec tor Acti vati on
The sync signal detector starts operation by release of reset, or by accepting input of a sync
signal after its transition from power-down mode to active mode and release of module stop.
The signal given to the detector is the polarity pulse assigned by the SYCT bit of the sync signal
control register (SYNCR). The detector starts operation even if this pulse was a noise pulse with
a width short of the regular width. The minimum pulse width which can activate the detector is
not constant de pendi ng on t he i nt erna l opera t ion of t he input c irc ui t. Acc ordi ngly, i f t he a ssured
activation of the detector is required, input a pulse with a width greater than 4/ φs (φs = fosc/2
(Hz)). In such a case, care is required to noise, etc., because even a pulse with a width smaller
than 4φ/s may cause activation.
Rev. 2.0, 11/ 00, page 810 of 1037
28.16 Servo Interrupt
28.16.1 Overview
The interrupt exception processing of the servo module is started by one of ten factors, i.e. the
drum speed error detector (×2), drum phase error detector, capstan speed error detector (×2),
capstan phase error detector, HSW timing generator (×2), sync detector and CTL circuit. For
these interrupt factors, see each of their circuit sections in this manual.
Also, see section 5, Exception Handling.
28.16.2 Register Configuration
Table 28.27 shows the list of the registers which control the interrupt of the servo section.
Table 28.27 Registers which Control the Interrupt of the Servo Section
Name Abbrev. R/W Size Init i al Value Address
Servo interrupt
permission register 1 SIENR1 R/W Byte H'00 H'FD0B8
Servo interrupt
permission register 2 SIENR2 R/W Byte H'FC H'FD0B9
Servo interrupt r equest
register 1 SIRQR1 R/W Byte H'00 H'FD0BA
Servo interrupt r equest
register 2 SIRQR2 R/W Byte H'FC H'FD0BB
28.16.3 Register Description
(1) Servo Interrupt Permission Register 1 (SIENR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1
0
R/W
IEDRM3
R/W R/WR/W
IEDRM2 IEDRM1
Bit :
Initial value :
R/W :
SIENR1 controls the permission and prohibition of the interrupt of the servo section. SIENR1 is
an 8-bit readable/writable register. It is initialized to H'00 by a reset, stand-by or module stop.
Rev. 2.0, 11/ 00, page 811 of 1037
Bit 7: Drum Phase Error Detection Interrupt Permission Bit (IEDRM3)
Bit 7
IEDRM3 Description
0 Prohibits t he int errupt request th r ough I RRDRM3 ( Init ial va lue)
1 Perm it s t he interr upt request through IRRDRM 3
Bit 6: Drum Speed Error Detection (lock detection) Interrupt Permission Bit (IEDRM2)
Bit 6
IEDRM2 Description
0 Prohibits t he int errupt request th r ough I RRDRM2 ( Init ial va lue)
1 Perm it s t he interr upt request through IRRDRM 2
Bit 5: Drum Speed Error Detection (OVF, latch) Interrupt Permission Bit (IEDRM1)
Bit 5
IEDRM1 Description
0 Prohibits t he int errupt request th r ough I RRDRM1 ( Init ial va lue)
1 Perm it s t he interr upt request through IRRDRM 1
Bit 4: Capstan Phase Error Detection Interrupt Permission Bit (IECAP3)
Bit 4
IECAP3 Description
0 Prohibit s t he interr upt request thr ough IRRCAP3 (Initial value)
1 Perm it s the interrupt request through IRRCAP3
Bit 3: Capstan Speed Error Detection (lock detection) Interrupt Permission Bit (IECAP2)
Bit 3
IECAP2 Description
0 Prohibit s t he interr upt request thr ough IRRCAP2 (Initial value)
1 Perm it s the interrupt request through IRRCAP2
Rev. 2.0, 11/ 00, page 812 of 1037
Bit 2: Capstan Speed Error Detection (OVF, latch) Interrupt Permission Bit (IECAP1)
Bit 2
IECAP1 Description
0 Prohibit s t he interr upt request thr ough IRRCAP1 (Initial value)
1 Perm it s the interrupt request through IRRCAP1
Bit 1: HSW Timing Generation (counter clear, capture) Interrupt Permission bit
(IEHSW2)
Bit 1
IEHSW2 Description
0 Prohibit s t he interr upt request thr ough IRRHSW2 (I nitial value)
1 Perm it s the interrupt request through IRRHSW2
Bit 0: HSW Timing Generation (OVW, matching, STRIG) Interrupt Permission bit
(IEHSW1)
Bit 0
IEHSW1 Description
0 Prohibit s t he interr upt request thr ough IRRHSW1 (I nitial value)
1 Perm it s the interrupt request through IRRHSW1
Rev. 2.0, 11/ 00, page 813 of 1037
(2) Servo Interrupt Permission Register 2 (SIENR2)
0
0
1
0
R/W
23456
1
7——————
—————— R/W
IESNC IECTL
11111
Bit :
Initial value :
R/W :
SIENR2 controls the permission and prohibition of the interrupt of the servo section. SIENR2 is
an 8-bit readable/writable register. It is initialized to H'FC by a reset, stand-by or module stop.
Bits 7 to 2: Reserved
No read or write is valid. If a read is attempted, an undetermined value is read out.
Bit 1: Vertical Sync Signal Interrupt Permission Bit (IESNC)
Bit 1
IESNC Description
0 Prohibits the inter r upt ( int er r upt t o t he ver t ical sync signal) request t hr ough IRRSNC
(Init ial value)
1 Permit s t he int er r upt r equest t hr ough I RRSNC
Bit 0: CTL Interrupt Permission Bit (IECTL)
Bit 0
IECTL Description
0 Prohibits t he int errupt request th r ough I RRCTL (Initial value)
1 Perm it s t he interr upt request through IRRCTL
Rev. 2.0, 11/ 00, page 814 of 1037
(3) Serv o Interrupt Re quest Re g i st e r 1 ( SIRQ R1 )
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
0
R/(W)*
56
0
7IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0
R/(W)*
IRRDRM3
R/(W)*
R/(W)*
R/(W)*
IRRDRM2 IRRDRM1
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SIRQR1 displays an occurrence of an interrupt request of the servo section. If the interrupt
request occ urre d, the c orresponding bi t is set t o 1.
SIRQR1 is an 8-bit readable/writable register. Writing is allowed only in the case of writing 0 to
clear the flag. It is initialized to H'00 by a reset, stand-by or module stop.
Bit 7 : Drum P ha se E r ror De t e ctor Inte r rupt Re quest Bit (IRRDRM3)
Bit 7
IRRDRM3 Description
0 No interr upt r equest from t he dr um phase er r or detector (Initial value)
1 Int er r upt request ed f r om the drum phase er r or det ector
Bit 6 : Drum Spe ed Er r o r Dete c t o r ( l o c k de t e cti o n) Int e rr upt Request B i t (IRRDRM2)
Bit 6
IRRDRM2 Description
0 No interr upt r equest from t he dr um speed er r or detector ( lock det ect ion)
(Init ial value)
1 Int er r upt request ed f r om the drum speed er r or det ector ( lock detect ion)
Bit 5 : Drum Spe ed Er r o r Dete c t o r ( O VF , l at c h) Int e r rupt Re quest Bit (IRRDRM1)
Bit 5
IRRDRM1 Description
0 No interr upt r equest from t he dr um speed er r or detector ( O VF, latc h) (I nitial value)
1 Int er r upt request ed f r om the drum speed er r or det ector ( O VF, lat ch)
Rev. 2.0, 11/ 00, page 815 of 1037
Bit 4 : Ca pst an Phase E r ror De t e ctor Inte r rupt Re quest Bit (IRRCAP3)
Bit 4
IRRCAP3 Description
0 No interr upt r equest from t he capst an phase er r or detector (I nit ial value)
1 Int er r upt request ed f r om the capstan phase er r or det ector
Bit 3 : Ca pst an Spee d Erro r Dete c t o r ( l o c k de t e cti o n) Int e rr upt Request B i t (IRRCAP2)
Bit 3
IRRCAP2 Description
0 No interrupt r equest f r om the capstan speed er r or det ect or ( lock detect ion)
(Init ial value)
1 Int er r upt r equest ed from t he dr um speed er r or det ect or ( lock det ect ion)
Bit 2 : Ca pst an Spee d Erro r Dete c t o r ( O VF , l at c h) Int e r rupt Re quest Bit (IRRCAP1)
Bit 2
IRRCAP1 Description
0 No interr upt r equest from t he capst an speed er r or detector ( O VF, latc h)( I nit ial value)
1 Int er r upt request ed f r om the capstan speed er r or det ector ( O VF, lat ch)
Bit 1: HSW Timing Generator (counter clear, capture) Interrupt Permission Bit
(IRRHSW2)
Bit 1
IRRHSW2 Description
0 No interr upt r equest from t he HSW tim ing generat or (count er clear , capt ur e)
(Init ial value)
1 Int er r upt request ed f r om the HSW timing generat or ( c ount er clear, captur e)
Bit 0: HSW Timing Generator (OVW, matching, STRIG) Interrupt Permission Bit
(IRRHSW1)
Bit 0
IRRHSW1 Description
0 No interr upt r equest from t he HSW tim ing generat or (O VW, m atching, STRIG)
(Init ial value)
1 Int er r upt request ed f r om the HSW timing generat or ( OVW, m at ching, STRIG )
Rev. 2.0, 11/ 00, page 816 of 1037
(4) Serv o Interrupt Re quest Re g i st e r 2 ( SIRQ R2 )
0
0
1
0
R/(W)*
23456
1
7——————
—————— R/(W)*
IRRSNC IRRCTL
11111
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SIRQR2 displays an occurrence of an interrupt request of the servo section. If the interrupt
request occ urre d, the c orresponding bi t is set t o 1.
SIRQR2 is an 8-bit readable/writable register. Writing 0 after reading 1 is allowed; no other
writing is allowed. It is initialized to H'FC by a reset, stand-by or module stop.
Bits 7 to 2: Reserved
No read or write is valid. If a read is attempted, an undetermined value is read out.
Bit 1 : Ver tica l Sy nc Signal Inte r rupt Re quest Bit (IRRSNC)
Bit 1
IRRSNC Description
0 No interrupt r equest f r om the sync signal detector ( VD, noise) (Initial value)
1 Int er r upt r equest ed f r om the sync signal detector ( VD, noise)
Bit 0 : CT L Si g nal Inte rrupt Re quest Bit (IRRCT L )
Bit 0
IRRCTL Description
0 No interr upt r equest from CTL ( I nit ial value)
1 Int er r upt request ed f r om CTL
Rev. 2.0, 11/ 00, page 817 of 1037
28.17 Modu le S t op Con t rol Reigster (MSTP CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
MSTPCR comprises two 8-bit readable/writable registers, that perform module stop mode
control. When the MSTP1 bit is set to 1, servo circuit and 12-bit PWM stop the operation at the
end of the bus cycle and enter to the module stop mode. For details, see 4.5 Module stop mode.
MSTPCR is initialized to H'FFFF by a reset.
Bit 1: Module Stop 1 (MSTP1)
This bit specifies module stop mode of the servo circuit and 12-bit PWM.
MSTPCRL
Bit 1
MSTP1 Description
0 Clear the m odule stop m ode of the Serv o Circuit and 12- bit PWM
1 Set t he m odule stop m ode of the Serv o Circuit and 12- bit PWM (I nitial value)
Rev. 2.0, 11/ 00, page 818 of 1037
Rev. 2.0, 11/ 00, page 819 of 1037
Section 29 Electrical Characteristics
29.1 Absolute Maximum Ratings
Table 29.1 lists the absolute maximum ratings.
Tabl e 2 9 . 1 Absolute M a x i m um Ra t i ng s
Item Symbol Value Unit
Power supply voltage Vcc −0.3 to +7.0 V
Input voltage ( por ts other t han por t 0) Vin −0.3 to Vcc+0.3 V
Input voltage ( por t 0) Vin −0.3 to AVcc+0.3 V
A/D converter power supply voltage AVcc −0.3 to +7.0 V
A/D converter input volt age AVin −0.3 to AVcc+0.3 V
Servo power supply voltage SVcc −0.3 to +7.0 V
Servo amplifier input voltage Vin −0.3 to SVcc +
0.3 V
Operating temper ature Topr −20 t o +75 °C
Operating temper ature ( At Flash m em or y
program/erase) Topr 0 to +75 °C
Storage t em per ature Tstr −55 to +125 °C
Notes: 1. Permanent damage m ay occur to the chip if absolute maximum r at ings ar e exceeded.
Normal operation should be under t he conditions specified in Electrical Characteristics.
Exceeding thes e values can result in incorrec t oper ation and reduced reliability .
2. All voltages ar e r elative to Vss = SVss = AVss = 0.0 V.
Rev. 2.0, 11/ 00, page 820 of 1037
29.2 Electrical Characteristics of HD64F2194
29.2.1 DC Characteristics of HD64F2194
Table 29.2 DC Characteristics of HD64F2194, HD64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0. 0 V, T a = –20 t o + 75°C unl ess otherwise
specified.)
Values
Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes
MD0 Vcc=2.7 to 5.5V 0.9 Vcc Vcc+0.3
0.8 Vcc Vcc+0.3
5(6
,
10,
, FWE,
,&
,
,54
to
,54
Vcc=2.7 to 5.5V 0.9 Vcc Vcc+0.3
SCK1, SCK2, SI1, SI2,
&6
, FTIA, FTIB, FTIC,
FTID, TRIG, TMBI,
$'75*
0.8 Vcc Vcc+0.3
Vcc–0.5 Vcc+0.3OSC1, X1
Vcc=2.7 to 5.5V Vcc–0.3 Vcc+0.3
0.7 Vcc Vcc+0.3P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PS0 to PS4
Vcc=2.7 to 5.5V 0.8 Vcc Vcc+0.3
Input high
voltage VIH
Csyn c 0.7 Vcc Vcc+0.3
V
Rev. 2.0, 11/ 00, page 821 of 1037
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
MD0 Vcc=2.7 to 5.5V –0.3 0.1 Vcc
−0.3 0.2 Vcc
5(6
,
10,
, FWE,
,&
,
,54
to
,54
Vcc=2.7 to 5.5V −0.3 0.1 Vcc
SCK1, SCK2, SI1, SI2,
&6
, FTIA, FTIB, FTIC,
FTID, TRIG, TMBI,
$'75*
−0.3 0.2 Vcc
−0.3 0.5
OSC1, X1
Vcc=2.7 to 5.5V −0.3 0.3
−0.3 0.3 Vcc
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PS0 to PS4
Vcc=2.7 to 5.5V −0.3 0.2 Vcc
Input low
voltage VIL
Csync −0.3 0.2 Vcc
V
−IOH=1.0mA Vcc–1.0 V
−IOH=0.5mA Vcc
–0.5 V Refer-
ence
value
Output
high
voltage
VOH SO1, SO2, SCK1,
SCK2, PWM1, PWM2,
PWM3, PWM4 , PWM14,
STRB, BUZZ, TMO,
TMOW, FTOA, FTOB,
PPG70 to PPG77,
RP0 to RP7,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PS0 to PS4
−IOH=0.1mA
Vcc=2.7 to 5.5V Vcc–0.5 V
Rev. 2.0, 11/ 00, page 822 of 1037
Values
Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes
IOL=1.6mA
0.6 VSO1, SO2, SCK1,
SCK2, PWM1, PWM2,
PWM3, PWM 4 ,
PWM14, STRB, BUZZ,
TMO, TMOW, FTOA,
FTOB, PPG70 to
PPG77,
RP0 to RP7,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
PS0 to PS4
IOL=0.4mA
Vcc=2.7 to 5.5V
0.4 V
IOL=20mA
1.5 V
IOL=1.6mA
0.6 V
Output
low
voltage
VOL
P80 to P87,
IOL=0.4mA
Vcc=2.7 to 5.5V
0.4 V
MD0, OSC1
5(6
,
10,
, FWE,
,54
to
,54
,
,&
Vin=0.5 to Vcc–
0.5V
1.0
SCK1, SCK2, SI1, SI2,
&6
, FTIA, FTIB, FTIC,
FTID, TRIG, TMBI,
$'75*
Vin=0.5 to Vcc–
0.5V
1.0
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P53,
P60 to P67,
P70 to P77,
P80 to P87,
PS0 to PS4
Vin=0.5 to Vcc–
0.5V
1.0
Input
/output
leakage
current
IIL
P00 to P07,
AN8 to ANB Vin=0.5 to
AVcc–0.5V
1.0
µA
Rev. 2.0, 11/ 00, page 823 of 1037
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
Pull-up
MOS
current
−Ip P10 to P17,
P20 to P27,
P30 to P37,
Vcc=5.0V,
Vin=0V 50 300 µA Note 1
All input pins except
power supply, P13, P23,
P24 and analog system
pins
fin=1 MHz,
Vin=0V,
Ta=25°C
15 pF
Input
capaci-
tance
Cin
P13, P23, P24 fin=1 MHz,
Vin=0V,
Ta=25°C
20 pF
Vcc=5V,
fOSC=10 MHz,
High-speed
mode
50 70 mA Note 2
Active
mode
current
dissipa-
tion (CPU
operating)
IOPE Vcc
Vcc=5V,
fOSC=10 MHz,
Medium-speed
mode (1/64)
35 mA Refer-
ence
value
Active
mode
current
dissipa-
tion (reset)
IRES Vcc Vcc=5V,
fOSC=10 MHz — 30 45 mA Note 2
Sleep
mode
current
dissipa-
tion
ISLEEP Vcc Vcc=5V,
fOSC=10 MHz
High-speed
mode
20 30 mA Note 2
Vcc=2.7V,
With 32kHz
crystal
oscillator
(φ sub=φw/2)
90 150 Note 2
Subactive
mode
current
dissipa-
tion
ISUB Vcc
Vcc=2.7V,
With 32kHz
crystal
oscillator
(φ sub=φw/8)
40
µA
Refer-
ence
value,
Note 2
Vcc=2.7V,
With 32kHz
crystal
oscillator
(φ sub=φw/2)
15 30 Note 2
Subsleep
mode
current
dissipa-
tion
ISUBSLP Vcc
Vcc=2.7V,
With 32kHz
crystal
oscillator
(φ sub=φw/8)
10
µA
Refer-
ence
value,
Note 2
Rev. 2.0, 11/ 00, page 824 of 1037
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
Vcc=2.7V,
With 32kHz
crystal
oscillator
510 µA Note 2
Watch
mode
current
dissipa-
tion
IWATCH Vcc
Vcc=5.0V,
With 32kHz
crystal
oscillator
10 µ
A Reference
value
Note 2
Standby
mode
current
dissipa-
tion
ISTBY Vcc X1=Vcc,
Without 32kHz
crystal
oscillator
5µA Note 2
RAM data
retaining
voltage in
standby
mode
VSTBY 2.0 V
Notes: Do not open the AVcc and AVss pin even when t he A/D conver t er is not in use.
1. Current value when the r elevant bit of the pull-up MO S select r egister ( PUR1 to PUR3)
is set to 1.
2. The current on t he pull-up M O S or t he out put buffer excluded.
Table 29.3 Pin Status at Current Dissipation Measurement
Mode RES pin I nternal State Pin Oscillator Pin
Active mode
High-speed, medium-
speed
Vcc Operating Vcc
Sleep mode
High-speed, medium-
speed
Vcc CPU and servo
circuits stopped. Vcc
Reset Vss Reset Vcc
Standby mode Vcc All stopped Vcc
Main clock:
Cry s tal os c illa tor
Sub clock:
X1 pin = Vcc
Subactive mode Vcc CPU and timer A
operating Vcc
Subsleep mode Vcc Timer A operat ing Vcc
Watch m ode Vcc Timer A oper at ing Vcc
Main clock:
Cry s tal os c illa tor
Sub clock:
Cry s tal os c illa tor
Rev. 2.0, 11/ 00, page 825 of 1037
Table 29.4 Bus Drive Characteristics of HD64F2194, HD64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0. 0 V, T a = –20 t o + 75°C unl ess otherwise
specified.) Applicable pin: SCL, SDA
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
VT−0.2Vcc V
VT+
0.7Vcc V
Schmidt
trigger
input
voltage VT+
–VT−
SCL, SDA
0.05Vcc V
Input High
voltage VIH SCL, SDA 0.7Vcc Vcc+0.5 V
Input Low
voltage VIL SCL, SDA −0.5 0.2Vcc V
IOL=8mA
0.5Output
Low
voltage
VOL SCL, SDA
IOL=3mA
0.4
V
SCL and
SDA
output fall
time
tof SCL, SDA 20+
0.1Cb 250 ns
Rev. 2.0, 11/ 00, page 826 of 1037
29.2.2 Allowable Output Currents of HD64F2194, HD64F2194C
The specifications for the digital pins are shown below.
Table 29.5 Allowable Output Currents
(Conditions: Vcc = 2.7 to 5.5 V, Vss = 0.0 V, T a = –20 t o + 75°C)
Item Symbol Value Unit Notes
Allowable input cur r ent ( to chip) IO2mA1
Allowable input cur r ent ( to chip) IO22 mA 2
Allowable input cur r ent ( to chip) IO10 mA 3
Allowable output curr ent ( f rom chip) −IO2mA4
Total allowable input cur r ent ( to chip) ΣIO80 mA 5
Total allowable output current (f r om
chip) −ΣIO50 mA 6
Notes: 1. The allowable input cur r ent is t he m axim um value of t he current f lowing from each I/O
pin to VSS (except for por t 8, SCL and SDA).
2. The allowable input cur r ent is t he m aximum value of t he cur r ent flowing from each I /O
pin to VSS. This applies to port 8.
3. The allowable input cur r ent is t he m aximum value of t he cur r ent flowing from each I /O
pin to VSS. This applies to SCL and SDA.
4. The allowable output curr ent is t he m aximum value of t he cur r ent flowing from VCC to
each I/ O pin.
5. The total allowable input cur rent is t he sum of t he cur r ents flowing from all I/ O pins to
VSS simultaneously.
6. The total allowable output curr ent is t he sum of t he cur r ent s f lowing fr om VCC to all I/O
pins.
Rev. 2.0, 11/ 00, page 827 of 1037
29.2.3 AC Characteristics of HD64F2194, HD64F2194C
Table 29.6 AC Characteristics of HD64F2194, HD64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Notes
Clock oscillation
frequency fOSC OSC1 , OSC2 8 10 MHz
Cl ock cycle ti me tcyc OSC1 , OSC2 100 125 ns Figure 29.1
Subclock
oscillation
frequency
fXX1, X2 Vcc=2.7 to 5.5V 32.768 kHz
Subcl ock cycle
time tsubcyc X1, X2 Vcc=2.7 to 5.5V 30.518 µ
s Figure 29.2
OSC1, OSC2 Crystal oscillator 10 msOscillation
stabilization time trc
X1, X2 32kHz crystal
oscillator
Vcc=2.7 to 5.5V
2s
External clock high
width tCPH OSC1 40
ns
Ext ernal clock low
width tCPL OSC1 40
ns
Ext ernal clock rise
time tCPr OSC1 10 ns
Ext ernal clock fal l
time tCPf OSC1 10 ns
Figure 29.1
External clock
stabilization delay
time
tDEXT OSC1 500 µ
s Figure 29.3
Subclock input low
level pulse width tEXCLL X1 Vcc=2.7 to 5.5V 15.26 µ
s
Subclock input high
level pulse width tEXCLH X1 Vcc=2.7 to 5.5V 15.26 µ
s
Subclock input rise
time tEXCLr X1 Vcc=2.7 to 5.5V 10 ns
Subclock input fall
time tECXLf X1 Vcc=2.7 to 5.5V 10 ns
Figure 29.2
Rev. 2.0, 11/ 00, page 828 of 1037
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Figure
5(6
pin low level
width tREL
5(6
Vcc=2.7V to
5.5V 20
tcyc Figure
29.4
Input pin high level
width tIH
,54
to
,54
,
10,
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID, TRIG
Vcc=2.7V to
5.5V 2
tcyc
tsubcyc
Input pin low level
width tIL
,54
to
,54
,
10,
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID, TRIG
Vcc=2.7V to
5.5V 2
tcyc
tsubcyc
Figure
29.5
t
cyc
t
CPH
V
IL
V
IH
OSC1
t
CPL
t
CPf
t
CPr
Figure 29. 1 System Clock Timi ng
t
EXCLf
t
subcyc
t
EXCLH
t
EXCLL
t
EXCLr
V
IL
V
IH
X1 Vcc 0.5
Fi g ur e 2 9 . 2 Subc loc k Input T i m i ng
Rev. 2.0, 11/ 00, page 829 of 1037
Vcc
OSC1
t
DEXT
*
RES
(Internal)
4.0V
The t
DEXT
includes the RES pin Low level width 20 t
cyc
.
Note: *
Figure 29.3 External Clock Stabilization Delay Timing
RES V
IL
t
REL
Fi g ur e 2 9 . 4 Re set Input Timi ng
t
IL
t
IH
V
IH
IRQ0 to IRQ5,
NMI, IC,
ADTRG, TMBI,
FTIA, FTIB,
FTIC, FTID,
TRIG
V
IL
Fi g ur e 2 9 . 5 Input Timi ng
Rev. 2.0, 11/ 00, page 830 of 1037
29.2.4 Serial Interface Timing of HD64F2194, HD64F2194C
Table 29.7 Serial Interface Timing of HD64F2194, HD64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Figure
Asynchroniza-
tion 4
SCK1
Clock
synchronization 6
Input clock cycle tscyc
SCK2 2
tcyc
Input clock pulse
width tSCKW SCK1,
SCK2 0.4 0.6 tscyc
SCK1 1.5 tcyc
Input clock rise time tSCKr
SCK2 60 ns
SCK1 1.5 tcyc
Input clock fall time tSCKf
SCK2 60 ns
Figure
29.6
Transmit data delay
time (clock sync) tTXD SO1 100 ns
Receive data setup
time (clock sync) tRXS SI1 100
ns
Receive data hold
time (clock sync) tRXH SI1 100
ns
Figure
29.7
Transmit data output
delay time tTXD SO2 200 ns
Receive data setup
time (clock sync) tRXS SI2 180
ns
Receive data hold
time (clock sync) tRXH SI2 180
ns
Figure
29.7
&6
setup time tCSS
&6
1
tscyc
&6
hold time tCSH
&6
1
tscyc
Figure
29.8
Rev. 2.0, 11/ 00, page 831 of 1037
tSCKf
tSCKr
VIL or VOL
VIH or VOH
SCK1
tSCKW tscyc
Figure 29. 6 SCK1 Clock Timi ng
V
IL
V
IH
t
TXD
SCK1,
SCK2
SO1,
SO2
SI1,
SI2
t
RXS
t
RXH
Fi g ur e 2 9 . 7 SCI I/ O Ti m i ng / Cloc k Sy nc hr o ni zation M o de
V
IH
V
IH
V
IL
CS
SCK2
t
CSH
t
CSS
Fi g ur e 2 9 . 8 SCI2 Chi p Select Timing
Rev. 2.0, 11/ 00, page 832 of 1037
LSI output pin
Timing reference level
V
OH
: 2.0V
V
OL
: 0.8V
30pF 12k
2.4k
Vcc
Figure 29. 9 O utput Load Conditi ons
Rev. 2.0, 11/ 00, page 833 of 1037
Table 29.8 I2C Bus Interface Ti ming of HD64F2194, H D64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Test
Conditions Min Typ Max Unit Figure
SCL input cycle time tSCL 12 tcyc
SCL input high pulse width tSCLH 3 tcyc
SCL input low pulse width tSCLL 5 tcyc
SCL, SDA input rise time tsr
7.5*1tcyc
SCL, SDA input fall time tsf
300 ns
SCL, SDA input spike pulse
removal time tsp
1t
cyc
SDA input bus free time tBUF 5 tcyc
Start condition input hold time tSTAH 3 tcyc
Re-transmit start condition
input setup time tSTAS 3 tcyc
Stop condition input setup time tSTOS 3 tcyc
Data input setup time tSDAS 0.5 tcyc
Data input hold time tSDAH 0 ns
SCL, SDA capacity load Cb
400 pF
Figure
29.10
Note: 1. Can also be set to 17.5 t cyc depending on t he selection of clock t o be used by t he I2C
module.
Rev. 2.0, 11/ 00, page 834 of 1037
t
STAH
t
Sr
t
SDAH
t
SCL
t
SCLL
t
SCLH
t
Sf
t
STAS
t
SP
t
STOS
t
SDAS
V
IL
V
IH
SDA
SCL
P*S*Sr*P*
S, P and Sr denote the following:
S : Start conditions
P : Stop conditions
Sr: Re-transmit start conditions
Note: *
t
BUF
Figure 29. 10 I2C Bus Int e rface I/ O T i m i ng
Rev. 2.0, 11/ 00, page 835 of 1037
29.2.5 A/D Converter Characteristics of HD64F2194, HD64F2194C
Table 29.9 A/D Converter Characteristics of HD64F2194, HD64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
Analog power
supply voltage AVcc AVcc Vcc-
0.3 Vcc Vcc+
0.3 V
Analog input
voltage AVIN AN0 to AN7,
AN8 to ANB AVss AVcc V
AICC AVcc AVcc=5.0V 2.0 mAAnalog power
supply current AISTOP AVcc Vcc=2.7 to 5.5V
At reset and in
power-down mode
10 µA
Analog input
capacitance CAIN AN0 to AN7,
AN8 to ANB 30 pF
Allowable signal
source impedance RAIN AN0 to AN7,
AN8 to ANB 10 kΩ
Resolution 10 Bit
Absol ute accu racy A Vcc=5 .0V ±
4LSB
Conversion time 13.4 26.6 µs
Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc
= Vcc and AVss = Vss.
Rev. 2.0, 11/ 00, page 836 of 1037
29.2.6 Servo Section Electrical Characteristics of HD64F2194, HD64F2194C
Table 29.10 Servo Section Electrical Characteristics of HD64F2194, HD64F2194C
(reference values)
(Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0 .0 V, Ta = 25 °C unless otherwise specified.)
Reference Values
Item Symbol Applicable
Pins Test Conditions Min Ty p Max Unit Note
CTLGR3=0, CTLGR2=0, CTLGR1=0,
CTLGR0=0, f=10kHz 32.0 34.0 36.0
CTLGR3=0, CTLGR2=0, CTLGR1=0,
CTLGR0=1, f=10kHz 34.5 36.5 38.5
CTLGR3=0, CTLGR2=0, CTLGR1=1,
CTLGR0=0, f=10kHz 37.0 39.0 41.0
CTLGR3=0, CTLGR2=0, CTLGR1=1,
CTLGR0=1, f=10kHz 39.5 41.5 43.5
CTLGR3=0, CTLGR2=1, CTLGR1=0,
CTLGR0=0, f=10kHz 42.0 44.0 46.0
CTLGR3=0, CTLGR2=1, CTLGR1=0,
CTLGR0=1, f=10kHz 44.5 46.5 48.5
CTLGR3=0, CTLGR2=1, CTLGR1=1,
CTLGR0=0, f=10kHz 47.0 49.0 51.0
CTLGR3=0, CTLGR2=1, CTLGR1=1,
CTLGR0=1, f=10kHz 49.5 51.5 53.5
CTLGR3=1, CTLGR2=0, CTLGR1=0,
CTLGR0=0, f=10kHz 52.0 54.0 56.0
CTLGR3=1, CTLGR2=0, CTLGR1=0,
CTLGR0=1, f=10kHz 54.5 56.5 58.5
CTLGR3=1, CTLGR2=0, CTLGR1=1,
CTLGR0=0, f=10kHz 57.0 59.0 61.0
CTLGR3=1, CTLGR2=0, CTLGR1=1,
CTLGR0=1, f=10kHz 59.5 61.5 63.5
CTLGR3=1, CTLGR2=1, CTLGR1=0,
CTLGR0=0, f=10kHz 62.0 64.0 66.0
CTLGR3=1, CTLGR2=1, CTLGR1=0,
CTLGR0=1, f=10kHz 64.5 66.5 68.5
CTLGR3=1, CTLGR2=1, CTLGR1=1,
CTLGR0=0, f=10kHz 67.0 69.0 71.0
PB-CTL
input
amplifier
voltage
gain
CTL (+)
CTLGR3=1, CTLGR2=1, CTLGR1=1,
CTLGR0=1, f=10kHz 69.5 71.5 73.5
dB
V+TH AC coupling,
C=0.1µF Typ (non pol) 250
PB-CTL
Schmidt
input V−TH
CTLSMT (i)
AC coupling,
C=0.1µF Typ (non pol) −
250
mVp
Analog
switch ON
resistance
REB 150 Ω
CTL (+) 8
REC-CTL
output
current
ICTL CTL (−)Series resistance = 0 Ω8mA
REC-CTL
inter-pin
resistance
RCTL 10 kΩ
CTL
reference
output
voltage
CTLREF 1/2
SVcc V
Rev. 2.0, 11/ 00, page 837 of 1037
Refere nce Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
CFG pin bias
voltage CFG 1/2
SVCC
V
CFG input level CFG AC coupling,
C=1µF Typ, f=1kHz 1.0
Vpp
CFG input
impedance CFG 10 kΩ
V+THCF Rise thre sh old le ve l 2.25
CFG input
threshold voltage V−THCF
CFG
Fall threshold level 2.75
V
V+THDF Rising edge
Schmidt level 1.95
DFG Schmidt input
V−THDF
DFG
Falling edge
Schmidt level 1.85
V
V+THDP Rising edge
Schmidt level 3.55
DPG Schmidt input
V−THDP
DPG
Falling edge
Schmidt level 3.45
V
VOH −IOH=0.1mA 4.0
VOM No load, Hiz=1 2.5
3-level output
voltage
VOL
Vpulse
IOL=0.1mA 1.0
V
3-level output pin
divided voltage
resistance
Vpulse 15 kΩ
CFG Duty CFG AC coupling,
C=1µF Typ, f=1kHz 48 52 %
Rev. 2.0, 11/ 00, page 838 of 1037
Table 29.11 Servo Section Electrical Characteristics of HD64F2194, HD64F2194C
(Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0 .0 V, Ta = 25 °C unless otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
Digital input high
voltage VIH 0.8
Vcc Vcc+
0.3
Digital input low
voltage VIL
COMP,
EXCTL,
EXCAP,
EXTTRG −0.3 0.2
Vcc
V
Digital output high
voltage VOH −IOH=1mA Vcc
–1.0
Digital output low
voltage VOL
H.AmpSW,
C.Rotary,
VIDEOFF,
AUDIOFF,
DRMPWM,
CAPPWM,
SV1, SV2
IOL=1.6mA 0.6
V
Current dissipation ICCSV SVcc At no load 510mA
Rev. 2.0, 11/ 00, page 839 of 1037
29.2.7 FLASH Memory Characteristics
Table 29.12 shows the flash memory characteristics.
Table 29.12 Flash Memory Characteristics (Preliminary)
Conditions: Vcc = 5.0 V ± 10%, AVcc = 5. 0 V ± 10%, Vss = AVss = 0 V, T a = 0 t o + 75 °C
(operating temperature range at programming/erasing)
Item Symbol Test
conditions Min Typ Max Unit
Programming time*1*2*4tP10 200 ms/
32 bytes
Erasing time*1*3*5tE100 1200 ms/
block
No. of reprogramming NWEC 100 Times
Wait time afte r SWE-b it setting*1x10
µ
s
Wait time a fte r PSU-bit setting*1y50
µ
s
Wait time afte r P-b it setting*1*4z 150 200 µs
Wait time afte r P-b it clearing *1α10 µ
s
Wait time afte r PSU-bit clearing*1β10 µ
s
Wait tim e after PV-bit setting*1γ4 µ
s
Wait time afte r d u mmy write*1ε2 µ
s
Wait tim e after PV-bit clearing*1η4 µ
s
At
programming
Maximum No. of programmings*1*4*5N When z
= 200 µs1000 Times
Wait time afte r SWE-b it setting*1x10
µ
s
Wait time a fte r ESU-bit setting*1y 200 µ
s
Wait time afte r E-b it setting*1*6z5
10 ms
Wait time afte r E-b it clearing *1α10 µ
s
Wait time afte r ESU-bit clearing*1β10 µ
s
Wait tim e after EV-bit setting*1γ20 µ
s
Wait time afte r d u mmy write*1ε2 µ
s
Wait tim e after EV-bit clearing*1η5 µ
s
At erasing
Maximum No. of erasings*1*6N 120 240 Times
Notes: 1. Perform each time set ting according to t he pr ogr am m ing/ er asing algorithm .
2. Programm ing t ime per 32 byt es ( total tim e of set ting P-bit of t he flash memor y control
register. Program m ing verif y t ime is not included).
Rev. 2.0, 11/ 00, page 840 of 1037
3. Time to erase 1 block (total tim e of set ting E-bit of t he flash memor y control regist er .
Erasing verify time is not included).
4. Maximum pr ogr am m ing t ime ( tP (max.)) = Wait time after P-bit setting (z) × Maximum
No. of pr ogr am m ing ( N)
5. No. of tim es when wait time after P- bit set ting (z) = 200 µs. Set maximum No. of
program m ing shall be set less than maximum pr ogr am m ing tim e (tP (max.)) according
to t he act ual setting (z).
6. Relationship between wait t ime after E- bit setting (z) and maximum No. of er asing ( N)
for maximum erasing time (tE (ma x .) ) is as follo ws :
tE (max.) = Wait time after E-bit setting × Maximum No. of er asing ( N)
Set the ( z) and ( N) values so that they sat isfy t he above equation.
(Ex.) When z = 5 [ms] , N = 240 t imes
(Ex.) When z = 10 [ms] , N = 120 t imes
29.2.8 Usage Note
The F-ZTAT version and the Mask ROM version satisfy the electrical characteristics indicated
in this manual, but the actual power value, operating margin, and noise margin may differ from
those in this manual, due to the difference of production process, on-chip ROM, layout pattern,
etc.
When executing the system examination using the F-ZTAT version, be sure to execute the same
system examination using the Mask ROM version when changing to the Mask ROM version.
Rev. 2.0, 11/ 00, page 841 of 1037
29.3 Elect rical Characteristics of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A
29.3.1 DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A
Table 29.13 DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes
MD0 Vcc=2.5 to 5.5V 0.9 Vcc Vcc+0.3
0.8 Vcc Vcc+0.3
5(6
,
10,
,
,&
,
,54
to
,54
Vcc=2.5 to 5.5V 0.9 Vcc Vcc+0.3
SCK1, SCK2, SI1, SI2,
&6
, FTIA, FTIB, FTIC,
FTID, TRIG, TMBI,
$'75*
0.8 Vcc Vcc+0.3
Vcc–0.5 Vcc+0.3OSC1, X1
Vcc=2.5 to 5.5V Vcc–0.3 Vcc+0.3
0.7 Vcc Vcc+0.3P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PS0 to PS4
Vcc=2.5 to 5.5V 0.8 Vcc Vcc+0.3
Input high
voltage VIH
Csyn c 0.7 Vcc Vcc+0.3
V
Rev. 2.0, 11/ 00, page 842 of 1037
Values
Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes
MD0 Vcc=2.5 to 5.5V −0.3 0.1 Vcc
−0.3 0.2 Vcc
5(6
,
10,
,
,&
,
,54
to
,54
Vcc=2.5 to 5.5V −0.3 0.1 Vcc
SCK1, SCK2, SI1, SI2,
&6
, FTIA, FTIB, FTIC,
FTID, TRIG, TMBI,
$'75*
−0.3 0.2 Vcc
−0.3 0.5
OSC1, X1
Vcc=2.5 to 5.5V −0.3 0.3
−0.3 0.3 Vcc
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PS0 to PS4
Vcc=2.5 to 5.5V −0.3 0.2 Vcc
Input low
voltage VIL
Csync −0.3 0.2 Vcc
V
−IOH=1.0mA Vcc–1.0 V
−IOH=0.5mA Vcc–
0.5 V Refer-
ence
value
Output
high
voltage
VOH SO1, SO2, SCK1,
SCK2, PWM1, PWM2,
PWM3, PWM 4 ,
PWM14, STRB, BUZZ,
TMO, TMOW, FTOA,
FTOB, PPG70 to
PPG77,
RP0 to RP7,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PS0 to PS4
−IOH=0.1mA
Vcc=2.5 to 5.5V Vcc–0.5 V
Rev. 2.0, 11/ 00, page 843 of 1037
Values
Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes
IOL=1.6mA
0.6 VSO1, SO2, SCK1,
SCK2, PWM1, PWM2,
PWM3, PWM 4 ,
PWM14, STRB, BUZZ,
TMO, TMOW, FTOA,
FTOB, PPG70 to
PPG77,
RP0 to RP7,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
PS0 to PS4
IOL=0.4mA
Vcc=2.5 to 5.5V
0.4 V
IOL=20mA
1.5 V
IOL=1.6mA
0.6 V
Output
low
voltage
VOL
P80 to P8 7
IOL=0.4mA
Vcc=2.5 to 5.5V
0.4 V
MD0, OSC1
5(6
,
10,
,
,54
to
,54
,
,&
Vin=0.5 to
Vcc–0.5V
1.0
SCK1, SCK2, SI1, SI2,
&6
, FTIA, FTIB, FTIC,
FTID, TRIG, TMBI,
$'75*
Vin=0.5 to
Vcc–0.5V
1.0
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P8 7
PS0 to PS4
Vin=0.5 to
Vcc–0.5V
1.0
Input
/output
leakage
current
IIL
P00 to P07,
AN8 to ANB Vin=0.5 to
AVcc–0.5V
1.0
µA
Rev. 2.0, 11/ 00, page 844 of 1037
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
Pull-up
MOS
current
−Ip P10 to P17,
P20 to P27,
P30 to P3 7
Vcc=5.0V,
Vin=0V 50 300 µA Note 1
Input
capacity Cin All input pins except
power supply, P23, P24
and analog system pins
fin=1 MHz,
Vin=0V,
Ta=25°C
15 pF
P23, P24 fin=1 MHz,
Vin=0V,
Ta=25°C
20 pF
Vcc=5V,
fOSC=10 MHz
High-speed
mode
50 70 mA Note 2
Active
mode
current
dissipa-
tion (CPU
operating)
IOPE Vcc
Vcc=5V,
fOSC=10 MHz
Medium-speed
mode (1/64)
35 mA Refer-
ence
value
Active
mode
current
dissipa-
tion (reset)
IRES Vcc Vcc=5V,
fOSC=10 MHz 25 45 mA Note 2
Sleep
mode
current
dissipa-
tion
ISLEEP Vcc Vcc=5V,
fOSC=10 MHz
High-speed
mode
20 30 mA Note 2
Vcc=2.5V,
With 32kHz
crystal
oscillator
(φ sub=φw/2)
40 100 Note 2
Subactive
mode
current
dissipa-
tion
ISUB Vcc
Vcc=2.5V,
With 32kHz
crystal
oscillator
(φ sub=φw/8)
20
µA
Refer-
ence
value,
Note 2
Vcc=2.5V,
With 32kHz
crystal
oscillator
(φ sub=φw/2)
15 30 Note 2
Subsleep
mode
current
dissipa-
tion
ISUBSLP Vcc
Vcc=2.5V,
With 32kHz
crystal
oscillator
(φ sub=φw/8)
10
µA
Refer-
ence
value,
Note 2
Rev. 2.0, 11/ 00, page 845 of 1037
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
Vcc=2.5V,
With 32kHz
crystal
oscillator
510 µA Note 2
Watch
mode
current
dissipa-
tion
IWATCH Vcc
Vcc=5.0V,
With 32kHz
crystal
oscillator
10 µ
A Reference
value
Note 2
Standby
mode
current
dissipa-
tion
ISTBY Vcc X1=Vcc,
Without 32kHz
crystal
oscillator
5µA Note 2
RAM data
retaining
voltage in
standby
mode
VSTBY Vcc 2.0 V
Notes: Do not open the AVcc and AVss pin even when t he A/D conver t er is not in use.
1. Current value when the r elevant bit of the pull-up MO S select r egister ( PUR1 to PUR3)
is set to 1.
2. The current on t he pull-up M O S or t he out put buffer excluded.
Table 29.14 Pin Status at Current Dissipation Measurement
Mode RES Pin Internal State Pin Oscillator Pin
Active mode
High-speed, medium-
speed
Vcc Operating Vcc
Sleep mode
High-speed, medium-
speed
Vcc CPU and servo
circuits stopped Vcc
Reset Vss Reset Vcc
Standby mode Vcc All stopped Vcc
Main clock:
Cry s tal os c illa tor
Sub clock:
X1 pin = Vcc
Subactive mode Vcc CPU and timer A
operating Vcc
Subsleep mode Vcc Timer A operat ing Vcc
Watch m ode Vcc Timer A oper at ing Vcc
Main clock:
Cry s tal os c illa tor
Sub clock:
Cry s tal os c illa tor
Rev. 2.0, 11/ 00, page 846 of 1037
Table 29.15 Bus Drive Characteristics of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0. 0 V, T a = –20 t o + 75°C unl ess otherwise
specified.) Applicable pin: SCL, SDA
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
VT−0.2 Vcc V
VT+
0.7 Vcc V
Schmidt
trigger
input
voltage VT+
−VT−
SCL, SDA
0.05 Vcc V
Input High
voltage VIH SCL, SDA 0.7 Vcc Vcc+0.5 V
Input Low
voltage VIL SCL, SDA −0.5 0.2 Vcc V
IOL=8mA
0.5Output
Low
voltage
VOL SCL, SDA
IOL=3mA
0.4
V
SCL and
SDA
output fall
time
tof SCL, SDA 20+
0.1Cb 250 ns
Rev. 2.0, 11/ 00, page 847 of 1037
29.3.2 Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A
The specifications for the digital pins are shown below.
Table 29.16 Allowable Output Currents of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = 2.5 to 5.5 V, Vss = 0.0 V, T a = –20 t o + 75°C)
Item Symbol Value Unit Notes
Allowable input cur r ent ( to chip) IO2mA1
Allowable input cur r ent ( to chip) IO22 mA 2
Allowable input cur r ent ( to chip) IO10 mA 3
Allowable output curr ent ( f rom chip) −IO2mA4
Total allowable input cur r ent ( to chip) ΣIO80 mA 5
Total allowable output current (f r om
chip) −ΣIO50 mA 6
Notes: 1. The allowable input cur r ent is t he m axim um value of t he current f lowing from each I/O
pin to VSS (except for por t 8, SCL and SDA).
2. The allowable input cur r ent is t he m aximum value of t he cur r ent flowing from each I /O
pin to VSS. This applies to port 8.
3. The allowable input cur r ent is t he m aximum value of t he cur r ent flowing from each I /O
pin to VSS. This applies to SCL and SDA.
4. The allowable output curr ent is t he m aximum value of t he cur r ent flowing from VCC to
each I/ O pin.
5. The total allowable input cur rent is t he sum of t he cur r ents flowing from all I/ O pins to
VSS simultaneously.
6. The total allowable output curr ent is t he sum of t he cur r ent s f lowing fr om VCC to all I/O
pins.
Rev. 2.0, 11/ 00, page 848 of 1037
29.3.3 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A
Table 29.17 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Notes
Clock oscillation
frequency fOSC OSC1 , OSC2 8 10 MHz
Cl ock cycle ti me tcyc OSC1 , OSC2 100 125 ns Figure
29.11
Subclock
oscillation
frequency
fXX1, X2 Vcc=2.5 to 5.5V 32.768 kHz
Subcl ock cycle
time tsubcyc X1, X2 Vcc=2.5 to 5.5V 30.518 µ
s Figure
29.12
OSC1, OSC2 Crystal oscillator 10 msOscillation
stabilization time trc
X1, X2 32kHz crystal
oscillator
Vcc=2.5 to 5.5V
2s
External clock high
width tCPH OSC1 40
ns
Ext ernal clock low
width tCPL OSC1 40
ns
Ext ernal clock rise
time tCPr OSC1 10 ns
Ext ernal clock fal l
time tCPf OSC1 10 ns
Figure
29.11
External clock
stabilization delay
time
tDEXT OSC1 500 µ
s Figure
29.13
Subclock input low
level pulse width tEXCLL X1 Vcc=2.5 to 5.5V 15.26 µ
s
Subclock input high
level pulse width tEXCLH X1 Vcc=2.5 to 5.5V 15.26 µ
s
Figure
29.12
Rev. 2.0, 11/ 00, page 849 of 1037
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Figure
Subclock input rise
time tEXCLr X1 Vcc=2.5 to 5.5V 10 ns
Subclock input fall
time tEXCLf X1 Vcc=2.5 to 5.5V 10 ns
Figure
29.12
5(6
pin low level
width tREL
5(6
Vcc=2.5V to
5.5V 20
tcyc Figure
29.14
Input pin high level
width tIH
,54
to
,54
,
10,
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID, TRIG
Vcc=2.5V to
5.5V 2
tcyc
tsubcyc
Input pin low level
width tIL
,54
to
,54
,
10,
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID, TRIG
Vcc=2.5V to
5.5V 2
tcyc
tsubcyc
Figure
29.15
t
cyc
t
CPH
V
IL
V
IH
OSC1
t
CPL
t
CPf
t
CPr
Figure 29. 11 System Clock Timi ng
Rev. 2.0, 11/ 00, page 850 of 1037
t
EXCLf
t
subcyc
t
EXCLH
t
EXCLL
t
EXCLr
V
IL
V
IH
X1 Vcc 0.5
Fi g ur e 2 9 . 1 2 Subc l o c k Input T i m i ng
Vcc
OSC1
t
DEXT
*
RES
(Internal)
4.0V
The t
DEXT
includes the RES pin Low level width 20 t
cyc
.
Note: *
Figure 29.13 External Clock Stabilization Delay Timing
Rev. 2.0, 11/ 00, page 851 of 1037
RES V
IL
t
REL
Fi g ur e 2 9 . 1 4 Re se t Input Timi ng
t
IL
t
IH
V
IH
IRQ0 to IRQ5,
NMI, IC,
ADTRG, TMBI,
FTIA, FTIB,
FTIC, FTID,
TRIG
V
IL
Fi g ur e 2 9 . 1 5 Input T i m i ng
Rev. 2.0, 11/ 00, page 852 of 1037
29.3.4 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A
Table 29.18 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191,
HD6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Figure
Asynchroniza-
tion 4
SCK1
Clock
synchronization 6
Input clock cycle tscyc
SCK2 2
tcyc
Input clock pulse
width tSCKW SCK1,
SCK2 0.4 0.6 tscyc
SCK1 1.5 tcyc
Input clock rise time tSCKr
SCK2 60 ns
SCK1 1.5 tcyc
Input clock fall time tSCKf
SCK2 60 ns
Figure
29.16
Transmit data delay
time (clock sync) tTXD SO1 100 ns
Receive data setup
time (clock sync) tRXS SI1 100
ns
Receive data hold
time (clock sync) tRXH SI1 100
ns
Figure
29.17
Transmit data output
delay time tTXD SO2 200 ns
Receive data setup
time (clock sync) tRXS SI2 180
ns
Receive data hold
time (clock sync) tRXH SI2 180
ns
Figure
29.17
&6
setup time tCSS
&6
1
tscyc
&6
hold time tCSH
&6
1
tscyc
Figure
29.18
Rev. 2.0, 11/ 00, page 853 of 1037
tSCKf
tSCKr
VIL or VOL
VIH or VOH
SCK1
tSCKW tscyc
Figure 29. 16 SCK1 Clock Timi ng
V
IL
V
IH
t
TXD
SCK1,
SCK2
SO1,
SO2
SI1,
SI2
t
RXS
t
RXH
Fi g ur e 2 9 . 1 7 SCI I/ O T i m i ng / Cloc k Sy nc hroni z a t i o n M o de
V
IH
V
IH
V
IL
CS
SCK2
t
CSH
t
CSS
Fi g ur e 2 9 . 1 8 SCI2 Chip Select Timing
Rev. 2.0, 11/ 00, page 854 of 1037
LSI output pin
Timing reference level
V
OH
: 2.0 V
V
OL
: 0.8 V
30 pF 12k
2.4k
Vcc
Figure 29. 19 O utput Load Conditi ons
Rev. 2.0, 11/ 00, page 855 of 1037
Table 29.19 I2C Bus Interfac e Timi ng of HD6432194, H D6432193, H D6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Test
Conditions Min Typ Max Unit Figure
SCL input cycle time tSCL 12 tcyc
SCL input high pulse width tSCLH 3 tcyc
SCL input low pulse width tSCLL 5 tcyc
SCL, SDA input rise time tsr
7.5*tcyc
SCL, SDA input fall time tsf
300 ns
SCL, SDA input spike pulse
removal time tsp
1t
cyc
SDA input bus free time tBUF 5 tcyc
Start condition input hold time tSTAH 3 tcyc
Re-transmit start condition
input setup time tSTAS 3 tcyc
Stop condition input setup time tSTOS 3 tcyc
Data input setup time tSDAS 0.5 tcyc
Data input hold time tSDAH 0 ns
SCL, SDA capacity load Cb
400 pF
Figure
29.10
Note: *Can also be set to 17. 5 tcyc depending on the selection of clock to be used by t he I2C
module.
Rev. 2.0, 11/ 00, page 856 of 1037
t
STAH
t
Sr
t
SDAH
t
SCL
t
SCLL
t
SCLH
t
Sf
t
STAS
t
SP
t
STOS
t
SDAS
V
IL
V
IH
SDA
SCL
P*S*Sr*P*
S, P and Sr denote the following:
S : Start conditions
P : Stop conditions
Sr: Re-transmit start conditions
Note: *
t
BUF
Figure 29. 20 I2C Bus Int e rface I/ O T i m i ng
Rev. 2.0, 11/ 00, page 857 of 1037
29.3.5 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A
Table 29.20 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0. 0 V, Ta = –20 t o + 75 °C unl ess
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
Analog power
supply voltage AVcc AVcc Vcc–
0.3 Vcc Vcc+
0.3 V
Analog input
voltage AVIN AN0 to AN7,
AN8 to ANB AVss AVcc V
AICC AVcc AVcc=5.0V 2.0 mAAnalog power
supply current AISTOP AVcc Vcc=2.5 to 5.5V
At reset and in
power-down mode
10 µA
Analog input
capacitance CAIN AN0 to AN7,
AN8 to ANB 30 pF
Allowable signal
source impedance RAIN AN0 to AN7,
AN8 to ANB 10 kΩ
Resolution 10 Bit
Absol ute accu racy A Vcc=5 .0V ±
4LSB
Conversion time 13.4 26.6 µs
Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc
= Vcc and AVss = Vss.
Rev. 2.0, 11/ 00, page 858 of 1037
29.3.6 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192,
HD6432191, HD6432194C, HD6432194B, and HD6432194A
Table 29.21 Servo Section Electrical Characteristics of HD6432194, HD6432193,
HD6432192, HD6432191, H D6432194C, HD6432194B, and HD6432194A
(reference values)
(Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0 .0 V, Ta = 25 °C unless otherwise specified.)
Reference Values
Item Symbol Applicable
Pins Test Conditions Min Ty p Max Unit Note
CTLGR3=0, CTLGR2=0, CTLGR1=0,
CTLGR0=0, f=10kHz 32.0 34.0 36.0
CTLGR3=0, CTLGR2=0, CTLGR1=0,
CTLGR0=1, f=10kHz 34.5 36.5 38.5
CTLGR3=0, CTLGR2=0, CTLGR1=1,
CTLGR0=0, f=10kHz 37.0 39.0 41.0
CTLGR3=0, CTLGR2=0, CTLGR1=1,
CTLGR0=1, f=10kHz 39.5 41.5 43.5
CTLGR3=0, CTLGR2=1, CTLGR1=0,
CTLGR0=0, f=10kHz 42.0 44.0 46.0
CTLGR3=0, CTLGR2=1, CTLGR1=0,
CTLGR0=1, f=10kHz 44.5 46.5 48.5
CTLGR3=0, CTLGR2=1, CTLGR1=1,
CTLGR0=0, f=10kHz 47.0 49.0 51.0
CTLGR3=0, CTLGR2=1, CTLGR1=1,
CTLGR0=1, f=10kHz 49.5 51.5 53.5
CTLGR3=1, CTLGR2=0, CTLGR1=0,
CTLGR0=0, f=10kHz 52.0 54.0 56.0
CTLGR3=1, CTLGR2=0, CTLGR1=0,
CTLGR0=1, f=10kHz 54.5 56.5 58.5
CTLGR3=1, CTLGR2=0, CTLGR1=1,
CTLGR0=0, f=10kHz 57.0 59.0 61.0
CTLGR3=1, CTLGR2=0, CTLGR1=1,
CTLGR0=1, f=10kHz 59.5 61.5 63.5
CTLGR3=1, CTLGR2=1, CTLGR1=0,
CTLGR0=0, f=10kHz 62.0 64.0 66.0
CTLGR3=1, CTLGR2=1, CTLGR1=0,
CTLGR0=1, f=10kHz 64.5 66.5 68.5
CTLGR3=1, CTLGR2=1, CTLGR1=1,
CTLGR0=0, f=10kHz 67.0 69.0 71.0
PB-CTL
input
amplifier
voltage
gain
CTL (+)
CTLGR3=1, CTLGR2=1, CTLGR1=1,
CTLGR0=1, f=10kHz 69.5 71.5 73.5
dB
V+TH AC coupling,
C=0.1µF Typ (non pol) 250
PB-CTL
Schmidt
input V−TH
CTLSMT (i)
AC coupling,
C=0.1µF Typ (non pol) −
250
mVp
Analog
switch ON
resistance
REB 150 Ω
CTL (+) 8
REC-CTL
output
current
ICTL CTL (−)Series resistance = 0 Ω8mA
REC-CTL
inter-pin
resistance
RCTL 10 kΩ
Rev. 2.0, 11/ 00, page 859 of 1037
Refere nce Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
CTL reference
output voltage CTLREF 1/2
SVCC
V
CFG pin bias
voltage CFG 1/2
SVCC
V
CFG input level CFG AC coupling,
C=1µF Typ, f=1kHz 1.0
Vpp
CFG input
impedance CFG 10 kΩ
V+THCF Rise thre sh old le ve l 2.25
CFG input
threshold value V−THCF
CFG
Fall threshold level 2.75
V
V+THDF Rising edge
Schmidt level 1.95
DFG Schmidt input
V−THDF
DFG
Falling edge
Schmidt level 1.85
V
V+THDP Rising edge
Schmidt level 3.55
DPG Schmidt input
V−THDP
DPG
Falling edge
Schmidt level 3.45
V
VOH −IOH=0.1mA 4.0
VOM No load, Hiz=1 2.5
3-level output
voltage
VOL
Vpulse
IOL=0.1mA 1.0
V
3-level output pin
divided voltage
resistance
Vpulse 15 kΩ
CFG Duty CFG AC coupling,
C=1µF Typ, f=1kHz 48 52 %
Rev. 2.0, 11/ 00, page 860 of 1037
Table 29.22 Servo Section Electrical Characteristics of HD6432194, HD6432193,
HD6432192, HD6432191, H D6432194C, HD6432194B, and HD6432194A
(Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0 .0 V, Ta = 25 °C unless otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
Digital input high
voltage VIH 0.8
Vcc Vcc+
0.3
Digital input low
voltage VIL
COMP,
EXCTL,
EXCAP,
EXTTRG −0.3 0.2
Vcc
V
Digital output high
voltage VOH −IOH=1mA Vcc–
1.0
Digital output low
voltage VOL
H.AmpSW,
C.Rotary,
VIDEOFF,
AUDIOFF,
DRMPWM,
CAPPWM,
SV1, SV2
IOL=1.6mA 0.6
V
Current dissipation ICCSV SVcc At no load 510mA
Rev. 2.0, 11/ 00, page 861 of 1037
Appendix A Instruction Set
A.1 Instructions
[Operation Notation]
Rd General r egister (destination) *1
Rs Gener al r egister ( s our ce) *1
Rn General r egister *1
ERn G ener al regist er ( 32- bit r egister)
MAC Multiplication-Addition register ( 32- bit r egist er ) *2
(EAd) Destination operand
(EAs) Source oper and
EXR Ext end r egist er
CCR Condition code register
N N (negat ive f lag) in CCR
Z Z (zer o) flag in CCR
V V (o v erf lo w) f lag in CCR
C C (carry) flag in CCR
PC Pr ogr am count er
SP Stack pointer
#IMM I m m ediat e dat a
disp Displacement
+ Addition
−Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Exclusive logical OR
→Move from the left to the right
∼Logical complement
( ) <> Content s of oper and
:8/ : 16/ : 24/ : 32 8/16/ 24/ 32 bit length
Rev. 2.0, 11/ 00, page 862 of 1037
Notes: 1. General regist er is 8- bit ( R0H to R7H, R0L to R7L) , 16- bit ( R0 to R7) or 32- bit (ER0 to
ER7).
2. MAC register cannot be used in t his LSI.
[Condition Code Notation]
Symbol Description
Modified according to t he instr uct ion result
*Not fixed (value not guar ant eed)
0 Always cleared to 0
1 Always set to 1
−Not aff ect ed by t he instr uct ion execut ion result
Rev. 2.0, 11/ 00, page 863 of 1037
Tabl e A.1 List of Inst r uc t i o n Se t
(1) Data Transfer Instruction
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
MOV.L @aa:32,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd)
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
LDM @SP+,(ERm-ERn)
STM (ERm-ERn),@-SP
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W
L
W
L
L
L
2
4
6
2
2
2
2
2
2
2
4
4
4
8
4
8
4
8
4
8
6
10
6
10
2
2
2
2
4
4
2
4
6
2
4
6
4
6
4
6
6
8
6
8
MOV
POP
PUSH
LDM
STM
MOVFPE
MOVTPE
Mnemonic
Size
Addressing Mode and Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
#xx:8 Rd8
Rs8 Rd8
@ERs Rd8
@(d:16,ERs) Rd8
@(d:32,ERs) Rd8
@ERs Rd8,ERs32+1 ERs32
@aa:8 Rd8
@aa:16 Rd8
@aa:32 Rd8
Rs8 @ERd
Rs8 @(d:16,ERd)
Rs8 @(d:32,ERd)
ERd32-1 ERd32,Rs8 @ERd
Rs8 @aa:8
Rs8 @aa:16
Rs8 @aa:32
#xx:16 Rd16
Rs16 Rd16
@ERs Rd16
@(d:16,ERs) Rd16
@(d:32,ERs) Rd16
@ERs Rd16,ERs32+2 ERs32
@aa:16 Rd16
@aa:32 Rd16
Rs16 @ERd
Rs16 @(d:16,ERd)
Rs16 @(d:32,ERd)
ERd32-2 ERd32,Rs16 @ERd
Rs16 @aa:16
Rs16 @aa:32
#xx:32 ERd32
ERs32 ERd32
@ERs ERd32
@(d:16,ERs) ERd32
@(d:32,ERs) ERd32
@ERs ERd32,ERs32+4 ERs32
@aa:16 ERd32
@aa:32 ERd32
ERs32 @ERd
ERs32 @(d:16,ERd)
ERs32 @(d:32,ERd)
ERd32-4 ERd32,ERs32 @ERd
ERs32 @aa:16
ERs32 @aa:32
@SP Rn16,SP+2 SP
@SP ERn32,SP+4 SP
SP-2 SP,Rn16 @SP
SP-4 SP,ERn32 @SP
(@SP ERn32,SP+4 SP)
Repeat for the number of returns
(SP-4 SP,ERn32 @SP)
Repeat for the number of returns
Operation Condition
Code
No of
Execution
States *
1
IHNZVC
Advanced Mode
2
4
2
4
4
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
1
1
2
3
5
3
2
3
4
2
3
5
3
2
3
4
2
1
2
3
5
3
3
4
2
3
5
3
3
4
3
1
4
5
7
5
5
6
4
5
7
5
5
6
3
5
3
5
7/9/11 [1]
7/9/11 [1]
[2]
[2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cannot be used in this LSI
—
—
—
—
—
Rev. 2.0, 11/ 00, page 864 of 1037
(2) Arithmetic Instructions
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
DAA Rd
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
DAS Rd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
MULXS.B Rs,Rd
MULXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
TAS @ERd *
3
MAC @ERn+,@ERm+
CLRMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
STMAC MACH,ERd
STMAC MACL,ERd
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
B
W
B
W
B
W
B
B
W
W
L
L
B
W
L
W
L
W
L
B
2
4
6
2
4
6
2
2
4
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
2
2
4
4
2
2
2
2
2
2
2
2
2
2
ADD
ADDX
ADDS
INC
DAA
SUB
SUBX
SUBS
DEC
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
NEG
EXTU
EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
Mnemonic Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Rd8+#xx:8 Rd8
Rd8+Rs8 Rd8
Rd16+#xx:16 Rd16
Rd16+Rs16 Rd16
ERd32+#xx:32 ERd32
ERd32+ERs32 ERd32
Rd8+#xx:8+C Rd8
Rd8+Rs8+C Rd8
ERd32+1 ERd32
ERd32+2 ERd32
ERd32+4 ERd32
Rd8+1 Rd8
Rd16+1 Rd16
Rd16+2 Rd16
ERd32+1 ERd32
ERd32+2 ERd32
Rd8 10 Decimal adjust Rd8
Rd8-Rs8 Rd8
Rd16-#xx:16 Rd16
Rd16-Rs16 Rd16
ERd32-#xx:32 ERd32
ERd32-ERs32 ERd32
Rd8-#xx:8-C Rd8
Rd8-Rs8-C Rd8
ERd32-1 ERd32
ERd32-2 ERd32
ERd32-4 ERd32
Rd8-1 Rd8
Rd16-1 Rd16
Rd16-2 Rd16
ERd32-1 ERd32
ERd32-2 ERd32
Rd8 10 Decimal adjust Rd8
Rd8 Rs8 Rd16(Multiplication w/o sign)
Rd16 Rs16 ERd32
(Multiplication w/o sign)
Rd8 Rs8 Rd16(Multiplication w/o sign)
Rd16 Rs16 ERd32
(Multiplication w/o sign)
Rd16 Rs8 Rd16 (RdH: Rmainder, RdL:
Quatient)(Division w/o sign)
ERd32 Rs16 ERd32 (Ed:Remainder,
Rd: Quatient)(Division with sign)
Rd16 Rs8 Rd16(RdH: Rmainder, RdL:
Quatient)(Division w/o sign)
ERd32 Rs16 ERd32 (Ed:Remainder,
Rd: Quatient)(Division with sign)
Rd8-#xx:8
Rd8-Rs8
Rd16-#xx:16
Rd16-Rs16
ERd32-#xx:32
ERd32-ERs32
0-Rd8 Rd8
0-Rd16 Rd16
0-ERd32 ERd32
0 (<Bits 15 to 8> of Rd16)
0(<Bits 31 to 16> of ERd32)
(<Bit7> of Rd16)
(<Bits 15 to 8> of Rd16)
(<Bit15> of ERd32)
(<Bits31 to 16> of ERd32)
@ERd-0 CCR set, (1)
(<Bit7> of @ERd)
Operation Condition
Code
IHNZVC Advanced Mode
4
—
—
—
*
1
1
2
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
3
1
1
1
1
1
1
1
1
1
1
1
1
12
20
13
21
12
20
13
21
1
1
2
1
3
1
1
1
1
1
1
1
1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
*
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
*
—
—
—
—
—
—
—
—
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
—
—
—
—
—
[6]
[6]
[8]
[8]
0
0
[5]
[5]
—
—
—
[5]
[5]
—
—
—
—
—
[7]
[7]
[7]
[7]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
*
—
—
—
—
—
—
—
—
0
0
0
0
0
—
—
—
—
—
Cannot be used in this LSI [2]
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Rev. 2.0, 11/ 00, page 865 of 1037
(3) Logic Opera t ions Instruct i ons
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
NOT.B Rd
NOT.W Rd
NOT.L ERd
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
W
L
2
4
6
2
4
6
2
4
6
2
2
4
2
2
4
2
2
4
2
2
2
AND
OR
XOR
NOT
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Rd8 #xx:8 Rd8
Rd8 Rs8 Rd8
Rd16 #xx:16 Rd16
Rd16 Rs16 Rd16
ERd32 #xx:32 ERd32
ERd32 ERs32 ERd32
Rd8 #xx:8 Rd8
Rd8 Rs8 Rd8
Rd16 #xx:16 Rd16
Rd16 Rs16 Rd16
ERd32 #xx:32 ERd32
ERd32 ERs32 ERd32
Rd8 #xx:8 Rd8
Rd8 Rs8 Rd8
Rd16 #xx:16 Rd16
Rd16 Rs16 Rd16
ERd32 #xx:32 ERd32
ERd32 ERs32 ERd32
~Rd8 Rd8
~Rd16 Rd16
~ERd32 ERd32
Operation Condition
Code
IHNZVC
Advanced Mode
1
1
2
1
3
2
1
1
2
1
3
2
1
1
2
1
3
2
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Rev. 2.0, 11/ 00, page 866 of 1037
(4) Shift Instructi ons
SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
ROTXL.B Rd
ROTXL.B #2,Rd
ROTXL.W Rd
ROTXL.W #2,Rd
ROTXL.L ERd
ROTXL.L #2,ERd
ROTXR.B Rd
ROTXR.B #2,Rd
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
ROTXR.L #2,ERd
ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L ERd
ROTR.L #2,ERd
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SHAL
SHAR
SHLL
SHLR
ROTXL
ROTXR
ROTL
ROTR
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation Condition
Code
IHNZVC
Advanced Mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
C
0
MSB LSB
CMSB LSB
CMSB LSB
C
MSB LSB
C
MSB LSB
C
0
MSB LSB
C
0
MSB LSB
C
MSB LSB
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Rev. 2.0, 11/ 00, page 867 of 1037
(5) Bit Manipulation Instructions
BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
BSET
BCLR
BNOT
BTST
BLD
BILD
BST
BIST
BAND
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
(#xx:3 of Rd8) 1
(#xx:3 of @ERd) 1
(#xx:3 of @aa:8) 1
(#xx:3 of @aa:16) 1
(#xx:3 of @aa:32) 1
(Rn8 of Rd8) 1
(Rn8 of @ERd) 1
(Rn8 of @aa:8) 1
(Rn8 of @aa:16) 1
(Rn8 of @aa:32) 1
(#xx:3 of Rd8) 0
(#xx:3 of @ERd) 0
(#xx:3 of @aa:8) 0
(#xx:3 of @aa:16) 0
(#xx:3 of @aa:32) 0
(Rn8 of Rd8) 0
(Rn8 of @ERd) 0
(Rn8 of @aa:8) 0
(Rn8 of @aa:16) 0
(Rn8 of @aa:32) 0
(#xx:3 of Rd8) [~(#xx:3 of Rd8)]
(#xx:3 of @ERd) [~(#xx:3 of @ERd)]
(#xx:3 of @aa:8) [~(#xx:3 of @aa:8)]
(#xx:3 of @aa:16) [~(#xx:3 of @aa:16)]
(#xx:3 of @aa:32) [~(#xx:3 of @aa:32)]
(Rn8 of Rd8) [~(Rn8 of Rd8)]
(Rn8 of @ERd) [~(Rn8 of @ERd)]
(Rn8 of @aa:8) [~(Rn8 of @aa:8)]
(Rn8 of @aa:16) [~(Rn8 of @aa:16)]
(Rn8 of @aa:32) [~(Rn8 of @aa:32)]
~(#xx:3 of Rd8) Z
~(#xx:3 of @ERd) Z
~(#xx:3 of @aa:8) Z
~(#xx:3 of @aa:16) Z
~(#xx:3 of @aa:32) Z
~(Rn8 of Rd8) Z
~(Rn8 of @ERd) Z
~(Rn8 of @aa:8) Z
~(Rn8 of @aa:16) Z
~(Rn8 of @aa:32) Z
(#xx:3 of Rd8) C
(#xx:3 of @ERd) C
(#xx:3 of @aa:8) C
(#xx:3 of @aa:16) C
(#xx:3 of @aa:32) C
~(#xx:3 of Rd8) C
~(#xx:3 of @ERd) C
~(#xx:3 of @aa:8) C
~(#xx:3 of @aa:16) C
~(#xx:3 of @aa:32) C
C(#xx:3 of Rd8)
C (#xx:3 of @ERd)
C(#xx:3 of @aa:8)
C (#xx:3 of @aa:16)
C(#xx:3 of @aa:32)
~C (#xx:3 of Rd8)
~C (#xx:3 of @ERd)
~C (#xx:3 of @aa:8)
~C (#xx:3 of @aa:16)
~C (#xx:3 of @aa:32)
C(#xx:3 of Rd8) C
C(#xx:3 of @ERd) C
C (#xx:3 of @aa:8) C
C(#xx:3 of @aa:16) C
C (#xx:3 of @aa:32) C
Operation Condition
Code
IHNZVC
Advanced Mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
4
4
5
6
1
4
4
5
6
1
3
3
4
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Rev. 2.0, 11/ 00, page 868 of 1037
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
BIAND
BOR
BIOR
BXOR
BIXOR
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
C [~(#xx:3 of Rd8)] C
C [~(#xx:3 of @ERd)] C
C [~(#xx:3 of @aa:8)] C
C [~(#xx:3 of @aa:16)] C
C [~(#xx:3 of @aa:32)] C
C(#xx:3 of Rd8) C
C(#xx:3 of @ERd) C
C(#xx:3 of @aa:8) C
C(#xx:3 of @aa:16) C
C(#xx:3 of @aa:32) C
C [~(#xx:3 of Rd8)] C
C [~(#xx:3 of @ERd)] C
C [~(#xx:3 of @aa:8)] C
C [~(#xx:3 of @aa:16)] C
C [~(#xx:3 of @aa:32)] C
C (#xx:3 of Rd8) C
C (#xx:3 of @ERd) C
C (#xx:3 of @aa:8) C
C (#xx:3 of @aa:16) C
C (#xx:3 of @aa:32) C
C [~(#xx:3 of Rd8)] C
C [~(#xx:3 of @ERd)] C
C [~(#xx:3 of @aa:8)] C
C [~(#xx:3 of @aa:16)] C
C [~(#xx:3 of @aa:32)] C
Operation
IHNZVC
Advanced Mode
2
2
2
2
2
4
4
4
4
4
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Condition
Code
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Rev. 2.0, 11/ 00, page 869 of 1037
(6) Branch Instruct i ons
BRA d:8(BT d:8)
BRA d:16(BT d:16)
BRN d:8(BF d:8)
BRN d:16(BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8(BHS d:8)
BCC d:16(BHS d:16)
BCS d:8(BLO d:8)
BCS d:16(BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
Bcc
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation
I
Branch
Condition
HNZVC
Advanced Mode
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
Always
Never
CZ=0
CZ=1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
NV=0
NV=1
if condition is true then
PC PC+d
else next;
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Code
BGT d:8
BGT d:16
BLE d:8
BLE d:16
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
JMP
BSR
JSR
RTS
PC ERn
PC aa:24
PC @aa:8
PC @-SP,PC PC+d:8
PC @-SP,PC PC+d:16
PC @-SP,PC ERn
PC @-SP,PC aa:24
PC @-SP,PC @aa:8
PC @SP+
2
2
4
4
2
4
2
4
2
4
2
22
2
3
2
3
2
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Z(N V)=0
Z(N V)=1
5
4
5
4
5
6
5
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Rev. 2.0, 11/ 00, page 870 of 1037
(7) System Control Instructions
TRAPA #xx:2
RTE
SLEEP
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
STC CCR,Rd
STC EXR,Rd
STC CCR,@ERd
STC EXR,@ERd
STC CCR,@(d:16,ERd)
STC EXR,@(d:16,ERd)
STC CCR,@(d:32,ERd)
STC EXR,@(d:32,ERd)
STC CCR,@-ERd
STC EXR,@-ERd
STC CCR,@aa:16
STC EXR,@aa:16
STC CCR,@aa:32
STC EXR,@aa:32
ANDC #xx:8,CCR
ANDC #xx:8,EXR
ORC #xx:8,CCR
ORC #xx:8,EXR
XORC #xx:8,CCR
XORC #xx:8,EXR
NOP
—
—
—
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
B
B
W
W
W
W
W
W
W
W
W
W
W
W
B
B
B
B
B
B
—
TRAPA
RTE
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
PC @-SP,CCR @-SP,
EXR @-SP,<Vector> PC
EXR @SP+,CCR @SP+,
PC @SP+
Transition to power-down state
#xx:8 CCR
#xx:8 EXR
Rs8 CCR
Rs8 EXR
@ERs CCR
@ERs EXR
@(d:16,ERs) CCR
@(d:16,ERs) EXR
@(d:32,ERs) CCR
@(d:32,ERs) EXR
@ERs CCR,ERs32+2 ERs32
@ERs EXR,ERs32+2 ERs32
@aa:16 CCR
@aa:16 EXR
@aa:32 CCR
@aa:32 EXR
CCR Rd8
EXR Rd8
CCR @ERd
EXR @ERd
CCR @(d:16,ERd)
EXR @(d:16,ERd)
CCR @(d:32,ERd)
EXR @(d:32,ERd)
ERd32-2 ERd32,CCR @ERd
ERd32-2 ERd32,EXR @ERd
CCR @aa:16
EXR @aa:16
CCR @aa:32
EXR @aa:32
CCR #xx:8 CCR
EXR #xx:8 EXR
CCR #xx:8 CCR
EXR #xx:8 EXR
CCR #xx:8 CCR
EXR #xx:8 EXR
PC PC+2
Operation
IHNZVC
Advanced Mode
2
4
2
4
2
4
2
4
2
2
2
2
4
4
4
4
6
6
10
10
6
6
10
10
4
4
4
4
6
6
8
8
6
6
8
8
2
5 [9]
2
1
2
1
1
3
3
4
4
6
6
4
4
4
4
5
5
1
1
3
3
4
4
6
6
4
4
4
4
5
5
1
2
1
2
1
2
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8 [9]
Condition
Code
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Rev. 2.0, 11/ 00, page 871 of 1037
(8) Block Tra nsfer Instruc ti ons
EEPMOV.B
EEPMOV.W
—
—
EEPMOV
Mnemonic Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation
IHNZVC Advanced Mode
4
4
4+2n *2
4+2n *2
—
—
—
—
—
—
—
—
—
—
—
—
Condition
Code
if R4L 0
Repeat @ER5 @ER6
ER5+1 ER5
ER6+1 ER6
R4L-1 R4L
Until R4L=0
else next;
if R4 0
Repeat @ER5 @ER6
ER5+1 ER5
ER6+1 ER6
R4-1 R4
Until R4=0
else next;
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States *
1
Notes: 1. The values indicated in t he column of num ber of execut ion st at es apply when
instruction code and oper and exist in the on- chip mem or y.
2. n is the initial setting value of R4L or R4.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
[1] 7 stat es when t he num ber of r et ur n/ r et r act r egist er s is 2, 9 st ates when the number of
registers is 3, and 11 st at es when t he num ber of r egister s is 4.
[2] Cannot be used in this LSI .
[3] Set t o 1 when a car r y or bor r ow occurs at bit 11, otherwise cleared to 0.
[4] Set t o 1 when a car r y or bor r ow occurs at bit 27, otherwise cleared to 0.
[5] Retains the value bef or e com put at ion when the com put at ion r esult is 0, ot her wise
cleared to 0.
[6] Set t o 1 when t he divisor is negative, ot her wise cleared t o 0.
[7] Set t o 1 when t he divisor is 0, ot her wise cleared t o 0.
[8] Set t o 1 when t he quot ient is negat ive, ot her wise cleared t o 0.
[9] 1 is added to t he num ber of execution states when EXR is valid.
Rev. 2.0, 11/ 00, page 872 of 1037
A.2 Instruction Codes
A.2 Instruction Codes
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
Mnemonic Instruction Format
1st byte
B
B
W
W
L
L
L
L
L
B
B
B
B
W
W
L
L
B
B
B
B
B
B
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
0
7
0
7
0
0
0
0
9
0
E
1
7
6
7
0
0
0
7
7
7
6
6
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
rd
8
9
9
A
A
B
B
B
rd
E
rd
6
9
6
A
1
6
1
6
C
E
A
A
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
8
rs
1
rs
1
1 ers
0
8
9
rs
rs
6
rs
6
F
4
0 IMM
0 erd
1
3
0
1
2
3
4
5
6
7
8
9
IMM
IMM
IMM
IMM
abs
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
rd
rd
rd
0 erd
0 erd
0 erd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0
1
rd
0
0
0
0
0
0
0
0
0
0
0
0
0
0 IMM
0 IMM 0
0
6
0
7
7
IMM
IMM
abs
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
IMM
IMM
abs
6
6
6
6 0 IMM 0
7
6
0 IMM 0
7
6
2nd byte 3rd byte 4th byte 5th byte 6th byte 7the byte 8th byte 9th byte 10th byte
Size
Instruction
0 ers 0 erd
IMM
Rev. 2.0, 11/ 00, page 873 of 1037
Bcc
(Cont.)
BCLR
BIAND
BILD
BIOR
BIST
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
Mnemonic Instruction Format
1st byte
—
—
—
—
—
—
—
—
—
—
—
—
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
4
5
4
5
4
5
4
5
4
5
4
5
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
A
8
B
8
C
8
D
8
E
8
F
8
2
D
F
A
A
2
D
F
A
A
6
C
E
A
A
7
C
E
A
A
4
C
E
A
A
7
D
F
A
A
A
B
C
D
E
F
0 IMM
0 erd
1
3
rn
0 erd
1
3
1 IMM
0 erd
1
3
1 IMM
0 erd
1
3
1 IMM
0 erd
1
3
1 IMM
0 erd
1
3
disp
disp
disp
disp
disp
disp
abs
abs
abs
abs
abs
abs
0
0
0
0
0
0
rd
0
8
8
rd
0
8
8
rd
0
0
0
rd
0
0
0
rd
0
0
0
rd
0
8
8
7
7
6
6
7
7
7
7
7
7
6
6
disp
disp
disp
disp
disp
disp
2
2
abs
2
2
abs
6
6
abs
7
7
abs
4
4
abs
7
7
abs
0 IMM
0 IMM
rn
rn
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
7
6
7
7
7
6
2
2
6
7
4
7
0 IMM
rn
1 IMM
1 IMM
1 IMM
1 IMM
0
0
0
0
0
0
7
6
7
7
7
6
2
2
6
7
4
7
0 IMM
rn
1 IMM
1 IMM
1 IMM
1 IMM
0
0
0
0
0
0
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 2.0, 11/ 00, page 874 of 1037
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BSR d:8
BSR d:16
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
Mnemonic Instruction Format
1st byte
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
—
—
B
B
B
B
B
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
5
5
6
7
7
6
6
5
C
E
A
A
7
C
E
A
A
1
D
F
A
A
1
D
F
A
A
4
C
E
A
A
0
D
F
A
A
0
D
F
A
A
5
C
7
D
F
A
A
1 IMM
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
rn
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
rn
0 erd
abs
1
3
disp
0
0 IMM
0 erd
abs
1
3
rd
0
0
0
rd
0
0
0
rd
0
8
8
rd
0
8
8
rd
0
0
0
rd
0
8
8
rd
0
8
8
0
rd
0
8
8
7
7
7
7
7
7
6
6
7
7
7
7
6
6
6
6
5
5
abs
7
7
abs
1
1
abs
1
1
abs
4
4
abs
0
0
abs
0
0
abs
disp
7
7
abs
1 IMM
1 IMM
0 IMM
0 IMM
0 IMM
0 IMM
rn
rn
0 IMM
0 IMM
0 IMM
0 IMM
rn
rn
0 IMM
0 IMM
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
7
7
7
6
7
7
6
6
5
7
1
1
4
0
0
7
1 IMM
0 IMM
0 IMM
rn
0 IMM
0 IMM
rn
0 IMM
0
0
0
0
0
0
0
0
7
7
7
6
7
7
6
6
5
7
1
1
4
0
0
7
1 IMM
0 IMM
0 IMM
rn
0 IMM
0 IMM
rn
0 IMM
0
0
0
0
0
0
0
0
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 2.0, 11/ 00, page 875 of 1037
BTST
BXOR
CLRMAC
CMP
DAA
DAS
DEC
DIVXS
DIVXU
EEPMOV
EXTS
EXTU
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
CLRMAC
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
DAA Rd
DAS Rd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
EEPMOV.B
EEPMOV.W
EXTS.W Rd
EXTS.L ERd
EXTU.W Rd
EXTU.L ERd
Mnemonic Instruction Format
1st byte
Cannot be used in this LSI
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
—
B
B
W
W
L
L
B
B
B
W
W
L
L
B
W
B
W
—
—
W
L
W
L
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
A
1
7
1
7
1
0
1
1
1
1
1
1
0
0
5
5
7
7
1
1
1
1
3
C
E
A
A
3
C
E
A
A
5
C
E
A
A
rd
C
9
D
A
F
F
F
A
B
B
B
B
1
1
1
3
B
B
7
7
7
7
0 IMM
0 erd
abs
1
3
rn
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
IMM
rs
2
rs
2
1 ers
0
0
0
5
D
7
F
D
D
rs
rs
5
D
D
F
5
7
rd
0
0
0
rd
0
0
0
rd
0
0
0
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
rd
0 erd
0 erd
0
0
rd
0 erd
C
4
rd
0 erd
rd
0 erd
7
7
6
6
7
7
5
5
5
5
3
3
abs
3
3
abs
5
5
abs
IMM
1
3
9
9
0 IMM
0 IMM
rn
rn
0 IMM
0 IMM
rs
rs
8
8
0
0
abs
0
0
abs
0
0
abs
IMM
rd
0 erd
F
F
7
6
7
3
3
5
0 IMM
rn
0 IMM
0
0
0
7
6
7
3
3
5
0 IMM
rn
0 IMM
0
0
0
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 2.0, 11/ 00, page 876 of 1037
INC
JMP
JSR
LDC
LDM
LDMAC
MAC
MOV
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
JMP @ERn
JMP @aa:24
JMP @@aa:8
JSR @ERn
JSR @aa:24
JSR @@aa:8
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
LDM.L @SP+, (ERn-ERn+1)
LDM.L @SP+, (ERn-ERn+2)
LDM.L @SP+, (ERn-ERn+3)
LDMAC ERs,MACH
LDMAC ERs,MACL
MAC @ERn+,@ERm+
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
Mnemonic Instruction Format
Cannot be used in this LSI
1st byte
B
W
W
L
L
—
—
—
—
—
—
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
—
B
B
B
B
B
B
B
B
B
B
B
B
0
0
0
0
0
5
5
5
5
5
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
6
6
7
6
2
6
6
6
6
7
A
B
B
B
B
9
A
B
D
E
F
7
1
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
rd
C
8
E
8
C
rd
A
A
8
E
8
0
5
D
7
F
0 ern
abs
0 ern
abs
IMM
4
0
1
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
IMM
rs
0 ers
0 ers
0 ers
0 ers
abs
0
2
1 erd
1 erd
0 erd
rd
rd
rd
0 erd
0 erd
0
0
1
rs
rs
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
rd
rd
rd
0
rd
rd
rd
rs
rs
0
abs
abs
0
6
6
6
6
7
7
6
6
6
6
6
6
6
6
6
6
6
7
9
9
F
F
8
8
D
D
B
B
B
B
D
D
D
disp
A
abs
disp
A
IMM
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0
0
2
2
7
7
7
2
A
0
0
0
0
0
0
0
0
0
0
0
0
0 ern+1
0 ern+2
0 ern+3
rd
abs
rs
6
6
disp
disp
B
B
abs
abs
2
2
0
0
abs
abs
disp
disp
disp
disp
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10 byte
Size
Instruction
Rev. 2.0, 11/ 00, page 877 of 1037
MOV
(Cont.)
MOVFPE
MOVTPE
MULXS
MULXU
NEG
NOP
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa :16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,Rd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16 ,ERd
MOV.L @aa:32 ,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd) *
1
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
MULXS.B Rs,Rd
MULXS.W Rs,ERd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
NOP
Mnemonic Instruction Format
1st byte
Cannot be used in this LSI
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
B
B
B
W
B
W
B
W
L
—
6
3
6
6
7
0
6
6
7
6
6
6
6
6
7
6
6
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
5
1
1
1
0
C
rs
A
A
9
D
9
F
8
D
B
B
9
F
8
D
B
B
A
F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
7
7
7
0
1 erd
abs
8
A
0
rs
0 ers
0 ers
0 ers
0 ers
0
2
1 erd
1 erd
0 erd
1 erd
8
A
0
1 ers
0
0
0
0
0
0
0
0
0
0
0
0
C
C
rs
rs
8
9
B
0
rs
rs
rs
rd
rd
rd
rd
0
rd
rd
rd
rs
rs
0
rs
rs
rs
0 erd
0 erd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rd
0 erd
rd
rd
0 erd
0
6
6
6
6
7
6
6
6
6
6
7
6
6
6
5
5
abs
IMM
disp
B
abs
disp
B
abs
9
F
8
D
B
B
9
F
8
D
B
B
0
2
2
A
0 ers
0 ers
0 ers
0 ers
0
2
1 erd
1 erd
0 erd
1 erd
8
A
rs
rs
abs
rd
abs
rs
abs
IMM
0 erd
0 erd
0
0 erd
0 erd
0 erd
0 ers
0 ers
0
0 ers
0 ers
0 ers
rd
0 erd
6
6
disp
B
abs
disp
B
abs
2
A
disp
disp
0 erd
abs
0 ers
abs
disp
disp
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 2.0, 11/ 00, page 878 of 1037
NOT
OR
ORC
POP
PUSH
ROTL
ROTR
ROTXL
ROTXR
RTE
RTS
NOT.B Rd
NOT.W Rd
NOT.L ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
ORC #xx:8,CCR
ORC #xx:8,EXR
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
ROTL.B Rd
ROTL.B #2, Rd
ROTL.W Rd
ROTL.W #2, Rd
ROTL.L ERd
ROTL.L #2, ERd
ROTR.B Rd
ROTR.B #2, Rd
ROTR.W Rd
ROTR.W #2, Rd
ROTR.L ERd
ROTR.L #2, ERd
ROTXL.B Rd
ROTXL.B #2, Rd
ROTXL.W Rd
ROTXL.W #2, Rd
ROTXL.L ERd
ROTXL.L #2, ERd
ROTXR.B Rd
ROTXR.B #2, Rd
ROTXR.W Rd
ROTXR.W #2, Rd
ROTXR.L ERd
ROTXR.L #2, ERd
RTE
RTS
Mnemonic Instruction Format
1st byte
B
W
L
B
B
W
W
L
L
B
B
W
L
W
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
—
1
1
1
C
1
7
6
7
0
0
0
6
0
6
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
7
7
7
rd
4
9
4
A
1
4
1
D
1
D
1
2
2
2
2
2
2
3
3
3
3
3
3
2
2
2
2
2
2
3
3
3
3
3
3
6
4
0
1
3
IMM
rs
4
rs
4
F
IMM
4
7
0
F
0
8
C
9
D
B
F
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
7
7
rd
rd
0 erd
rd
rd
rd
0 erd
0
1
rn
0
rn
0
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
0
0
6
0
6
6
IMM
4
4
D
D
0 ers
IMM
7
F
IMM
0 erd
0 ern
0 ern
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 2.0, 11/ 00, page 879 of 1037
SHAL
SHAR
SHLL
SHLR
SLEEP
STC
STM
STMAC
SHAL.B Rd
SHAL.B #2, Rd
SHAL.W Rd
SHAL.W #2, Rd
SHAL.L ERd
SHAL.L #2, ERd
SHAR.B Rd
SHAR.B #2, Rd
SHAR.W Rd
SHAR.W #2, Rd
SHAR.L ERd
SHAR.L #2, ERd
SHLL.B Rd
SHLL.B #2, Rd
SHLL.W Rd
SHLL.W #2, Rd
SHLL.L ERd
SHLL.L #2, ERd
SHLR.B Rd
SHLR.B #2, Rd
SHLR.W Rd
SHLR.W #2, Rd
SHLR.L ERd
SHLR.L #2, ERd
SLEEP
STC.B CCR,Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:16,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:32,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-ERd
STC.W EXR,@-ERd
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
STM.L(ERn-ERn+1) , @-SP
STM.L (ERn-ERn+2) , @-SP
STM.L (ERn-ERn+3) , @-SP
STMAC MACH,ERd
STMAC MACL,ERd
Mnemonic Instruction Format
1st byte
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
B
B
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
C
9
D
B
F
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
8
0
1
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
0
rd
rd
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
6
6
6
6
7
7
6
6
6
6
6
6
6
6
6
9
9
F
F
8
8
D
D
B
B
B
B
D
D
D
1 erd
1 erd
1 erd
1 erd
0 erd
0 erd
1 erd
1 erd
8
8
A
A
F
F
F
0
0
0
0
0
0
0
0
0
0
0
0
0 ern
0 ern
0 ern
6
6
disp
disp
B
B
abs
abs
A
A
0
0
abs
abs
disp
disp
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Cannot be used in this LSI
Rev. 2.0, 11/ 00, page 880 of 1037
SUB
SUBS
SUBX
TAS
TRAPA
XOR
XORC
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
TAS @ERd*
2
TRAPA #x:2
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
XORC #xx:8,CCR
XORC #xx:8,EXR
Mnemonic Instruction Format
1st byte
B
W
W
L
L
L
L
L
B
B
B
—
B
B
W
W
L
L
B
B
1
7
1
7
1
1
1
1
B
1
0
5
D
1
7
6
7
0
0
0
8
9
9
A
A
B
B
B
rd
E
1
7
rd
5
9
5
A
1
5
1
rs
3
rs
3
1 ers
0
8
9
IMM
rs
E
IMM
IMM
rs
5
rs
5
F
IMM
4
rd
rd
rd
0 erd
0 erd
0 erd
0 erd
0 erd
rd
0
0
rd
rd
rd
0 erd
0
1
7
6
0
IMM
B
IMM
5
5
0 erd
0 ers
IMM
IMM
C
IMM
0 erd
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Notes: *1 Either 1 or 0 can be set to bit 7 in 4th byte of MOV.L Ers, @(d: 32, Erd) instruction.
*2 Only register ER0,ER1,ER4, or ER5 should be used when using the TAS instruction.
00
Rev. 2.0, 11/ 00, page 881 of 1037
[Legend]
IMM: Immediate data (2, 3, 8, 16, 32 bits)
abs: Absolute address (8, 16, 24, 32 bit s)
disp: Displacement (8, 16, 32 bits)
rs, rd, rn: Register fields (8-bit register or 16-bit register is selected in 4 bits. rs, rd and
rn correspond to the operand type Rs, Rd, and Rn respectively.)
ers, erd, ern, erm: Register fields (address register or 32-bit register is selected in 3 bits. ers, erd
ern and erm c orrespond to t he opera nd t ype E Rs, E Rd, E Rn and Rm
respectively.)
The following table shows the correspondence between the register field and the general
register.
Address Register , 32-bi t
Register 16-bi t Regi st er 8-bi t Regi st er
Register
Field General
Register Register
Field General
Register Register
Field General
Register
000
001
:
:
:
:
111
ER0
ER1
:
:
:
:
ER7
0000
0001
:
:
:
:
0111
1000
1001
:
:
:
:
1111
R0
R1
:
:
:
:
R7
E0
E1
:
:
:
:
E7
0000
0001
:
:
:
:
0111
1000
1001
:
:
:
:
1111
R0H
R1H
:
:
:
:
R7H
R0L
R1L
:
:
:
:
R7L
Rev. 2.0, 11/ 00, page 882 of 1037
A.3 Op erat ion Code Map
Table A.3 shows an operation code map.
Instruction code: 1st byte 2nd byte
AH AL BH BL
BH highest bit is set to 0.
BH highest bit is set to 1
0
NOP
BRA
MULXU
BSET
AH AL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
BRN
DIVXU
BNOT
2
BHI
MULXU
BCLR
3
BLS
DIVXU
BTST
STC
STMAC
LDC
LDMAC
4
ORC
OR
BCC
RTS
OR
BORBIOR
6
ANDC
AND
BNE
RTE
AND
5
XORC
XOR
BCS
BSR
XOR
BXOR
BIXOR
BAND
BIAND
7
LDC
BEQ
TRAPA
BST BIST
BLD BILD
8
BVC
MOV
9
BVS
A
BPL
JMP
B
BMI
EEPMOV
C
BGE
BSR
D
BLT
MOV
E
ADDX
SUBX
BGT
JSR
F
BLE
MOV.B
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
ADD
SUB
MOV
MOV
CMP
Table A.3(3)
Table A.3 Operation Code Map (1)
**
Note: * Cannot be used in this LSI
Table
A.3(2)
Table
A.3(2)
Table
A.3(2) Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2) Table
A.3(2) Table
A.3(2)
Rev. 2.0, 11/ 00, page 883 of 1037
Instruction code: 1st byte 2nd byte
AH AL BH BL
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
6A
79
7A
0
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
MOV
SHLL
SHLR
ROTXL
ROTXR
NOT
1
LDM
BRN
ADD
ADD
2
BHI
MOV
CMP
CMP
3
STM
NOT
BLS
SUB
SUB
4
SHLL
SHLR
ROTXL
ROTXR
BCC
MOVFPE
OR
OR
5
INC
EXTU
DEC
BCS
XOR
XOR
6
MAC
BNE
AND
AND
7
INC
SHLL
SHLR
ROTXL
ROTXR
EXTU
DEC
BEQ
LDCSTC
8
SLEEP
BVC
MOV
ADDS
SHAL
SHAR
ROTL
ROTR
NEG
SUBS
9
BVS
A
CLRMAC
BPL
MOV
B
NEG
BMI
ADD
MOV
SUB
CMP
C
SHAL
SHAR
ROTL
ROTR
BGE
MOVTPE
D
INC
EXTS
DEC
BLT
E
TAS
BGT
F
INC
SHAL
SHAR
ROTL
ROTR
EXTS
DEC
BLE
BH
AH AL
Table A.3 Operation Code Map (2)
**
Note: * Cannot be used in this LSI
* *
Table
A.3(4)
Table
A.3(3) Table
A.3(3) Table
A.3(3)
Table
A.3(4)
Rev. 2.0, 11/ 00, page 884 of 1037
Instruction code: 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
r is the register specification section.
Absolute address is set at aa.
DH highest bit is set to 0.
DH highest bit is set to 1.
Notes:
AH AL BH BL CH
CL
01C05
01D05
01F06
7Cr06 *
1
7Cr07 *
1
7Dr06 *
1
7Dr07 *
1
7Eaa6 *
2
7Eaa7 *
2
7Faa6 *
2
7Faa7 *
2
0
MULXS
BSET
BSET
BSET
BSET
1
DIVXS
BNOT
BNOT
BNOT
BNOT
2
MULXS
BCLR
BCLR
BCLR
BCLR
3
DIVXS
BTST
BTST
BTST
BTST
4
OR
5
XOR
6
AND
789ABCDEF
1.
2.
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
Table A.3 Operation Code Map (3)
Rev. 2.0, 11/ 00, page 885 of 1037
Instruction code: 1st byte 2nd byte
AH AL BH BL
3th byte 4th byte
CH CL DH DL
FH highest bit is set to 0.
FH highest bit is set to 1.
5th byte 6th byte
EH EL FH FL
Instruction code: 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
HH highest bit is set to 0.
HH highest bit is set to 1.
Note: * Absolute address is set at aa.
5th byte 6th byte
EH EL FH FL
7th byte 8th byte
GH GL HH HL
6A10aaaa6*
6A10aaaa7*
6A18aaaa6*
6A18aaaa7*
AHALBHBLCHCLDHDLEH
EL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
6A30aaaaaaaa6
*
6A30aaaaaaaa7
*
6A38aaaaaaaa6
*
6A38aaaaaaaa7
*
AHALBHBL ... FHFLGH
GL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
Table A.3 Operation Code Map (4)
Rev. 2.0, 11/ 00, page 886 of 1037
A.4 Num b er of Execut i on St at es
This section explains execution state and how to calculate the number of execution states for
each instruction of the H8S/2194 CPU.
Table A.5 indicates number of cycles of instruction fetch and data read/write during instruction
execution, and table A.4 indicates number of states required for each instruction size.
The number of execution states can be obtained from the equation below.
Number of execution states = I ⋅ SI + J ⋅ SJ + K ⋅ SK + L ⋅ SL + M ⋅ SM + N ⋅ SN
(1) Examples of execution state number calculation
The conditions are as follows: In advanced mode, program and stack areas are set in the on-chip
memory, a wait is inserted every 2 states in the on-chip supporting module access with 8-bit bus
width.
1. BSET # 0, @ FFFFC 7:8
From Table A.5,
I = L = 2, J = K = M = N = 0
From Table A.4,
SI = 1, SL = 2
Number of execution states = 2 × 1 + 2 × 2 = 6
2. JSR @@3 0
From Table A.5,
I = J = K = 2, L = M = N = 0
From Table A.4,
SI = SJ = SK = 1
Number of execution states = 2 × 1 + 2 × 1 + 2 × 1 = 6
Rev. 2.0, 11/ 00, page 887 of 1037
Table A.4 Number of States Required for Each Execution Status (Cycle)
Target of Access
On- Chi p Suppor ting M odule
Execution St at us ( Cycl e) On-Chi p M e m or y 8-bit bus 16-bit bus
Instruction fetch SI
Branch address read SJ
Stack operat ion SK
——
Byte data access SL22
Word data access SM
1
4
Int er nal operat ion SN1
Rev. 2.0, 11/ 00, page 888 of 1037
Table A.5 Instr uc ti on Exe c uti on Status (No. of Cy cles)
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
ADD ADD.B #xx:8,Rd
ADD.B Rs, Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD L #xx:32,ERd
ADD.L ERs,ERd
1
1
2
1
3
1
ADDS ADDS #1/2/4,ERd 1
ADDX ADDX #xx:8,Rd
ADDX Rs,Rd 1
1
AND AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx.16,Rd
AND.W Rs,Rd
AND L #xx:32,ERd
AND.L ERs,ERd
1
1
2
1
3
2
ANDC ANDC #xx:8,CCR
ANDC #xx:8,EXR 1
2
BAND BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3@aa:8
BAND #xx:3@aa:16
BAND #xx:3@aa:32
1
2
2
3
4
1
1
1
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
BHI d:16
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 2.0, 11/ 00, page 889 of 1037
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
Bcc BGT d:16
BLE d:16 2
21
1
BCLR BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
1
2
2
3
4
1
2
2
3
4
2
2
2
2
2
2
2
2
BIAND BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BILD BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BIOR BIOR #xx:8,Rd
BIOR #xx:8,@ERd
BIOR #xx:8,@aa:8
BIOR #xx:8,@aa:16
BIOR #xx:8,@aa:32
1
2
2
3
4
1
1
1
1
BIST BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
1
2
2
3
4
2
2
2
2
BIXOR BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BLD BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BNOT BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
1
2
2
3
4
1
2
2
3
2
2
2
2
2
2
2
Rev. 2.0, 11/ 00, page 890 of 1037
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
BNOT BNOT Rn,@aa:32 4 2
BOR BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BSET BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
1
2
2
3
4
1
2
2
3
4
2
2
2
2
2
2
2
2
BSR BSR d:8 2 2
BSR d:16 2 2 1
BST BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
1
2
2
3
4
2
2
2
2
BTST BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
1
2
2
3
4
1
2
2
3
4
1
1
1
1
1
1
1
1
BXOR BXOR #xx:3,Rd
BXOR #xx:3,@E Rd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
CLRMAC CLRMAC Cannot be used in this LSI.
CMP CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
1
1
2
1
3
1
DAA DAA Rd 1
DAS DAS Rd 1
Rev. 2.0, 11/ 00, page 891 of 1037
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
DEC DEC.B Rd
DEC.W #1/2,Rd
DEC.L #1/2 ERd
1
1
1
DIVXS DIVXS.B Rs,Rd
DIVXS.W Rs,ERd 2
211
19
DIVXU DIVXU.B Rs,Rd
DIVXU.W Rs,ERd 1
111
19
EEPMOV EEPMOV.B
EEPMOV.W 2
22n+2*2
2n+2*2
EXTS EXTS.W Rd
EXTS.L ERd 1
1
EXTU EXTU.W Rd
EXTU.L ERd 1
1
INC INC.B Rd
INC.W #1/2,Rd
INC.L #1/2,ERd
1
1
1
JMP JMP @ERN
JMP @aa:24 2
21
JMP @@aa:8 2 2 1
JSR JSR @ERn 2 2
JSR @aa:24 2 2 1
JSR @@aa:8 2 2 2
LCD LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @E Rs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @E Rs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
1
2
1
1
2
2
3
3
5
5
2
2
3
3
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LDM LDM.L
@SP+,(ERn−ERn+1)
LDM.L
@SP+,(ERn−ERn+2)
LDM.L
@SP+,(ERn−ERn+3)
2
2
2
4
6
8
1
1
1
LDMAC LDMAC ERs,MACH
LDMAC ERs,MACL
MAC MAC @ERn+,@ERm+
Cannot be used in this LSI.
Rev. 2.0, 11/ 00, page 892 of 1037
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
MOV MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
MOV.L @aa:32,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd)
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
1
1
1
2
4
1
1
2
3
1
2
4
1
1
2
3
2
1
1
2
4
1
2
3
1
2
4
1
2
3
3
1
2
3
5
2
3
4
2
3
5
2
3
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
MOVFPE MOVFPE @:aa:16,Rd
MOVTPE MOVTPE Rs,@:aa:16 Cannot be used in this LSI.
MULXS MULXS.B Rs,Rd 2 11
MULXS . W Rs,ERd 2 19
MULXU MULXU.B Rs,Rd 1 11
MULXU.W Rs,ERd 1 19
Rev. 2.0, 11/ 00, page 893 of 1037
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
NEG NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP NOP 1
NOT NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR OR.B #xx:8 ,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
1
1
2
1
3
2
ORC ORC #xx:8,CCR
ORC #xx:8,EXR 1
2
POP POP.W Rn
POP.L ERn 1
21
21
1
PUSH PUSH.W Rn
PUSH.L ERn 1
21
21
1
ROTL ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
1
1
1
1
1
1
ROTR ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L ERd
ROTR.L #2,ERd
1
1
1
1
1
1
ROTXL ROTXL.B Rd
ROTXL.B #2,Rd
ROTXL.W Rd
ROTXL.W #2,Rd
ROTXL.L ERd
ROTXL.L #2,ERd
1
1
1
1
1
1
ROTXR ROTXR.B Rd
RPTXR.B #2,Rd
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
ROTXR.L #2,ERd
1
1
1
1
1
1
RTE RTE 2 2/3*11
RTS RTS 2 2 1
Rev. 2.0, 11/ 00, page 894 of 1037
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
SHAL SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
1
1
1
1
1
1
SHAR SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
1
1
1
1
1
1
SHLL SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
1
1
1
1
1
1
SHLR SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
1
1
1
1
1
1
SLEEP SLEEP 1 1
STC STC.B CCR.Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:1 6,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:3 2,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-E Rd
STC.W EXR,@-ERd
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
1
1
2
2
3
3
5
5
2
2
3
3
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
STM STM.L (E Rn-ERn+1),
@-Sp
STM.L (ERn-E Rn+2),
@-Sp
STM.L (ERn-E Rn+3),
@-Sp
2
2
2
4
6
8
1
1
1
STMAC STMAC MACH,ERd
STMAC MACL,ERd Cannot be used in this LSI.
SUB SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
1
2
1
3
1
SUBS SUBS #1/2/4,ERd 1
Rev. 2.0, 11/ 00, page 895 of 1037
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
SUBX SUBX #xx:8,Rd
SUBX Rs,Rd 1
1
TAS TAS @ERd*322
TRAPA TRAPA #x:2 2 2 2/3*12
XOR XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
1
1
2
1
3
2
XORC XORC #xx:8,CCR
XORC #xx:8,EXR 1
2
Notes: 1. 3 applies when EXR is valid, and 2 applies when invalid.
2. Applies when the t r ansf er dat a is n byt es.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.0, 11/ 00, page 896 of 1037
A.5 Bus Status During Instruct ion Execution
Table A.6 indicates execution status of each instruction available in this LSI. For the number of
states required for each execution status, see table A.4, Number of States Required for Each
Execution Status (Cycle).
[How to see the table]
Instruction
JMP@aa:24 R:W 2nd
Internal operation
1 state
R:W EA
12345678
End of instruction
Order of execution
Effective address is read by word.
Read/write not executed
The 2nd word of the instruction currently being
executed is read by word.
[Legend]
R : B Read by byte
R : W Read by wor d
W : B Write by byte
W : W Write by word
: M Bus not t r ansferred im m ediately aft er this cycle
2nd Address of the 2nd word (3rd and 4th bytes)
3rd Address of the 3rd word (5th and 6th byt es)
4th Address of the 4th word ( 7t h and 8t h byt es)
5th Address of the 5th word ( 9t h and 10t h byt es)
NEXT The head address of t he inst r uct ion immediately af t er t he instr uct ion
current ly being executed
EA Execut ion addr ess
VEC Vector address
Rev. 2.0, 11/ 00, page 897 of 1037
Table A.6 Instr uc ti on Exe c uti on Status
Instruction 1 2 3 4 5 6 7 8 9
ADD.B # xx :8,Rd R:W NEXT
ADD.B Rs,Rd R:W NEXT
ADD.W #xx:16,Rd R:W 2 nd R:W NE X T
ADD.W Rs,Rd R:W NEXT
ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
ADD.L ERs,ERd R:W NEXT
ADDS #1/2/4,ERd R:W NEXT
ADDX #xx:8,Rd R:W NEXT
ADDX Rs,Rd R:W NEXT
AND.B # xx :8,Rd R:W NEXT
AND.B Rs,Rd R:W NEXT
AND.W #xx:16,Rd R:W 2 nd R:W NE X T
AND.W Rs,Rd R:W NEXT
AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
AND.L ERs,ERd R:W 2nd R:W NEXT
ANDC #xx: 8,CCR R:W NEXT
ANDC #xx: 8,EXR R:W 2nd R:W NEXT
BAND #xx:3,Rd R:W NEXT
BAND #xx:3,@ERd R: W 2n d R:B EA R:W:M NEXT
BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th
BRA d:8 (BT d : 8) R:W NEXT R:W EA
BRN d:8 (BT d: 8) R:W NEXT R:W EA
BHI d:8 R:W NEXT R:W EA
BLS d:8 R:W NEXT R:W EA
BCC d:8 (BHS d:8 ) R:W NEXT R:W EA
BCS d:8 (BLO d: 8) R:W NEXT R:W EA
BNE d:8 R:W NEXT R:W EA
BEQ d:8 R:W NEXT R:W EA
BVC d:8 R:W NEXT R:W EA
BVS d:8 R:W NEXT R:W EA
BPL d:8 R:W NEXT R:W EA
BMI d:8 R:W NEXT R:W EA
BGE d:8 R:W NEXT R:W EA
BLT d:8 R:W NEXT R:W EA
BGT d:8 R:W NEXT R:W EA
BLE d:8 R:W NEXT R:W EA
BRA d:16 (BT d:16) R:W 2nd Internal
operation 1
state
R:W EA
BRN d:16 (BF d:16) R:W 2nd Internal
operation 1
state
R:W EA
BHI d:16 R:W 2nd Internal
operation 1
state
R:W EA
BLS d:16 R:W 2nd Internal
operation 1
state
R:W EA
BCC d:16 (BHS
d:16) R:W 2nd Internal
operation 1
state
R:W EA
BCS d:16 (BLO d:16) R:W 2nd Internal
operation 1
state
R:W EA
BNE d:16 R:W 2nd Internal
operation 1
state
R:W EA
BEQ d:16 R:W 2nd Internal
operation 1
state
R:W EA
BVC d:16 R:W 2nd Internal
operation 1
state
R:W EA
BVS d:16 R:W 2nd Internal
operation 1
state
R:W EA
BPL d:16 R:W 2nd Internal
operation 1
state
R:W EA
BMI d:16 R:W 2nd Internal
operation 1
state
R:W EA
BGE d:16 R:W 2nd Internal
operation 1
state
R:W EA
Rev. 2.0, 11/ 00, page 898 of 1037
Instruction 1 2 3 4 5 6 7 8 9
BLT d:16 R:W 2nd Internal
operation 1
state
R:W EA
BGT d:16 R:W 2nd Internal
operation 1
state
R:W EA
BLE d:16 R:W 2nd Internal
operation 1
state
R:W EA
BCLR #xx:3,Rd R:W NEXT
BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR #xx:3,@aa : 8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,Rd R:W NEXT
BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BIAND # xx :3,Rd R:W NEXT
BIAND #xx : 3,ERd R:W 2n d R:B EA R:W : M NEXT
BIAND #xx : 3,@aa:8 R:W 2 nd R:B EA R:W:M NEXT
BIAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BIAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BILD #xx:3,Rd R:W NEXT
BILD #xx:3 ,@ERd R: W 2n d R:B EA R:W:M NEXT
BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BIOR #xx:3,Rd R:W NE X T
BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEX T
BOIR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BOIR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BOIR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BIST #x x:3,Rd R:W NEXT
BIST #x x:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BIST #x x:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BIXOR #xx :3,Rd R:W NEXT
BIXOR #xx :3,@ERd R: W 2nd R:B EA R:W:M NEXT
BIXOR #xx: 3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BIXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BIXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BLD # xx :3,Rd R:W NE X T
BLD # xx :3,@ERd R:W 2nd R:B E A R:W:M NEX T
BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BNOT #xx:3,Rd R:W NEXT
BNOT #xx: 3,ERd R:W 2n d R:B:M EA R:W:M NEXT W:B EA
BNOT #xx: 3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BNOT Rn,Rd R:W NEXT
BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BNOT Rn @aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
Rev. 2.0, 11/ 00, page 899 of 1037
Instruction 1 2 3 4 5 6 7 8 9
BNOT Rn @aa:16 R:W 2nd R:W 3rd R:B:W EA R:W : M NEXT W:B EA
BNOT Rn @aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BOR #x x:3,Rd R:W NEXT
BOR #xx:3,ERd R:W 2n d R:B EA R:W : M NEXT
BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT
BSET #xx:3,Rd R:W NEXT
BSET #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W : M NEXT W:B EA
BSET Rn,Rd R:W NEXT
BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W : B EA
BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4t h R:B:M EA R:W:M NEXT W:B EA
BSR d:8 R:W NEXT R:W EA W:W: M
stack(H) W:W stack(L)
BSR d:16 R:W 2nd Internal
operation 1
state
R:W EA W:W:M
stack(H) W:W stack(L)
BST #xx:3,Rd R:W NEXT
BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BTST #x x:3,Rd R:W NEXT
BTST #x x:3,@ERd R:W 2nd R:B EA R:W : M NEXT
BTST #x x:3,@aa:8 R:W 2nd R:B EA R:W : M NEXT
BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BTST Rn,Rd R:W NEXT
BTST Rn,@ERd R:W 2n d R:B EA R:W:M NEXT
BTST Rn,@aa: 8 R:W 2nd R:B EA R:W: M NEXT
BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BOXR #xx:3,Rd R:W NEXT
BOXR #xx:3,@ERd R:W 2nd R:B EA R:W: M NEXT
BOXR #xx:3,@aa:8 R:W 2nd R:B EA R:W: M NEXT
BOXR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BOXR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
CLRMAC Cannot be used in this LSI.
CMP.B #xx:8,Rd R: W NEXT
CMP.B Rs,Rd R:W NEXT
CMP.W # xx:16,Rd R:W 2nd R:W NEX T
CMP.W Rs,Rd R:W NEXT
CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
CMP.L ERs,ERd R:W NEXT
DAA Rd R:W NEXT
DAS Rd R:W NEXT
DEC.B Rd R:W NEXT
Rev. 2.0, 11/ 00, page 900 of 1037
Instruction 1 2 3 4 5 6 7 8 9
DEC.W #1/2,Rd R:W NEXT
DEC.W #1/2,ERd R:W NEXT
DIVXS.B Rs,Rd R:W 2n d R:W NEXT Internal operation 11 state
DIVXS.W Rs,ERd R:W 2n d R:W NEXT Internal operation 19 state
DIVXU.B Rs,Rd R:W NEXT Internal operation 11 state
DIVXU.W Rs,ERd R:W NEXT Internal operation 19 state
EEPMOV.B R:W 2nd R:B EAs *1R:B EAd *1R:B EAs *2W:B EAd *2R:W NEXT
EEPMOV.W R:W 2nd R:B EAs *1R:B EAd *1R:B EAs *2W:B EAd *2R:W NEXT
EXTS.W Rd R:W NEXT ← Repeat n times *2 →
EXTS.L ERd R:W NEXT
EXTU.W Rd R: W NEXT
EXTU.L ERd R:W NEXT
INC.B Rd R:W NE X T
INC.W #1/ 2,Rd R:W NE X T
INC.L #1/2,ERd R:W NEXT
JMP @ERn R:W NEXT R:W EA
JMP @aa:24 R:W 2nd Internal
operation 1
state
R:W EA
JMP @@aa:8 R:W NEXT R:W:M aa:8 R:W:M aa:8 Internal
operation 1
state
R:W EA
JSR @ERn R:W NE X T R:W EA W:W:M
stack(H) W:W stack (L)
JSR @aa:24 R:W 2nd Internal
operation 1
state
R:W EA W:W:M
stack(H) W:W stack (L)
JSR @@aa :8 R:W NEXT R:W:M aa:8 R:W aa:8 W:W:M
stack(H) W:W stack (L) R:W EA
LCD #xx .8,CCR R:W NEXT
LCD #xx .8,EX R R:W 2n d R:W NEXT
LCD Rs ,CCR R:W NEXT
LCD Rs ,EXR R:W NEXT
LCD @ERs ,CCR R:W 2nd R: W NEXT R:W EA
LCD @ERs ,EXR R:W 2nd R:W NE X T R:W EA
LCD @(d:16 ,ERs),CCR R:W 2nd R:W 3rd R: W NEXT R:W EA
LCD @(d:16,ERs),EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LCD @(d:32,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LCD @(d:32,ERs),EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LCD @ERs+,CCR R:W 2nd R: W NEXT In ternal
operation 1
state
R:W EA
LCD @ERs+,EXR R:W 2nd R:W NE X T Inte r nal
operation 1
state
R:W EA
LCD @aa:16,CCR R:W 2nd R:W 3rd R:W NE X T R: W EA
LCD @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LCD @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LCD @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LDM.L @SP+,
(ERn-ERn+1) R:W 2nd R:W:M NEXT Internal
operation 1
state
R:W:M
stack(H) *3R:W
stack(L) *3
LDM.L @SP+,
(ERn-ERn+2) R:W 2nd R:W:M NEXT Internal
operation 1
state
R:W:M
stack(H) *3R:W
stack(L) *3
LDM.L @SP+,
(ERn-ERn+3) R:W 2nd R:W:M NEXT Internal
operation 1
state
R:W:M
stack(H) *3R:W
stack(L) *3
LD MAC ERs,MAC H
LD MAC ERs,MAC L
MAC @ERn+,@ERm+
Cannot be used in this LSI.
Rev. 2.0, 11/ 00, page 901 of 1037
Instruction 1 2 3 4 5 6 7 8 9
MOV.B #xx:8 , Rd R:W NEXT
MOV.B Rs,Rd R:W NEXT
MOV.B @ERs,Rd R:W NEXT R:B EA
MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA
MOV.B @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA
MOV.B @ERs+,Rd R:W NEXT In t ernal
operation 1
state
R:B EA
MOV.B @aa:8,Rd R:W NEXT R:B EA
MOV.B @aa:16,Rd R:W 2 nd R:W NEXT R:B EA
MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.B Rs,@ERd R:W NEXT W: B EA
MOV.B Rs,@(d:16,ERd ) R:W 2nd R:W NEXT W :B EA
MOV.B Rs,@(d:32,ERd ) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA
MOV.B Rs,@-ERd R:W NEXT Int ernal
operation 1
state
W:B EA
MOV.B Rs,@aa:8 R:W NEXT W: B EA
MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W: B EA
MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:B EA
MOV.W #xx:16,Rd R:W 2nd R:W NEXT
MOV.W Rs,Rd R:W NEXT
MOV.W @ERs,Rd R:W NEXT R:W EA
MOV.W @(d:16,ERs), Rd R:W 2nd R:W NEXT R:W EA
MOV.W @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
MOV.W @ERs+,Rd R:W NEXT Internal
operation 1
state
R:W EA
MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA
MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.W Rs,@ERd R:W NEXT W:W EA
MOV.W Rs,@(d:16, ERd ) R:W 2nd R:W NEXT W:W EA
MOV.W Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
MOV.W Rs,@-ERd R:W NEXT Internal
operation 1
state
W:W EA
MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA
MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:W EA
MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
MOV.L ERs,ERd R:W NEXT
MOV.L @ERs ,ERd R:W 2nd R:W: M NEX T R:W: M EA R:W EA+2
MOV.L @(d:16,ERs ),ERd R:W 2n d R:W : M 3rd R:W NEXT R:W : M EA R:W EA+2
MOV.L @(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT R:W:M EA R:W EA+2
MOV.L @ERs+,ERd R:W 2nd R:W:M NEXT Internal
operation 1
state
R:W:M EA R:W EA+2
MOV.L @aa:16,ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2
MOV.L @aa:32,ERd R:W 2nd R:W:M 3rd R:W 4th R:W NEXT R:W:M EA R:W EA+2
MOV.L ERs,@ERd R:W 2nd R:W:M NEXT W:W:M EA W:W EA+2
MOV.L ERs,@(d:16 , ERd ) R:W 2nd R:W: M 3rd R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@(d:32,ERd) R:W 2nd R:W:W 3rd R:W:M 4th R:W 5th R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@-ERd R:W 2nd R:W:M NEXT Internal
operation 1
state
W:W:M EA W:W EA+2
Rev. 2.0, 11/ 00, page 902 of 1037
Instruction 1 2 3 4 5 6 7 8 9
MOV.L ERs,@aa:1 6 R:W 2nd R:W:M 3rd R:W NEXT W : W : M EA W: W EA+2
MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16 Cannot be used in this LSI.
MULXS.B Rs ,Rd R:W 2nd R:W NEXT Internal operation 11 state
MULXS.W Rs,Rd R:W 2nd R:W NEXT Internal operation 19 state
MULXU.B Rs,Rd R:W NEXT Internal operation 11 state
MULXU.W Rs,Rd R:W NEXT Internal operation 19 state
NEG.B Rd R:W NEXT
NEG.W Rd R:W NEXT
NEG.L ERd R:W NEXT
NOP R:W NEXT
NOT.B Rd R:W NEXT
NOT.W Rd R:W NEX T
NOT.L ERd R:W NEXT
OR.B #xx:8,Rd R:W NE X T
OR.B Rs,Rd R:W NEXT
OR.W #xx:16,Rd R:W 2nd R:W NEXT
OR.W Rs ,Rd R:W NEXT
OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
OR.L ERs,ERd R:W 2nd R:W NEXT
ORC #xx:8,CCR R:W NEXT
ORC #xx:8,EXR R:W 2nd R:W NEX T
POP.W Rn R:W NEXT Internal
operation 1
state
R:W EA
POP.L ERn R:W 2n d R:W:M NEXT Interna l
operation 1
state
R:W:M EA R:W EA+2
PUSH.W Rn R:W NEXT Internal
operation 1
state
W:W EA
PUSH.L ERn R:W 2nd R:W:M NEXT Inte rnal
operation 1
state
W:W:M EA W:W EA+2
ROTL.B Rd R:W NEXT
ROTL.B #2, Rd R:W NEXT
ROTL.W Rd R: W NEXT
ROTL.W #2 ,Rd R:W NE X T
ROTL.L ERd R:W NEXT
ROTL.L #2, ERd R:W NEXT
ROTR.B Rd R:W NEXT
ROTR.B # 2,Rd R:W NEXT
ROTR.W Rd R: W NEXT
ROTR.W #2,Rd R: W NEXT
ROTR.L ERd R:W NEXT
ROTR.L # 2 ,ERd R:W NEXT
ROTXL. B Rd R: W NEXT
ROTXL. B #2. Rd R:W NE X T
ROTXL. W Rd R:W NE X T
ROTXL. W #2 ,Rd R:W NEX T
ROTXL.L ERd R:W NEXT
ROTXL.L #2,ERd R:W NEXT
ROTXR.B Rd R:W NEX T
ROTXR.B #2,Rd R:W NEX T
ROTXR.W Rd R: W NEXT
ROTXR.W #2, Rd R:W NEXT
Rev. 2.0, 11/ 00, page 903 of 1037
Instruction 1 2 3 4 5 6 7 8 9
ROTXR.L ERd R:W NEXT
ROTXR.L #2.ERd R:W NEXT
RTE R:W NEXT R:W
stack(EXR) R:W stack(H) R:W stack(L) Internal
operation 1
state
R:W *4
RTS R:W NEXT R:W:M
stack(H) R:W stack (L) Internal
operation 1
state
R:W *4
SHAL.B Rd R:W NEXT
SHAL B #2,Rd R:W NEXT
SHAL.W Rd R:W NEXT
SHAL.W #2 , Rd R:W NEXT
SHAL.L ERd R:W NEXT
SHAL.L #2,ERd R:W NEXT
SHAR.B Rd R:W NEXT
SHAR.B #2,Rd R:W NEXT
SHAR.W Rd R:W NEXT
SHAR.W #2,Rd R:W NEXT
SHAR.L ERd R:W NEXT
SHAR.L #2,ERd R:W NEXT
SHLL.B Rd R:W NEXT
SHLL.B #2,Rd R:W NEXT
SHLL .W Rd R:W NEXT
SHLL.W #2,Rd R:W NEXT
SHLL.L ERd R:W NEXT
SHLL.L #2,ERd R:W NEXT
SHLR.B Rd R:W NEXT
SHLR.B #2,Rd R:W NEXT
SHLR.W Rd R: W NEXT
SHLR.W #2,Rd R:W NEXT
SHLR.L ERd R:W NEXT
SHLR.L #2 , ERd R:W NEXT
SLEEP R:W NEXT Internal
operation: M
STC CCR,Rd R:W NEX T
STC EXR,Rd R:W NEXT
STC CCR,@ERd R:W 2nd R:W NEXT W: W EA
STC EXR,@ERd R:W 2nd R:W NEXT W:W EA
STC CCR,@(d:16,ERd ) R:W 2nd R:W 3rd R:W NEXT W: W EA
STC EXR,@(d:16,ERd ) R:W 2 nd R:W 3rd R:W NEXT W:W EA
STC CCR,@(d:32,ERd ) R:W 2nd R:W 3rd R:W 4t h R: W 5th R:W NE X T W:W EA
STC EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA
STC CCR,@-ERd R:W 2n d R:W NEXT Internal
operation 1
state
W:W EA
STC EXR, @-E Rd R:W 2nd R:W NEXT Intern al
operation 1
state
W:W EA
STC CCR,@a a:1 6 R: W 2nd R:W 3rd R:W NEXT W:W E A
STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA
STC CCR,@a a:3 2 R: W 2nd R:W 3rd R:W 4th R:W NEXT W:W E A
STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
STM.L (ERn-
ERn+1),@-SP R:W 2nd R:W:M NEXT Internal
operation 1
state
W:W:M
stack (H) *3W:W
stack (L) *3
STM.L (ERn-
ERn+2),@-SP R:W 2nd R:W:M NEXT Internal
operation 1
state
W:W:M
stack (H) *3W:W
stack (L) *3
STM.L (ERn-
ERn+3),@-SP R:W 2nd R:W:M NEXT Internal
operation 1
state
W:W:M
stack (H) *3W:W
stack (L) *3
Rev. 2.0, 11/ 00, page 904 of 1037
Instruction 1 2 3 4 5 6 7 8 9
STMAC MACH,ERd
STMAC MACL, E Rd
Cannot be used in this LSI.
SUB.B Rs,Rd R:W NEXT
SUB.W #xx:16,Rd R:W 2nd R:W NEXT
SUB.W Rs,Rd R:W NEXT
SUB.L #xx:32,ERd R:W 2nd R:W 3nd R:W NEXT
SUB.L ERs,ERd R:W NEXT
SUB #1/2/ 4,ERd R:W NEXT
SUBX #xx : 8,Rd R:W NEXT
SUBX Rs,Rd R:W NEXT
TAS @ERd*8R:W 2nd R:W NEXT R:B:M EA W:B EA
TRAPA #x:2 R:W NEXT Inte rnal
operation 1
state
W:W stack(L) W:W stack(H) W:W
stack(EXR) R:W:M VEC R:W VEC+2 Internal
operation 1
state
R:W *7
XOR.B #xx :8,Rd R:W NEXT
XOR.B Rs,Rd R:W NEXT
XOR.W # xx :16,Rd R:W 2nd R:W NE X T
XOR.W Rs,Rd R:W NEXT
XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
XOR.L ERs,ERd R:W 2nd R:W NEXT
XORC #x x:8,CCR R:W NE X T
XORC #x x:8,EXR R: W 2nd R:W NEXT
Reset exception
handling R:W:M VEC R:W VEC+2 Intern al
operation 1
state
R:W *5
Interrupt exc eption
handling R:W *6Internal
operation 1
state
W:W stack(L) W:W stack(H) W:W
stack(EXR) R:W:M VEC R:W VEC+2 Internal
operation 1
state
R:W *7
Notes: 1. EAs is t he cont ent s of ER5, and EAd is the contents of ER6.
2. 1 is added to EAs and EAd after execut ion. n is the initial value of R4L or R4. W hen
0 is set to n, R4L or R4 is not execut ed.
3. Repeated twice for 2- unit r et r act / r et ur n, thr ee t imes for 3- unit r et r act/r et ur n, and f our
times for 4-retract/return.
4. Head address after r et ur n.
5. Start addr ess of the pr ogr am .
6. Pre-fet c h addr ess obt ained by adding 2 to t he PC to be r et r act ed.
When ret ur ning fr om sleep m ode, st andby m ode or wat ch m ode, inter nal oper at ion is
executed instead of r ead oper at ion.
7. Head address of the inter r upt pr ocess r out ine.
8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.0, 11/ 00, page 905 of 1037
A.6 Change of Condition Codes
This section explains change of condition codes after instruction execution of the CPU. Legend
of the following tables is as follows.
m = 31: L ongword size
m = 15: W ord size
m = 7: Byte size
Si: Bit i of source opera nd
Di: Bit i of de sti nat i on opera nd
Ri: Bit i of result
Dn: Specified bit of destination operand
−: No affection
: Cha nges depe ndi ng on exe c uti on re sult
0: Always cleared to 0
1: Always se t to 1
*: Value undetermined
Z': Z fl a g before e xec ut ion
C': C fl a g before e xec ut ion
Rev. 2.0, 11/ 00, page 906 of 1037
Tabl e A.7 Change of Co ndi t i o n Co de
Instruc-
tion H N Z V C Definition
ADD H=Sm-4⋅Dm-4+Dm-4⋅
5P
+Sm-4⋅
5P
N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
V=Sm⋅Dm⋅
5P
+
6P
⋅
'P
⋅Rm
C=Sm⋅Dm+Dm⋅
5P
+Sm⋅
5P
ADDS −−−−−
ADDX H=Sm-4⋅Dm-4+Dm-4⋅
5P
+Sm-4⋅
5P
N=Rm
Z=Z'⋅
5P
⋅
⋅
5
V=Sm⋅Dm⋅
5P
+
6P
⋅
'P
⋅Rm
C=Sm⋅Dm+Dm⋅
5P
+Sm⋅
5P
AND −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
ANDC Value in the bit corresponding t o execut ion
result is stor ed.
No flag change when EXR.
BAND −−−− C=C'⋅Dn
Bcc −−−−−
BCLR −−−−−
BIAND −−−− C=C'⋅
'Q
BILD −−−− C=
'Q
BIOR −−−− C=C'+
'Q
BIST −−−−−
BIXOR −−−− C=C'⋅Dn+
&
⋅
'Q
BLD −−−− C=Dn
BNOT −−−−−
BOR −−−− C=C'+Dn
BSET −−−−−
BSR −−−−−
BST −−−−−
BTST −− −−Z=
'Q
BXOR −−−− C=C'⋅
'Q
+
&
⋅Dn
CLRMAC Cannot be used in this LSI .
Rev. 2.0, 11/ 00, page 907 of 1037
Instruc-
tion H N Z V C Definition
CMP H=Sm-4⋅
'P
+
'P
⋅Rm-4+Sm-4⋅Rm-4
N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
V=
6P
⋅Dm⋅
5P
+Sm⋅
'P
⋅Rm
C=Sm⋅
'P
+
'P
⋅Rm+Sm⋅Rm
DAA **N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C: Decimal addition carry
DAS **N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C: Decimal subtraction borr ow
DEC − − N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
V=Dm⋅
5P
DIVXS −−−N=Sm⋅
'P
+
6P
⋅Dm
Z=
6P
⋅
6P
⋅
⋅
6
DIVXU −−−N=Sm
Z=
6P
⋅
6P
⋅
⋅
6
EEPMOV −−−−−
EXTS −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
EXTU −0 0 −Z=
5P
⋅
5P
⋅
⋅
5
INC − − N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
V=
'P
⋅
5P
JMP −−−−−
JSR −−−−−
LDC Value in t he bit cor r esponding to execution
result is stor ed.
No flag change when EXR.
LDM −−−−−
LDMAC
MAC
Cannot be used in this LSI.
MOV −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
Rev. 2.0, 11/ 00, page 908 of 1037
Instruc-
tion H N Z V C Definition
MOVFPE
MOVTPE
Cannot be used in this LSI.
MULXS −−−N=R2m
Z=
5P
⋅
5P
⋅
⋅
5
MULXU −−−−−
NEG H=Dm-4+Rm-4
N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
V=Dm⋅Rm
C=Dm+Rm
NOP −−−−−
NOT −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
OR −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
ORC Value in the bit cor responding to execution
result is stor ed. No flag change when EXR.
POP −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
PUSH −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
ROTL −0N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C=Dm(In case of 1 bit ) , C=Dm-1( I n case of 2
bits)
ROTR −0N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C=D0(In case of 1 bit), C=D-1(In case of 2 bits)
ROTXL −0N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C=Dm(In case of 1 bit), C= Dm- 1(In case of 2 bits)
ROTXR −0N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C=D0(In case of 1 bit), C=D1 (In case of 2 bits)
RTE Value in the bit corresponding t o execut ion
result is stor ed.
RTS −−−−−
Rev. 2.0, 11/ 00, page 909 of 1037
Instruc-
tion H N Z V C Definition
SHAL −N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
V=Dm⋅Dm-1+
'P
⋅
'P
(In case of 1 bit)
V=Dm⋅Dm-1⋅Dm-2⋅
'P
⋅
'P
⋅
'P
(In case of 2bits)
C=Dm(In case of 1 bit), C= Dm- 1(In case of 2 bits)
SHAR −0N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C=D0(In case of 1 bit), C=D1 (In case of 2 bits)
SHLL −0N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C=Dm(In case of 1 bit), C= Dm- 1(In case of 2 bits)
SHLR −0 0 N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
C=D0(In case of 1 bit), C=D1 (In case of 2 bits)
SLEEP −−−−−
STC −−−−−
STM −−−−−
STMAC Cannot be used in this LSI.
SUB H=Sm-4⋅
'P
+
'P
⋅Rm-4+Sm-4⋅Rm-4
N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
V=
6P
⋅Dm⋅
5P
+Sm⋅
'P
⋅Rm
C=Sm⋅
'P
+
'P
⋅Rm+Sm⋅Rm
SUBS −−−−−
SUBX H=Sm-4⋅
'P
+
'P
⋅Rm-4+Sm-4⋅Rm-4
N=Rm
Z=Z'⋅
5P
⋅
⋅
5
V=
6P
⋅Dm⋅
5P
+Sm⋅
'P
⋅Rm
C=Sm⋅
'P
+
'P
⋅Rm+Sm⋅Rm
TAS −0−N=Dm
Z=
'P
⋅
'P
⋅
⋅
'
TRAPA −−−−−
XOR −0−N=Rm
Z=
5P
⋅
5P
⋅
⋅
5
XORC Value in the bit cor r esponding t o execut ion
result is stor ed. No flag change when EXR.
Rev. 2.0, 11/ 00, page 910 of 1037
Appendix B Internal I/O Registers
B.1 Addresses
Address*Register
Name R/W Access Bus
Width76543210Module
Name
H'D000 DGKp15 DGKp14 DGKp13 DGKp12 DGKp11 DGKp10 DGKp9 DGKp8
H'D001
DGKp W 16 16
DGKp7 DGKp6 DGKp5 DGKp4 DGKp3 DGKp2 DGKp1 DGKp0
H'D002 DGKs15 DGKs14 DGKs13 DGKs12 DGKs11 DGKs10 DGKs9 DGKs8
H'D003
DGKs W 16 16
DGKs7 DGKs6 DGKs5 DGKs4 DGKs3 DGKs2 DGKs1 DGKs0
H'D004 DAp15 DAp14 DAp13 DAp12 DAp11 DAp10 DAp9 DAp8
H'D005
DAp W 16 16
DAp7 DAp6 DAp5 DAp4 DAp3 DAp2 DAp1 DAp0
H'D006 DBp15 DBp14 DBp13 DBp12 DBp11 DBp10 DBp9 DBp8
H'D007
DBp W 16 16
DBp7 DBp6 DBp5 DBp4 DBp3 DBp2 DBp1 DBp0
H'D008 DAs15 DAs14 DAs13 DAs12 DAs11 DAs10 DAs9 DAs8
H'D009
DAs W 16 16
DAs7 DAs6 DAs5 DAs4 DAs3 DAs2 DAs1 DAs0
H'D00A DBs15 DBs14 DBs13 DBs12 DBs11 DBs10 DBs9 DBs8
H'D00B
DBs W 16 16
DBs7 DBs6 DBs5 DBs4 DBs3 DBs2 DBs1 DBs0
H'D00C DOfp15 DOfp14 DOfp13 DOfp12 DOfp11 DOfp10 DOfp9 DOfp8
H'D00D
DOfp W 16 16
DOfp7 DOfp6 DOfp5 DOfp4 DOfp3 DOfp2 DOfp1 DOfp0
H'D00E DOfs15 DOfs14 DOfs13 DOfs12 DOfs11 DOfs10 DOfs9 DOfs8
H'D00F
DOfs W 16 16
DOfs7 DOfs6 DOfs5 DOfs4 DOfs3 DOfs2 DOfs1 DOfs0
Drum digital
filter
H'D010 CGKp15 CGKp14 CGKp13 CGKp12 CGKp11 CGKp10 CGKp9 CGKp8
H'D011
CGKp W 16 16
CGKp7 CGKp6 CGKp5 CGKp4 CGKp3 CGKp2 CGKp1 CGKp0
H'D012 CGKs15 CGKs14 CGKs13 CGKs12 CGKs11 CGKs10 CGKs9 CGKs8
H'D013
CGKs W 16 16
CGKs7 CGKs6 CGKs5 CGKs4 CGKs3 CGKs2 CGKs1 CGKs0
H'D014 CAp15 CAp14 CAp13 CAp12 CAp11 CAp10 CAp9 CAp8
H'D015
CAp W 16 16
CAp7 CAp6 CAp5 CAp4 CAp3 CAp2 CAp1 CAp0
H'D016 CBp15 CBp14 CBp13 CBp12 CBp11 CBp10 CBp9 CBp8
H'D017
CBp W 16 16
CBp7 CBp6 CBp5 CBp4 CBp3 CBp2 CBp1 CBp0
H'D018 CAs15 CAs14 CAs13 CAs12 CAs11 CAs10 CAs9 CAs8
H'D019
CAs W 16 16
CAs7 CAs6 CAs5 CAs4 CAs3 CAs2 CAs1 CAs0
H'D01A CBs15 CBs14 CBs13 CBs12 CBs11 CBs10 CBs9 CBs8
H'D01B
CBs W 16 16
CBs7 CBs6 CBs5 CBs4 CBs3 CBs2 CBs1 CBs0
H'D01C COfp15 COfp14 COfp13 COfp12 COfp11 COfp10 COfp9 COfp8
H'D01D
COfp W 16 16
COfp7 COfp6 COfp5 COfp4 COfp3 COfp2 COfp1 COfp0
H'D01E COfs15 COfs14 COfs13 COfs12 COfs11 COfs10 COfs9 COfs8
H'D01F
COfs W 16 16
COfs7 COfs6 COfs5 COfs4 COfs3 COfs2 COfs1 COfs0
Capstan
digital filter
H'D020 −−−−DZs11 DZs10 DZs9 DZs8
H'D021
DZs W 16 16
DZs7 DZs6 DZs5 DZs4 DZs3 DZs2 DZs1 DZs0
H'D022 −−−−DZp11 DZp10 DZp9 DZp8
H'D023
DZp W 16 16
DZp7 DZp6 DZp5 DZp4 DZp3 DZp2 DZp1 DZp0
H'D024 −−−−CZs11 CZs10 CZs9 CZs8
H'D025
CZs W 16 16
CZs7 CZs6 CZs5 CZs4 CZs3 CZs2 CZs1 CZs0
H'D026 −−−−CZp11 CZp10 CZp9 CZp8
H'D027
CZp W 16 16
CZp7 CZp6 CZp5 CZp4 CZp3 CZp2 CZp1 CZp0
H'D028 DFIC R/W 8 −DROV DPHA DZPON DZSON DSG2 DSG1 DSC0
H'D029 CFIC R/W 8
16
−CROV CPHA CZPON CZSON CSG2 CSG1 CSG0
H'D02A DFUCR R/W 8 16 −−PTON CP/
'3
CFEPS DFEPS CFESS DFESS
Digital filter
Rev. 2.0, 11/ 00, page 911 of 1037
Address*Register
Name R/W Access Bus
Width76543210Module
Name
H'D030 DFPR15 DFPR14 DFPR13 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8
H'D031
DFPR W 16 16
DFPR7 DFPR6 DFPR5 DFPR4 DFPR3 DFPR2 DFPR1 DFPR0
H'D032 DFER15 DFER14 DFER13 DFER12 DFER11 DFER10 DFER9 DFER8
H'D033
DFER R/W 16 16
DFER7 DFER6 DFER5 DFER4 DFER3 DFER2 DFER1 DFER0
H'D034 DFRUDR1
5DFRUDR1
4DFRUDR1
3DFRUDR1
2DFRUDR1
1DFRUDR1
0DFRUDR9 DFRUDR8
H'D035
DFRUDR W 16 16
DFRUDR7 DFRUDR6 DFRUDR5 DFRUDR4 DFRUDR3 DFRUDR2 DFRUDR1 DFRUDR0
H'D036 DFRLDR15 DFRLDR14 DFRLDR13 DFRLDR12 DFRLDR11 DFRLDR10 DFRLDR9 DFRLDR8
H'D037
DFRLDR W 16 16
DFRLDR7 DFRLDR6 DFRLDR5 DFRLDR4 DFRLDR3 DFRLDR2 DFRLDR1 DFRLDR0
H'D038 DFVCR R/W 8 16 DFCS1 DFCS0 DFOVF DFRFON DF-R/UNR OPCNT DFRCS1 DFRCS0
H'D039 DPGCR R/W 8 16 DPCS1 DPCS0 DPOVF N/V HSWES −−−
H'D03A DPPR15 DPPR14 DPPR13 DPPR12 DPPR11 DPPR10 DPPR9 DPPR8
H'D03B
DPPR2 W 16 16
DPPR7 DPPR6 DPPR5 DPPR4 DPPR3 DPPR2 DPPR1 DPPR0
H'D03C DPPR1 W 8 16 −−−−DPPR19 DPPR18 DPPR17 DPPR16
H'D03D DPER1 W 8 16 −−−−DPER19 DPER18 DPER17 DPER16
H'D03E DPER15 DPER14 DPER13 DPER12 DPER11 DPER10 DPER9 DPER8
H'D03F
DPER2 W 16 16
DPER7 DPER6 DPER5 DPER4 DPER3 DPER2 DPER1 DPER0
Drum error
detector
H'D050 CFPR15 CFPR14 CFPR13 CFPR12 CFPR11 CFPR10 CFPR9 CFPR8
H'D051
CFPR W 16 16
CFPR7 CFPR6 CFPR5 CFPR4 CFPR3 CFPR2 CFPR1 CFPR0
H'D052 CFER15 CFER14 CFER13 CFER12 CFER11 CFER10 CFER9 CFER8
H'D053
CFER R/W 16 16
CFER7 CFER6 CFER5 CFER4 CFER3 CFER2 CFER1 CFER0
H'D054 CFRUDR1
5CFRUDR1
4CFRUDR1
3CFRUDR1
2CFRUDR1
1CFRUDR1
0CFRUDR9 CFRUDR8
H'D055
CFRUDR W 16 16
CFRUDR7 CFRUDR6 CFRUDR5 CFRUDR4 CFRUDR3 CFRUDR2 CFRUDR1 CFRUDR0
H'D056 CFRLDR15 CFRLDR14 CFRLDR13 CFRLDR12 CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8
H'D057
CFRLDR W 16 16
CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0
H'D058 CFVCR R/W 8 16 CFCS1 CFCS0 CFOVF CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0
H'D059 CPGCR R/W 8 16 CPCS1 CPCS0 CPOVF CR/RF SELCFG2 −−−
H'D05A CPH15 CPH14 CPH13 CPH12 CPH11 CPH10 CPH9 CPH8
H'D05B
CPPR2 W 16 16
CPH7 CPH6 CPH5 CPH4 CPH3 CPH2 CPH1 CPH0
H'D05C CPPR1 W 8 16 −−−−CPH19 CPH18 CPH17 CPH16
H'D05D CPER1 W 8 16 −−−−CPER19 CPER18 CPER17 CPER16
H'D05E CPER15 CPER14 CPER13 CPER12 CPER11 CPER10 CPER9 CPER8
H'D05F
CPER2 W 16 16
CPER7 CPER6 CPER5 CPER4 CPER3 CPER2 CPER1 CPER0
Capstan
error detector
H'D060 HSM1 R/W 8 FLB FLA EMPB EMPA OVWB OVWA CLRB CLRA
H'D061 HSM2 R/W 8
16
FRT FGR2OFF LOP EDG ISEL SOFG OFG VFF/NFF
H'D062 HSLP W 8 16 LOB3 LOB2 LOB1 LOB0 LOA3 LOA2 LOA1 LOA0
H'D064 −ADTRGA STRIGA NarrowFFA VFFA AFFA VpulseA MlevelA
H'D065
FPDRA W 16 16
PPGA7 PPGA6 PPGA5 PPGA4 PPGA3 PPGA2 PPGA1 PPGA0
H'D066 FTPRA*W 16 FTPRA15 FTRPA14 FTRPA13 FTRPA12 FTRPA11 FTRPA10 FTRPA9 FTRPA8
H'D066 FTCTR*R16
16
FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8
H'D067 FTPRA*W 16 FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0
H'D067 FTCTR*R16
16
FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0
H'D068 −ADTRGB STRIGB NarrowFFB VFFB AFFB VpulseB MlevelB
H'D069
FPDRB W 16 16
PPGB7 PPGB6 PPGB5 PPGB4 PPGB3 PPGB2 PPGB1 PPGB0
H'D06A FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8
H'D06B
FTPRB W 16 16
FTPRB7 FTPRB6 FTPRB5 FTPRB4 FPTRB3 FPTRB2 FPTRB1 FPTRB0
H'D06C DFCTR*W 8 ISEL2 CCLR CKSL DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0
H'D06C DFCRB R 8
16
−−−DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0
H'D06D DFCRB W 8 16 −−−DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0
HSW timing
generator
* Assign to
the same
address.
H'D06E CHCR W 8 V/N HSWPOL CRH HAH SIG3 SIG2 SIG1 SIG0 4-head
special-
effects
playback
H'D06F ADDVR R/W 8
16
−−−HMSK HIZ CUT VPON POL Additional V
Rev. 2.0, 11/ 00, page 912 of 1037
Address*Register
Name R/W Access Bus
Width76543210Module
Name
H'D070 −−−−XR11 XR10 XR9 XR8
H'D071
XDR W 16 16
XR7 XR6 XR5 XR4 XR3 XR2 XR1 XR0
H'D072 −−−−TRD11 TRD10 TRD9 TRD8
H'D073
TRDR W 16 16
TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0
H'D074 XTCR R/W 8 16 −CAPRF AT/
08
TRK/
;
EXC/REF XCS DVRER1 DVREF0
X-value,
TRK-value
H'D078 −−−−DPWDR11 DPWDR10 DPWDR9 DPWDR8
H'D079
DPWDR R/W 16 16
DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0
H'D07A DPWCR W 8 DPOL DDC DHIZ DH/L DSFDF DCK2 DCK1 DCK0
Drum 12-bit
PWM
H'D07B CPWCR W 8
16
CPOL CDC CHIZ CH/L CSF/DF CCK2 CCK1 CCK0
H'D07C −−−−CPWDR11 CPWDR10 CPWDR9 CPWDR8
H'D07D
CPWDR R/W 16 16
CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0
Capstan 12-
bit PWM
H'D080 CTCR W 8 NT/PAL FLSC FLSB FSLA CCS LCTL UNCTL SLWM
H'D081 CTLM R/W 8
16
ASM REC/
3%
FW/RV MD4 MD3 MD3 MD1 MD0
H'D082 −−−−CMT1B CMT1A CMT19 CMT18
H'D083
RCDR1 W 16 16
CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10
H'D084 −−−−CMT2B CMT2A CMT29 CMT28
H'D085
RCDR2 W 16 16
CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20
H'D086 −−−−CMT3B CMT3A CMT39 CMT38
H'D087
RCDR3 W 16 16
CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30
H'D088 −−−−CMT4B CMT4A CMT49 CMT48
H'D089
RCDR4 W 16 16
CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40
H'D08A −−−−CMT5B CMT5A CMT59 CMT58
H'D08B
RCDR5 W 16 16
CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50
H'D08C DI/O R/W 8 VCTR2 VCTR1 VCTR0 −BPON BPS BPF DI/O
H'D08D BTPR R/W 8
16
LSP7 LSP6 LSP5 LSP4 LSP3 LSP2 LSP1 LSP0
CTL circuit
H'D090 REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8
H'D091
RFD W 16 16
REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0
H'D092 CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8
H'D093
CRF W 16 16
CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0
H'D094 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8
H'D095
RFC R/W 16 16
RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0
H'D096 RFM R/W 8 RCF VNA CVS REX CRD OD/EV VST VEG
H'D097 RFM2 R/W 8
16
(TBC)*−−−−−−FDS
Reference
signal
generator
* The TBC
bit is
available
only in the
H8S/2194C
series.
H'D098 CTVC R/W 8 CEX CEG −−−CFG HSW CTL
H'D099 CTLR W 8
16
CTL7 CTL6 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0
H'D09A CDVC R/W 8 MCGain CMK CMN DVTRG CRF CPS1 CPS0
H'D09B CDIVR1 W 8
16
−CDV16 CDV15 CDV14 CDV13 CDV12 CDV11 CDV10
H'D09C CDIVR2 W 8 −CDV26 CDV25 CDV24 CDV23 CDV22 CDV21 CDV20
H'D09D CTMR W 8
16
−−CPM5 CPM4 CPM3 CPM2 CPM1 CPM0
H'D09E FGCR W 8 16 −−−−−−−DRF
Frequency
divider
H'D0A0 SPMR R/W 8 8 CTLSTOP −CFGCOMP EXCELON DPGSW COMP H.Amp.SW C.Rot
H'D0A1 SPCR R/W 8 8 −−−SPCR4 SPCR3 SPCR2 SPCR1 SPCR0
H'D0A2 SPDR R/W 8 8 −−−SPDR4 SPDR3 SPDR2 SPDR1 SPDR0
H'D0A3 SVMCR R/W 8 8 −−SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0
H'D0A4 CTLGR R/W 8 8 −−−CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0
Servo port
control
Rev. 2.0, 11/ 00, page 913 of 1037
Address*Register
Name R/W Access Bus
Width76543210Module
Name
H'D0B0 VTR W 8 16 −−VTR5 VTR4 VTR3 VTR2 VTR1 VTR0
H'D0B1 HTR W 8 16 −−−−HTR3 HTR2 HTR1 HTR0
H'D0B2 HRTR W 8 16 HRTR7 HRTR6 HRTR5 HRTR4 HRTR3 HRTR2 HRTR1 HRTR0
H'D0B3 HPWR W 8 16 −−−−HPWR3 HPWR2 HPWR1 HPWR0
H'D0B4 NWR W 8 16 −−NWR5 NWR4 NWR3 NWR2 NWR1 NWR0
H'D0B5 NDR W 8 16 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
H'D0B6 SYNCR R/W 8 16 −−−−NID/VD NOIS FLD SYCT
Sync
detector
H'D0B8 SIENR1 R/W 8 16 IEDR3 IEDR2 IEDR1 IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1
H'D0B9 SIENR2 R/W 8 16 −−−−−−IESNC IESTL
H'D0BA SIRQR1 R/W 8 16 IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
H'D0BB SIRQR2 R/W 8 16 −−−−−−IRRSNC IRRCTL
Servo
interrupt
control
H'D0C0 R/W 8 8
H'D0C1 R/W 8 8
H'D0C2 R/W 8 8
H'D0C3 R/W 8 8
H'D0C4 R/W 8 8
H'D0C5 R/W 8 8
H'D0C6 R/W 8 8
H'D0C7 R/W 8 8
H'D0C8 R/W 8 8
H'D0C9 R/W 8 8
H'D0CA R/W 8 8
H'D0CB R/W 8 8
H'D0CC R/W 8 8
H'D0CD R/W 8 8
H'D0CE R/W 8 8
H'D0CF
32 byte Data
Buffer
R/W 8 8
32-byte
buffer SCI2
H'D0D0 R/W 8 8
H'D0D1 R/W 8 8
H'D0D2 R/W 8 8
H'D0D3 R/W 8 8
H'D0D4 R/W 8 8
H'D0D5 R/W 8 8
H'D0D6 R/W 8 8
H'D0D7 R/W 8 8
H'D0D8 R/W 8 8
H'D0D9 R/W 8 8
H'D0DA R/W 8 8
H'D0DB R/W 8 8
H'D0DC R/W 8 8
H'D0DD R/W 8 8
H'D0DE R/W 8 8
H'D0DF
32 byte Data
Buffer
R/W 8 8
32-byte
buffer SCI2
H'D0E0 STAR R/W 8 8 −−−STA4 STA3 STA2 STA1 STA0
H'D0E1 EDAR R/W 8 8 −−−EDA4 EDA3 EDA2 EDA1 EDA0
H'D0E2 SCR2 R/W 8 8 TEIE ABTIE −GAP1 GAP0 CKS2 CKS1 CKS0
H'D0E3 SCSR2 R/W 8 8 TEI −−SOL ORER WT ABT STF
32-byte
buffer SCI2
Rev. 2.0, 11/ 00, page 914 of 1037
Address*Register
Name R/W Access Bus
Width76543210Module
Name
H'D100 TIER R/W 8 16 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA
H'D101 TCSRX R/W 8 16 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
H'D102 FRCH FRCH7 FRCH6 FRCH5 FRCH4 FRCH3 FRCH2 FRCH1 FRCH0
H'D103 FRCL
R/W 8/16 16
FRCL7 FRCL6 FRCL5 FRCL4 FRCL3 FRCL2 FRCL1 FRCL0
H'D104 OXRAH*OCRAH7 OCRAH6 OCRAH5 OCRAH4 OCRAH3 OCRAH2 OCRAH1 OCRAH0
H'D105 OCRAL*
R/W 8/16 16
OCRAL7 OCRAL6 OCRAL5 OCRAL4 OCRAL3 OCRAL2 OCRAL1 OCRAL0
H'D104 OCRBH*OCRBH7 CORBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0
H'D105 OCRBL*
R/W 8/16 16
OCRBL7 OCRBL6 OCRBL5 CORBL4 CORBL3 CORBL2 CORBL1 CORBL0
H'D106 TCRX R/W 8 16 IEDGA IEDGB IEDGC IEDGD BUFEA FUFEB CKS1 CKS0
H'D107 TOCR R/W 8 16 ICSB ICSC ICSD OCRS OEA OEB OLVLA OLVLB
H'D108 ICRAH ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0
H'D109 ICRAL
R8/1616
ICRAL7 ICRAL6 ICRAL5 ICRAL4 ICRAL3 ICRAL2 ICRAL1 ICRAL0
H'D10A ICRBH ICRBH7 ICRBH6 ICRBH5 ICRBH4 ICRBH3 ICRBH2 ICRBH1 ICRBH0
H'D10B ICRBL
R8/1616
ICRBL7 ICRBL6 ICRBL5 ICRBL4 ICRBL3 ICRBL2 ICRBL1 ICRBL0
H'D10C ICRCH ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0
H'D10D ICRCL
R8/1616
ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0
H'D10E ICRDH ICRDH7 ICRDH6 ICRDH5 ICRDH4 ICRDH3 ICRDH2 ICRDH1 ICRDH0
H'D10F ICRDL
R8/1616
ICRDL7 ICRDL6 ICRDL5 ICRDL4 ICRDL3 ICRDL2 ICRDL1 ICRDL0
Timer X1
* OCRA and
OCRB
addresses
are the
same.
Switched by
OCSR bit in
IOCR.
H'D110 TMB R/W 8 8 TMB17 TMBIF TMPIE −−TMP12 TMP11 TCB10
H'D111 TCB R 8 8 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10
H'D111 TLB W 8 8 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10
Timer B
H'D112 LMR R/W 8 8 LMIF LMIE −−LMR3 LMR2 LMR1 LMR0
H'D113 LTC R 8 8 LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0
H'D113 RCR W 8 8 RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0
Timer L
H'D118 TMRM1 R/W 8 8 CLR2 AC/BR RLD RLCK PS21 PC20 RLD/CAP CPS
H'D119 TMRM2 R/W 8 8 LAT RS11 PS10 PS31 PS30 CP/SLM CAPF SLW
H'D11A TMRCP1 R 8 8 TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10
H'D11B TMRCP2 R 8 8 TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20
H'D11C TMRL1 W 8 8 TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
H'D11D TMRL2 W 8 8 TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20
H'D11E TMRL3 W 8 8 TMR37 TMR36 TMR35 TMR34 TMR33 TMR32 TMR31 TMR30
H'D11F TMRCS R/W 8 8 TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 −−
Timer R
H'D120 PWDRL W 8 8 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
H'D121 PWDRU W 8 8 −−PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
H'D122 PWCR R/W 8 8 −−−−−−−PWMCR0
14-bit PWM
H'D126 PWR0 W 8 8 PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
H'D127 PWR1 W 8 8 PW17 PW16 PW15 PW14 PW13 PW12 PW11 PW10
H'D128 PWR2 W 8 8 PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20
H'D129 PWR3 W 8 8 PW37 PW36 PW35 PW34 PW33 PW32 PW31 PW30
H'D12A PW8CR R/W 8 8 −−−−PWC3 PWC2 PWC1 PWC0
8-bit PWM
H'D12C ICR1 R 8 8 ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 CIR10
H'D12D PCSR R/W 8 8 ICIF ICIE ICEG NCon/off −DCS2 DCS1 DCS0
PSU
Rev. 2.0, 11/ 00, page 915 of 1037
Address*Register
Name R/W Access Bus
Width76543210Module
Name
H'D130 ADRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2
H'D131 ADRL R16 8 ADR1 ADR0
H'D132 AHRH AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2
H'D133 AHRL R16 8 AHR1 AHR0
H'D134 ADCR R/W 8 8 CK HCH1 HCH0 SCH3 SCH2 SCH1 SCH0
H'D135 ADCSR R/W 8 8 SEND HEND ADIE SST HST BUSY SCNL
H'D136 ADTSR R/W 8 8 TRGS1 TRGS0
A/D
H'D138 TLK W 8/16 16 TLR27 TLR26 TLR25 TLR24 TLR23 TLR22 TLR21 TLR20
H'D138 TCK R 8/16 16 TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10
H'D139 TLJ W 8/16 16 TDR27 TDR26 TDR25 TDR24 TDR23 TDR22 TDR21 TDR20
H'D139 TCJ R 8/16 16 TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10
H'D13A TMJ R/W 8/16 16 PS11 PS10 ST 8/16 PS21 PS20 TGL T/R
H'D13B TMJC R/W 8/16 16 BUZZ1 BUZZ0 MON1 MON0 TMJ2IE TMJ1IE (PS22)*
H'D13C TMJS R/W 8/16 16 TMJ2I TMJ1I
Timer J
* The PS2 2
bit is
available
only in the
H8S/2194C
series.
H'D148 SMR1 R/W 8 8 C/
$
CHR PE O/
(
STOP MP CKS1 CKS0
H'D149 BRR1 R/W 8 8
H'D14A SCR1 R/W 8 8 TEI RIE TE RE MPIE TEIE CKE1 CKE0
H'D14B TDR1 R/W 8 8
H'D14C SSR1 R/W 8 8 TDRE RDRF ORER FER PER TEMD MPB MPBT
H'D14D RDR1 R 8 8
H'D14E SCMR1 R/W 8 8 SDIR SINV SMIF
Clock
synchronizati
on/start-stop
sync SCI
H'D158 ICCR R/W 8 8 ICE IEIC MST TRS ACKE BBSY IRIC SCP
H'D159 ICSR R/W 8 8 ESTP STOP IRTR AASX AL AAS ADZ ACKB
H'D15E ICDR*R/W 8 8 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0
H'D15E SARX*R/W 8 8 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
H'D15F ICMR*R/W 8 8 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
H'D15F SAR*R/W 8 8 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
IIC interface
* Access
varies
depending
on ICE bit.
H'FFB0 TA023 TA022 TA021 TA020 TA019 TA018 TA017 TA016
H'FFB1 TA015 TA014 TA013 TA012 TA011 TA010 TA009 TA008
H'FFB2
TAR0 R/W 8 8
TA007 TA006 TA005 TA004 TA003 TA002 TA001
H'FFB3 TA123 TA122 TA121 TA120 TA119 TA118 TA117 TA116
H'FFB4 TA115 TA114 TA113 TA112 TA111 TA110 TA109 TA108
H'FFB5
TAR1 R/W 8 8
TA107 TA106 TA105 TA104 TA103 TA102 TA101
H'FFB6 TA223 TA222 TA221 TA220 TA219 TA218 TA217 TA216
H'FFB7 TA215 TA214 TA213 TA212 TA211 TA210 TA209 TA208
H'FFB8
TAR2 R/W 8 8
TA207 TA206 TA205 TA204 TA203 TA202 TA201
H'FFB9 TRCR R/W 8 8 TRC2 TRC1 TRC0
ATC
H'FFBA TMA R/W 8 8 TMAOV TMAIE TMA3 TMA2 TMA1 TMA0
H'FFBB TCA R 8 8 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Ti mer A
H'FFBC WTCSR R/W 8/16 16 OVF WT/
,7
TME RSTS RST/
10,
CKS2 CKS1 CKS0
H'FFBD WTCNT R/W 8/16 16 WDT
H'FFC0 PDR0 R 8 8 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00
H'FFC1 PDR1 R/W 8 8 PDR17 PDR16 PDR15 PDR14 PDR13 PDR12 PDR11 PDR10
H'FFC2 PDR2 R/W 8 8 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20
H'FFC3 PDR3 R/W 8 8 PDR37 PDR36 PDR35 PDR34 PDR33 PDR32 PDR31 PDR30
H'FFC4 PDR4 R/W 8 8 PDR47 PDR46 PDR45 PDR44 PDR43 PDR42 PDR41 PDR40
H'FFC5 PDR5 R/W 8 8 PDR53 PDR52 PDR51 PDR50
H'FFC6 PDR6 R/W 8 8 PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60
H'FFC7 PDR7 R/W 8 8 PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70
H'FFC8 PDR8 R/W 8 8 PDR87 PDR86 PDR85 PDR84 PDR83 PDR82 PDR81 PDR80
Port da t a
register
H'FFCD PMR0 R/W 8 8 PMR07 PMR06 PMR05 PMR04 PMR03 PMR02 PMR01 PMR00
H'FFCE PMR1 R/W 8 8 PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10
H'FFCF PMR2 R/W 8 8 PMR27 PMR26 PMR25 PMR20
Port mode
register
Rev. 2.0, 11/ 00, page 916 of 1037
Address*Register
Name R/W Access Bus
Width76543210Module
Name
H'FFD0 PMR3 R/W 8 8 PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR3 1 PMR30 Port mode
register
H'FFD1 PCR1 W 8 8 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10
H'FFD2 PCR2 W 8 8 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20
H'FFD3 PCR3 W 8 8 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30
H'FFD4 PCR4 W 8 8 PCR47 PCR46 PCR45 PCR44 PCR43 PCR42 PCR41 PCR40
H'FFD5 PCR5 W 8 8 PCR53 PCR52 PCR51 PCR50
H'FFD6 PCR6 W 8 8 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60
H'FFD7 PCR7 W 8 8 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70
H'FFD8 PCR8 W 8 8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR380
Port control
register
H'FFDB PMR4 R/W 8 8 PMR40
H'FFDC PMR5 R/W 8 8 PMR53 PMR52 PMR51 PMR50
H'FFDD PMR6 R/W 8 8 PMR67 PMR66 PMR65 PMR64 PMR63 PMR62 PMR61 PMR60
H'FFDE PMR7 R/W 8 8 PMR77 PMR76 PMR75 PMR74 PMR73 PMR72 PMR71 PMR70
H'FFDF PMR8 R/W 8 8 PMR83 PMR82 PMR81 PMR80
Port mode
register
H'FFE1 PUR1 R/W 8 8 PUR17 PUR16 PUR15 PUR14 PUR13 PUR12 PUR11 PUR10
H'FFE2 PUR2 R/W 8 8 PUR27 PUR26 PUR25 PUR24 PUR23 PUR22 PUR21 PUR20
H'FFE3 PUR3 R/W 8 8 PUR37 PUR36 PUR35 PUR34 PUR33 PUR32 PUR31 PUR30
Port pull-up
select
register
H'FFE4 RTPEGR R/W 8 8 RTPEGR1 RTPEGR0
H'FFE5 RTPSR R/W 8 8 RTPSR7 RTPSR6 RTPSR5 RTPSR4 RTPSR3 RTPSR2 RTPSR1 RTPSR0
RTP TRG
select
H'FFE8 SYSCR R/W 8 8 INTM1 INTM0 XRST NMIEG1 NMIEG0
H'FFE9 MDCR R/W 8 8 MDS0
H'FFEA SBYCR R/W 8 8 SSBY STS2 STS1 STS0 SCK1 SCK0
H'FFEB LPWRCR R/W 8 8 DTON LSON NESEL SA1 SA0
H'FFEC MSTPCRH R/W 8 8 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8
H'FFED MSTPCRL R/W 8 8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
H'FFEE STCR R/W 8 8 IICX IICRST FLASHE
System
control
register
H'FFF0 IEGR R/W 8 8 IRQ5EG IRQ4EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0 IRQ edge
H'FFF1 IENR R/W 8 8 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E IRQ enable
H'FFF2 IRQR R/W 8 8 IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F IRQ status
H'FFF3 ICRA R/W 8 8 ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0
H'FFF4 ICRB R/W 8 8 ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0
H'FFF5 ICRC R/W 8 8 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
H'FFF6 ICRD R/W 8 8 ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0
IRQ priority
control
H'FFF8 FLMCR1 R/W 8 8 FWE SWE EV PV E P
H'FFF9 FLMCR2 R/W 8 8 FLER ESU PSU
H'FFFA EBR1 R/W 8 8 EB9 EB8
H'FFFB EBR2 R/W 8 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Only for
FLASH
version.
H'FFF8 FLMCR1 R/W 8 8 FWE SWE ESU1 PSU1 EV1 PV1 E1 P1
H'FFF9 FLMCR2 R/W 8 8 FLER ESU2 PSU2 EV2 PV2 E2 P2
F'FFFA EBR1 R/W 8 8 EB13 EB12 EB11 EB10 EB9 EB8
F'FFFB EBR2 R/W 8 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Only for
FLASH
version in the
H8S/2194C
Note: *Lower 16 bits of t he addr ess.
Rev. 2.0, 11/ 00, page 917 of 1037
B.2 Fun c t i o n Li st
H'D000: Gain Constant DGKp: Drum Digital Filter
H'D001: Gain Constant DGKp: Drum Digital Filter
H'D002: Gain Constant DGKs: Drum Digital Filter
H'D003: Gain Constant DGKs: Drum Digital Filter
Bit :
Initial value :
R/W : *
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
H'D004: Coefficient DAp: Dr um Di g i t al Filter
H'D005: Coefficient DAp: Dr um Di g i t al Filter
H'D006: Coefficient DBp: Drum Digital Filter
H'D007: Coefficient DBp: Drum Digital Filter
H'D008: Coefficient DAs: Dr um Di g i t al Filter
H'D009: Coefficient DAs: Dr um Di g i t al Filter
H'D00A: Coefficient DBs: Drum Digital Filter
H'D00B: Coefficient DBs: Drum Digital Filter
Bit :
Initial value :
R/W : *
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Rev. 2.0, 11/ 00, page 918 of 1037
H'D00C: Offset DOfp: Drum Digital Filter
H'D00D: Offset DOfp: Drum Digital Filter
H'D00E: Offset DOfs: Drum Digital Filter
H'D00F: Offset DOfs: Drum Digital Filter
Bit :
Initial value :
R/W : *
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
H'D010: Gain Constant CGKp: Capstan Di gital Filter
H'D011: Gain Constant CGKp: Capstan Di gital Filter
H'D012: Gain Constant CGKs: Capstan Di gital Filter
H'D013: Gain Constant CGKs: Capstan Di gital Filter
Bit :
Initial value :
R/W : *
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Rev. 2.0, 11/ 00, page 919 of 1037
H'D014: Coefficient CAp: Capst a n Di g i t al Filter
H'D015: Coefficient CAp: Capst a n Di g i t al Filter
H'D016: Coefficient CBp: Capstan Digital Filter
H'D017: Coefficient CBp: Capstan Digital Filter
H'D018: Coefficient CAs: Capst a n Di g i t al Filter
H'D019: Coefficient CAs: Capst a n Di g i t al Filter
H'D01A: Coefficient CBs: Capstan Digital Filter
H'D01B: Coefficient CBs: Capstan Digital Filter
Bit :
Initial value :
R/W : *
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
H'D01C: Offset COfp: Capstan Digital Filter
H'D01D: Offset COfp: Capstan Digital Filter
H'D01E: Offset COfs: Capstan Digital Filter
H'D01F: Offset COfs: Capstan Digital Filter
Bit :
Initial value :
R/W : *
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Rev. 2.0, 11/ 00, page 920 of 1037
H'D020: Delay Initialization Register DZs: Digital filter
H'D021: Delay Initialization Register DZs: Digital filter
H'D022: Delay Initialization Register DZp: Digital filter
H'D023: Delay Initialization Register DZp: Digital filter
H'D024: Delay Initialization Register CZs: Digital filter
H'D025: Delay Initialization Register CZs: Digital filter
H'D026: Delay Initialization Register CZp: Digital filter
H'D027: Delay Initialization Register CZp: Digital filter
131415 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
WWWWWWW
12
000000
111
1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 921 of 1037
H'D028: Drum System Digital Filter Control Register DFIC: Digital Filter
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/(W)
DPHA
R/(W)*
DROV DZPON DZSON DSG2 DSG1 DSG0
1
Note: * Only 0 can be written.
Note: * Optional
Drum system range over flag
0 Filter computation result does not exceed 12 bits.
1 Filter computation result exceeds 12 bits.
Drum phase system filter computation start bit
0 Phase system filter computation is OFF.
Phase system computation result Y is not added to Es.
1 Phase system filter computation is ON.
Drum phase system Z
-1
initialization bit
0 Phase system Z
-1
reflects DZp value.
1 Phase system Z
-1
does not relect DZp value.
Drum speed system Z
-1
initialization bit
0 Speed system Z
-1
reflects DZs value.
1 Speed system Z
-1
does not relect DZs value.
Drum system gain control bit
DSG2 DSG1 DSG0 Description
0 0 0 x 1
1 x 2
1 0 x 4
1 x 8
1 0 0 x 16
1 (x 32)*
1 0 (x 64)*
1 Invalid (do not set)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 922 of 1037
H'D029: Capstan System Digital Filter Control Register CFIC: Digital Filter
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/(W)
CPHA
R/(W)*
CROV CZPON CZSON CSG2 CSG1 CSG0
1
Note: * Only 0 can be written.
Capstan system range over flag
0 Filter computation result does not exceed 12 bits.
1 Filter computation result exceeds 12 bits.
Capstan phase system filter computation start bit
0 Phase system filter computation is OFF.
Phase system computation result Y is not added to Es.
1 Phase system filter computation is ON.
Capstan phase system Z
-1
initialization bit
0 Phase system Z
-1
reflects CZp value.
1 Phase system Z
-1
does not relect CZp value.
Capstan speed system Z
-1
initialization bit
0 Speed system Z
-1
reflects CZs value.
1 Speed system Z
-1
does not relect CZs value.
Capstan system gain control bit
CSG2 CSG1 CSG0 Description
0 0 0 x 1
1 x 2
1 0 x 4
1 x 8
1 0 0 x 16
1 (x 32)*
1 0 (x 64)*
1 Invalid (do not set)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 923 of 1037
H'D02A: Digital Filter Control Register DFUCR: Di g i t al Filter
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
67
R/WR/WR/W
PTON CP/DP CFEPS DFEPS CFESS DFESS
11
Phase system computation result PWM output bit
0 Output normal filter computation result to PWM pin.
1 Output only phase system computation result to PWM pin.
PWM output select bit
0 Output drum phase system computation result (CAPPWM)
1 Output capstan phase system computation result (DRMPWM)
Drum phase system error data transfer bit
0 Transfer data by HSW (NHSW) signal latch.
1 Transfer data at the time of error data write.
Capstan phase system error data transfer bit
0 Transfer data by DVCFG2 signal latch.
1 Transfer data at the time of error data write.
Capstan speed system error data transfer bit
0 Transfer data by DVCFG signal latch.
1 Transfer data at the time of error data write.
Drum speed system error data transfer bit
0 Transfer data by NCDFG signal latch.
1 Transfer data at the time of error data
write.
Bit :
Initial value :
R/W :
H'D030: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector
H'D031: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
H'D032: DFG Speed Error Data Register DFER: Drum Error Dete c tor
H'D033: DFG Speed Error Data Register DFER: Drum Error Dete c tor
0
R
*
/W
13
0
R
*
/W
14
0
R
*
/W
15 1032547
0
R
*
/W
6
0
R
*
/W
9
0
R
*
/W
8
0
R
*
/W
11
0
R
*
/W
10
0
R
*
/W
0
R
*
/W R
*
/W R
*
/WR
*
/W R
*
/WR
*
/W R
*
/W
12
000000
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 924 of 1037
H'D034: DF G Loc k Uppe r Data Re gi ste r DF RUDR: Dr um Er r or De te c tor
H'D035: DF G Loc k Uppe r Data Re gi ste r DF RUDR: Dr um Er r or De te c tor
1
W
13
1
W
14
0
W
15 1032547
1
W
6
1
W
9
1
W
8
1
W
11
1
W
10
1
W
1
WWWWWWW
12
111111
Bit :
Initial value :
R/W :
H'D036: DFG Lock Lower Data Register DFRLDR: Drum Error Detec tor
H'D037: DFG Lock Lower Data Register DFRLDR: Drum Error Detec tor
0
W
13
0
W
14
1
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 925 of 1037
H'D038: Dr um Spe e d Er r or De te c ti o n Contr ol Re gi ste r DF VCR: Dr um Er r or De te c tor
0
0
1
0
(R)/W
*
2
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*
1
56
0
7DFRFON
DF-R/UNR
DPCNT DFRCS1 DFRCS0
0
R/W
DFCS1
(R)/W
*
2
RR/W
DFCS0 DFOVF
Notes:
Clock source select bit
DFCS1 DFCS0
0 0 φs
1 φs/2
1 0 φs/4
1 φs/8
Counter overflow flag
0 Normal status
1 Counter overflows.
Error data limit function select bit
0 Limit function OFF
1 Limit function ON
Drum lock flag
0 Drum speed system is not locked.
1 Drum speed system is locked.
Drum phase system filter computation auto start bit
0 Filter computation by drum lock detection is not excuted.
1 Filter computation of phase system is executed at the time of
drum lock detection.
Drum lock counter setting bit
DFRCS1 DFRCS0 Description
0 0 Underflow by 1 lock detection
1 Underflow by 2 lock detections
1 0 Underflow by 3 lock detections
1 Underflow by 4 lock detections
Description
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. When read, counter value is read.
Rev. 2.0, 11/ 00, page 926 of 1037
H'D039: Drum Phase Error Dete c tion Control Register DPG CR: Drum Error Detec tor
0
1
12
1
3
0
4
0
R/W
5
0
6
0
7
R/WR/(W)*
DPOVF
R/W
DPCS0
0
R/W
DPCS1 N/V HSWES
1
Note: * Only 0 can be written.
Error data latch signal select bit
0 HSW (VideoFF) signal
1 NHSW (NarrowFF) signal
Edge select bit
0 Latch at rising edge
1 Latch at falling edge
Bit :
Initial value :
R/W :
Clock source select bit
DPCS1 DPCS0
0 0 φs
1 φs/2
1 0 φs/3
1 φs/4
Counter overflow flag
0 Normal status
1 Counter overflows.
Description
———
———
H'D03A: Specified Drum Phase Preset Data Register 2 DPPR2: Drum Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
H'D03C: Specified Drum Phase Preset Data Register 1 DPPR1: Drum Error Detector
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7
WW
1
Bit :
Initial value :
R/W :
————
————
Rev. 2.0, 11/ 00, page 927 of 1037
H'D03D: Drum Phase Error Data Register 1 DPER1: Drum Error Dete ctor
0
0
1
0
R*/W
2
0
R*/W
3
0
4
1
5
1
6
1
7
R*/WR*/W
1
Bit :
Initial value :
R/W :
—— ——
—— ——
H'D03E: Drum Phase Error Data Register 2 DPER2: Drum Error Detec tor
0
R*/W
13
0
R*/W
14
0
R*/W
15 1032547
0
R*/W
6
0
R*/W
9
0
R*/W
8
0
R*/W
11
0
R*/W
10
0
R*/W
0
R*/W R*/W R*/WR*/W R*/WR*/W R*/W
12
000000
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
H'D050: Specified CFG Speed Preset Data Register CFPR: Capstan Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
H'D052: CFG Speed Error Data Register CFER: Capstan Error Detector
0
R*/W
13
0
R*/W
14
0
R*/W
15 1032547
0
R*/W
6
0
R*/W
9
0
R*/W
8
0
R*/W
11
0
R*/W
10
0
R*/W
0
R*/W R*/W R*/WR*/W R*/WR*/W R*/W
12
000000
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
H'D054: CF G Loc k Uppe r Data Re gi ste r CF RUDR: Capstan Er r or De te c tor
1
W
13
1
W
14
0
W
15 1032547
1
W
6
1
W
9
1
W
8
1
W
11
1
W
10
1
W
1
WWWWWWW
12
111111
Bit :
Initial value :
R/W :
H'D056: CFG Lock Lower Data Register CFRLDR: Capstan Err or Dete c tor
0
W
13
0
W
14
1
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 928 of 1037
H'D058: Capstan Speed Err or Detec ti on Control Register
CFVCR: Ca pst an E r ror Dete c t o r
0
0
1
0
(R)/W
*2
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*1
56
0
7CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0
0
R/W
CFCS1
(R)/W
*2
RR/W
CFCS0 CFOVF
Notes:
Capstan phase system filter computation auto start bit
0 Filter computation by capstan lock detection is not excuted.
1 Filter computation of phase system is executed at the time of
drum lock detection.
Bit :
Initial value :
R/W :
Capstan lock counter setting bit
CFRCS1 CFRCS0 Description
0 0 Underflow by 1 lock detection
1 Underflow by 2 lock detections
1 0 Underflow by 3 lock detections
1 Underflow by 4 lock detections
Clock source select bit
CFCS1 CFCS0
0 0 φs
1 φs/2
1 0 φs/4
1 φs/8
Counter overflow flag
0 Normal status
1 Counter overflows.
Error data limit function select bit
0 Limit function OFF
1 Limit function ON
Capstan lock flag
0 Capstan speed system is not locked.
1 Capstan speed system is locked.
Description
1. Only 0 can be written.
2. When read, counter value is read.
Rev. 2.0, 11/ 00, page 929 of 1037
H'D059: Capstan Phase Er r or Dete c tion Control RegisterCP G CR: Capst a n Err or Det e ctor
0
1
12
1
3
0
4
0
R/W
5
0
6
0
7
R/WR/(W)*
CPOVF
R/W
CPCS0
0
R/W
CPCS1 CR/RF SELCFG2
1
Note: * Only 0 can be written.
Preset signal select bit
0 Preset by REF30P signal
1 Preset by CRRF signal
Preset, latch signal select bit
0 Preset by CAPREF30 signal and latch by DVCTL signal
1 Preset by REF30P signal and latch by DVCFG2 signal
Bit :
Initial value :
R/W :
Clock source select bit
CPCS1 CPCS0
0 0 φs
1 φs/2
1 0 φs/4
1 φs/8
Counter overflow flag
0 Normal status
1 Counter overflows.
Description
———
———
H'D05A: Specified Capstan Phase Preset Data Register 2 CPPR2: Capstan Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
Bit :
Initial value :
R/W :
H'D05C: Specified Capstan Phase Preset Data Register 1 CPPR1: Capstan Error Detector
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7
WW
1
Bit :
Initial value :
R/W :
————
————
Rev. 2.0, 11/ 00, page 930 of 1037
H'D05D: Capstan Phase Err or Data Register 1 CPER1: Capstan Error Detector
0
0
1
0
R*/W
2
0
R*/W
3
0
4
1
5
1
6
1
7
R*/WR*/W
1
Bit :
Initial value :
R/W :
————
————
Note: * Note that only detected error data can be read.
H'D05E: Capstan Phase Er r or Data Register 2 CPER2: Capstan Error Detector
0
R*/W
13
0
R*/W
14
0
R*/W
15 1032547
0
R*/W
6
0
R*/W
9
0
R*/W
8
0
R*/W
11
0
R*/W
10
0
R*/W
0
R*/W R*/W R*/WR*/W R*/WR*/W R*/W
12
000000
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
Rev. 2.0, 11/ 00, page 931 of 1037
H'D060: HSW Mode Register 1 H SM1: HSW Timi ng Ge nerator
0
0
1
0
R/W
2
0
R/(W)*
3
0
4
1
R
1
R
56
0
7EMPA OVWB OVWA CLRB CLRA
0
R
FLB
R/WR/(W)*
R
FLA EMPB
Note: * Only 0 can be written.
FIFO2 full flag
0 FIFO2 is not full
1 FIFO2 is full
FIFO1 full flag
0 FIFO1 is not full
1 FIFO1 is full
FIFO2 empty flag
0 Data remains in FIFO2
1 FIFO2 is empty
FIFO1 empty flag
0 Data remains in FIFO1
1 FIFO1 is empty
FIFO2 overwrite flag
0 Normal operation
1 Data is written to FIFO1 while it is full. Write 0 to clear the flag.
FIFO1 overwrite flag
0 Normal operation
1 Data is written to FIFO1 while it is full. Write 0 to clear the flag.
FIFO2 pointer clear
0 Normal operation
1 Clear FIFO2 pointer
FIFO1 pointer clear
0 Normal operation
1 Clear FIFO1 pointer
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 932 of 1037
H'D061: HSW Mode Register 2 H SM2: HSW Timi ng Ge nerator
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7EDG ISEL1 SOFG OFG VFF/NFF
0
R/W
FRT
R/WR/WR/W
FGR20FF LOP
Free-run bit
0 5-bit DFG counter and 16-bit timer
1 16-bit FRC
FRG2 clear stop bit
0 16-bit counter clear by DFG reference register 2 is enabled
1 16-bit counter clear by DFG reference register 2 is disabled
Mode select bit
0 Signal mode
1 Loop mode
DFG edge select bit
0 Calculated by DFG rising edge
1 Calculated by DFG falling edge
Interrupt select bit
0 Interrupt request is generated by rising of FIFO STRIG signal
1 Interrupt request is generated by FIFO match signal
FIFO output group select bit
0 20-level output by FIFO1 and FIFO2
1 10-level output by FIFO1 only
Output FIFO group flag
0 Outputting pattern by FIFO1
1 Outputting pattern by FIFO2
VideoFF/NarrowFF output switchover bit
0 VideoFF output
1 NarrowFF output
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 933 of 1037
H'D062: HSW Loop Stage Setting Register HSLP: H SW Timi ng Gener ator
0
*
1
*
R/W
2
*
R/W
3
*
4
*
R/W
5
*
6
*
7
R/WR/WR/W
LOB1
R/W
LOB2
*
R/W
LOB3 LOB0 LOA3 LOA2 LOA1 LOA0
FIFO1 stage setting bit
HSM2 HSLP Description
Bit 5 Bit 3 Bit 2 Bit 1 Bit 0
LOP LOA3 LOA2 LOA1 LOA0
0 * * * * Single mode
1 0 0 0 0 Output stage 0 of FIFO1
1 Output stage 0 and 1 of FIFO1
1 0 Output stage 0 to 2 of FIFO1
1 Output stage 0 to 3 of FIFO1
1 0 0 Output stage 0 to 4 of FIFO1
1 Output stage 0 to 5 of FIFO1
1 0 Output stage 0 to 6 of FIFO1
1 Output stage 0 to 7 of FIFO1
1 0 0 0 Output stage 0 to 8 of FIFO1
1 Output stage 0 to 9 of FIFO1
1 0 Setting disabled
1
1 0 0
1
1 0
1
Note: * Don't care.
FIFO2 stage setting bit
HSM2 HSLP Description
Bit 5 Bit 7 Bit 6 Bit 5 Bit 4
LOP LOB3 LOB2 LOB1 LOB0
0 * * * * Single mode
1 0 0 0 0 Output stage 0 of FIFO2
1 Output stage 0 and 1 of FIFO2
1 0 Output stage 0 to 2 of FIFO2
1 Output stage 0 to 3 of FIFO2
1 0 0 Output stage 0 to 4 of FIFO2
1 Output stage 0 to 5 of FIFO2
1 0 Output stage 0 to 6 of FIFO2
1 Output stage 0 to 7 of FIFO2
1 0 0 0 Output stage 0 to 8 of FIFO2
1 Output stage 0 to 9 of FIFO2
1 0 Setting disabled
1
1 0 0
1
1 0
1
Note: * Don't care.
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 934 of 1037
H'D064: FIF O O utput Patte r n Regi ste r 1 F P DRA: H SW Timi ng G e ner ator
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
NarrowFFA
VFFA AFFA VpulseA MlevelA
1WWW
ADTRGA STRIGA
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGA4 PPGA3 PPGA2 PPGA1 PPGA0
*
W
PPGA7
WWW
PPGA6 PPGA5
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
—
—
H'D066: FIFO Ti mi ng Patter n Register 1 FTP RA: HSW Timing Ge nerator
Bit :
Initial value :
R/W :
1
*
W
FTPRA
1
0
*
W
FTPRA
0
3
*
W
FTPRA
3
2
*
W
FTPRA
2
5
*
W
FTPRA
5
4
*
W
FTPRA
4
7
*
W
FTPRA
7
6
*
W
FTPRA
6
9
*
W
FTPRA
9
8
*
W
FTPRA
8
11
*
W
FTPRA11
10
*
W
FTPRA10FTPRA13 FTPRA12FTPRA15 FTPRA14
12
*
13
*
14
*
15
*
WWWW
H'D066: FIFO Ti me r Capture Register 1 F TCTR: HSW Timing Gener ator
Bit :
Initial value :
R/W :
1
0
R
FTCTR
1
0
0
R
FTCTR
0
3
0
R
FTCTR
3
2
0
R
FTCTR
2
5
0
R
FTCTR
5
4
0
R
FTCTR
4
7
0
R
FTCTR
7
6
0
R
FTCTR
6
9
0
R
FTCTR
9
8
0
R
FTCTR
8
11
0
R
FTCTR11
10
0
R
FTCTR10FTCTR13 FTCTR12FTCTR15 FTCTR14
12
0
13
0
14
0
15
0
RRRR
H'D068: FIFO O utput Pattern Register 2 FP DRB: HSW Timing Ge nerator
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
NarrowFFB
VFFB AFFB VpulseB MlevelB
1WWW
ADTRGB STRIGB
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGB4 PPGB3 PPGB2 PPGB1 PPGB0
*
W
PPGB7
WWW
PPGB6 PPGB5
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
—
—
Note: * Undetermined
Rev. 2.0, 11/ 00, page 935 of 1037
H'D06A: FIFO Timi ng Patte rn Register 2 F TPRB: HSW Timi ng Ge nerator
1
FTPRB
1
0
FTPRB
0
3
FTPRB
3
2
FTPRB
2
5
FTPRB
5
4
FTPRB
4
7
FTPRB
7
6
FTPRB
6
9
FTPRB
9
8
FTPRB
8
11
FTPRB11
10
FTPRB10FTPRB13 FTPRB12FTPRB15 FTPRB14
12131415
Bit :
Initial value :
R/W : *
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
****
WWWW
Note: * Undetermined
H'D06C: DFG Reference Register 1 DFCRA: HSW Timi ng G e ner ator
0
*
1
*
W
2
*
W
3
*
4
*
W
0
W
56
0
7DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0
0
W
ISEL2
WWW
CCLR CKSL
Interrupt select bit
0 Interrupt request is generated by clear signal of 16-bit timer counter
1 Interrupt request is generated by VD signal in PB mode
DFG counter clear bit
0 Normal operation
1 Clear 5-bit DFG counter
16-bit counter clock source select bit
0 φs/4
1 φs/8
Bit :
Initial value :
R/W :
H'D06C: DFG Reference Count Register DFCTR: HSW Timing Generator
0
0
1
0
R
2
0
R
3
0
4
0
R
56
1
7DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0
RR
11
Bit :
Initial value :
R/W :
———
———
H'D06D: DFG Reference Register 2 DFCRB: HSW Timing Generator
0
*
1
*
W
2
*
W
3
*
4
*
W
56
1
7DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0
WW
11
Bit :
Initial value :
R/W :
———
———
Note: * Undetermined
Rev. 2.0, 11/ 00, page 936 of 1037
H'D06E: Special Effect Playback Control Register
CHCR: 4-head Special Effect Playback Circuit
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HAH SIG3 SIG2 SIG1 SIG0
0
W
V/N
WWW
HSWPOL CRH
HSW output signal select bit
0 VideoFF signal output
1 Narrow FF signal output
COMP polarity select bit
0 Positive
1 Negative
C.Rotary synchronization control bit
0 Synchronous
1 Asynchronous
H.AmpSW synchronization control bit
0 Synchronous
1 Asynchronous
Signal control bits
SIG3 SIG2 SIG1 SIG0 Output pin
C.Rotary H.Amp SW
0 0 * * L L
1 0 0 HSW
L
1 HSW H
1 0 L HSW
1 H HSW
1 0 0 * HSW EX-OR COMP COMP
1 HSW EX-NOR COMP COMP
1 0 HSW EX-OR RTP0 RTP0
1 HSW EX-NOR RTP0 RTP0
Note: * Don't care.
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 937 of 1037
H'D06F : Addi ti onal V Contr ol Re gi ste r ADDVR: Addi ti onal V Si gnal G e ne r ator
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
1
67
R/WR/W
HMSK HiZ CUT VPON POL
11
Note: * Don't care.
OSCH mask bit
0 OSCH added
1 OSCH not added
High impedance bit
0 3-level output from Vpulse pin
1 Vpulse pin is set as 3-state (H/L/HiZ) pin
Additional V output control bits
CUT VPON POL Description
0 0 * Low level
1 0 Negative polarity (Figure 28.46)
1 Positive polarity (Figure 28.45)
1 * 0 Immediate level
(high-impedance when HiZ bit = 1)
1 High level
Bit :
Initial value :
R/W :
———
———
H'D070: X-Val ue Data Re gi ste r XDR: X-Val ue, TRK-Val ue
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
XD1 XD0XD3 XD2XD5 XD4XD7 XD6XD9 XD8
XD11 XD10
000000
Bit :
Initial value :
R/W :
————
————
H'D072: TRK -Val ue Data Re gi ste r TRDR: X-Val ue , TRK -Val ue
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
TRD1 TRD0TRD3 TRD2TRD5 TRD4TRD7 TRD6TRD9 TRD8
TRD11 TRD10
000000
Bit :
Initial value :
R/W :
————
————
Rev. 2.0, 11/ 00, page 938 of 1037
H'D074: X-Value/TRK-Value Control Register
XTCR: X-Value, TRK-Value Adjustment Circuit
0
0
1
0
R/W
2
0
W
3
0
4
0
W
5
0
6
0
7
R/WWW
AT/MU
W
CAPRF TRK/X EXC/REF XCS DVREF1 DVREF0
1
Capstan phase adjustment auto/manual select bit
0 Manual mode
1 Auto mode
External sync signal edge select bit
0 Generated at EXCAP rising edge
1 Generated at EXCAP rising and falling edge
Capstan phase adjustment register select bit
0 CAPREF30 is generated only by XDR setting value
1 CAPREF30 is generated by XDR and TRDR setting values
Reference signal select bit
0 Generated by REF30P signal
1 Generated by external referece signal
Clock source select bit
0 φs
1 φs/2
REF30P frequency division rate select bit
DVREF1 DVREF0 Description
0 0 1-division
1 2-division
1 0 3-division
1 4-division
Bit :
Initial value :
R/W :
—
—
H'D078: Drum 12-bit PWM Data Register DPWDR: Drum 12-Bit PWM
1
0
R/W
DPWDR1
0
0
R/W
DPWDR0
3
0
R/W
DPWDR3
2
0
R/W
DPWDR2
5
0
R/W
DPWDR5
4
0
R/W
DPWDR4
7
0
R/W
DPWDR7
6
0
R/W
DPWDR6
9
0
R/W
DPWDR9
8
0
R/W
DPWDR8
11
0
R/W
DPWDR11
10
0
R/W
DPWDR10
12
1
13
1
14
1
15
1
Bit :
Initial value :
R/W :
————
————
Rev. 2.0, 11/ 00, page 939 of 1037
H'D07A: Drum 12-Bit PWM Control Registor DPWCR: Drum 12-Bit PWM
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7DH/L DSF/DF DCK2 DCK1 DCK0
0
W
DPOL
WWW
DDC DHiZ
Positive polarity
Negative polarity output
0
1
Polarity switchover bit
Fixed output bit, PWM pin output bit
01 0 Low level output from PWM pin
HiZ H/LDC Fixed output bit, PWM pin output bit
1 High level output form PWM pin
1
0*High impedance from PWM pin
**PWM modulated signal output
Note: * Don't care.
Modulate error data from digital filter circuit
Modulate data written in data register
0
1
Output data select bit
Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and phase
filtering results are modulated by PWMs and output from the CAPPWM and DRMPWM pins.
However, it is possible to output only drum phase filter results from CAPPWM pin and only capstan
phase filter result from DRMPWM pin, by DFUCR settings of the digital filter circuit.
See the section explaining the digital filter computation circuit.
Carrier frequency select bits Carrier frequency select bits
000φ/2
CK1 CK0CK2
1φ/4
10φ/8
1φ/16
010φ/32
1φ/64
10φ/128
1 (Do not set)
Bit :
Initial value :
R/W :
H'D07B: Capstan 12-Bit PWM Control Register CPWCR: Capstan 12-Bit P WM
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7CH/L CSF/DF CCK2 CCK1 CCK0
0
W
CPOL
WWW
CDC CHiZ
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 940 of 1037
H'D07C: Capstan 12-Bit P WM Data Register CPWDR: Capstan 12-Bi t PWM
1
0
R/W
CPWDR1
0
0
R/W
CPWDR0
3
0
R/W
CPWDR3
2
0
R/W
CPWDR2
5
0
R/W
CPWDR5
4
0
R/W
CPWDR4
7
0
R/W
CPWDR7
6
0
R/W
CPWDR6
9
0
R/W
CPWDR9
8
0
R/W
CPWDR8
11
0
R/W
CPWDR11
10
0
R/W
CPWDR10
12
1
13
1
14
1
15
1
Bit :
Initial value :
R/W :
————
————
H'D080: CTL Control Register CTCR: CTL Circuit
0
0
1
0
R
2
0
W
3
0
4
1
W
5
1
6
0
7
WW W
FSLB
W
FSLC
0
W
NT/PL FSLA CCS LCTL UNCTL SLWM
NTSC/PAL select bit
0 NTSC mode (frame rate: 30 Hz)
1 PAL mode (frame rate: 25 Hz)
Long CTL bit
0 Clock source (CCS) operates at the setting value
1 Clock source (CCS) operates for further 8-division after
operating at the setting value
CTL undetected bit
0 Detected
1 Undetected
Mode select bit
0 Normal mode
1 Slow mode
Clock source select bit
0 φs
1 φs/2
Operating frequency select bits
FSLC FSLB FSLA Description
0 0 0 Reserved (do not set)
1 Reserved (do not set)
1 0 fosc = 8 MHz
1 fosc = 10 MHz (Initial value)
1 * * Reserved (do not set)
Note: * Don't care.
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 941 of 1037
H'D081: CTL Mode Register CTLM: CTL Circuit
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
FW/RV
R/W
REC/PB
0
R/W
ASM MD4 MD3 MD2 MD1 MD0
Record/playback mode bits
ASM REC/PB Description
0 0 Playback mode (PLAYBACK)
1 Record mode (RECORD)
1 0 Assemble mode
1 Invalid (do not set)
Direction bit
0 FORWARD
1 REVERSE
CTL mode select bits
Bit :
Initial value :
R/W :
H'D082: REC-CTL Duty Data Re gi ste r 1 RCDR1: CTL Circuit
1111
131415 103254769811 10
CMT11
W
12
0
CMT10
W
0
CMT13
W
0
CMT12
W
0
CMT15
W
0
CMT14
W
0
CMT17
W
0
CMT16
W
0
CMT19
W
0
CMT18
W
0
CMT1B
W
0
CMT1A
W
0
Bit :
Initial value :
R/W :
————
————
H'D084: REC-CTL Duty Data Re gi ste r 2 RCDR2: CTL Circuit
1111
131415 103254769811 10
CMT21
W
12
0
CMT20
W
0
CMT23
W
0
CMT22
W
0
CMT25
W
0
CMT24
W
0
CMT27
W
0
CMT26
W
0
CMT29
W
0
CMT28
W
0
CMT2B
W
0
CMT2A
W
0
Bit :
Initial value :
R/W :
————
————
H'D086: REC-CTL Duty Data Re gi ste r 3 RCDR3: CTL Circuit
1111
131415 103254769811 10
CMT31
W
12
0
CMT30
W
0
CMT33
W
0
CMT32
W
0
CMT35
W
0
CMT34
W
0
CMT37
W
0
CMT36
W
0
CMT39
W
0
CMT38
W
0
CMT3B
W
0
CMT3A
W
0
Bit :
Initial value :
R/W :
————
————
Rev. 2.0, 11/ 00, page 942 of 1037
H'D088: REC-CTL Duty Data Re gi ste r 4 RCDR4: CTL Circuit
1111
131415 103254769811 10
CMT41
W
12
0
CMT40
W
0
CMT43
W
0
CMT42
W
0
CMT45
W
0
CMT44
W
0
CMT47
W
0
CMT46
W
0
CMT49
W
0
CMT48
W
0
CMT4B
W
0
CMT4A
W
0
Bit :
Initial value :
R/W :
————
————
H'D08A: REC-CTL Duty Data Re gi ste r 5 RCDR5: CTL Circuit
1111
131415 103254769811 10
CMT51
W
12
0
CMT50
W
0
CMT53
W
0
CMT52
W
0
CMT55
W
0
CMT54
W
0
CMT57
W
0
CMT56
W
0
CMT59
W
0
CMT58
W
0
CMT5B
W
0
CMT5A
W
0
Bit :
Initial value :
R / W :
————
————
H'D08C: Duty I/O Register DI/O: CTL Circuit
0
1
1
0
R/(W)*
2
0
W
3
0
45
1
67
R/WWW
VCTR0
1
W
VCTR1
1
W
VCTR2 BPON BPS BPF DI/O
1
Note: * Only 0 can be written.
Bit pattern detection ON/OFF bit
0 Bit pattern detection OFF
1 Bit pattern detection ON
Bit pattern detection start bit
0 Normal status
1 Starts 8-bit bit pattern detection
Duty I/O register
Bit pattern detection flag
0 Bit pattern (8-bit) is not detected
1 Bit pattern (8-bit) is detected
VCTR2 VCTR1 VCTR0 Number of 1-pulse for detection
0 0 0 2
1 4 (SYNC mark)
1 0 6
1 8 (mark A, short)
1 0 0 12 (mark A, long)
1 16
1 0 24 (mark B)
1 32
VISS interrupt setting bits
Bit :
Initial value :
R/W :
—
—
Rev. 2.0, 11/ 00, page 943 of 1037
H'D08D: Bit Pattern Register BTPR: CTL Circuit
0
1
1
1
R*/W
2
1
R*/W
3
1
45
1
67
R*/WR*/WR*/W
LSP5
1
R*/W
LSP4
1
R*/W
LSP6
1
R*/W
LSP7 LSP3 LSP2 LSP1 LSP0
Note: * Writes are disabled during bit pattern detection.
Bit :
Initial value :
R/W :
H'D090: Reference Frequency Register 1 RFD: Reference Signal Generator
15
1
REF15
W
14
1
REF14
W
13
1
REF13
W
12
1
REF12
W
11
1
REF11
W
10
1
REF10
W
9
1
REF9
W
8
1
REF8
W
7
1
REF7
W
6
1
REF6
W
5
1
REF5
W
4
1
REF4
W
3
1
REF3
W
2
1
REF2
W
1
1
REF1
W
0
1
REF0
W
Bit :
Initial value :
R/W :
H'D092: Reference Frequency Register 2 CRF: Reference Signal Generator
15
1
CRF15
W
14
1
CRF14
W
13
1
CRF13
W
12
1
CRF12
W
11
1
CRF11
W
10
1
CRF10
W
9
1
CRF9
W
8
1
CRF8
W
7
1
CRF7
W
6
1
CRF6
W
5
1
CRF5
W
4
1
CRF4
W
3
1
CRF3
W
2
1
CRF2
W
1
1
CRF1
W
0
1
CRF0
W
Bit :
Initial value :
R/W :
H'D094: REF30 Counter Register RFC: Reference Signal Generator
15
0
RFC15
14
0
RFC14
13
0
RFC13
12
0
RFC12
11
0
RFC11
10
0
RFC10
9
0
RFC9
8
0
RFC8
7
0
RFC7
6
0
RFC6
5
0
RFC5
4
0
RFC4
3
0
RFC3
2
0
RFC2
1
0
RFC1
0
0
RFC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 944 of 1037
H'D096: Reference Frequency Mode Register RFM: Reference Signal Generator
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7REX CRD OD/EV VST VEG
0
W
RCS
WWW
VNA CVS
Clock source select bit
0 φs/2
1 φs/4
Mode select bit
0 Manual mode
1 Auto mode
Manual select bit
0 VD sync
1 Free-run
External signal synchronization select bit
0 VD signal or free-run
1 External signal sync
DVCFG2 synchronization select bit
0 At mode switching
1 DVCFG2 signal synchronized
ODD/EVEN edge switchoverselect bit
0 Generated at field signal rising (EVEN)
1 Generated at field signal rising (ODD)
VideoFF counter set
0 VideoFF signal turns counter set OFF
1 VideoFF signal turns counter set OFF
VideoFF edge select bit
0 Set at VideoFF signal rising
1 Set at VideoFF signal falling
Bit :
Initial value :
R/W :
H'D097: Reference Frequency Mode Register 2 RFM2: Reference Signal Generator
0
0
1
1
2
1
3
1
4
1
567 FDS
111 R/W
Field select bit
0 Generated by selected ODD or EVEN VD
signal
1 Generated by VD signal immediately after
mode transition
TBC select bit
0 Reference signal is generated with VD
1 Reference signal is generated in free-run
Bit :
Initial value :
R/W :
(TBC)*——————
(R/W)*——————
Note: * The TBC bit is readable/writable only in the
H8S/2194C series. This bit cannot be
modified in the H8S/2194 series, and the
reference signal is therefore generated in
free-run.
Rev. 2.0, 11/ 00, page 945 of 1037
H'D098: DVCTL Contr ol Re gi ste r CTVC: Fr equency Di v i de r
0
*
1
*
R
2
*
R
34567
R
CFG HSW
0
W
0
W
CEX CEG CTL
111
DVCTL signal generation select bit
0 Generated by PB-CTL signal
1 Generated by external input signal
External sync signal edge select bit
0 Rising edge
1 Falling edge
CFG flag
0 CFG level is low
1 CFG level is high
HSW flag
0 HSW level is low
1 HSW level is high
CTL flag
0 REC or PB-CTL level is low
1 REC or PB-CTL level is high
Bit :
Initial value :
R/W :
———
———
Note: * Undetermined
H'D099: CTL Frequency Division Register CTLR: Frequency Divider
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7CTL4 CTL3 CTL2 CTL1 CTL0
0
W
CTL7
WWW
CTL6 CTL5
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 946 of 1037
H' D0 9A: DVCF G Cont r o l Re g i st e r CDVC: F requency Di v i der
0
0
1
0
W
2
0
W
34
0
W
5
1
6
1
7
WR
CMK CMN
W
DVTRG
0
R/W*
MCGin CRF CPS1 CPS0
0
Note: * Only 0 can be written
Mask CFG flag
0 CFG normal operation
1 DVCFG is detected while mask is set (race detection)
CFG mask status bit
0 Mask is released by capstan mask timer
1 Mask is set by capstan mask timer
CFG mask select bit
0 Capstan mask timing function ON
1 Capstan mask timing function OFF
PB (ASM)-to-REC transition timing sync ON/OFF select bit
0 PB (ASM)-to-REC transition timing sync ON
1 PB (ASM)-to-REC transition timing sync OFF
CFG frequency division edge select bit
0 Execute frequency division operation at CFG rising edge
1 Execute frequency division operation at CFG rising
and falling edges
CFG mask timer clock select bit
CPS1 CPS0 Description
0 0 φs/1024
1 φs/512
1 0 φs/256
1 φs/128
Bit :
Initial value :
R/W :
—
—
H'D09B: CFG Frequency Division Register 1 CDIVR1: F r equency Di v i de r
0
0
1
0
W
2
0
W
34
0
W
5
0
67
WW
CDV15 CDV14
0
W
CDV16
0
W
CDV13 CDV12 CDV11 CDV10
1
Bit :
Initial value :
R/W :
—
—
H' D0 9C: CF G F r e quency Di v i sion Re g i st e r 2 CDIVR2 : F r equency Di v i de r
0
0
1
0
W
2
0
W
34
0
W
5
0
67
WW
CDV25 CDV24
0
W
CDV26
0
W
CDV23 CDV22 CDV21 CDV20
1
Bit :
Initial value :
R/W :
—
—
Rev. 2.0, 11/ 00, page 947 of 1037
H' D0 9D: DVCF G M ask Int e rval Reg i st e r CTM R: F r eque nc y Di v i de r
0
1
1
1
W
2
1
W
34
1
W
5
1
67
WW
CPM5 CPM4
1
W
CPM3 CPM2 CPM1 CPM0
11
Bit :
Initial value :
R/W :
——
——
H'D09E: FG Control Register FGCR: Frequency Divider
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7
W
DRF
1
DFG edge select bit
0 NCDFG signal rising edge is selected
1 NCDFG signal falling edge is selected
Bit :
Initial value :
R/W :
———————
———————
H'D0A0: Servo Port Mode Register SPMR: Servo Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
567 EXCTLON DPGSW COMP
H.Amp.SW
C.Rot
0
R/W
CTLSTOP
R/WR/W
CFGCOMP
1
CFG input method switch bit
0 Zero cross type comparator method for CFG signal input
1 Digital signal input method for CFG signal input
CTLSTOP bit
0 CTL circuit operates
1 CTL circuit does not operate
EXCTL pin function switch bit
0 EXCTL/PS4 pin functions as EXCEL input pin
1 EXCTL/PS4 pin functions as PS4 I/O pin
COMP pin function switch bit
0 COMP/PS2 pin functions as COMP input pin
1 COMP/PS2 pin functions as PS2 I/O pin
H.AmpSW pin function switch bit
0 H.AmpSW/PS1 pin functions as H.AmpSW output pin
1 H.AmpSW/PS1 pin functions as PS1 I/O pin
C.Rotary pin function switch bit
0 C.Rotary/PS0 pin functions as C.Rotary output pin
1 C.Rotary/PS0 pin functions as PS0 I/O pin
DPG pin functionswitch bit
0 Separate input for drum control system input
(DPG/PS3 pin functions as DPG input pin)
1 Weight input for drum control system input
(DPG/PS3 pin functions as PS3 I/O pin)
Bit :
Initial value :
R/W :
—
—
Rev. 2.0, 11/ 00, page 948 of 1037
H'D0A1: Servo Control Register SPCR: Servo Port
0
0
1
0
W
2
0
W
3
0
4
0
W
567 SPCR4 SPCR3 SPCR2 SPCR1 SPCR0
WW
111
SPCRn Description
0 PSn pin functions as input pin
1 PSn pin functions as output pin
Bit :
Initial value :
R/W :
———
———
H'D0A2: Servo Data Register SPDR: Servo Port Controller
0
0
1
0
2
0
3
0
4
0
567 SPDR4 SPDR3 SPDR2 SPDR1 SPDR0
111R/WR/WR/W R/WR/W
Bit :
Initial value :
R/W :
———
———
H'D0A3: Servo Monitor Control Register SVMCR: Servo Port
0
0
1
0
2
0
3
0
4
0
567 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0
11 R/WR/WR/W
0
SVMCR5
R/W R/WR/W
SVMCR5 SVMCR4 SVMCR3 Description
0 0 0 REF30 signal is output from SV2 output pin
1 CAPREF30 signal is output from SV2 output pin
1 0 CREF signal is output from SV2 output pin
1 CTLMONI signal is output from SV2 output pin
1 0 0 DVCFG signal is output from SV2 output pin
1 CFG signal is output from SV2 output pin
1 0 DFG signal is output from SV2 output pin
1 DPG signal is output from SV2 output pin
SVMCR2 SVMCR1 SVMCR0 Description
0 0 0 REF30 signal is output from SV1 output pin
1 CAPREF30 signal is output from SV1 output pin
1 0 CREF signal is output from SV1 output pin
1 CTLMONI signal is output from SV1 output pin
1 0 0 DVCFG signal is output from SV1 output pin
1 CFG signal is output from SV1 output pin
1 0 DFG signal is output from SV1 output pin
1 DPG signal is output from SV1 output pin
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 949 of 1037
H'D0A4: CTL Gain Control Register CTLGR: Servo Port
0
0
1
0
2
0
3
0
4
0
567 CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0
1
1R/WR/WR/W
0
CTLE/A
R/W R/WR/W
CTL select bit
0 AMP output
1 EXCTL
CTL amp feedback SW bit
0 CTLFB SW is OFF
1 CTLFB SW is ON
CTL amp gain setting bit
CTLGR3 CTLGR2 CTLGR1 CTLGR0 CTL outpu gain
0 0 0 0 34.0 dB
1 36.5 dB
1 0 39.0 dB
1 41.5 dB
1 0 0 44.0 dB
1 46.5 dB
1 0 49.0 dB
1 51.5 dB
1 0 0 0 54.0 dB
1 56.5 dB
1 0 59.0 dB
1 61.5 dB
1 0 0 64.0 dB*
1 66.5 dB*
1 0 69.0 dB*
1 71.5 dB*
Bit :
Initial value :
R/W :
——
——
Note: * With a setting of 64.0dB or more, the CTLAMP is in a
very sensitive status. When configuring the set board,
be concerned about countermeasure against noise
around the control head signal input port.
Also, thoroughly set the filter between the CTLAMP
and CTLSMT.
H'D0B0: Vertic al Sync Signal Threshold Value Register VTR: Sync Detector (Servo)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7
WWW
VTR5 VTR4 VTR3 VTR2 VTR1 VTR0
1
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 950 of 1037
H'D0B1: Horizontal Sync Signal Threshold Value Register HTR: Sync Detector (Servo)
0
0
1
0
W
2
0
W
3
0
456
1
7
WW
HTR3 HTR2 HTR1 HTR0
111
Bit :
Initial value :
R/W :
————
————
H'D0B2: H Pulse Adjustment Start Time Setting Register H RTR: Sync Detector (Ser vo)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HRTR4 HRTR3 HRTR2 HRTR1 HRTR0
0
W
HRTR7
WWW
HRTR6 HRTR5
Bit :
Initial value :
R/W :
H'D0B3: H Pulse Wi dth Setting Register H PWR: Sync Detector (Ser vo)
0
0
1
0
W
2
0
W
3
0
456
1
7
WW
HPWR3 HPWR2 HPWR1 HPWR0
111
Bit :
Initial value :
R/W :
————
————
H'D0B4: Noise Detecti on Window Setting Register NWR: Sync Detector (Servo)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7
WWW
NWR5 NWR4 NWR3 NWR2 NWR1 NWR0
1
Bit :
Initial value :
R/W :
——
——
H'D0B5: Noi se De te c ti on Re gi ste r NDR: Sync De te c tor (Se r vo)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7NDR4 NDR3 NDR2 NDR1 NDR0
0
W
NDR7
WWW
NDR6 NDR5
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 951 of 1037
H'D0B6: Sync Si gnal Contr ol Re gi ste r SYNCR: Sync De te c tor (Se r vo)
0
0
1
0
R
2
0
R/(W)*
3
1
456
1
7
R/WR/W
NIS/VD NOIS FLD SYCT
111
Note: * Only 0 can be written.
Interrupt select bit
0 Noise level interrupt
1 VD interrupt
Noise detection flag
0 Noise count is less than four times of NDR setting value
1 Noise count is over four times of NDR setting value
Field detection flag
0 Odd field
1 Even field
Sync signal polarity select bit
SYCT Description Polarity
0 Positive
1 Negative
Bit :
Initial value :
R/W :
————
————
Rev. 2.0, 11/ 00, page 952 of 1037
H'D0B8: Servo Interrupt Enable Register 1 SIENR1: Servo Interrupt
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1
0
R/W
IEDRM3
R/WR/WR/W
IEDRM2 IEDRM1
Drum phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRDRM3
1 Interrupt request is enabled by IRRDRM3
Drum speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM2
1 Interrupt request is enabled by IRRDRM2
Drum speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM1
1 Interrupt request is enabled by IRRDRM1
Capstan phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRCAP3
1 Interrupt request is enabled by IRRCAP3
Capstan speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP2
1 Interrupt request is enabled by IRRCAP2
Capstan speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP1
1 Interrupt request is enabled by IRRCAP1
HSW timing generation (counter clear, capture)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW2
1 Interrupt request is enabled by IRRHSW2
HSW timing generator (OVW, match, STRIG)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW1
1 Interrupt request is enabled by IRRHSW1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 953 of 1037
H'D0B9: Servo Interrupt Enable Register 2 SIENR2: Servo Interrupt
0
0
1
0
R/W
23456
1
7
R/W
IESNC IECTL
11111
Vertical sync signal interrupt enable bit
0 Interrupt (vertical sync signal interrupt)
request is disabled by IRRSNC
1 Interrupt (vertical sync signal interrupt)
request is enabled by IRRSNC
CTL interrupt enable bit
0 Interrupt request is
disabled by IRRCTL
1 Interrupt request is
enabled by IRRCTL
Bit :
Initial value :
R/W :
——————
——————
Rev. 2.0, 11/ 00, page 954 of 1037
H' D0 BA: Se rvo Interrupt Re que st Re g i st e r 1 SIRQ R1 : Ser vo Int errupt
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
0
R/(W)*
56
0
7IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0
R/(W)*
IRRDRM3
R/(W)*
R/(W)*
R/(W)*
IRRDRM2 IRRDRM1
Note: * Only 0 can be written to clear the flag.
Drum phase error detector interrupt request bit
0 Drum phase error detector interrupt request is not generated
1 Drum phase error detector interrupt request is generated
Drum speed error detector (lock detection) interrupt request bit
0 Drum speed error detector (lock detection) interrupt request is not generated
1 Drum speed error detector (lock detection) interrupt request is generated
Drum speed error detector (OVF, latch) interrupt request bit
0 Drum speed error detector (OVF, latch) interrupt request is not generated
1 Drum speed error detector (OVF, latch) interrupt request is generated
Capstan phase error detector (OVF, latch) interrupt request bit
0 Capstan phase error detector (OVF, latch) interrupt request is not generated
1 Capstan phase error detector (OVF, latch) interrupt request is generated
Capstan speed error detector (lock detection) intrerrupt request bit
0 Capstan speed error detector (lock detection) interrupt request is not generated
1 Capstan speed error detector (lock detection) interrupt request is generated
Capstan speed error detector (OVF, latch) interrupt request bit
0 Capstan speed error detector (OVF, latch) interrupt request in not generated
1 Capstan speed error detector (OVF, latch) interrupt request in generated
HSW timing generator (counter clear, capture)
interrupt request bit
0 HSW timing generator (counter clear, capture) interrupt
request is not generated
0 HSW timing generator (counter clear, capture) interrupt
request is generated
HSW timing generator (OVW, match, STRIG)
interrupt request bit
0 HSW timing generator (OVM, match, STRIG)
interrupt request is not generated
1 HSW timing generator (OVM, match, STRIG)
interrupt request is generated
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 955 of 1037
H'D0BB: Servo Interrupt Request Register 2 SIRQR2: Se rvo Interrupt
0
0
1
0
R/(W)*
23456
1
7
R/(W)*
IRRSNC IRRCTL
11111
Note: * Only 0 can be written to clear the flag.
Vertical sync signal interrupt request bit
0 Sync signal detector (VD, noise) interrupt
request is not generated
1 Sync signal detector (VD, noise) interrupt
request is generated
CTL interrupt request bit
0 CTL interrupt request is not
generated
1 CTL interrupt request is
generated
Bit :
Initial value :
R/W :
——————
——————
H'D0E0: Star t Addr e ss Re giste r STAR: 32-Byte Buffe r SCI2
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
56
1
7
R/WR/W
STA4 STA3 STA2 STA1 STA0
11
Bit :
Initial value :
R/W :
———
———
H'D0E1: End Addr e ss Re gi ste r EDAR: 32-Byte Buffe r SCI2
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
56
1
7
R/WR/W
EDA4 EDA3 EDA2 EDA1 EDA0
11
Bit :
Initial value :
R/W :
———
———
Rev. 2.0, 11/ 00, page 956 of 1037
H'D0E2: Serial Control Register 2 SCR2: 32-Byte Buffer SCI2
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
567
R/WR/W
GAP1
0
R/W
ABTIE
R/W
TEIE GAP0 CKS2 CKS1 CKS0
01
Transfer data interval select bits
GAP1 GAP0 Transfer data interval
0 0 No interval
0 1 8-clock interval
1 0 24-clock interval
0 1 56-clock interval
Transfer end interrupt enable bit
0 Transfer-end interrupt request is disabled
1 Transfer-end interrupt request is enabled
Transfer interrupt enable bit
0 Transfer interrupt request is disabled
1 Transfer interrupt request is enabled
Bit :
Initial value :
R/W :
Transfer clock select bits
CKS2 CKS1 CKS0 SCK2 pin Clock source Transfer clock frequency
φ = 10 MHz φ = 5 MHz
0 0 0 Sprescaler S φ/256 25.6 µs 51.2 µs
0 0 0 φ/64 6.4 µs 12.8 µs
0 0 0 φ/32 3.2 µs 6.4 µs
0 0 0 φ/16 1.6 µs 3.2 µs
0 0 0 φ/8 0.8 µs 1.6 µs
0 0 0 φ/4 0.4 µs 0.8 µs
0 0 0 φ/2
—
0.4 µs
0 0 0 External clock
—
—
—
Prescaler frequency
division rate
SCK2
output
SCK2
input
—
—
Rev. 2.0, 11/ 00, page 957 of 1037
H'D0E3: Serial Control Status Register 2 SCSR2: 32-Byte Buffer SCI2
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/W
567
R/WR/(W)*
SOL
R/(W)*
TEI ORER WT ABT STF
011
Note: * Only 0 can be written to clear the flag.
Transfer end interrupt request flag
0 [Clear conditions]
When 0 is written after reading 1
1 [Setting conditions]
When transmission or reception ends
Abort flag
0 [Clear conditions]
When 0 is written after reading 1
1 [Setting conditions]
When CS pin output level becomes high
during transfer
Overrun error flag
0 [Clear conditions]
When 0 is written after reading 1
1 [Setting conditions]
When extra pulse is over-applied to correct
transfer clock or clock input is generated after
transfer end, when using external clock
Wait flag
0 [Clear conditions]
When 0 is written after reading 1
1 [Setting conditions]
When read/write instruction to serial data
buffer (32-bit) is generated while transfer is in
progress or during CS input standby
Extension data bit
0 Read: SO2 pin output level is low
Write: SO2 pin output level is changed to low
1 Read: SO2 pin output level is high
Write: SO2 pin output level is changed to high
Start flag
0 Read: Transfer stops
Write: Transfer aborted and SCI2 initialized
1 Read: Transfer in progress, or CS input
standby
Write: Transfer starts
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 958 of 1037
H'D100: Timer Interrupt Enable Register ITER: Timer X1
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ICICE
R/W
ICIBE
0
R/W
ICIAE ICIDE OCIAE OCIBE OVIE ICSA
ICFA interrupt request (ICIA) is disabled
ICFA interrupt request (ICIA) is enabled
0
1
Input capture A interrupt enable bit
FTIA pin input is selected
for input capture A input
HSW is selected for input
capture A input
0
1
Input capture input select A bit
ICFB interrupt request (ICIB) is disabled
ICFB interrupt request (ICIB) is enabled
0
1
Input capture B interrupt enable bit
ICFC interrupt request (ICIC) is disabled
ICFC interrupt request (ICIC) is enabled
0
1
Input capture C interrupt enable bit
ICFD interrupt request (ICID) is disabled
ICFD interrupt request (ICID) is enabled
0
1
Input capture D interrupt enable bit
OCFC interrupt request
(OCIC) is disabled
OCFC interrupt request
(OCIC) is enabled
0
1
Output compare interrupt enable bit
OCFB interrupt request (OCIB) is disabled
OCFB interrupt request (OCIB) is enabled
0
1
Output compare interrupt B enable bit
OCFA interrupt request (OCIA) is disabled
OCFA interrupt request (OCIA) is enabled
0
1
Output compare interrupt A enable bit
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 959 of 1037
H'D101: Ti me r Contr ol / Status Regi ste r X TCSRX: Ti me r X1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/ WR/(W)*
ICFB
0
R/(W)*
ICFA
R/(W)*
ICFD
R/(W)*
ICFC
R/(W)*
OCFB
R/(W)*
OCFA CCLRA
R/(W)*
OVF
Note: * Only 0 can be written to bits 7 to 1 to clear the flags.
Output compare flag A
[Clearing conditions]
When 0 is written to OCFA after reading
OCFA = 1
[Setting conditions]
When FRC = OCRA
0
1
Output compare flag B
[Clearing conditions]
When 0 is written to OCFB after reading
OCFB = 1
[Setting conditions]
When FRC = OCRB
0
1
Timer overflow
[Clearing conditions]
When 0 is written to OVF after reading
OVF = 1
[Setting conditions]
When FRC changes from H'FFFF to
H'0000
0
1
Input capture flag D
[Clearing conditions]
When 0 is written to ICFD after reading
ICFD = 1
[Setting conditions]
When input capture signal is generated
0
1
Input capture flag C
[Clearing conditions]
When 0 is written to ICFC after reading
ICFC = 1
[Setting conditions]
When input capture signal is generated
0
1
Input capture flag B
[Clearing conditions]
When 0 is written to ICFB after reading
ICFB = 1
[Setting conditions]
When FRC value is transferred to ICRB by
input capture signal
0
1
Input capture flag A
[Clearing conditions]
When 0 is written to ICFA after reading
ICFA = 1
[Setting conditions]
When FRC value is transferred to ICRA by
input capture signal
0
1
Counter clearFRC clearing is disabled
FRC clearing is enabled
0
1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 960 of 1037
H'D102: Free Running Count e r H FRCH: Time r X1
H'D103: Free Running Count e r L F RCL : Time r X1
0
3
0
R/W
5
0
R/W
7
0
9
0
R/W
11
0
13
0
15
R/WR/WR/W
0
R/W R/W
1
0
2
0
R/W
4
0
R/W
6
0
8
0
R/W
10
0
12
0
14
FRC
FRCH FRCL
R/WR/WR/WR/W
0
R/W
0
Bit :
Initial value :
R/W :
H'D104: O utput Compar e Re gi ste r AH , BH O CRAH , O CRBH : Ti me r X1
H'D105: O utput Compare Re gi ste r AL, BL O CRAL, O CRBL: Ti me r X1
1
3
1
R/W
5
1
R/W
7
1
9
1
R/W
11
1
13
1
15
R/WR/WR/W
1
R/W R/W
1
1
2
1
R/W
4
1
R/W
6
1
8
1
R/W
10
1
12
1
14
OCRA, OCRB
OCRAH, OCRBH OCRAL, OCRBL
R/WR/WR/WR/W
1
R/W
0
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 961 of 1037
H'D106: Ti me r Contr ol Re gi ster X TCRX: Ti me r X1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
IEDGB
0
R/W
IEDGA
R/W
IEDGD
R/W
IEDGC
R/W
BUFEB
R/W
BUFEA CKS0
R/W
CKS1
Capture at falling edge of input capture input A
Capture at rising edge of input capture input A
0
1
Input capture edge select A
Capture at falling edge of input capture input B
Capture at rising edge of input capture input B
0
1
Input capture edge select B
Capture at falling edge of input capture input C
Capture at rising edge of input capture input C
0
1
Input capture edge select C
Capture at falling edge of input capture input D
Capture at rising edge of input capture input D
0
1
Input capture edge select D
ICRC is not used as buffer register for ICRB
ICRC is used as buffer register for ICRB
0
1
Buffer enable B
ICRC is not used as buffer register for ICRA
ICRC is used as buffer register for ICRA
0
1
Buffer enable A
Clock selct bit Clock select
00 CKS0CKS1
10 01
Internal clock: count at φ/4
Internal clock: count at φ/16
Internal clock: count at φ/64
11 DVCFG: Edge detection p
ulse selected by CFG
frequency division timer
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 962 of 1037
H'D107: Timer O utput Compare Control Register TOCR: Timer X1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
ICSC
0
R/W
ICSB
R/W
OSRS
R/W
ICSD
R/W
OEB
R/W
OEA OLVLB
R/W
OLVLA
FTIB pin is selected for input capture B input
VD is selected for input capture B input
0
1
Input capture input select B
Low level
High level
0
1
Output level B
FTIC pin is selected for input capture C input
DVCTL is selected for input capture C input
0
1
Input capture input select C
FTID pin is selected for input capture D input
NHSW is selected for input capture D input
0
1
Input capture input select D
OCRA register is selected
OCRB register is selected
0
1
Output compare register select
Low level
High level
0
1
Output level A
Output compare A output is disabled
Output compare A output is enabled
0
1
Output enable A
Bit :
Initial value :
R/W :
0
1
Output enable B
Output compare B output is disabled
Output compare B output is enabled
Rev. 2.0, 11/ 00, page 963 of 1037
H'D108: Input Captur e Re gi ste r AH ICRAH : Ti me r X1
H'D109: Input Captur e Re gi ste r AL ICRAL: Ti me r X1
H' D1 0A: Input Capt ur e Re giste r B H ICRB H : T i m e r X1
H'D10B: Input Captur e Re gi ster BL ICRBL: Ti me r X1
H' D1 0C: Input Capt ur e Re giste r CH ICRCH: T i m e r X1
H' D1 0D: Input Capt ur e Re giste r CL ICRCL : T i m e r X1
H'D10E: Input Captur e Re gi ste r DH ICRDH : Ti me r X1
H' D1 0F: Input Capt ur e Reg i st e r DL ICRDL: T i m e r X1
0
3
0
R
5
0
R
7
0
9
0
R
11
0
13
0
15
RRR
0
RR
1
0
2
0
R
4
0
R
6
0
8
0
R
10
0
12
0
14
ICRA, ICRB, ICRC, ICRD
ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL
RRRR
0
R
0
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 964 of 1037
H'D110: Timer M ode Register B TM B: Time r B
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
0
6
0
7
R/WR/W
TMBIE
R/(W)*
TMBIF
0
R/W
TMB17 TMB12 TMB11 TMB10
Note: * Only 0 can be written to clear the flag.
Interval function is selected
Auto reload function is selected
0
1
Auto reload function select bit
[Setting conditions]
When TCB overflows
[Clearing conditions]
When 0 is written after reading 1
0
1
Timer B interrupt request flag
Timer B interrupt request is disabled
Timer B interrupt request is enabled
0
1
Timer B interrupt enable bit
00 0 Internal clock: Count at φ/16384
TMB11 TMB10TMB12 Clock select
0 1 Internal clock: Count at φ/4096
1
0
0
0 0 Internal clock: Count at φ/1024
1 1 Internal clock: Count at φ/512
01 0 Internal clock: Count at φ/128
0 1 Internal clock: Count at φ/32
1
1
1
1 0 Internal clock: Count at φ/8
1 1 Count at rising/falling edge of external
event (TMBI)
Note: * External event edge selection is set at PMR51 in port mode register 5
(PMR5).
See section 12.2.4, Port Register 5 (PMR5).
Clock select bit
Bit :
Initial value :
R/W :
——
——
H'D111: Timer Counter B TCB: Timer B
0
0
1
0
R
2
0
R
345
0
6
0
7
RR
TCB15
0
R
TCB14
0
R
TCB13
R
TCB16
0
R
TCB17 TCB12 TCB11 TCB10
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 965 of 1037
H'D111: Timer Load Register B TLB: Ti me rB
0
0
1
0
W
2
0
W
345
0
6
0
7
WW
TLB15
0
W
TLB14
0
W
TLB13
W
TLB16
0
W
TLB17 TLB12 TLB11 TLB10
Bit :
Initial value :
R/W :
H'D112: Timer L M ode Register LM R: Timer L
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5
1
6
0
7
R/WR/WR/W
LMIE
0
R/(W)*
LMIF IMR3 IMR2 IMR1 IMR0
Note:
*
Only 0 can be written to clear the flag.
Timer L interrupt request flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When LTC overflow, underflow or compare
match clear occurs
0
1
Timer L interrupt enable bit
Timer L interrupt request is disabled
Timer L interrupt request is enabled
0
1
Up count control
Down count control
0
1
Up/down count control
Clock select bit
Clock select
00 0 Count at rising edge of PB and REC-CTL
LMR1 LMR0R2
1 Count at falling edge of PB and REC-CTL
1*Count DVCFG2
01 *Internal clock: Count at φ/128
1*Internal clock: Count at φ/64
Note: * Don't care.
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 966 of 1037
H'D113: Linear Ti me Counter LTC: Timer L
0
0
1
0
R
2
0
3
0
456
0
7
RRRR
LTC6
0
R
LTC5
0
R
LTC4
0
R
LTC7 LTC3 LTC2 LTC1 LTC0
Bit :
Initial value :
R/W :
H'D113: Re l oad/ Compare M atc h Re gi ste r RCR: Time r L
0
0
1
0
W
2
0
3
0
456
0
7
WWWW
RCR6
0
W
RCR5
0
W
RCR4
0
W
RCR7 RCR3 RCR2 RCR1 RCR0
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 967 of 1037
H'D118: Timer R Mode Regi ster 1 TM RM1: Ti mer R
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
RLD
R/W
AC/BR
0
R/W
CLR2 RLCK PS21 PS20 RLD/CAP CPS
TMRU-2 is not cleard at the time of capture
TMRU-2 is cleard at the time of capture
0
1
TMRU-2 clear select bit
Deceleration
Acceleration
0
1
Acceleration/deceleration select bit
TMRU-2 is not used as reload timer
TMRU-2 is used as reload timer
0
1
Execution/non-execution of reload by TMRU-2
Reload at CFG rising edge
Reload at TMRU underflow
0
1
TMRU-2 reload timing select bit
00 Count at TMRU-1 underflow
PS20PS21
1 PSS, count at φ/256
01 PSS, count at φ/128
PSS, count at φ/64
1
TMRU-2 clock source select bits
TMRU-2 clock source select
Capture signal at CFG rising edge
Capture signal at IRQ3 edge
0
1
TMRU-1 capture signal select bit
TMRU-1 functions as reload timer
TMRU-1 functions as capture timer
0
1
TMRU-1 operation mode select bit
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 968 of 1037
H'D119: Timer R Mode Regi ster TM RM2: Ti mer R
0
0
1
0
R/(W)*
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/(W)*
R/WR/W
PS10
R/W
PS11
0
R/W
LAT PS31 PS30 CP/SLM CAPF SLW
TMRU-1 clock source select bits
TMRU-1 clock source select
00 Count at CFG rising edge
PS10PS11
1 PSS, count at φ/4
01 PSS, count at φ/256
1 PSS, count at φ/512
TMRU-3 clock source select bits
TMRU-3 clock source select
00 Count at rising edge of DVCTL from frequency divider
PS30PS31
1 PSS, count at φ/4096
01 PSS, count at φ/2048
1 PSS, count at φ/1024
Interrupt select bit
Interrupt request by TMRU-2 capture signal is enabled
Interrupt request by slow tracking mono-multi end is enabled
0
1
Capture signal flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMRU-2 capture signal is generated while CP/SLM bit = 0
0
1
Slow tracking mono-multi flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When slow tracking mono-multi ends while
CP/SLM bit = 1
0
1
TMRU-2 captrue signal select bits
*0 Capture at TMRU-3 underflow
CPSLAT
01 Capture at CFG rising edge
1 Capture at IRQ3 edge
TMRU-2 capture signal select
Note: * Don't care.
Bit :
Initial value :
R/W :
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.0, 11/ 00, page 969 of 1037
H'D11A: Timer R Capture Register 1 TM RCP1: Time R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC17
R
TMRC16
R
TMRC15
R
TMRC14
R
TMRC13
R
TMRC12
R
TMRC11
R
TMRC10
Bit :
Initial value :
R/W :
H'D11B: Timer R Capture Register 2 TM RCP2: Time R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC27
R
TMRC26
R
TMRC25
R
TMRC24
R
TMRC23
R
TMRC22
R
TMRC21
R
TMRC20
Bit :
Initial value :
R/W :
H'D11C: Timer R Load Register 1 TM RL1: Time r R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR17
W
TMR16
W
TMR15
W
TMR14
W
TMR13
W
TMR12
W
TMR11
W
TMR10
Bit :
Initial value :
R/W :
H'D11D: Timer R Load Register 2 TM RL2: Time r R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR27
W
TMR26
W
TMR25
W
TMR24
W
TMR23
W
TMR22
W
TMR21
W
TMR20
Bit :
Initial value :
R/W :
H'D11E: Timer R Load Register 3 TM RL3: Timer R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR37
W
TMR36
W
TMR35
W
TMR34
W
TMR33
W
TMR32
W
TMR31
W
TMR30
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 970 of 1037
H' D1 1F: T i m e r R Co nt r o l / St a tus Regi st e r T M RCS: T i m e r R
0
1
1
1
2
0
R/(W)*
3
0
4
0
R/(W)*
5
0
6
0
7
R/(W)*
R/W
TMRI1E
R/W
TMRI2E
0
R/W
TMRI3E TMRI3 TMRI2 TMRI1
Note: * Only 0 can be written to clear the flag.
TMRI3 interrupt request is disabled
TMRI3 interrupt request is enabled
0
1
TMRI3 interrupt enable bit
TMRI2 interrupt request is disabled
TMRI2 interrupt request is enabled
0
1
TMRI2 interrupt enable bit
TMRI1 interrupt request is disabled
TMRI1 interrupt request is enabled
0
1
TMRI1 interrupt enable bit
TMRI1 interrupt request flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMRU-1 underflows
0
1
TMRI2 interrupt request flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMRU-2 underflows or when capstan motor
acceleration/deceleration operation ends
0
1
TMRI3 interrupt request flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When interrupt source selected at CP/SLM bit in
TMRM2 is generated
0
1
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 971 of 1037
H'D120: PWM Data Register L P WDRL: 14-Bit PWM
0
0
1
0
2
0
3
0
4
0
5
0
67
W
PWDRL0
W
PWDRL1
W
PWDRL2
W
PWDRL3
W
PWDRL4
W
PWDRL5
0
W
PWDRL6
W
PWDRL7
0
Bit :
Initial value :
R/W :
H'D121: PW M Data Re gi ste r U P WDRU: 14-Bi t PW M
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
W
PWDRU0
W
PWDRU1
W
PWDRU2
W
PWDRU3
W
PWDRU4
W
PWDRU5
1
Bit :
Initial value :
R/W :
——
——
H'D122: PWM Control Regi sterPWCR: 14-Bit PWM
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7
R/W
PWCR0
1
Clock select bit
Note: * tφ: PWM input clock frequency
Input clock is φ/2 (tφ = 2/φ)
Generate PWM waveform with conversion frequency of
16384/φ and minimum pulse width of 1/φ
Input clock is φ/4 (tφ = 4/φ)
Generate PWM waveform with conversion frequency of
32768/φ and minimum pulse width of 2/φ
0
1
Bit :
Initial value :
R/W :
———————
———————
H'D126: 8-Bit PWM Data Register 0 PWR0: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW04 PW03 PW02 PW01 PW00
0
W
PW07
WWW
PW06 PW05
Bit :
Initial value :
R/W :
H'D127: 8-Bit PWM Data Register 1 PWR1: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW14 PW13 PW12 PW11 PW10
0
W
PW17
WWW
PW16 PW15
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 972 of 1037
H'D128: 8-Bit PWM Data Register 2 PWR2: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW24 PW23 PW22 PW21 PW20
0
W
PW27
WWW
PW26 PW25
Bit :
Initial value :
R/W :
H'D129: 8-Bit PWM Data Register 3 PWR3: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW34 PW33 PW32 PW31 PW30
0
W
PW37
WWW
PW36 PW35
Bit :
Initial value :
R/W :
H'D12A: 8-Bit PWM Control Regi ster PW8CR: 8-Bit PWM
0
0
1
0
R/W
2
0
R/W
3
0
4567 PWC3 PWC2 PWC1 PWC0
R/WR/W
1111
Output polarity select bits
Positive polarity
Negative polarity
0
1(n = 3 to 0)
Bit :
Initial value :
R/W :
————
————
H' D1 2C: Input Capt ur e Re giste r 1 ICR1 : PSU
0
0
1
0
R
2
0
R
3
0
4
0
R
0
R
56
0
7ICR14 ICR13 ICR12 ICR11 ICR10
0
R
ICR17
RRR
ICR16 ICR15
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 973 of 1037
H'D12D: Prescaler Unit Control/Status Register PCSR: P SU
0
0
1
0
R/W
2
0
R/W
3
1
4
0
R/W
5
0
6
0
7
R/WR/W
ICEG
R/W
ICIE
0
R/(W)*
ICIF NCon/off DCS2 DCS1 DCS0
Note: * Only 0 can be written to clear the flag.
Interrupt request by input capture is disabled
Interrupt request by input capture is enabled
0
1
Input capture interrupt enable bit
Frequency division clock output select bits
Frequency division
clodk output select
00 0 PSS, output φ/32
DCS1 DCS0DCS2
1 PSS, output φ/16
1 0 PSS, output φ/8
1 PSS, output φ/4
01 0 PSW, output φW/32
1 PSW, output φW/16
1 0 PSW, output φW/8
1 PSW, output φW/4
Input capture interrupt flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When input capture is executed at IC pin edge
0
1
Noise cancel function of IC pin is disabled
Noise cancel function of IC pin is enabled
0
1
Noise cancel ON/OFF bit
IC pin edge select bit
Falling edge of IC pin input is detected
Rising edge of IC pin input is detected
0
1
Bit :
Initial value :
R/W :
—
—
Rev. 2.0, 11/ 00, page 974 of 1037
H'D130: Softwar e Tr i gge r A/ D Re sul t Re gi ste r H ADRH : A/ D Conve r te r
H'D131: Softwar e Tr i gge r A/ D Re sul t Re gi ste r L ADRL: A/ D Conve r te r
ADRH ADRL
1 032547
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
——————
——————
H'D132: Hardware Tr i gger A/D Result Register H AHRH: A/D Converter
H'D133: Hardware Tr i gger A/D Result Register L AHRL: A/D Converter
AHRH AHRL
1 032547
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
——————
——————
Rev. 2.0, 11/ 00, page 975 of 1037
H' D134: A/D Control Registe r ADCR: A/ D Conve r t e r
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
1
7
R/WR/WR/W
HCH1
0
R/W
CK HCH0 SCH3 SCH2 SCH1 SCH0
Clock select
0 Conversion frequency = 266 states
1 Conversion frequency = 134 states
Hardware channel select bits
HCH1 HCH2 Analog input channel
0 0 AN8
1 AN9
1 0 ANA
1 ANB
Software channel select bits
SCH3 SCH2 SCH1 SCH0 Analog input channel
0 0 0 0 AN0
1 AN1
1 0 AN2
1 AN3
1 0 0 AN4
1 AN5
1 0 AN6
1 AN7
1 0 0 0 AN8
1 AN9
1 0 ANA
1 ANB
1 * * Software-triggered conversion
channel is not selected
Notes: 1. If conversion is started by software when SCH3 to
SCH0 are set to 11xx, the conversion result is
undetermined. Hardware- or external-triggered
conversion, however, will be performed on the channel
selected by HCH1 and HCH0.
2. * Don't care.
Bit :
Initial value :
R/W :
—
—
Rev. 2.0, 11/ 00, page 976 of 1037
H' D135: A/D Control/Status Regi ste r ADCSR: A/ D Conve r t e r
0
0
1
0
R
2
0
R
3
0
4
0
R/W
5
0
67
R//(W)*RR/W
ADIE
0
R/(W)*
SEND SST HST BUSY SCNLHEND
1
A/D interrupt enable bit
0 Interrupt (ADI) upon A/D conversion end is disabled
1 Interrupt (ADI) upon A/D conversion end is enabled
Software A/D start flag
0 Read: Indicates that software-triggered A/D conversion
has ended or been stopped
Write: Software-triggered A/D conversion is aborted
1 Read: Indicates that software-triggered A/D conversion
is in progress
Write: Starts software-triggered A/D conversion
Busy flag
0 No contention for A/D conversion
1 Indicates an attempt to execute software-triggerd
A/D conversion was canceled by the start of hardware-
triggered A/D conversion.
Software-triggered A/D conversion cancel flag
0 No contention for A/D conversion
1 Indicates that software-triggered A/D
conversion was canceled by the start of
hardware-triggered A/D conversion.
Hardware A/D status flag
0 Read: Hardware- or external -triggered A/D conversion is
not in progress
Write: Hardware- or external-triggered A/D conversion is
aborted
1 Hardware- or external-triggered A/D conversion has
ended or been stopped
Software A/D end flag
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When software-triggered A/D conversion has ended
Hardware A/D end flag
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When hardware- or external-triggered A/D
conversion has ended
Bit :
Initial value :
R/W :
—
—
Note: * Only 0 can be written to clear the flag.
Rev. 2.0, 11/ 00, page 977 of 1037
H'D136: A/D Trigger Select Register ADTSR: A/D Converter
0123
0
4
R/W
567 TRGS1
0
R/W
TRGS0
111111
Trigger select bits
TRGS1 TRGS0
0 0 Hardware- or external-triggered A/D
conversion is disabled
1 Hardware-triggered (ADTRG) A/D conversion
is selected
1 0 Hardware-triggered (DFG) A/D conversion
is selected
1 External-triggered (ADTRG) A/D conversion
is selected
Bit :
Initial value :
R/W :
——————
——————
H'D138: Timer Load Register K TLK : Ti mer J
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR25
W
TLR26
1
W
TLR27 TLR24 TLR23 TLR22 TLR21 TLR20
Bit :
Initial value :
R/W :
H'D138: Timer Counter K TCK: Ti mer J
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR25
R
TDR26
1
R
TDR27 TDR24 TDR23 TDR22 TDR21 TDR20
Bit :
Initial value :
R/W :
H'D139: Timer Load Register J TLJ: Time r J
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR15
W
TLR16
1
W
TLR17 TLR14 TLR13 TLR12 TLR11 TLR10
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 978 of 1037
H'D139: Timer Counter J TCJ: Timer J
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR15
R
TDR16
1
R
TDR17 TDR14 TDR13 TDR12 TDR11 TDR10
Bit :
Initial value :
R/W :
H'D13A: Timer M ode Regi ster J TM J: Ti mer J
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ST
R/W
PS10
0
R/W
PS11 8/16 PS21 PS20 TGL T/R
TMJ-2 toggle flag
TMJ-2 toggle output is 0
TMJ-2 toggle output is 1
0
1
Timer output/remote-controller output
select bit TMJ-1 timer output
TMJ-1 toggle output (data
transmitted from remote
controller)
0
1
TMJ-1 and TMJ-2 operate separately
TMJ-1 and TMJ-2 operate together as 16-bit
0
1
8-bit/16-bit operation select bit
Stop TMJ-1 clock supply in remote control mode
Start TMJ-1 clock supply in remote control mode
0
1
Remote-controlled operation start bit
Note: * External clock edge selection is set in edge select register (IEGR).
See section explaining edge select register (IEGR).
When using external clock in remote control mode, set opposite edges for IRQ1 and IRQ2 edges
(eg. When falling edge is set for IRQ1, set rising edge for IRQ2).
00 PS10PS11
1
01
PSS, count at /512
PSS, count at /256
PSS, count at /4
1 Count at rising/falling edge of external clock (IRQ1)
TMJ-1 input clock select bits TMJ-1 input clock select
Notes: 1. The edge selection for the external clock inputs is made by setting the edge select
register (IEGR). See section 6.2.4, Edge Select Register (IEGR) for more
information.
2. Don't care.
3. Available only in the H8S/2194C series.
PS20PS21PS22
*3
Counthing by the PSS, /16384
Counthing by the PSS, /2048
Counting at underflowing of the TMJ-1
Counting at the leading edge or the trailing edge of
the external clock inputs (IRQ2)
*1
Counting by the PSS, /1024 (available only the
H8S/2194C series)
TMJ-2 input clock select bits TMJ-2 input clock select
Bit :
Initial value :
R/W :
0
1
0
1
0
1
*2*2
0
1
Rev. 2.0, 11/ 00, page 979 of 1037
H'D13B: Timer J Control Regi ster TM JC: Time r J
01
0
2
0
R/W
34
0
R/W
5
0
6
0
7
R/WR/W
MON1
R/W
BUZZ0
0
R/W
BUZZ1 MON0 TMJ2IE TMJ1IE
11
/4096
BUZZ0 Output signalBUZZ1
Frequency when
= 10 MHz
/8192 2.44 kHz
1.22 kHz
Output monitor signal
00
1
10
1 Output Timer J BUZZ signal
Buzzer output select bits
TMJ2I interrupt request is disabled
TMJ2I interrupt request is enabled
0
1
TMJ2I interrupt enable bit
TMJ1I interrupt request is disabled
TMJ1I interrupt request is enabled
0
1
TMJ1I interrupt enable bit
PB or REC-CTL
MON0MON1
DVCTL
Output TCA7
00
1
1*
Monitor output select bits
Monitor output select
Note: * Don't care.
Bit :
Initial value :
R/W :
— (PS22)*
— (R/W)*
H8S/2194 series: When ths is read, 1 will
always be readout.
Writes are disabled.
H8S/2194C series: This bit, together with
bit 3 and 2 (PS21,PS20)
in TMJ, selects the input
clock for TMJ-2.
Note: * Bit 0 is readable/writable only in the H8S/2194C series.
Rev. 2.0, 11/ 00, page 980 of 1037
H'D13C: Timer J Status Register TMJS: Time r J
0123456
0
7
R/(W)*
TMJ1I
0
R/(W)*
TMJ2I
111111
Note: * Only 0 can be written to clear the flag.
TMJ1I interrupt request flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMJ-1 underflows
0
1
TMJ2I interrupt request flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMJ-2 underflows
0
1
Bit :
Initial value :
R/W :
——————
——————
Rev. 2.0, 11/ 00, page 981 of 1037
H'D148: Serial Mode Register SMR1: SCI1
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Start-stop synchronous mode
Clock synchronouns mode
0
1
Communication mode
Multiprocessor function is disabled
Multiprocessor format is selected
0
1
Multiprocessor mode
Clock select Clock select
00 CKS0CKS1
1
01
φ clock
φ/4 clock
φ/16 clock
1φ/64 clock
8-bit data
7-bit data
0
1
Character length
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted,
and LSB-first/MSB-first selection is not available.
Even parity
*
1
Odd parity
*
2
0
1
Parity mode
Notes: 1. When even parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the parity
bit is even. In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the parity
bit is odd. In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is odd.
1 Stop bit
*
1
2 Stop bit
*
2
0
1
Stop bit length
Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end
of a transmit character before it is sent.
2. In transmission, two 1 bits (stop bits) are added to the end
of a transmit character before it is sent.
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
0
1
Parity enable
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit
is added to transmit data before transmission. In reception, the parity bit is
checked for the parity (even or odd) specified by the O/E bit.
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 982 of 1037
H'D149: Bi t Rate Re gi ster BRR1: SCI1
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 983 of 1037
H'D14A: Serial Control Register SCR1: SCI1
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Transmit-data-empty interrupt (TXI) request is disabled*
Transmit-data-empty interrupt (TXI) request is enabled
0
1
Transmit interrupt enable bit
Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0,
or clearing the TIE bit to 0.
Reveive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is disabled*
Reveive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is enabled
0
1
Receive interrupt enable bit
Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag,
then clearing the flag to 0, or clearing the RIE bit to 0.
Transmission is disabled
*
1
Transmission is enabled
*
2
0
1
Transmit enable bit
Notes: 1. The TDRE flag in SSR1 is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and TDRE flag in SSR1
is cleared to 0.
SMR1 setting must be performed to decide the transmission format before setting the TE bit to 1.
Reception is disabled
*
1
Reception is enabled
*
2
0
1
Receive enable bit
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial
clock input is detected in synchronous mode.
SMR1 setting must be performed to decide the reception format before setting the RE bit to 1.
Multiprocessor interrupts are disabled (normal reception performed)
[Clearing conditions]
(1) When the MPIE bit is cleared to 0
(2) When data with MPB = 1 is received
Multiprocessor interrupt are enabled*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF,
FER, and ORER flags in SSR1 are disabled until data with the multiprocessor bit set to 1 is received.
0
1
Multiprocessor interrupt enable bit
Note: * When receive data including MPB = 0 is reveived, receive data transfer from RSR to RDR1, receive error detection, and
setting of the RDRF, FER, and ORER flags in SSR1, is not performed. When receive data with MPB = 1 is received,
the MPB bit in SSR1 is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR1 are set to 1) and FER and ORER flag setting is enabled.
Clock enable bits
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
Clock select
00 Internal clock/SCK1 pin function as I/O port
*
1
CKE0CKE1
Internal clock/SCK1 pin function as serial clock output
*
1
1 Internal clock/SCK1 pin function as clock output
*
2
Internal clock/SCK1 pin function as serial clock output
01 External clock/SCK1 pin function as clock input
*
3
External clock/SCK1 pin function as serial clock input
1 External clock/SCK1 pin function as clock input
*
3
Start-stop synchronous mode
Clock synchronous mode
Start-stop synchronous mode
Clock synchronous mode
Start-stop synchronous mode
Clock synchronous mode
Start-stop synchronous mode
Clock synchronous mode External clock/SCK1 pin function as serial clock input
Transmit-end interrupt (TEI) request is disabled*
Transmit-end interrupt (TEI) request is enabled*
0
1
Transmit end interrupt enable bit
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it
to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 984 of 1037
H'D14B: Tr ansmi t Data Re gi ste r TDR1: SCI1
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 985 of 1037
H'D14C: Serial Status Register SSR1: SCI1
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
1
Multiprocessor bit transfer
Transmit data register empty
[Clearing conditions]
(1) When 0 is written in TDRE after reading TDRE = 1
[Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When data is transferred from TDR1 to TSR and data can be written to TDR1
0
1
Transmit end
0 [Clearing conditions]
(1) When 0 is written in TDRE after reading TDRE = 1
[Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When TDRE = 1 at trasmission of the last bit of a 1-byte serial
transmit character
1
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Multiprocessor bit
0 [Clearing conditions]*
When data with a 0 multiprocessor bit is received
[Setting conditions]
When data with a 1 multiprocessor bit is reveived
1
Note: * Retains its previous state when the RE bit in SCR1 is cleared to 0 with
multiprocessor format.
[Clearing conditions]
*
1
When 0 is written in PER after reading PER = 1
[Setting conditions]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR1
*
2
0
1
Parity error
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set. Also,
subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Receive data register full
[Clearing conditions]
When 0 is written in RDRF after reading RDRF = 1
[Setting conditions]
When serial reception ends normally adn receive data is transferred from RSR to RDR1
0
1
Note: RDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception
or when the RE bit in SCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set
to 1, an overrun error will occur and the receive data will be lost.
Overrun errro
[Clearing conditions]
*
1
When 0 is written in ORER after reading ORER = 1
[Setting conditions]
When the next serial reception is completed while RDRF = 1
*
2
0
1
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. The receive data prior to the overrun error is retained in RDR1, and the data received subsequently is lost.
Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Framing error
[Clearing conditions]
*
1
When 0 is written in FER after reading FER = 1
[Setting conditions]
When the SCI1 checks the stop bit at the end of the receive data when reception
ends, and the stop bit is 0.
*
2
0
1
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
If a framing error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set.
Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Bit :
Initial value :
R/W :
Note: * Only 0 can be written to clear the flag.
Rev. 2.0, 11/ 00, page 986 of 1037
H'D14D: Receive Data Register RDR1 : SCI1
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit :
Initial value :
R/W :
H'D14E: Serial Interface Mode Register SCMR1: SCI1
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Normal SCI mode
Reserved mode
0
1
Serial communication inteface
mode select
Data invert TDR1 contents are transmitted
without modification
Receive data is stored in RDR1
without modification
TDR1 contents are onverted before
being transmitted
Receive data is stored in RDR1
in inverted form
0
1
TDR1 contents are transmitted LSB-first
Receive data is stored in RDR1 LSB-first
TDR1 contents are transmitted MSB-first
Receive data is stored in RDR1 MSB-first
0
1
Data transfer direction
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 987 of 1037
H'D158: I2C Bus Control Regi st e r ICCR: IIC B us Interf a c e
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
Note: * Only 0 can be written to clear the falg.
I
2
C bus interface enable
0 I
2
C bus interface module disabled, with SCL and SDA signal pins
set to port function. Initialization of the internal state of the I2C
module. SAR and SARX can be accessed
1 I
2
C bus interface module enabled for transfer operation (pins SCL
and SCA are driving the bus)
I
2
C bus interface interrupt enable
0 Interrupt request is disabled
1 Interrupt request is enabled
Acknowledge bit judgment selection
0 The value of the acknowledge bit is ignored, and continuous transfer is performed
1 If the acknowledge bit is 1, continuous transfer is interrupted
Bus busy
0 Bus is free
[Clearing conditions] When a stop condition is detected
1 Bus is busy
[Setting conditions] When a start condition is detected
I
2
C bus interface interrupt request flag
0 Waiting for transfer, or transfer in progress
[Clearing conditions]
(1) When 0 is written in IRIC after reading IRIC = 1
1 Interrupt requested
[Setting conditions]
■ I
2
C bus format master mode
(1) When a start condition is detected in the bus line state after a start condition is
issued (when the TDRE flag is set to 1 because of first frame transmission)
(2) When a wait is inserted between the data and acknowledge bit when WAIT = 1
(3) At the end of data transfer
(at the rise of the 9th transmit clock pulse, and at the fall of the 8th transmit/
receive clock pulse when a wait is inserted)
(4) When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
(5) When 1 is reveived as teh acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
■ I
2
C bus format slave mode
(1) When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1) and at the end of data transfer up to
the subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
(2) When the general call address is detected
(when FS = 0 and the ADZ flag is set to 1) and at the end of data transfer up to
the subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
(3) When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
(4) When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
■ Synchronous serial format
(1) At the end of data transfer (when the TDRE or RDRF flag is set to 1)
(2) When a start condition is detected with serial format selected
When conditions are occurred such that the TDRE or RDRF flag is set to 1
Start condition/stop condition prohibit
0 Writing 0 issues a start or stop condition, in combination with the BBSY flag
1 Reading always returns a value of 1
Writing is ignored
Master/slave select
Transmit/receive select
MST TRS
0 0 Slave reveive mode
1 Slave transmit mode
1 0 Master receive mode
1 Master transmit mode
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 988 of 1037
H'D159: I2C Bus Stat us Re g i st e r ICSR: IIC B us Interf a c e
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
Error stop condition detection flage
0 No error stop condition
[Clearing conditions]
(1) When 0 is written in ESTP after reading ESTP = 1
(2) When the IRIC flag is cleared to 0
1 ■ In I
2
C bus format slave mode
Error stop condition detected
[Setting conditions]
• When a stop condition is detected during frame transfer
■ In other mode
No meaning
Normal stop condition detection flag
0 No normal stop condition
[Clearing conditions]
(1) When 0 is written in STOP after reading STOP = 1
(2) When the IRIC flag is cleared to 0
1 ■ In I
2
C bus format slave mode
Normal stop condition detected
[Setting conditions]
• When a stop condition is detected after completion of frame transfer
■ In other mode
No meaning
I
2
C bus interface continuous transmission/reception interrupt request flag
0 Waiting for transfer, or transfer in progress
[Clearing conditions]
(1) When 0 is written in IRTR after reading IRTR = 1
(2) When the IRIC flag is cleared to 0
1 Continuous transfer state
[Setting conditions]
■ In I
2
C bus interface slave mode
• When the TDRE or RDRF flag is set to 1 when AASX = 1
■ In other mode
• When the TDRE or RDRF flag is set to 1
Second slave address recognition flag
0 Second slave address not recognized
[Clearing conditions]
(1) When 0 is written in AASX after reading AASX = 1
(2) When a start condition is detected
(3) In master mode
1 Second slave address recognized
[Setting conditions]
• When the second slave address is detected in slave receive mode while FSX = 0
Arbitration lost flag
0 Bus arbitration won
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in AL after reading AL = 1
1 Arbitration lost
[Setting conditions]
(1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode
(2) If the internal SCL line is high at the fall of SCL in master transmit mode
Slave address recognition flag
0 Slave address or general call address not recognized
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in AAS after reading AAS = 1
(3) In master mode
1 Slave address or general call address recognized
[Setting conditions]
• When the slave address or general call address is detected in slave receive mode
General call address recognition flag
0 General call address not recognized
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in ADZ after reading ADZ = 1
(3) In master mode
1 General call address recognized
[Setting conditions]
• When the general call address is detected in slave receive mode
Acknowledge bit
0 Receive mode: 0 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has acknowldeged the data (signal is 0)
1 Receive mode; 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowldeged the data (signal is 1)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 989 of 1037
H'D15E: I2C Bus Data Regi ste r ICDR: IIC Bus Inte r fac e
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
Bit :
Initial value :
R/W :
H' D15E: Second Slave Addre ss Re gi ste r SARX: IIC Bus Interfac e
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
Bit :
Initial value :
R/W :
Format select
Used combined with SAR FS bit.
Rev. 2.0, 11/ 00, page 990 of 1037
H'D15F: I2C Bus M o de Re g i st e r ICM R: IIC B us Int e r f a c e
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
MSB-first/LSB-first select
0 MSB-first
1 LSB-first
Wait insertion bit
0 Data and acknowledge bits transferred consecutively
1 Wait inserted between data and acknowledge bits
Transfer clock select bits
Bit counter
Bit/frame
BC2 BC1 BC0 Clock sync I
2
C bus format
serial format
0 0 0 8 9
1 1 2
1 0 2 3
1 3 4
0 0 0 4 5
1 5 6
1 0 6 7
1 7 8
Bit :
Initial value :
R/W :
Note: * See STCR Bit 6.
IICX* CKS2 CKS1 CKS0 Clock Transfer rate
φ=5 MHz φ=8 MHz φ=10 MHz
0 0 0 0 φ/28 179 kHz 286 kHz 357 kHz
1 φ/40 125 kHz 200 kHz 250 kHz
1 0 φ/48 104 kHz 167 kHz 208 kHz
1 φ/64 78.1 kHz 125 kHz 156 kHz
1 0 0 φ/80 62.5 kHz 100 kHz 125 kHz
1 φ/100 50.0 kHz 80.0 kHz 100 kHz
1 0 φ/112 44.6 kHz 71.4 kHz 89.3 kHz
1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz
1 0 0 0 φ/56 89.3 kHz 143 kHz 179 kHz
1 φ/80 62.5 kHz 100 kHz 125 kHz
1 0 φ/96 52.1 kHz 83.3 kHz 104 kHz
1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz
1 0 0 φ/160 31.3 kHz 50.0 kHz 62.5 kHz
1 φ/200 25.0 kHz 40.0 kHz 50.0 kHz
1 0 φ/224 22.3 kHz 35.7 kHz 44.6 kHz
1 φ/256 19.5 kHz 31.3 kHz 39.1 kHz
Rev. 2.0, 11/ 00, page 991 of 1037
H' D1 5F: Sl a v e Addr ess Reg i st e r SAR: IIC Bus Int e rface
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Format select bit
SAR SARX Format select
Bit 0 Bit 0
FS FX
0 0 I
2
C bus format
• SAR and SARX slave addresses recognized
1 I
2
C bus format
• SAR slave address recognized
• SARX slave address ignored
1 0 I
2
C bus format
• SAR slave address ignored
• SARX slave address recognized
1 I
2
C bus format
• SAR and SARX slave addresses ignored
Bit :
Initial value :
R/W :
H'FFB0: Trap Addre ss Re g i st e r 0 TAR0 : ATC
H'FFB3: Trap Addre ss Re g i st e r 1 TAR1 : ATC
H'FFB6: Trap Addre ss Re g i st e r 2 TAR2 : ATC
0
0
1
0
R/W
2
0
R/W
34567
R/W
A18 A17 A16
00
R/W
0
R/W R/W
A23 A22 A21
00
R/W R/W
A20 A19
0
0
1
0
R/W
2
0
R/W
34567
R/W
A10 A9 A8
00
R/W
0
R/W R/W
A15 A14 A13
00
R/W R/W
A12 A11
01
0
R/W
2
0
R/W
34567
A2 A1
00
R/W
0
R/W R/W
A7 A6 A5
00
R/W R/W
A4 A3
0
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
—
—
Rev. 2.0, 11/ 00, page 992 of 1037
H'FFB9: Addre ss T r a p Co ntrol Re g i st e r ATCR: ATC
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
1
6
1
7
R/W
TRC2 TRC1 TRC0
1
Trap control 0
0 Address trap function 0 is
disabled
1 Address trap function 0 is
enabled
Trap control 1
0 Address trap function 1 is
disabled
1 Address trap function 1 is
enabled
Trap control 2
0 Address trap function 2 is
disabled
1 Address trap function 2 is
enabled
Bit :
Initial value :
R/W :
—————
—————
Rev. 2.0, 11/ 00, page 993 of 1037
H'FFBA: Timer Mode Register A TMA: Timer A
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5
1
6
0
7
R/WR/WR/W
TMAIE
0
R/(W)*
TMAOV TMA3 TMA2 TMA1 TMA0
Note: * Only 0 can be written to clear the flag.
[Clearing conditions]
When 0 is written to TMAOV after reading
TMAOV = 1
[Setting conditions]
When TCA overflows
0
1
Timer A overflow flag
Interrupt request by Timer A (TMAI) is disabled
Interrupt request by Timer A (TMAI) is enabled
0
1
Timer A interrupt enable bit
Timer A clock source is PSS
Timer A clock source is PSW
0
1
Clock source, prescaler select bit
PSS, φ/16384
TMA1 TMA0
TMA2
Prescaler frequency division rate (interval timer)
or overflow frequency (time-base) Operation mode
PSS, φ/8192
PSS, φ/4096
PSS, φ/1024
0
TMA3
PSS, φ/512
PSS, φ/256
PSS, φ/64
PSS, φ/16
1 s
Interval timer
mode
Clock time
base mode
0.5 s
0.25 s
0.03125 s
0
1
0
1
1
Clear PSW and TCA to H'00
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock select bits
Note: φ = f osc
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 994 of 1037
H'FFBB: Timer Counter A TCA: TimerA
0
0
1
0
R
2
0
R
3
0
4567
RR
TCA3
0
R
TCA4
0
R
TCA5
0
R
TCA6
0
R
TCA7 TCA2 TCA1 TCA0
Bit :
Initial value :
R/W :
H'FFBC: Watchdog Timer Control/Status Register WTCSR: WDT
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
RSTS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: * Only 0 can be written to clear the flag.
Overflow flag
WTCNT is initialized to H'00 and halted
WTCNT counts
0
1
NMI interrupt request is disabled
Internal reset request is generated
0
1
Timer mode select bit
Timer enable bit
Reset or NMI
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when WTCNT overflows
Watchdog timer mode: Sends the CPU a reset or NMI interrupt
request when WTCNT overflows
0
1
[Clearing conditions]
(1) Write 0 in the TME bit
(2) Read WTCSR when OVF = 1, then write 0 in OVF
[Setting conditions]
When WTCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.)
0
1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 995 of 1037
H'FFBD: Watchdog Timer Counter WTCNT: WDT
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit :
Initial value :
R/W :
H'FFC0: Port Data Register 0 PDR0: I/O Port
01
R
2
R
34
RR
57 PDR04 PDR03 PDR02 PDR01 PDR00
R
PDR07
RRR
PDR06 PDR05
6
Bit :
Initial value :
R/W : ————————
H'FFC1: Port Data Register 1 PDR1: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR14 PDR13 PDR12 PDR11 PDR10PDR17 PDR16 PDR15
Bit :
Initial value :
R/W :
H'FFC2: Port Data Register 2 PDR2: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR24 PDR23 PDR22 PDR21 PDR20PDR27 PDR26 PDR25
Bit :
Initial value :
R/W :
H'FFC3: Port Data Register 3 PDR3: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR34 PDR33 PDR32 PDR31 PDR30PDR37 PDR36 PDR35
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 996 of 1037
H'FFC4: Port Data Register 4 PDR4: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR44 PDR43 PDR42 PDR41 PDR40PDR47 PDR46 PDR45
Bit :
Initial value :
R/W :
H'FFC5: Port Data Register 5 PDR5: I/O Port
0
0
1
0
234
11
5
1
7
1
6
R/W
PDR51
R/W
PDR50
0
R/W
PDR52
0
R/W
PDR53
Bit :
Initial value :
R/W :
————
————
H'FFC6: Port Data Register 6 PDR6: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR64 PDR63 PDR62 PDR61 PDR60
0
R/W
PDR67
R/WR/WR/W
PDR66 PDR65
Bit :
Initial value :
R/W :
H'FFC7: Port Data Register 7 PDR7: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR74 PDR73 PDR72 PDR71 PDR70
0
R/W
PDR77
R/WR/WR/W
PDR76 PDR75
Bit :
Initial value :
R/W :
H'FFC8: Port Data Register 8 PDR8: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR84 PDR83 PDR82 PDR81 PDR80
0
R/W
PDR87
R/WR/WR/W
PDR86 PDR85
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 997 of 1037
H'FFCD: Port Mode Register 0 PMR0: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR04 PMR03 PMR02 PMR01 PMR00PMR07 PMR06 PMR05
P07/AN7 to P00/IRQ0 rin function select bits
P0n/ANn pin functions as P0n input port
P0n/ANn pin functions as ANn input port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFCE: Port Mode Register 1 PMR1: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR14 PMR13 PMR12 PMR11 PMR10PMR17 PMR16 PMR15
P17/TMOW pin functions as P17 I/O port
P17/TMOW pin functions as TMOW output port
0
1
P17/TMOW pin function select bit
P1n/IRQn pin functions as P1n I/O port
P1n/IRQn pin functions as IRQn input port
0
1
P15/IRQ5 to P10/IRQ0 pin function select bits
(n = 5 to 0)
P16/IC pin functions as P16 I/O port
P16/IC pin functions as IC input port
0
1
P16/IC pin function select bit
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 998 of 1037
H'FFCF: Port Mode Register 2 PMR2: I/O Port
0
0
1
1
2
1
3
1
4
10
R/W
5
0
7
0
R/W R/WR/W
6PMR20PMR27 PMR26 PMR25
P27/SCK2 pin functions as P27 I/O port
P27/SCK2 pin functions as SCK2 I/O port
0
1
P26/SO2 pin functions as P26 I/O port
P26/SO2 pin functions as SO2 output port
0
1
P25/SI2 pin functions as P25 I/O port
P25/SI2 pin functions as S12 input port
0
1
P26/SO2 pin functions as CMOS output
P26/SO2 pin functions as NMOS open drain output
0
1
P27/SCK2 pin function select bit
P26/SO2 pin function select bit
P25/SI2 pin function select bit
P26/SO2 pin PMOS control bit
Bit :
Initial value :
R/W :
————
————
H'FFD0: Port Mode Register 3 PMR3: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR34 PMR33 PMR32 PMR31 PMR30PMR37 PMR36 PMR35
P3n/PWMm pin functions as P3n I/O port
P3n/PWMm pin functions as PWMm output port
0
1
P36/BUZZ pin functions as P36 I/O port
P36/BUZZ pin functions as BUZZ output port
0
1
P37/TMO pin functions as P37 I/O port
P37/TMO pin functions as TMO output port
0
1
P37/TMO pin function select bit
Notes: If the TMO pin is used for remote control sending, a careless timer output
pulse may be output when the remote control mode is set after the output
has been switched to the TMO output. Perform the switching and setting in
the following order.
[1] Set the remote control mode.
[2] Set the TMJ-1 and 2 counter data of the timer J.
[3] Switch the P37/TMO pin to the TMO output pin.
[4] Set the ST bit to 1.
P36/BUZZ pin function select bit
P35/PWM3 to P32/PWM0 pin function select bit
P31/STRB pin functions as P31 I/O port
P31/STRB pin functions as STRB output port
0
1
P31/STRB pin function select bit
(n = 5 to 2, m = 3 to 0)
P30/CS pin functions as P30 I/o port
P30/CS pin functions as CS input port
0
1
P30/CS pin function select bit
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 999 of 1037
H'FFD1: Port Control Register 1 PCR1: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR14 PCR13 PCR12 PCR11 PCR10PCR17 PCR16 PCR15
P1n pin functions as input port
P1n pin functions as output port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFD2: Port Control Register 2 PCR2: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR24 PCR23 PCR22 PCR21 PCR20PCR27 PCR26 PCR25
P2n pin functions as input port
P2n pin functions as output port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFD3: Port Control Register 3 PCR3: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR34 PCR33 PCR32 PCR31 PCR30PCR37 PCR36 PCR35
P3n pin functions as input port
P3n pin functions as output port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1000 of 1037
H'FFD4: Port Control Register 4 PCR4: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR44 PCR43 PCR42 PCR41 PCR40PCR47 PCR46 PCR45
P4n pin functions as input port
P4n pin functions as output port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFD5: Port Control Register 5 PCR5: I/O Port
0
0
1
0
234
11
5
1
7
1
6
W
PCR51
W
PCR50
0
W
PCR52
0
W
PCR53
P5n pin functions as input port
P5n pin functions as output port
0
1(n = 3 to 0)
Bit :
Initial value :
R/W :
————
————
H'FFD6: Port Control Register 6 PCR6: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR64 PCR63 PCR62 PCR61 PCR60
0
W
PCR67
WWW
PCR66 PCR65
00 P6n/RPn pin functions as P6n general purpose input port
PCR6nPMR6n
1 P6n/RPn pin functions as P6n general purpose output port
*1 P6n/RPn pin functions as RPn realtime output port
Port Control Register 6
Note: * Don't care. (n = 7 to 0)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1001 of 1037
H'FFD7: Port Control Register 7 PCR7: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR74 PCR73 PCR72 PCR71 PCR70
0
W
PCR77
WWW
PCR76 PCR75
P7n pin functions as input port
P7n pin functions as output port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFD8: Port Control Register 8 PCR8: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR84 PCR83 PCR82 PCR81 PCR80
0
W
PCR87
WWW
PCR86 PCR85
P8n pin functions as input port
P8n pin functions as output port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFDB: Port Mode Register 4 PMR4: I/O Port
0
0
1
1
2
1
3
1
4
11
5
1
7
1R/W
6PMR40
P40/PWM14 pin functions as P40 I/O port
P40/PWM14 pin functions as PWM14 output port
0
1
P40/PWM14 pin function select bit
Bit :
Initial value :
R/W :
———————
———————
Rev. 2.0, 11/ 00, page 1002 of 1037
H'FFDC: Port Mode Register 5: PMR5: I/O Port
0
1
1
0
234
11
5
1
7
1
6
R/W
PMR51
0
R/W
PMR52
0
R/W
PMR53
P53/TRIG pin function as P53 I/O port
P53/TRIG pin function as TRIG input port
0
1
P53/TRIG pin function select bit
P52/TMBI pin function as P52 I/O port
P52/TMBI pin functions as TMB input port
0
1
P52/TMBI pin function select bit
The timer B event input detects the falling edge
The timer B event input detects the rising edge
0
1
Timer B event input edge select
Bit :
Initial value :
R/W :
———— —
———— —
H'FFDD: Port Mode Register 6 PMR6: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR64 PMR63 PMR62 PMR61 PMR60
0
R/W
PMR67
R/WR/WR/W
PMR66 PMR65
P6n/RPn pin functions as P6n I/O port
P6n/RPn pin functions as RPn output port
0
1
P67/RP7 to P60/RP0 pin function select bit
(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFDE: Port Mode Register 7 PMR7: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR74 PMR73 PMR72 PMR71 PMR70
0
R/W
PMR77
R/WR/WR/W
PMR76 PMR75
P77/PPG7 to P70/PPG0 pin function select bit
P7n/PPGn pin functions as P7n I/O port
P7n/PPGn pin functions as PPGn output port
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1003 of 1037
H'FFDF: Port Mode Register 8 PMR8: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
11
56
1
7PMR83 PMR82 PMR81 PMR80
1R/WR/W
P83/SV2 pin functions as P83 I/O port
P83/SV2 pin functions as SV2 output port
0
1
P83/SV2 pin function select bit
P82/SV1 pin functions as P82 I/O port
P82/SV1 pin functions as SV1 output port
0
1
P82/SV1 pin function select bit
P81/EXCAP pin functions as P81 I/O port
P81/EXCAP pin functions as EXCAP input port
0
1
P81/EXCAP pin function select bit
P80/EXTTRG pin functions as P80 I/O port
P80/EXTTRG pin functions as EXTTRG input port
0
1
P80/EXTTRG pin function select bit
Bit :
Initial value :
R/W :
————
————
H'FFE1: Pull-Up MOS Select Register 1 PUR1: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR14 PUR13 PUR12 PUR11 PUR10PUR17 PUR16 PUR15
P1n pin has no pull-up MOS transistor
P1n pin has pull-up MOS transistor
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1004 of 1037
H'FFE2: Pull-Up MOS Select Register 2 PUR2: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR24 PUR23 PUR22 PUR21 PUR20PUR27 PUR26 PUR25
P2n pin has no pull-up MOS transistor
P2n pin has pull-up MOS transistor
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFE3: Pull-Up MOS Select Register 3 PUR3: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR34 PUR33 PUR32 PUR31 PUR30PUR37 PUR36 PUR35
P3n pin has no pull-up MOS transistor
P3n pin has pull-up MOS transistor
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFE4: Realtime Output Trigger Edge Select Register RTPEGR: I/O Port
0
0
1
0
R/W
2
1
3
1
4
11
56
1
7RTPEGR1 RTPEGR0
1R/W
00 Trigger input is disabled
RTPEGR0RTPEGR1
1 Rising edge of trigger input is selected
0
1 Rising and falling edges of trigger input is selected
1 Falling edge of trigger input is selected
Realtime output trigger edge select bit
Realtime output trigger edge select
Bit :
Initial value :
R/W :
——————
——————
Rev. 2.0, 11/ 00, page 1005 of 1037
H'FFE5: Realtime Output Trigger Select Register RTPSR: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7RTPSR4 RTPSR3 RTPSR2 RTPSR1 RTPSR0
0
R/W
RTPSR7
R/WR/WR/W
RTPSR6 RTPSR5
External trigger (TRIG pin) input is selected
Internal triggfer (HSW) input is selected
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFE8: System Control Register SYSCR: Syste m Co ntrol
0
1
1
0
R/W
2
0
R/W
3
1
4
0
R/W
5
0
6
0
7
RR
INTM1 INTM0 XRST NMIEG1 NMIEG0
0
00 0 Interrupt is controlled by I bit
INTM0INTM1
Interrupt
control mode
Interrupt control
1 1 Interrupt is controlled by I and UI bits and ICR
01 2 Cannot be used in the H8S/2194 Series
1 3 Cannot be used in the H8S/2194 Series
00 Interrupt request is generated at falling edge of NMI input
NMIEG0NMIEG1
1 Interrupt request is generated at rising edge of NMI input
*1 Interrupt request is generated at rising or falling edge of NMI input
Reset is generated by watchdog timer overflow
Reset is generaed by external reset input
0
1
Interrupt control mode
External reset
NMI edge select bits NMI edge select
Note: * Don't care.
Bit :
Initial value :
R/W :
—— —
—— —
Rev. 2.0, 11/ 00, page 1006 of 1037
H'FFE9: Mode Control Register MDCR: Sy stem Cont r o l
0
—*
1
0
2
0
3
0
4
0
5
0
6
0
7
R
MDS0
0
Note: * Determined by MD0 pin.
Mode select 0
Bit :
Initial value :
R / W :
———————
———————
Rev. 2.0, 11/ 00, page 1007 of 1037
H'FFEA: Standby Cont r o l Regi st e r SB YCR: Syst e m Co ntrol
0
0
1
0
R/W
2
0
3
0
4
0
R/W
5
0
6
0
7
R/WR/W
STS1
R/W
STS2
0
R/W
SSBY STS0 SCK1 SCK0
Transition to sleep mode after execution of SLEEP instruction in
high-speed mode or medium-speed mode
Transition to subsleep mode after execution of SLEEP
instruction in subactive mode
Transition to stadby mode, subactive mode, or watch mode after
execution of SLEEP instruction in high-speed mode or medium-
speed mode
Transition to watch mode or high-speed mode after execution of
SLEEP instruction in subactive mode
0
1
Software standby
System clock select System clock select
00 SCK0SCK1
10 01
Bus master is in high-speed mode
Medium-speed clock is φ/16
Medium-speed clock is φ/32
11 Medium-speed clock is φ/64
00 STS1STS2
00 10
Standby timer select bits
0
STS0
1
0
Standby time
8192 states
16384 states
32768 states
10 01 01
1
0
1
65536 states
11
*1
16 states
*2
131072 states
262144 states
Notes: 1. Don't care.
2. The standby time is 32 states when transited to
medium-speed mode φ/32 (SCK = 1, SCK = 0).
Do not select 16 states for Flash ROM version.
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 1008 of 1037
H'FFEB: Low-Power Control Register LPWRCR: Sy stem Cont r o l
0
0
1
0
R/W
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
NESEL
R/W
LSON
0
R/W
DTON SA1 SA0
Low-speed on flag
Noise elimination sampling frequency select
Subactive mode clock select Subactive mode clock select
Sampling at φ divided by 16
Sampling at φ divided by 4
0
1
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch
mode, or directly to high-speed mode
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode*, or a transition is made to sleep mode
or standby mode
• When a SLEEP instruction is executed in subactive mode, a transition is made
directily to high-speed mode, or a transition is made to subsleep mode
0
1
Direct transfer on flag
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch
mode, or directly to high-speed mode
• After watch mode is cleared, a transition is made to high-speed mode
• When a SLEEP instruction is executed in high-speed mode a transition is made to
watch mode, subactive mode, sleep mode or standby mode.
• When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode.
• After watch mode is cleared, a transition is made to subactive mode
0
1
Note: * Don't care.
00 SA0SA1
10 *1
Operating clock of CPU is φw/8
Operating clock of CPU is φw/4
Operating clock of CPU is φw/2
Bit :
Initial value :
R/W :
———
———
Rev. 2.0, 11/ 00, page 1009 of 1037
H'FFEC: Module Stop Control Register MSTPCRH: System Control
H'FFED: Module Stop Control Register MSTPCRL: System Control
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Module stop Module stop mode is released
Module stop mode is set
0
1
Bit :
Initial value :
R/W :
H'FFEE: Serial Timer Control Register STCR: System Control
7
—
0
—
6
IICX
0
R/W
5
IICRST
0
R/W
4
—
0
—
3
FLSHE
0
R/W
0
—
0
—
2
—
0
—
1
—
0
—
Flash memory control register enable bit
I2C controller reset bit
I2C transfer clock select
Used combined with ICMR CKS2 to CKS0
I2C bus interface controller is not reset
I2C bus interface controller is reset
0
1
Flash memory control register is not selected
Flash memory control register is selected
0
1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1010 of 1037
H'FFF0: IRQ Edge Select Register IEGR: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
R/WR/WR/W
IRQ4EG
R/W
IRQ5EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG2
0
6
IRQ0 pin detected dege select bits IRQ0 pin detected edge select
00 Interrupt request generaed at falling edge of IRQ0 pin input
IRQ0EG0IRQ0EG1
10 Interrupt request generaed at rising edge of IRQ0 pin input
*1 Interrupt request generaed at bath falling and rising edge of IRQ0 pin input
Note: * Don't care.
IRQ5 to IRQ1 pins detected edge select bits
Interrupt request generated at falling edge of IRQn pin input
Interrupt request generated at rising edge of IRQn pin input
0
1(n = 5 to 1)
Bit :
Initial value :
R/W :
—
—
H'FFF1: IRQ Enable Register IENR: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
R/WR/WR/W
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
6
IRQ5 to IRQ0 enable bits
IRQn interrupt is disabled
IRQn interrupt is enabled
0
1(n = 5 to 0)
Bit :
Initial value :
R/W :
——
——
Rev. 2.0, 11/ 00, page 1011 of 1037
H'FFF2: IRQ Status Register IRQR: Interrupt Controller
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
5
00
7
R/(W)*
R/(W)*
R/(W)*
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
6
Note: * Only 0 can be written to clear the flag.
IRQ5 to IRQ0 flag
[Clearing conditions]
Cleared by reading IRQnF set to 1, then writing 0 in IRQnF
When IRQn interrupt exception handling is executed
[Setting conditions]
(1) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnEG = 0)
(2) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnEG = 0)
(3) When a falling or rising edge occurs in IRQ0 input while both-edge detection is set (IRQ0EG1 = 1)
0
1
(n = 5 to 0)
Bit :
Initial value :
R/W :
——
——
H'FFF3: Interrupt Control Register A ICRA: Interrupt Controller
H'FFF4: Interrupt Control Register B ICRB: Interrupt Controller
H'FFF5: Interrupt Control Register C ICRC: Interrupt Controller
H'FFF6: Interrupt Control Register D ICRD: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7ICR4 ICR3 ICR2 ICR1 ICR0
0
R/W
ICR7
R/WR/WR/W
ICR6 ICR5
6
Interrupt control level
Corresponding interrupt source is control level 0 (non-priority)
Corresponding interrupt source is control level 1 (priority)
0
1(n = 7 to 0)
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1012 of 1037
H'FFF8: Flash Memory Control Register 1 FLMCR1:
FLASH ROM (H8S/2194 FLASH Version Only)
7
FWE
—*
R
6
SWE
0
R/W
5
—
0
—
4
—
0
—
3
EV
0
R/W
0
P
0
R/W
2
PV
0
R/W
1
E
0
R/W
Note: * Determined by the state of the FWE pin.
Program
Software write enable
Writes are disabled
Writes are enabled
[Setting condition] When FWE = 1
0
1
Flash write enable
When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
0
1
Erase-verify Erase-verify mode cleared
Transition to erase-verify mode
[Setting condition] When FWE = 1 and SWE = 1
0
1
Program-verify
Program-verify mode cleared
Transition to program-verufy mode
[Setting condition] When FWE = 1 and SWE = 1
0
1
Erase Erase mode cleared
Transition to erase mode
[Setting condition] When FWE = 1,
SWE = 1, and ESU = 1
0
1
Program mode cleared
Transition to program mode
[Setting condition] When FWE = 1,
SWE = 1, and PSU = 1
0
1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1013 of 1037
H'FFF8: Flash Memory Control Register 1 FLMCR1:
FLASH ROM (H8S/2194C FLASH Version Only)
7
FWE
—*
R
6
SWE
0
R/W
5
ESU1
0
R/W
4
PSU1
0
R/W
3
EV1
0
R/W
0
P1
0
R/W
2
PV1
0
R/W
1
E1
0
R/W
Note: * Determined by the state of the FWE pin.
Program
Software write enable
Writes are disabled
Writes are enabled
[Setting condition] When FWE = 1
0
1
Flash write enable
When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
0
1
Erase verify Erase-verify mode cleared
Transition to erase-verify mode
[Setting condition] When FWE = 1 and SWE = 1
0
1
Erase setup bit 1
Erase-setup cleared
Erase-setup
[Setting condition] When FWE = 1 and SWE = 1
0
1
Program setup bit 1
Program-setup cleared
Program-setup
[Setting condition] When FWE = 1 and SWE = 1
0
1
Program verify
Program-verify mode cleared
Transition to program-verufy mode
[Setting condition] When FWE = 1 and SWE = 1
0
1
Erase Erase mode cleared
Transition to erase mode
[Setting condition] When FWE = 1,
SWE = 1, and ESU = 1
0
1
Program mode cleared
Transition to program mode
[Setting condition] When FWE = 1,
SWE = 1, and PSU = 1
0
1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1014 of 1037
H'FFF9: Flash Memory Control Register 2 FLMCR2:
FLASH ROM (H8S/2194 FLASH Version Only)
7
FLER
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
PSU
0
R/W
2
—
0
—
1
ESU
0
R/W
Flash memory error
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition] Reset or hardware standby mode
An error has occurred during flash memeory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition] See section 7.8.3, Error Protection
0
1
Program setup
0 Program setup cleared
Program setup
[Setting condition] When FWE = 1, and SWE = 1
1
Erase setup
0 Erase setup cleared
Erase setup
[Setting condition] When FWE = 1, and SWE = 1
1
Bit :
Initial value :
R/W :
Rev. 2.0, 11/ 00, page 1015 of 1037
H'FFF9: Flash Memory Control Register 2 FLMCR2:
FLASH ROM (H8S/2194C FLASH Version Only)
7
FLER
0
R
6
—
0
—
5
ESU2
0
R/W
4
PSU2
0
R/W
3
EV2
0
R/W
0
P2
0
2
PV2
0
R/W
1
E2
0
Flash memory error
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition] Reset or hardware standby mode
An error has occurred during flash memeory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition] See section 8.8.3, Error Protection
0
1
Program 2
0 Program mode cleared
Transition to program-mode
[Setting condition] When FWE = 1, and SWE = 1,and ESU2=1
1
Erase 2
0 Erase mode cleared
Transition to erase mode
[Setting condition] When FWE = 1, and SWE = 1,and ESU2=1
1
Program-verify 2
0 Program-verify mode cleared
Transition to program-verify mode
[Setting condition] When FWE = 1, and SWE = 1
1
Erase-verify 2
0 Erase-verify mode cleared
Transition to erase-verify mode
[Setting condition] When FWE = 1, and SWE = 1
1
Program setup bit 2
0 Program-setup cleared
Program-setup
[Setting condition] When FWE = 1, and SWE = 1
1
Erase setup bit 2
0 Erase-setup cleared
Erase-setup
[Setting condition] When FWE = 1, and SWE = 1
1
Bit :
Initial value :
R/W : R/W R/W
Rev. 2.0, 11/ 00, page 1016 of 1037
H'FFFA: Erase Block Select Register 1 EBR1:
FLASH ROM (H8S/2194 FLASH Version Only)
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
EB8
0
R/W
2
—
0
—
1
EB9
0
R/W
Bit :
EBR1
Initial value :
R/W :
H'FFFA: Erase Block Select Register 1 EBR1:
FLASH ROM (H8S/2194C FLASH Version Only)
7
—
0
—
6
—
0
—
5
EB13
0
R/W
4
EB12
0
R/W
3
EB11
0
R/W
0
EB8
0
R/W
2
EB10
0
R/W
1
EB9
0
R/W
Bit :
EBR1
Initial value :
R/W :
H'FFFB: Erase Block Select Register 2 EBR2:
FLASH ROM (H8S/2194 FLASH Version Only)
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit :
EBR2
Initial value :
R/W :
Division of Erase Block
Block (size)
128-kbyte version
EB0 (1k bytes)
EB1 (1k bytes)
EB2 (1k bytes)
EB3 (1k bytes)
EB4 (28k bytes)
EB5 (16k bytes)
EB6 (8k bytes)
EB7 (8k bytes)
EB8 (32k bytes)
EB9 (32k bytes)
Address
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
H'001000 to H'007FFF
H'008000 to H'00BFFF
H'00C000 to H'00DFFF
H'00E000 to H'00FFFF
H'010000 to H'017FFF
H'018000 to H'01FFFF
Rev. 2.0, 11/ 00, page 1017 of 1037
H'FFFB: Erase Block Select Register 2 EBR2:
FLASH ROM (H8S/2194C FLASH Version Only)
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit :
EBR2
Initial value :
R/W :
Division of Erase Block
Block (size)
256-kbyte version
EB0 (1k bytes)
EB1 (1k bytes)
EB2 (1k bytes)
EB3 (1k bytes)
EB4 (28k bytes)
EB5 (16k bytes)
EB6 (8k bytes)
EB7 (8k bytes)
EB8 (32k bytes)
EB9 (32k bytes)
EB10 (32k bytes)
EB11 (32k bytes)
EB12 (32k bytes)
EB13 (32k bytes)
Address
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
H'001000 to H'007FFF
H'008000 to H'00BFFF
H'00C000 to H'00DFFF
H'00E000 to H'00FFFF
H'010000 to H'017FFF
H'018000 to H'01FFFF
H'020000 to H'027FFF
H'028000 to H'02FFFF
H'030000 to H'037FFF
H'038000 to H'03FFFF
Rev. 2.0, 11/ 00, page 1018 of 1037
Appendix C Pin Circuit Diagrams
C.1 Pin Circu it Diagrams
Circuit diagrams for all pins except power supply pins are shown in table C.1.
Legend
OUT
G
IN OUT
G
IN
PMOS NMOS Clocked gate signal
transmitted when G = 1 Signal transmitted
when G = 0
[Symbols]
RD: Rea d signa l
RST: Re set signa l
LPM: Power-down mode signal (1 in standby, watch, and subactive modes)
Hi-Z: High impedance
SLEEP: Sleep mode signal
Note: Numbers given for resistance values, etc., are reference values.
Rev. 2.0, 11/ 00, page 1019 of 1037
Table C.1 Pin Circuit Diagrams
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P00/AN0 to
P07/AN7
PMR0n·RD
SCH3 to SCH0
Hi-Z Retained Hi-Z
AN8 t o ANB
HCH1, HCH0
Hi-Z Retained Hi-Z
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P10/
,54
to
P15/
,54
P16/
,&
PUR1náPCR1n
RD
PDR1n
PMR1n
PCR1n
INT
INT = IRQ0 to IRQ5, IC
n = 0 to 6
PMR1n
Hi-Z
When
,54
to
,54
and
,&
input are selected, pin
input should be fixed high
or low.
Rev. 2.0, 11/ 00, page 1020 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P17/TMOW
PUR17áPCR17
TMOW
PDR17
PMR17
PCR17
RD
Hi-Z Ret ained Pull-up MOS:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P20/SI1
PUR20áPCR20
RD
PDR20
RXE
PCR20
SI1
RXE
RXE: Input control signal determined
by SCR and SMR.
Hi-Z
When SI1 input is selected,
pin input should be fixed
high or low.
Rev. 2.0, 11/ 00, page 1021 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P21/SO1
PUR21áPCR21
SO1
PDR21
TXE
PCR21
RD
TXE: Output control signal determined
by SCR and SMR.
Hi-Z Ret ained Pull-up MOS:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P22/SCK1
PUR22áPCR22
SCKO
SCKI
PDR22
CKOE
PCR22
RD
CKIE
SCKO:
SCKI:
CKOE:
CKIE:
Transfer clock output
Transfer clock input
Transfer clock output control signal
determined by SMR
Transfer clock input control signal
determined by SMR and SCR
Hi-Z
When SCK1 is set to input,
pin input should be fixed
high or low.
Rev. 2.0, 11/ 00, page 1022 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P23/SDA
P24/SCL
PUR2náPCR2n
SDA/SCL
PDR2n
IICE
PCR2n
RD
IICE
IICE
SDA/SCL
IICE: I
2
C bus enable signaln = 3, 4
Hi-Z Ret ained Pull-up MOS:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P26/SO2
PUR26áPCR26
SO2
PDR26
PDR26
PCR26
RD
Hi-Z Ret ained Pull-up MOS:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 2.0, 11/ 00, page 1023 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P25/SI2
PUR25áPCR25
RD
PDR25
PMR25
PCR25
SI2
PMR25
Hi-Z
When SI2 input is selected,
pin input should be fixed
high or low.
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P27/SCK2
PUR27áPCR27
SCKO
PDR27
PMR27
EXCK
PCR27
SCKI
RD
SCKO: Transfer clock output
SCKI: Transfer clock input
EXCK: External clock input control signal
determined by SMR1 or SMR2
n = 3, 6
Hi-Z
When SCK2 is set to input,
pin input should be fixed
high or low.
Rev. 2.0, 11/ 00, page 1024 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P30/
&6
PUR30áPCR30
RD
PDR30
PMR30
PCR30
CS
PMR30
Hi-Z
When
&6
input is selected,
pin input should be fixed
high or low.
P31/STRB
P32/PWM0
P33/PWM1
P34/PWM2
P35/PWM3
P36/BUZZ
P37/TMO
PUR3náPCR3n
OUT
PDR3n
PMR3n
PCR3n
n = 1 to 7
RD
OUR:
P31/STRB: SC12 strobe output
P32/PWM0: 8-bit PWM0 output
P33/PWM1: 8-bit PWM1 output
P34/PWM2: 8-bit PWM2 output
P35/PWM3: 8-bit PWM3 output
P36/BUZZ: Timer J buzzer output
P37/TMO: Timer J timer output
Hi-Z Ret ained Pull-up MOS:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 2.0, 11/ 00, page 1025 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P40/PWM14
OUT
PDR40
PMR40
PCR40
OUT PWM14
RD
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P41/FTIA
P42/PTIB
P43/FTIC
P44/FTID
RD
PDR4n
PCR4n
IN = FTIA, FTIB, FTIC, FTID*
n = 1 to 4
IN
Hi-Z
Note: *As pins FTIA to
FTID are always
active except in the
standby and watch
modes, a high or
low level should be
input to t hem .
P45/FTOA
P46/PTOB
OUT
PDR4n
TOE
PCR4n
RD n = 5, 6
OUT:
P45/FTOA: Timer X1 output compare output
FTOA
P46/FTOB: Timer X1 output compare output
FTOB
TOE: Output control signal determined by
TOCR
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 2.0, 11/ 00, page 1026 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P47
RD
PDR47
PCR47
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P50/
$'75*
RD
PDR50
TRGE
PCR50
ADTRG
TRGE: A/D trigger input control signal
TRGE
Hi-Z
When
$'75*
input is
selected, pin input should
be fixed high or low.
P51
RD
PDR51
PCR51
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 2.0, 11/ 00, page 1027 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P52/TMBI
P53/TRIG
RD
PDR5n
PMR5n
PCR5n
IN
IN = TMBI, TRIG
n = 2, 3
PMR5n
Hi-Z
When TMBI and TRIG
input are selected, pin
input should be fixed high
or low.
P60/RP0 to
P67/RP7
RD n = 0 to 7
PDRS6n
PCRS6n
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
P70/PPG0 to
P77/PPG7
PPGn
PDR7n
PMR7n
PCR7n
RD n = 0 to 7
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 2.0, 11/ 00, page 1028 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P80/
EXTTRG
P81/EXCAP
RD
PDR8n
PMR8n
PCR8n
IN
IN = EXTTRG, EXCAP
n = 0, 1
PMR8n
Hi-Z
When EXTTRG and
EXCAP input ar e selected,
pin input should be fixed
high or low.
P82/SV1
P83/SV2
OUT
PDR8n
PMR8n
PCR8n
RD
OUT = SV1, SV2
n = 2, 3
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
P84 to P87
RD n = 4 to 7
PDR8n
PCR8n
Hi-Z Ret ained Subactive mode:
Functions
Ot her m odes:
Hi-Z
Csync
Module STOP
Pin input should be fixed high or low.
Rev. 2.0, 11/ 00, page 1029 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Hi-Z Hi-ZCOMP/PS2
RD
SPMR2
COMP
SPMR2
SPDR2
SPCR2
Hi-Z
When COMP input is
selected, pin input should
be fixed high or low.
AUDIOFF
VIDEOFF
OUT
LPM
LPM:power-down mode signal
Hi-Z Hi-Z Hi-Z
CAPPWM
DRMPWM Low
output Low
output Low output
Vpulse
LPM
Three-
level
control
circuit
15 kΩ
Typ
Note: Resistance values are
reference value
15 kΩ
Typ
Low
output Low
output Low output
5(6
RST
Low input (High) ( High)
MD0
NMI When
10,
is not used, pin input
should be fixed high or low.
Rev. 2.0, 11/ 00, page 1030 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
C.Rotary/PS0
H.Ampsw/
PS1
OUT
SPDRn
SPMRn
SPCRn
RD
OUT = C.Rotary, H.Ampsw
n = 0, 1
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-ZEXCTL/PS4
RD
SPDR4
SPMR4
SPCR4
EXCTL
SPMR4
Hi-Z
When EXCTL input is
selected, pin input should
be fixed high or low.
CFG
+
-
+
-
+
-
CFGCOMP
CFGCOMP
P250
REF
M250 S
R
F/F
O
stp
VREF
VREF
CFG
BIAS
Res+ModuleSTOP
Rev. 2.0, 11/ 00, page 1031 of 1037
Pin St a t e s
Pin Names Circuit Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
DFG
DPG/PS3
RD
PDRn
DFG
DPG
PMRn
PCRn
DPG SW
DPG SW
RES+LPM
DFG
DPG
/PS3
Hi-Z Hi-Z
CTL (+ )
CTL (−)
CTLREF
CTLBias
CTLFB
CTLAmp (O)
CTLSMT (i)
+
-
-
+
+ -
CTLGR3 to 1 CTLFB CTLGR0
AMPSHORT
(REC-CTL)
AMPON
(PB-CTL)
PB-CTL (+)
PB-CTL (
-
)
CTLSMT (i)
CTLAmp (o)CTLFBCTLREF
CTL (+)CTL (-) CTLBias
Note
Note: Be sure to set a capacitor between
CTLAmp (o) and CTLSMT (i).
X2 Oscil-
lation Oscil-
lation Oscillation
X1
1 MΩ
Typ
Note: Resistance values are
reference values.
When the subclock is not used, set
X1 = high and X2 = open.
OSC2 Low output
OSC1
LPM
Oscil-
lation Oscil-
lation
Rev. 2.0, 11/ 00, page 1032 of 1037
Appendix D Port States in the Difference Processing States
D.1 Pin Circu it Diagrams
Table D.1 Port States Over vi ew
Port Reset Active Sleep Standby Watch Subactive Subsleep
P07 to
P00 High
imped-
ance
High
imped-
ance
High
imped-
ance
High
imped-
ance
High
imped-
ance
High
impedance High
impedance
P17 to
P10 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P27 to
P20 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P37 to
P30 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P47 to
P40 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P53 to
P50 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P67 to
P60 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P77 to
P70 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P87 to
P80 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
Rev. 2.0, 11/ 00, page 1033 of 1037
Appendix E Usage Notes
E.1 Power Supply Rise and Fall Order
Figure E. 1 shows the order in whic h t he power supply pi ns rise when t he c hi p is powered on, a nd
the order in which they fall when the chip is powered down. If the power supply voltages cannot
rise and fall simultaneously, power supply operations should be carried out in this order.
At power-on, wait until the microcomputer section power supply (VCC) has risen t o the
prescribed voltage, then raise the other analog power supplies.
At power-down, drop the analog power supplies first, followed by the microcomputer section
power supply (VCC).
When powering up and down, ensure that the voltage applied to the pins does not exceed the
respective power supply voltage.
VCC, AVCC
VCC
AVCC
SVCC
Vin
: Microcomputer section power supply voltage
: A/D converter power supply voltage
: Servo section power supply voltage
: Pin applied voltage
SVCC
VCC, AVCC
SVCC
Vin Vin
Fi g ur e E .1 P o we r Supply Ri se and F a l l Order
In power-down modes (except sleep mode), the analog power supplies can be turned off to
reduce current dissipation. When the microcomputer section power supply (VCC) is dropped to
the backup voltage in a power-down mode, the order shown in figure E.2 should be followed.
Make sure that the voltage applied to the pins does not exceed the respective power supply
voltage.
The A/D convert e r power supply (AVCC) should be set to the same potential as the
microcomputer section power supply (VCC). In all power-down modes except sleep mode, AVCC
is turned off inside the device. At this time, the AVCC current dissipation is defined as AISTOP.
Rev. 1.5, 09/ 00, page 1034 of 1037
V
CC
AV
CC
SV
CC
Vin
5 V
2.7 V
: Microcomputer section power supply voltage
: A/D converter power supply voltage
: Servo section power supply voltage
: Pin applied voltage
V
CC
, AV
CC
SV
CC
Vin
Fi g ur e E .2 P o we r Supply Co ntrol i n Powe r - Do wn M o de s
E.2 Pin Handling When the High-Speed Switching Circuit for Four-
Head Special Playback Is Not Used
Tab le E .1 shows how the C. Rot a ry, H.AmpSW , a nd COMP pi ns shoul d be ha ndl e d whe n t he
switching circuit for four-head special-effects playback is not used. C OMP i s an i nput pi n, a n d
the othe r t wo are out put pins.
When the switching circuit for four-head special-effects playback is not used, the related pins
should be handle d a s shown below.
Table E.1 Pin Handling When the High-Speed Switching Circuit for Four-Head Special
Pl a yba c k Is No t Use d
Pin No. Pin Name Connection
103 C.Rotary OPEN (output pin)*
104 H.AMP SW O PEN (output pin)*
105 COMP VSS
Note: *Output depends on the special- ef fect s c ont r o l r egister ( CHCR) v alue. If the initial
value is used, the out put is low-level.
Rev. 2.0, 11/ 00, page 1035 of 1037
E.3 S am pl e Ext ern al Ci rcui t s
Examples of external circuits for the servo section, and sync signal detection circuit are shown in
figures E. 3, E. 4.
(1) Servo Section
An exa mp l e of th e e xt e rna l c i r cu i t for th e DRMPW M output a nd CAPPW M out put pi ns i s
shown in figure E. 3.
R
1
DRMPWM
CAPPWN
C
1
Figure E.3 Sample External Circuit for Servo Section
(2) Sync Signal Detection Circuit Section
Figure E.4 shows an example of the external circuit for the sync signal detection circuit section.
33 k
Csync
Note: The figures shown are reference values.
Careful consideration should be given to board floating capacitance
and wiring characteristics when deciding on the constants.
10 pF
Figure E.4 Example of External Circuit for Sync Signal Detection Circuit Section
Rev. 2.0, 11/ 00, page 1036 of 1037
Appendix F List of Product Codes
Table F.1 Product Codes List of H8S/2194 Series and H8S/2194C Series
Product Type Product
Code Mar k Code
Package
(Hitachi
Package
Code)
Mask ROM
version HD6432194 HD6432194 (***) F 112- pin Q FP
(FP-112)
H8S/2194
F-ZTAT
version HD64F2194 HD64F2194F 112-pin QFP
(FP-112)
H8S/2193 Mask ROM
version HD6432193 HD6432193 (***) F 112- pin Q FP
(FP-112)
H8S/2192 Mask ROM
version HD6432192 HD6432192 (***)F 112-pin QFP
(FP-112)
H8S/2194
Series
H8S/2191 Mask ROM
version HD6432191 HD6432191 (***) F 112- pin Q FP
(FP-112)
Mask ROM
version HD6432194C HD6432194C (***)F 112-pin QFP
(FP-112)
H8S/2194C
F-ZTAT
version HD64F2194C HD64F2194CF 112- pin Q FP
(FP-112)
H8S/2194B Mask ROM
version HD6432194B HD6432194B (***)F 112-pin QFP
(FP-112)
H8S/2194C
Series
H8S/2194A Mask ROM
version HD6432194A HD6432194A (***)F 112-pin QFP
(FP-112)
Note: (***) is t he RO M code.
Rev. 2.0, 11/ 00, page 1037 of 1037
Appendix G External Dimensions
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.10
23.2 ± 0.3
*0.32 ± 0.08
0.65
1.6
0.8 ± 0.3
*0.17 ± 0.05
3.05 Max
23.2 ± 0.3
84 57
56
29
112
128
20
85
2.70
0
-
8
0.13 M
0.10
+0.15
-
0.10
1.23
0.30 ± 0.06
0.15 ± 0.04
Figure G . 1 Exte rmal Dime nsions (FP-112)
