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FSB70550 Motion SPM(R) 7 Series Features Application * UL Certified No. E209204 (UL1557) * 3-Phase Inverter Driver for Small Power AC Motor Drives * High Performance PQFN Package * 500 V RDS(on) = 1.85 Max FRFET MOSFET 3-Phase Inverter with Gate Drivers and Protection Related Source * AN-9077 - Motion SPM(R) 7 Series User's Guide * Separate Open-Source Pins from Low-Side MOSFETs for Three-Phase Current-Sensing * AN-9078 - Surface Mount Guidelines for Motion SPM(R) 7 Series * Active-HIGH Interface, Works with 3.3 / 5 V Logic, Schmitt-trigger Input General Description The FSB70550 is an advanced Motion SPM(R) 7 module providing a fully-featured, high-performance inverter output stage for AC Induction, BLDC and PMSM motors. These modules integrate optimized gate drive of the built-in MOSFETs (FRFET(R) technology) to minimize EMI and losses, while also providing multiple on-module protection features including under-voltage lockouts, thermal monitoring, fault reporting and interlock function. The built-in one HVIC translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's internal MOSFETs. Separate open-souce MOSFET terminals are available for each phase to support the widest variety of control algorithms. * Optimized for Low Electromagnetic Interference * HVIC Temperature-Sensing Built-In for Temperature Monitoring * HVIC for Gate Driving with Under-Voltage Protection and Interlock Function * Isolation Rating: 1500 Vrms / min. * Moisture Sensitive Level (MSL) 3 * RoHS Compliant 3D Package Drawing (Click to Activate 3D Content) Package Marking & Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FSB70550 FSB70550 PQFN27A 13'' 24 mm 1000 units (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 1 www.fairchildsemi.com FSB70550 Motion SPM(R) 7 Series December 2015 Inverter Part (each MOSFET unless otherwise specified.) Symbol Parameter Conditions Rating Unit 500 V VDSS Drain-Source Voltage of Each MOSFET *ID 25 Each MOSFET Drain Current, Continuous TCB = 25C (1st Notes 1) 5.3 A *ID 80 Each MOSFET Drain Current, Continuous TCB = 80C 3.9 A *IDP Each MOSFET Drain Current, Peak TCB = 25C, PW < 100 s 10.6 A *PD Maximum Power Dissipation TCB = 25C, For Each MOSFET 110 W Rating Unit Control Part (each HVIC unless otherwise specified.) Symbol Parameter Conditions VDD Control Supply Voltage Applied Between VDD and COM 20 V VBS High-side Bias Voltage Applied Between VB and VS 20 V VIN Input Signal Voltage Applied Between IN and COM -0.3 ~ VDD + 0.3 V VFO Fault Output Supply Voltage Applied Between FO and COM -0.3 ~ VDD + 0.3 V IFO Fault Output Current Sink Current FO Pin Current Sensing Input Voltage Applied Between Csc and COM VCSC 5 mA -0.3 ~ VDD + 0.3 V Rating Unit Total System Symbol TJ Parameter Conditions Operating Junction Temperature -40 ~ 150 C TSTG Storage Temperature -40 ~ 125 C VISO Isolation Voltage 1500 Vrms 60 Hz, Sinusoidal, 1 Minute, Connection Pins to Heat Sink Plate 1st Notes: 1. TCB is pad temperature of case bottom. 2. Marking " * " is calculation value or design factor. (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 2 www.fairchildsemi.com FSB70550 Motion SPM(R) 7 Series Absolute Maximum Ratings FSB70550 Motion SPM(R) 7 Series Pin descriptions Pin Number Pin Name 1 /FO Pin Description Fault Output 2 VTS Voltage Output of HVIC Temperature 3 Cfod Capacitor for Duration of Fault Output 4 Csc Capacitor (Low-pass Filter) for Short-circuit Current Detection Input 5 VDD Supply Bias Voltage for IC and MOSFETs Driving 6 IN_UH Signal Input for High-side U Phase 7 IN_VH Signal Input for High-side V Phase 8 (8a) COM 9 IN_WH Common Supply Ground 10 IN_UL Signal Input for Low-side U Phase 11 IN_VL Signal Input for Low-side V Phase 12 IN_WL Signal Input for Low-side W Phase 13 Nu Negative DC-Link Input for U Phase 14 U Output for U Phase 15 Nv Negative DC-Link Input for V Phase Signal Input for High-side W Phase 16 V Output for V Phase 17 W Output for W Phase 18 Nw 19 VS(W) Negative DC-Link Input for W Phase 20 PW Positive DC-Link Input for W Phase 21 PV Positive DC-Link Input for V Phase 22 PU Positive DC-Link Input for U Phase 23 (23a) VS(V) High-side Bias Voltage Ground for V Phase MOSFETs Driving 24 (24a) VS(U) High-side Bias Voltage Ground for U Phase MOSFETs Driving 25 VB(U) High-side Bias Voltage for U Phase MOSFETs Driving 26 VB(V) High-side Bias Voltage for V Phase MOSFETs Driving 27 VB(W) High-side Bias Voltage for W Phase MOSFETs Driving High-side Bias Voltage Ground for W phase Mosfet driving (19) V S(W) (23), (23a) V S(V) (24), (24a) V S(U) OUT(UH) (25) V B(U) (26) V B(V) (27) V B(W) (22) Pu (21) Pv (20) Pw VB(U) VS(U) VB(V) (14) U VB(W) OUT(VH) VS(V) (5) V DD (8),(8a) COM (6) IN_UH (7) IN_VH (9) IN_WH (10) IN_UL (11) IN_VL (12) IN_WL (1) /Fo (2) V TS (3) Cfod (4) Csc (16) V V DD COM OUT(WH) UH VS(W) VH (17) W WH UL OUT(UL) VL (13) Nu WL /Fo OUT(VL) V TS Cfod (15) Nv Csc OUT(WL) (18) Nw Figure 1. Pin Configuration and Internal Block Diagram 1st Notes: 4. Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM(R) 7 product. External connections should be made as indicated in Figure 2. 5. The suffix -a pad is connected with same number pin. ex) 8 and 8a is connected inside. (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 3 www.fairchildsemi.com Inverter Part (each MOSFET unless otherwise specified.) Symbol Parameter Conditions BVDSS Drain - Source Breakdown Voltage VIN = 0 V, ID = 1 mA (2nd Notes 1) IDSS Zero Gate Voltage Drain Current RDS(on) VSD Min Typ Max Unit 500 - - V VIN = 0 V, VDS = 500 V - - 1 mA Static Drain - Source Turn-On Resistance VDD = VBS = 15 V, VIN = 5 V, ID = 1.0 A - 1.6 1.85 Drain - Source Diode Forward Voltage VDD = VBS = 15V, VIN = 0 V, ID = -1.0 A - 0.9 1.2 V tON - 600 - ns tD(ON) - 540 - ns tOFF - 480 - ns - 410 - ns - 1.4 - A tD(OFF) Irr Switching Times VPN = 300 V, VDD = VBS = 15 V, ID = 1.0 A VIN = 0 V 5 V, Inductive Load L = 3 mH Low-Side MOSFET Switching (2nd Notes 2) - 90 - ns EON - 45 - J EOFF - 7 - J trr Control Part (each HVIC unless otherwise specified.) Symbol IQDD Parameter Quiescent VDD Current Conditions Min Typ Max Units VDD=15V, VIN=0V VDD - COM - 1.7 3.0 mA - 45 70 A IQBS Quiescent VBS Current VBS=15V, VIN=0V VB(X)-VS(X),VB(V)-VS(V), VB(W)-VS(W) IPDD Operating VDD Current VDD=15V,FPWM=20kHz, duty=50%, PWM signal input for Low side VDD - COM - 1.9 3.2 mA IPBS Operating VBS Current VBS=15V,FPWM=20kHz, duty=50%, PWM signal input for High side VB(U)-VS(U),VB(V)-VS(V), VB(W)-VS(W) - 300 400 A UVDDD Low-side Undervoltage Protection (Figure 6) VDD Undervoltage Protection Detection Level 7.4 8.0 9.4 V VDD Undervoltage Protection Reset Level 8.0 8.9 9.8 V High-side Undervoltage Protection (Figure 7) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V VTS HVIC Temperature sensing voltage output VDD=15V, THVIC=25C (2nd Notes 3) 580 675 770 mV VIH ON Threshold Voltage Logic High Level VIL OFF Threshold Voltage Logic Low Level VSC(ref) SC Current Trip Level VDD=15V tFOD Fault-out Pulse Width CFOD=33nF (2nd Notes 4) UVDDR UVBSD UVBSR IN - COM CSC - COM - - 2.4 V 0.8 - - V 0.45 0.5 0.55 V 1.0 1.4 1.8 ms 2nd Notes: 1. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM(R) 7 product. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VPN should not exceed BVDSS in any case. 2. tON and tOFF include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applications due to the effect of different printed circuit boards and wirings. Please see Figure 3 for the switching time definition with the switching test circuit of Figure 4. 3. VTS is only for sensing-temperature of module and cannot shutdown MOSFETs automatically. 4. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 24 x 10-6 x tFOD [F] (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 4 www.fairchildsemi.com FSB70550 Motion SPM(R) 7 Series Electrical Characteristics (TJ = 25C, VDD = VBS = 15 V unless otherwise specified.) Symbol Parameter Conditions Min. Typ. Max. Unit VPN Supply Voltage Applied Between P and N - 300 400 V VDD Control Supply Voltage Applied Between VDD and COM 13.5 15.0 16.5 V VBS High-Side Bias Voltage Applied Between VB and VS 13.5 15.0 16.5 V dVDD/dt, dVBS/dt Control Supply Variation -1.0 - 1.0 V/s tdead Blanking Time for Preventing VDD = VBS = 13.5 ~ 16.5 V, TJ 150C Arm-Short 500 - - ns fPWM PWM Switching Frequency - 15 - kHz Min. Typ. Max. Unit - 0.9 - C/W TJ 150C Thermal Resistance Symbol RJCB Parameter Junction to Case Thermal Resistance Conditions Bottom Single MOSFET Operating Condition (3rd Notes 1) 5-V Line These values depend on PWM control algorithm 15-V Line One-Leg Diagram of SPM C1 P V DD R5 Micom V PN VB HIN HO LIN VS Inverter Output C3 /Fo C5 V TS C SC C4 LO N R3 COM 10F C2 C6 R2 * Example of bootstrap paramters: C 1 = C 2 = 1 F ceramic capacitor, Figure 2. Recommended MCU Interface and Bootstrap Circuit with Parameters 3rd Notes: 1. RJCB is simulation value with application board layout. (Please refer user's guide SPM7 series) 2. Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above. 3. RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM(R) is compatible with standard CMOS or LSTTL outptus. 4. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 5 www.fairchildsemi.com FSB70550 Motion SPM(R) 7 Series Recommended Operating Condition ID 120% FSB70550 Motion SPM(R) 7 Series 100% ID t rr Irr V V ID D S ID V IN V D S IN 0 tD tO V (O F F ) tO N 10% IN (O N ) tD (O N ) ID 90% V ID F F 90% IN (O F F ) ID 10% ID (b ) T u rn -o ff (a ) T u rn -o n Figure 3. Switching Time Definition 5-V Line 15-V Line ID VDD VB HIN HO LIN VS /Fo LO L VDC + V DS - VTS COM Figure 4. Switching Test Circuit (Low-side) Input Signal UV Protection Status RESET High-side/Low-side DETECTION RESET UV BSR(DDR) UV BSD(DDD) MOSFET Drain Current Fault Output (Only Low-side UV protection) Figure 5. Under Voltage Protection (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 6 www.fairchildsemi.com c6 Protection Circuit state SET Internal MOSFET Gate-Source Voltage FSB70550 Motion SPM(R) 7 Series Control input c7 RESET c4 c3 c2 SC c1 c8 Output Current SC Reference Voltage Sensing Voltage of the shunt resistance CR circuit time constant delay Fault Output Signal c5 Figure 6. Short-Circuit Current Protection (with the external shunt resistance and CR connection) c1 : Normal operation: MOSFET ON and carrying current. c2 : Short circuit current detection (SC trigger). c3 : Hard MOSFET gate interrupt. c4 : MOSFET turns OFF. c5 : Fault output timer operation start : Fault-out width (tFOD) c6 : Input "L" : MOSFET OFF state. c7 : Input "H": MOSFET ON state, but during the active period of fault output the MOSFET doesn't turn ON. c8 : MOSFET OFF state Hin Lin Ho Lo Figure 7. Timing Chart of Interlock Function (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 7 www.fairchildsemi.com FSB70550 Motion SPM(R) 7 Series Temperature Sensing Voltage, VTS [V] 4.0 Min. Typ. Max. 3.5 Typ. 2.57V@125 3.0 2.5 Typ. 2.10V@100 2.0 1255 1005 1.5 Typ. 1.15V@50 505 1.0 0.5 0.0 0 25 50 75 100 125 150 175 HVIC Temperature, THVIC [] Figure 8. Temperature profile VTS vs. THVIC VS(W) VS(V) VS(U) P OUT(UH) C1 VB(U) VB(V) VB(W) VB(U) VS(U) VB(V) U VB(W) OUT(VH) VS(V) V M C3 VDC 15V 5V C2 R5 VDD VDD COM COM /Fo IN_UH IN_VH IN_WH IN_UL IN_VL IN_WL MCU C5 C8 C4 VTS Cfod Csc C7 OUT(WH) VS(W) W OUT(UL) /Fo Nu UH VH WH OUT(VL) UL Nv VL R3 WL Vts OUT(WL) Nw Cfod Csc R2 C6 Figure 9. Example of Application Circuit 4th Notes: 1. RC-coupling (R5 and C5, R2 and C6) and C1, C5, C7, C8 at each input of Motion SPM(R) 7 product and MCU are useful to prevent improper input signal caused by surge-noise. 2. Ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of HVIC. 3. All the filter capacitors should be connected close to Motion SPM 7 product, and they should have good characteristics for rejecting high-frequency ripple current. (c)2013 Fairchild Semiconductor Corporation FSB70550 Rev. 1.2 8 www.fairchildsemi.com 8 9 10 11 12 13 0.65 3 4 5 1 2 6.45 5.85 5.60 5.05 4.50 4.75 5.28 5.55 5.80 6.08 0.75(9X) 0.55 C A B 1.35 0.00 0.25 4.70 4.60 5.80 6.45 0.10 6 7 27 5.80 4.75 14 26 3.90 0.40(26X) 0.20 8a (1.15) 1.85 1.55 1.15 15 2.85 2.25 2.05 16 1.00 0.60 25 (1.50) 24 0.45 0.00 0.15 0.20 0.30 (1.60) 24a 23 23a 16 0.65 0.80 1.20 1.10 2.50 2.75 2.90 22 4.40 22 2.25 2.65 17 17 5.95 4.05 4.45 4.90 5.60 6.10 6.45 22 20 20 0.35 0.15 (4X) 19 18 18 0.35 (6X) 0.15 4.53 2.75 3.25 1.65 1.45 1.70 21 1.20 1.00 0.40 3.80 3.20 5.07 6.45 6.10 2.50 21 22 BOTTOM VIEW 21 22 13.00 12.80 PKG CL 21 20 SCALE: 2:1 A 20 19 18 B 18 22 22 22 PKG CL23 0.10 C 17 17 16 23a 24a 16 24 25 13.00 12.80 1.40 1.20 0.08 C C 0.30 0.20 0.05 0.00 15 8a 14 26 27 PIN 1 QUADRANT 0.10 C 1.40 1.20 1 2 3 4 5 6 7 8 9 10 11 12 TOP VIEW SEE DETAIL 'A' FRONT VIEW 13 SCALE: 2:1 SEATING PLANE 6.10 6.13 6.88 4.50 1.55 1.73 3.00 0.00 2.50 2.03 1.05 0.97 0.42 3.77 3.22 5.07 6.12 6.88 0.35 22 21 21 0.55 20 20 19 18 18 6.88 22 6.13 0.35 TYP 22 4.40 17 22 2.73 2.48 1.55 0.98 0.20 0.00 0.48 23 0.70 0.65 2.65 2.23 16 1.23 0.80 16 24 1.15 1.53 1.85 17 1.65 23a 24a 1.05 25 15 1.11 (9X) 8a 26 4.50 5.08 14 27 5.85 0.35 1 2 3 0.65 TYP 4 5 6 7 8 9 10 11 12 13 6.13 5.58 4.88 4.48 4.05 0.60 1.03 2.03 2.23 2.88 3.42 3.88 4.78 5.58 5.78 6.23 6.88 LAND PATTERN RECOMMENDATION SCALE: 2:1 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE IS NOT PRESENTLY REGISTERED TO ANY STANDARD COMMITTEE. B) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. C) ALL DIMENSIONS ARE IN MILLIMETERS. D) DRAWING CONFORMS TO ASME Y14.5M-1994. E) LAND PATTERN REFERENCE: QFN65P1290X1290X140-40N-40N F) DRAWING FILE NAME: MKT-PQFN27AREV3. G) IT IS NOT NECESSARY TO SOLDER 23a AND 24a, AND CAN BE OMITTED FROM THE FOOTPRINT H) FAIRCHILD SEMICONDUCTOR 4.78 5.25 5.80 6.10 2.70 2.73 1.33 0.10 0.28 4.72 4.63 5.78 0.30 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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