MOSTEK. 16,384 X 1-BIT DYNAMIC RAM MK4116(J/N/E)-2/3 FEATURES O) Recognized industry standard 16-pin config- uration from MOSTEK O) 150ns access time, 320ns cycle (MK 4116-2) 200ns access time, 375ns cycle (MK 4116-3) O + 10% tolerance on all power supplies (+12V, +5V) O Low power: 462mW active, 20mW standby (max) CO Output data controlled by CAS and unlatched at end of cycle to allow two dimensional chip selec- tion and extended page boundary DESCRIPTION The MK 4116 is a new generation MOS dynamic random access memory circuit organized as 16,384 words by 1 bit. As a state-of-the-art MOS memory device, the MK 4116 (16K RAM) incorporates advanced circuit techniques designed to provide wide operating margins, both internally and to the system user, while achieving performance levels in speed and power previously seen only in MOSTEKs high performance MK 4027 (4K RAM). The technology used to fabricate the MK 4116 is MOSTEK's double-poly, N-channel silicon gate, POLY If @ process. This process, coupled with the use of a single transistor dynamic storage cell, pro- vides the maximum possible circuit density and reliability, while maintaining high performance Common 1/0 capability using early write operation O Read-Modify-Write, RAS-only refresh, and Page- mode capability QO All inputs TTL compatible,low capacitance, and protected against static charge O 128 refresh cycles O ECL compatible on VBB power supply (-5.7V) capability. The use of dynamic circuitry through- out, including sense amplifiers, assures that power dissipation is minimized without any sacrifice in speed or operating margin. These factors combine to make the MK 4116 a truly superior RAM product. Multiplexed address inputs (a feature pioneered by MOSTEK for its 4K RAMS) permits the MK 4116 to be packaged in a standard 16-pin DIP. This recognized industry standard package configuration, while compatible with widely available automated testing and insertion equipment, provides highest possible system bit densities and simplifies system upgrade from 4K to 16K RAMs for new generation applications. Non-critical clock timing requirements allow use of the multiplexing technique while main- taining high performance. FUNCTIONAL DIAGRAM \"oo ee -_n "n ava 1m, pata (Dm BUFFER DATA OUT (Coun) oaTA our aurFER MEMORY ARRAY now DECODER 1 ae I28-SENSE ~ REFRESH AMPS ~ ee ee MEMORY = ARRAY DUMMY CELLS. COLUMN DECODERS vor 64 PIN CONNECTIONS Vee | Ge 16 Vss Din 2q Nis CAS WRITE 3 14 Dout Ras 4 DIZ Ag Ao 5q iz Az Ap 6 q| Dil Ay Ay 7q 10 Ag Voo eq H 9 Vee PIN NAMES Ag-Ag ADDRESS INPUTS WRITE READ/WRITE INPUT eas COLUMN ADDRESS VeB POWER (5V) STROBE Vec POWER (+5V) DIN DATA IN Vop POWER (+12V) Dout DATA OUT Vss GROUND Ree ROW ADDRESS STROBE V33 Oh ANE ile RAMSABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VBB.... 2... - eee eee .0.5V to +20V "Stresses areater than nose iste ander Voltage on VDD. Vcc supplies relative to VSS.......-.. 1.0V to +15.0V permanent damage to the device. This is a VBB-VSS (VDDVSS>OV) 20. ee tenes OV stress rating only and functiona ar eanar Operating temperature, TA (Ambient) ............-...04- ofc to+ 70T tions | above those ingicated In the opera. . . oO, Ih I n Storage temperature (Ambient) Ceramic............... 5BC to t+ 150C iiied, Exposure to spsolute maximum Storage temperature, (Ambient) Plastic ...........-..0000- ~65C to +125C raring raiabitign for extended periods may Short circuit output current 2.6... ee eens 5OmA * , Power dissipation .... 0.0... 0 cece cee ete 1 Watt RECOMMENDED DC OPERATING CONDITIONS (OC <TA< 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voitage Vop 10.8 12.0 13.2 Volts 2 Vcc 4.5 5.0 5.5 Volts 2,3 Vss 0 0 0 Volts 2 VBB 4.5 --5.0 5.7 Volts 2 Input High (Logic 1) Voltage, VinC 2.4 - 7.0 Volts 2 RAS, CAS, WRITE Input High (Logic 1} Voltage, VIH 2.2 _ 7.0 Volts 2 all inputs except RAS, CAS WRITE Input Low (Logic 0) Voltage, Vit 1.0 - 8 Volts 2 all inputs DC ELECTRICAL CHARACTERISTICS (0C <TA <= 70C) (VDD = 12.0V + 10%; VCC = 5.0V +10%; -5.7V < VBB < -4.5V:; VSS = OV) PARAMETER SYMBOL MIN MAX UNITS NOTES OPERATING CURRENT Ipp1 35 ,. mA 4 Average power supply operating current lec1 5 (RAS, CAS cycling; tac = tRC Min IBB1 200 LA STANDBY CURRENT Ipp2 1.5 mA Power supply standby current (RAS = Vinc, Icc2 -10 10 LA DouT = High Impedance) IBB2 100 UA REFRESH CURRENT ipp3 25 mA 4 Average power supply current, refresh mode Iec3 10 10 LA (RAS cycling, CAS = Vinc: tC = tRC Min IBB3 200 LA PAGE MODE CURRENT Ipp4 27 mA 4 Average power supply current, page-mode Iec4 5 operation (RAS =V},_,CAS cycling: 1BB4 200 BA tec = tpc Min INPUT LEAKAGE Wty -10 10 MA Input leakage current, any input (VgBp =-5V, OV< Vin < +7.0V, all other pins not under test = 0 volts) OUTPUT LEAKAGE lo(L) 10 10 LA Output leakage current (DQUT is disabled, OV < VouT <+5.5V) OUTPUT LEVELS Output high (Logic 1) voltage (QUT = 5mA) VOH 24 Volts 3 Output low (Logic GQ} voltage (IgUT = 4.2 mA} VOL 0.4 Volts NOTES: 1. Ta is specified here for operation at frequencies to tac = tac mode, Voc may be reduced to Vss without affecting refresh Cerinaraeuree ea iigaay eon aaeatan ee aigis tow tlon fy not guaranteed inthis mode, = VOM (iN) spesifcn for derating cue etng parameters are met. See figure 1 4. loon, lopg. and | D4 depend on cycle rate. See figures 2,3, and DD es. 2. All voltages referenced to Vgc. 5. loc1 and Icc4 depend upon output loading. During readout oF high level data Vcc is connected through a low impedance 3. Output voltage will swing from Vgg to Vcc when activated with (1352 typ) to data out. At all other times ! consists of no current loading, For purposes of maintaining data in standby V34 leakage currents only.ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (6,7,8) (OC<Tax 70C) '(Vpp = 12.0V + 10%; Vcc = 5.0V +10%, Vss = OV, VBB = -5.7V < VBB < -4.5V) MK 4116-2 MK 4116-3 PARAMETER SYMBOL MIN | MAX MIN |MAX UNITS NOTES Random read or write cycle time tre 320 375 ns 9 Read-write cycle time tRWC 320 375 ns 9 Read modify write cycle time tRMW 320 405 ns 9 Page mode cycle time , tpc 170 225 ns 9 Access time from RAS tRAC 150 200 ns 10,12 Access time from CAS tCAC 100 135 ns 11,12 Output buffer turn-off delay tOFF 0 40 0 50 ns 13 Transition time (rise and fall) tT 3 35 3 50 ns 8 RAS precharge time trp 100 120 ns RAS pulse width tRAS 150 |10,000} 200 {10,000 ns RAS hold time tRSH 100 135 ns CAS hold time tCSH 150 200 ns CAS pulse width tcas 100 110,000 135 | 10,000 ns RAS to CAS delay time tRCD 20 | 50 25 | 65 ns 14 CAS to RAS precharge time tCRP 20 20 ns Row Address set-up time tASR 0 0 ns Row Address hold time tRAH 20 25 ns Column Address set-up time tASC 10 10 ns Column Address hold time tCAH 45 55 ns Column Address hold time referenced to RAS tAR 95 120 ns Read command set-up time tRcs 0 ns Read command hold time tRCH 0 ns Write command hold time tWCH 45 55 ns Write command hold time referenced to RAS twcR 95 120 ns Write command pulse width twp 45 55 ns Write command to RAS lead time tRWL 50 70 ns Write command to CAS lead time tCWL 50 70 ns Data-in set-up time ips 0 0 ns 15 Data-in hold time tDH 45 55 ns 15 Data-in hold time referenced to RAS tDHR 95 120 ns CAS precharge time (for page-mode cycle only) tcp 60 80 ns Refresh period tREF 2 2 ms WRITE command set-up time twes -20 -20 ns 16 CAS to WRITE delay tcWD 60 80 ns 16 RAS to WRITE delay tRWD 110 145 ns 16 14. Operation within the tRCD (max) limit insures that tRAC (max) can be NOTES (Continued) 6. Several cycles are required after power-up before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose. 7. AC measurements assume tT = Sns. 8. VIHC (min) or VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also transition times are measured between VIRC or ViH and VIL. 9. The specifications for tRC (min) tRMW (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature range (OC <= TA = 70C) is assured 10. Assumes that tRCD <tRCD (Max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown, 11. Assumes that tRCD (max). 12. Measured with a load equivalent to 2 TTL loads and 100pF. 13. 1OFF (max} defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. V35 met. tRCD (max) is specified as a reference point only if tRCD is greater than the specified tRCD {max) limit, then access time is controlled exclusively by tCAC. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in delayed write or read-modify-write cycles. tWCS, tCWD and tRWD are restrictive operating parameters in read write and read modify write cycles only. If tWCS = tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance} throughout the entire cycle; If tC\WD = tCWD (min) and tRWD = tRWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell; If neither of the above sets of conditions is satisfied the condition of the data out (at access time) is indeterminate. Effective capacitance calculated from the equation C = 1At A = 3 volts and power supplies at nominal levels. . AV CAS = VIHC to disable DOUT. AV with DYNAMIC RAMSAC ELECTRICAL CHARACTERISTICS (OC <Ta <70)} (Vpp = 12.0V + 10%; Vss = OV; VeB = -5.7V < VBB < -4.5V) PARAMETER SYMBOL TYP MAX UNITS NOTES Input Capacitance (AgAg}, DIN Cy 4 5 pF 17 Input Capacitance RAS, CAS, WRITE Ci2 8 10 pF 17 Output Capacitance (DOUT) Co 5 7 pF 17,18 CYCLE TIME tecins) CYCLE TIME tac ins) 375 320 375 320 1000 500 400 300 250 1000 70 8 < a 2 = wi a : 5 > 30mA w & a a = = 8 som 50 * = 0 1.0 2.0 3.0 4.0 CYCLE RATE (MHz) = 103 /tacins) Fig. 1 Maximum ambient temperature versus cycie rate for extended frequency operation. Ta (max} for operation at cycling rates greater than 2.66 MHz (teyo<375ns) is determined by Ta (max) Cc = 70 9.0 x [cycle rate MHz 2.66) for -3. Ta (max) C = 70 9.0 x cycle rate MHz 3.125MHz) for -2 only. CYCLE TIME tacins) 1000 S00 uu 300 250 MAX 'DD3 SUPPLY CURRENT (mA) 40 9 1.0 a Oo 30 CYCLE RATE (MHz) =103 /tacins) Fig. 3) Maximum 'po3 versus cycle rate for device operation at extended frequencies. |pp3 (max) curve is defined by the equation: Vopgimax) mA = 10 + 6.5 x cycle rate [MHz] for -3 top (max) mA = 10 + 5.5 x cycle rate [MHz] for -2 1.0 20 30 40 CYCLE RATE (MHz) = 103 / tacos) Fig. 2 Maximum 'pp1 versus cycle rate for device operation at extended! frequencies. Ippo {max) curve is defined by the equation: Ipp1 (max) MA = 10 + 9.4 x cycle rate [MHz] for 3 Ipp1 (max) mA = 10 + 8.0 x cycle rate [MHz] for -2 CYCLE TIME tpc ins) 1000 800 400 300 250 5OmA MAX lopg SUPPLY CURRENT (mA) o 10 20 ae 40 CYCLE RATE (MHz) = 107 /tpp ins) Fig. 4 Maximum 'ppa versus cycle rate for device operation in page mode. Inp4 (max) curve is defined by the equation: Ipp4 (max) mA = 10 + 3.75 x cycle rate [MHz] for -3 lppg (max) MA = 10 + 3.2 x cycle rate [MHz] for -2 V36READ CYCLE RAS nee treo oS | tasr tRaH tase. tcan vi ADDRESSES | ABOESS aboness ae bom WRITE Ms WW bee | lea torr trac _________| a Von - TF J VALID S Dout VoL ~ OPEN DATA ; WRITE CYCLE (EARLY WRITE) DYNAMIC RAMS ae tre { Ras a pe t yp __m RAS y \ iL K A kt trsy ___ Re 2 tes et RCD -je bgp, ___ corp o \ _ Vine ~ CAS v \ | wom k Z bt ase RAH ki tasc Vin~ ROW COLUMN ADDRESSES , _ | _ ADDRESS = WT ML YW, Mivcs Com en : = VTL Rw tawe Ses fea bpp; m SIT TL om ar WII ton ware LLL os | Vou~ Dour Vo.- OPENREADWRITE/READMODIFYWRITE CYCLE RAS CAS ADDRESSES WRITE DoUT thwc, aMw ei Vingo on tar +| Vien kK j 7 t Rsu trp ba treo I t cas e-t ore Vine - { | Vix Vin > ASR pam pani tasc t 0 i X_asones sonees LANL Vine ADDRESS ADDRESS Z RWD tow. tres ie cwo ot rw we LMM N ha Swe _ t cac -m wm kee torr Von- ft VALID b Vou- [_ OPEN * DATA +} } trac L. tos sone 1. LLL VALID DATA KUM RASONLY REFRESH CYCLE NOTE: CAS = VyHc, WRITE = Dont Care t RC mp ADDRESSES yn, om WY) YUM My < OLPAGE MODE READ CYCLE mt 7 & * pon tap peo cas e et cpom| pe cas bat cas ho erp Vinee 7 GAS Viu- | ON Sr KS aH ~tcan toan bean taser - na tase conesses EVEL YUL, X XU cac CAC tcac ne torr Se t ofr > orr Dout Mae | OPEN 4 F EF = Le tee tees i trcn-o ~ i a. Sach om - ware LL Ud WML PAGE MODE WRITE CYCLE tras me A -, bt es ~ jo t RSH om tre Etec Me tcp pe teas om eet cag m pw Vine - / CAS View N jj tran | bem t cay can teau tasr asc tase ; tase ADDRESSES wn TTY OY eo M/ ADO 1) Vf TI ADD MW) WM twen ~ bet wen " leat won| ht cw om ht ew - po bow wae MLL WILL WII, IL WITT ja wee a t we he t we kotwer RwL tos yoo! lato my tos ma ton __ ts tou D Min TMI VaR KIN VALIO GHA ; VALID IN Vins DATA 3 DATA i, DATA tour " V-39 RAMS Sj P= <4 2 a a)DESCRIPTION (continued) System oriented features include + 10% tolerance on all power supplies, direct interfacing capability with high performance logic families such as Schottky TTL, maximum input noise immunity to minimize false triggering of the inputs (a common cause of soft errors), on-chip address and data registers which eliminate the need for interface registers, and two chip select methods to allow the user to determine the appropriate speed/power characteristics of his memory system. The MK 4116 also incorporates several flexible timing/operating modes. In addition to the usual read, write, and read-modify-write cycles, the MK 4116 is capable of delayed write cycles, page-mode operation and RAS-only_refresh. Proper control of the clock inputs(RAS, CAS and WRITE) allows common I/O capability, two dimen- sional chip selection, and extended page boundaries (when operating in page mode). ADDRESSING The 14 address bits required to decode1 of the 16,384 cell locations within the MK 4116 are multi- plexed onto the 7 address inputs and latched into the on-chip address latches by externally applying two negative going TTL-level clocks. The first clock, the Row Address Strobe (RAS), latches the 7 row address bits into the chip. The second clock, the Column Address Strobe (CAS), subsequently latches the 7 column address bits into the chip. Each of these signals, RAS and CAS, triggers a sequence of events which are controlled by different delayed internal clocks. The two clock chains are linked together logically in such a way that the address multiplexing operation is done outside of the critical path timing sequence for read data access. The later events in the CAS clock sequence are inhibited until_the occurence of a delayed signal derived from the RAS clock chain. This gated CAS feature allows the CAS clock to be externally activated as soon as the Row Address Hold Time specification (tRAH) has been satisfied and the address inputs have been changed from Row address to Column address information. Note that CAS can be activated at any time after tRAH and it will have no effect on the worst case data access time (tRAC) up to the point in time when the delayed row clock no longer inhibits the remain- ing sequence of column clocks. Two timing end- points result from the internal gating of CAS which are called tRCD (min) and tRCD (max). No data storage or reading errors will result if CAS is applied to the MK 4116 at a point in time beyond the trcp (max) limit. However, access time will then be de- termined exclusively by the access time from CAS (tCAC) rather_than from RAS (tRAc), and access time from RAS will be lengthened by the amount that tRCD exceeds the tRCD (max) limit. DATA INPUT/OUTPUT Data to be written into a selected cell is latched into an_on-chip register by a combination of WRITE and CAS while RAS is active. The later of the signals (WRITE or CAS) to make its negative transition is the strobe for the Data In (Din) register. This permits several options _in the write cycle timing. In a write cycle, if the WRITE input is brought low (active) prior to CAS, the Din is strobed by CAS, and the set-up and hold times are referenced to CAS. If the input data is not available at CAS time or if it is desired that the cycle be a read-write cycle. the WRITE signal will be delayed until after CAS has made its negative transition. In this delayed write cycle the data input set-up and_hold times are re- ferenced to the negative edge of WRITE rather than CAS. (To illustrate this feature, Diy is referenced to WRITE in the timing diagrams depicting the read- write and page-mode write cycles while the early write cycle diagram shows DiN referenced to CAS). Data is retrieved_from the memory in a read cycle by maintaining WRITE in the inactive or high state throughout the portion of the memory cycle in which CAS is active (low). Data read from the selected cell will be available at the output within the specified access time. DATA OUTPUT CONTROL The normal condition of the Data Output (DOUT) of the MK 4116 is the high impedance (open-circuit) state. That is to say, anytime CAS is at a high level, the DOUT pin will be floating. The only time the output will turn on and contain either a logic O or logic 1 is at access time during a read cycle. DOUT will remain valid from access time until CAS is taken back to the inactive (high level) condition. If the memory cycle in progress is a read, read-modify write, or a delayed write cycle, then the data output will go from the high impedance state to the active condition, and at access time will contain the dati read from the selected cell. This output data is the same polarity (not inverted) as the input data. Oncv having gone active, the output will remain valid until CAS is_taken to the precharge (logic 1) state, whether or not RAS goes into precharge. lf the cycle in progress is an early-write cycle (WRITE active before CAS goes active),then the output pin will maintain the high impedance state throughout the entire cycle. Note that with this type of output configuration, the user is given full control of the po AT pin simply by controlling the placement of command during a write cycle, and the pulse width of the Column Address Strobe during read operations. Note also that even though data is not latched at the output, data can remain valid from access time until the beginning of a sub- sequent cycle without paying any penalty in overall memory cycle time (stretching the cycle). This type of output operation results in some very significant system implications. Common {/O Operation If all write operations are handled in the early write mode,then D}jy can be connected directly to DOUT for a common I/O data bus. Data Output Control DOuUT will_remain valid during a read cycle from tcAc until CAS goes back to a high level (precharge), allowing data to be valid from one cycle up until a new memory cycle begins with no_penalty in cycle time. This also makes the RAS/CAS clock timing relationship very flexible. Two Methods of Chip Selection Since DOUT v40is not latched, CAS is not required to turn off the outputs of unselected memory devices in a matrix. This means that both CAS and/or RAS can be decod- ed for chip selection. If both RAS and CAS are decoded, thn a two dimensional (X,Y) chip select array can be realized. Extended Page Boundary Page-mode operation allows for successive memory cycles at multiple column locations of the same row address. By de- coding as a page cycle select signal, the page boundary can be extended beyond the 128 column locations in a single chip. (See page-mode operation). OUTPUT INTERFACE CHARACTERISTICS The three state data output buffer presents the data output pin with a low impedance to VCC for a logic 1 and a low impedance to Vsg for a logic 0. The effective resistance to Vcc (logic 1 state) is 420 maximum and 135Q. typically. The resistance to Vss (logic 0 state) is 95 22 maximum and 35 Q typically. The separate Vcc pin allows the output buffer to be powered from the supply voltage of the logic to which the chip is interfaced. During battery standby operation, the Vcc pin may have power removed without affecting the MK 4116 refresh operation. This allows all systern logic except the RAS timing circuitry and the refresh address logic to be turned off during battery standby to conserve power. PAGE MODE OPERATION The Page Mode feature of the MK 4116 allows for successive memory operations at multiple column locations of the same row address with increased speed without an increase in power. This is done by strobing the row address into the chip and maintain- ing the RAS signal at a logic 0 throughout all success- ive memory cycles in which the row address is com- mon. This page-mode of operation wil! not dissi- pate the_power associated with the negative going edge of RAS. Also, the time required for strobing in a new row address is eliminated, thereby decreas- ing the access and cycle times. The page boundary of a single MK 4116 is limited to the 128 column locations determined by all combi- nations of the 7 column address bits. However, in system applications which utilize more than 16,384 data words, (more than one 16K memory block), the page boundary can be extended by using CAS rather than RAS as the chip select signal. RAS is applied to all devices to latch the row address into each device and then is decoded and serves as a page cycle select signal. Only those devices which receive both Rie and CAS signals will execute a read or write cycle. REFRESH Refresh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 128 row addresses within each 2 millisecond time interval. Although any normal memory cycle will perform the refresh operation, this function is most easily accomp- lished with RAS-only cycles. RAS-only refresh results in a substantial reduction in operating power. This reduction in power is reflected in the IDp3 specification. POWER CONSIDERATIONS Most of the circuitry used in the MK 4116 is dynamic and most of the power drawn is the result of an address strobe edge. Consequently, the dynamic power is primarily a function of operating frequency rather than active duty cycle (refer to the MK 4116 current waveforms in figure 5). This current char- acteristic of the MK 4116 precludes inadvertent burn out of the device in the event that the clock inputs become shorted to ground due to system malfunction. Although no particular power supply noise restriction exists other than the supply voltages remain within the specified tolerance limits, adequate decoupling should be provided to suppress high frequency noise resulting from the transient current of the device. This insures optimum system performance and reliability. Bulk capacitance requirements are minimal since the MK 4116 draws very little steady state (DC) current. In system applications requiring tower power dissi- pation -the operating frequency (cycle rate) of the K 4116 can be reduced and the (guaranteed maxi- mum) average power dissipation of the device will be lowered in accordance with the Ipp1 (max) spec limit curve illustrated in figure 2. OTE: The MK 4116 family is guaranteed to have a maximum IDD1 requirement of 35mA @ 375ns cycle (320ns cycle for the -2) with an ambient temperature range from 0 to 70C. A lower operating frequency, for example 1 microsecond cycle, results in'a reduced maximum lIdd1 requirement of under 20mA with an ambient temperature range from 0 to 70C. It is possible the MK4116 family (-2 and 3 speed selections for example) at frequencies higher than specified, provided all AC operating parameters are met. Operation at shorter cycle times (<tRC min) results in higher power dissipation and, therefore, a reduction in ambient temperature is required. Refer to Figure 1 for derating curve. NOTE: Additional power supply tolerance has been included on the VBB supply to allow direct interface capability with both -5V systems -5.2V ECL systems. RAS/CAS CYCLE LONG RAS /EAS CYCLE FAS ONLY CYCLE 50 NANOSECONDS / DIVISION Fig. 5 Typical Current Waveforms V41 DYNAMIC RAMSAlthough RAS and/or CAS can be decoded and used as a chip select signal for the MK 4116,overall system power is minimized if the Row Address Strobe (R AS) is used for this purpose. Al! unselected de- vices (those which do not receive a RAS) will remain in a low_power (standby) mode regardless of the state of CAS. POWER UP The MK 4116 requires no particular power supply sequencing so long as the Absolute Maximum Rating Conditions are observed. However, in order to insure compliance with the Absolute Maximum Ratings, MOSTEK recommends sequencing of power supplies TYPICAL CHARACTERISTICS TYPICAL ACCESS TIME (NORMALIZED) vs. VDD. TYPICAL 1901 #4. YDO Ty + 80C (vopl/TRAC {vo * 12.0V) 0 Vop SUPPLY VOLTAGE (VOLTS) Vpp SUPPLY VOLTAGE (VOLTS? TYPICAL Ipp2 44. VoD TYPICAL IpD2 vs JUNCTION TEMPERATURE i 5 z 3 * & 5 Ippg SUPPLY CURRENT Imar Vib SUPPLY VOLTAGE (VOLTS! Ty. JUNCTION TEMPERATURE ( C) TYPICAL TEMPERATURE TYPICAL Trac (uvTrac (Ta = 50) (bog SUPPLY CURRENT ima) tre * 0 20 50 Ty, JUNCTION TEMPERATURE ( CP Ty, JUNCTION TEMPERATURE | C1 TYPICAL CLOCK INPUT LEVELS vs. VDD. TYPICAL CLOCK tNPUT LEVELS vs =s0c = 506 Bk INPUT LEVEL {VOLTS! * INBLIT LEVEL (VOI TSI 2 Vue SUPPLY VOLTAGE (VOLTS! 3 Vop SUPPLY VOLTAGE IVOLTS! TYPICAL ADDRESS AND DATA INPUT LEVELS wi. Veg 41 50C 40 45 50 5 Vag SUPPLY VOLTAGE (VOLTS! such that VgB is applied first and removed last. VBB shouid never be more positive than Vss when power is applied to Vpp. Under system failure conditions in which one or more supplies exceed the specified limits significant addi- tional margin against catastrophic ice failure may be achieved by forcing and CAS to the inactive state (high level). After power is applied to the device, the MK 4116 requires several cycles before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose. TYPICAL ACCESS TIME (NORMALIZED! 4. Veg TYPICAL vs JUNCTION Ta 50 3 ' 5 Ipp1 SUPPLY CURRENT ima) Ty, JUNCTION TEMPERATURE { Ct Vpp SUPPLY VOLTAGE IVOLTS) TYPICAL 1903 8. VOD TYPICAL, ACCESS TIME (NORMALIZED) vs. 2 1 2 2500 q ype q o : 8 & z 210 = g g = > z Bao & 2 a 2 2 g 8 2 3 zoe 8 Vcc SUPPLY VOLTAGE (VOLTS) Voo SUPPLY VOLTAGE (VOLTS! TYPICAL IDo4 vs VOD TYPICAL ippa vs. JUNCTION TEMPERATURE = 250m IpD4 SUPPLY CURRENT im) iDD4 SUPPLY CURRENT (mAl Ty. JUNCTION TEMPERATURE [C) Vpp SUPPLY VOLTAGE TYPICAL CLUCK INPUT LEVELS v3. Ty TYPICAL ADDRESS AND DATA INPUT LEVELS vt VoD. 30 Ty = 50C vied (MIND INPUT LEVEL VOLTS) ANPUT LEVEL IVOLTS) os 10 20 Ty, JUNCTION TEMPERATURE ( Gh Yoo SUPPLY VOLTAGE (VOLTS! TYPICAL ADDAESS AND DATA INPUT LEVELS ws. Ty n INPUT LEVEL (VOLTS! 10 110 a 50 90 Ty, JUNCTION TEMPERATURE ( C) V42