TPS61161QDRVRQ1 - Texas Instruments

VIN SW

GND

CTRL

COMP

20mA

TPS61161

ON/OFF

DIMMING

CONTROL

V 3Vto18V

22 Hm

1 Fm

220nF

set

1 Fm

L1: TDKVLCF5020T-220MR75-1

C1:MurataGRM188R61E105K

C2: MurataGRM21BR71H105K

D1:ONsemiMBR0540T1

TPS61161-Q1

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......................................................................................................................................................................................... SLVSA18 –SEPTEMBER 2009

WHITE LED DRIVER WITH DIGITAL AND PWM BRIGHTNESS CONTROL

FOR UP TO 10 LEDs IN SERIES

Check for Samples: TPS61161-Q1

1FEATURES

• Qualified for Automotive Applications • Flexible Digital and PWM Brightness Control

• 2.7-V to 18-V Input Voltage Range • Built-In Soft Start

• 38-V Open LED Protection for 10 LEDs • Up to 90% Efficiency

• 200-mV Reference Voltage With ±2% Accuracy • 2-mm × 2-mm × 0.8-mm 6-pin QFN (DRV)

Package With Thermal Pad

DESCRIPTION

With a 40-V rated integrated switch FET, the TPS61161 is a boost converter that drives up to 10 LEDs in series.

The boost converter runs at 600-kHz fixed switching frequency to reduce output ripple, improve conversion

efficiency, and allow for the use of small external components.

The default white LED current is set with the external sensor resistor Rset, and the feedback voltage is regulated

to 200 mV, as shown in the typical application. During the operation, the LED current can be controlled using the

1-wire digital interface ( EasyScale™ protocol) through the CTRL pin. Alternatively, a pulse width modulation

(PWM) signal can be applied to the CTRL pin through which the duty cycle determines the feedback reference

voltage. In either digital or PWM mode, the TPS61161 does not burst the LED current; therefore, it does not

generate audible noises on the output capacitor. For maximum protection, the device features integrated open

LED protection that disables the TPS61161 to prevent the output from exceeding the absolute maximum ratings

during open LED conditions.

The TPS61161 is available in a space-saving, 2-mm x 2-mm QFN (DRV) package with thermal pad.

Figure 1. Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS61161-Q1

SLVSA18 –SEPTEMBER 2009.........................................................................................................................................................................................

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

TAPACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING

–40°C to 125°C QFN – DRV Reel of 3000 TPS61161QDRVRQ1 PSJQ

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)

VALUE UNIT

Supply voltage on VIN (2) –0.3 to 20 V

Voltage on CTRL(2) –0.3 to 20 V

VIVoltage on FB and COMP(2) –0.3 to 3 V

Voltage on SW(2) –0.3 to 40 V

PDContinuous power dissipation See Dissipation Rating Table

TJOperating junction temperature range –40 to 150 °C

TSTG Storage temperature range –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

DISSIPATION RATINGS DERATING FACTOR

BOARD PACKAGE RθJC RθJA TA< 25°C TA= 70°C TA= 125°C

ABOVE TA= 25°C

Low-K(1) DRV 100°C/W 291°C/W 7.1 mW/°C 887 mW 568 mW 175 mW

High-K(2) DRV 75°C/W 15.4 mW/°C 1925 mW 1232 mW 385 mW

(1) The JEDEC low-K (1s) board used to derive this data was a 3in×3in, two-layer board with 2-ounce copper traces on top of the board.

(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in×3in, multilayer board with 1-ounce internal power and ground planes

and 2-ounce copper traces on top and bottom of the board.

RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT

VIInput voltage range, VIN 2.7 18 V

VOOutput voltage range VIN 38 V

L Inductor(1) 10 22 µH

fdim PWM dimming frequency 5 100 kHz

Duty At 10 kHz 0.5

PWM duty cycle resolution %

At 30 kHz 1.5

CIN Input capacitor 1 µF

COOutput capacitor(1) 0.47 10 µF

TAOperating ambient temperature –40 125 °C

(1) These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in

other applications but should be fully tested by the user.

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ELECTRICAL CHARACTERISTICS

VIN = 3.6 V, CTRL = VIN, TA= –40°C to 125°C, typical values are at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

VIInput voltage range, VIN 2.7 18 V

IQOperating quiescent current into VIN Device PWM switching no load 1.8 mA

ISD Shutdown current CRTL = GND, VIN = 4.2 V 1 µA

UVLO Undervoltage lockout threshold VIN falling 2.2 2.5 V

Vhys Undervoltage lockout hysteresis 70 mV

ENABLE AND REFERENCE CONTROL

V(CTRLh) CTRL logic high voltage VIN = 2.7 V to 18 V 1.2 V

V(CTRLl) CTRL logic low voltage VIN = 2.7 V to 18 V 0.4 V

R(CTRL) CTRL pull down resistor 400 800 1600 kΩ

toff CTRL pulse width to shutdown CTRL high to low 2.5 ms

tes_det EasyScale detection time(1) CTRL pin low 260 µs

tes_delay EasyScale detection delay 100 µs

tes_win EasyScale detection window time Measured from CTRL high 1 ms

VOLTAGE AND CURRENT CONTROL

VREF Voltage feedback regulation voltage 196 200 204 mV

V(REF_PWM) Voltage feedback regulation voltage under VFB = 50 mV 47 50 53 mV

brightness control VFB = 20 mV 17 20 23

IFB Voltage feedback input bias current VFB = 200 mV 2 µA

fSOscillator frequency 500 600 700 kHz

Dmax Maximum duty cycle VFB = 100 mV 90 93 %

tmin_on Minimum on pulse width 40 ns

Isink Comp pin sink current 100 µA

Isource Comp pin source current 100 µA

Gea Error amplifier transconductance 240 320 400 µmho

Rea Error amplifier output resistance 6 MΩ

fea Error amplifier crossover frequency 5 pF connected to COMP 500 kHz

POWER SWITCH

N-channel MOSFET on-resistance VIN = 3.6 V 0.3 0.6

RDS(on) Ω

VIN = 3.0 V 0.7

ILN_NFET N-channel leakage current VSW = 35 V, TA= 25°C 1 µA

OC and OLP

ILIM N-Channel MOSFET current limit D = Dmax 0.56 0.7 0.84 A

ILIM_Start Start up current limit D = Dmax 0.4 A

tHalf_LIM Time step for half current limit 5 ms

Vovp Open LED protection threshold 37 38 39 V

Open LED protection threshold on FB Measured on the FB pin, percentage

V(FB_OVP) 50%

of Vref, Vref = 200 mV and 20 mV

tREF VREF filter time constant 180 µs

tstep VREF ramp up time 213 µs

(1) To select EasyScale mode, the CTRL pin must be low for more than tes_det during tes_win

Product Folder Link(s): TPS61161-Q1

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 3.6 V, CTRL = VIN, TA= –40°C to 125°C, typical values are at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EasyScale TIMING

tstart Start time of program stream 2 µs

tEOS End time of program stream 2 360 µs

tH_LB High time low bit Logic 0 2 180 µs

tL_LB Low time low bit Logic 0 2 × tH_LB 360 µs

tH_HB High time high bit Logic 1 2 × tL_HB 360 µs

tL_HB Low time high bit Logic 1 2 180 µs

VACKNL Acknowledge output voltage low Open drain, Rpullup =15 kΩto VIN 0.4 V

tvalACKN Acknowledge valid time See (2) 2 µs

tACKN Duration of acknowledge condition See (2) 512 µs

THERMAL SHUTDOWN

Tshutdown Thermal shutdown threshold 160 °C

Thysteresis Thermal shutdown threshold hysteresis 15 °C

(2) Acknowledge condition active 0, this condition will only be applied in case the RFA bit is set. Open drain output, line needs to be pulled

high by the host with resistor load.

Product Folder Link(s): TPS61161-Q1

VIN

CTRL

COMP

GND

TOP VIEW

Thermal

Pad

6-PIN2mmx2mmx0.8mmQFN

TPS61161-Q1

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DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

VIN 6 I The input supply pin for the IC. Connect VIN to a supply voltage between 2.7V and 18V.

This is the switching node of the IC. Connect the inductor between the VIN and SW pin. This pin is also

SW 4 I used to sense the output voltage for open LED protection

GND 3 O Ground

FB 1 I Feedback pin for current. Connect the sense resistor from FB to GND.

Output of the transconductance error amplifier. Connect an external capacitor to this pin to compensate the

COMP 2 O regulator.

Control pin of the boost regulator. It is a multi-functional pin which can be used for enable control, PWM

CTRL 5 I and digital dimming.

The thermal pad should be soldered to the analog ground plane. If possible, use thermal via to connect to

Thermal Pad ground plane for ideal power dissipation.

Product Folder Link(s): TPS61161-Q1

Ramp

Generator

Oscillator

Current

Sensor

OLP

CTRL

GND

Reference

Control

Error

Amplifer

Rset

Vin

PWMControl

Soft

Start-up

COMP

TPS61161-Q1

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FUNCTIONAL BLOCK DIAGRAM

Product Folder Link(s): TPS61161-Q1

100

0 10 20 30 40 50

OutputCurrent-mA

4(12.8V),6(19.2V)LEDs

8(25.6V),10(32V)LEDs

6LEDs

V =3.6V

I4LEDs

8LEDs

10LEDs

Efficiency-%

100

0 10 20 30 40 50

10LEDs- TPS61161

V =5V

V =3.6V

V =12V

OutputCurrent-mA

Efficiency-%

300

400

500

600

700

800

900

1000

-40 -20 0 20 40 60 80 100 120 140

Temperature- C°

SwitchCurrentLimit-mA

300

400

500

600

700

800

900

1000

20 30 40 50 60 70 80 90

DutyCycle-%

SwitchCurrentLimit-mA

TPS61161-Q1

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TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

Efficiency TPS61161 VIN = 3.6 V; 4, 6, 8, 10 LEDs; L = 22 µH Figure 2

Efficiency TPS61161 Figure 3

Current limit TA= 25°C Figure 4

Current limit Figure 5

EasyScale step Figure 6

PWM dimming linearity VIN = 3.6 V; PWM Freq = 10 kHz and 40 kHz Figure 6

Output ripple at PWM dimming 8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; PWM Freq = 10 kHz Figure 8

Switching waveform 8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; L = 22 µH Figure 9

Start-up 8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; L =22 µH Figure 10

Open LED protection 8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; L = 22 µH Figure 11

EFFICIENCY EFFICIENCY

vs vs

OUTPUT CURRENT OUTPUT CURRENT

Figure 2. Figure 3.

SWITCH CURRENT LIMIT SWITCH CURRENT LIMIT

vs vs

DUTY CYCLE TEMPERATURE

Figure 4. Figure 5.

Product Folder Link(s): TPS61161-Q1

100

120

140

160

180

200

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

EasyScaleStepStep

FBVoltage-mV

120

160

200

0 20 40 60 80 100

PWMDutyCycle-%

10kHz,40kHz

FBVoltage-mV

t-1 s/divm

20V/div

VOUT

20mV/div

200mA/div

t-100 s/divm

PWM2V/div

VOUT 20mV/div AC

I 10mA/div

LED

t-2ms/div

CTRL

5V/div

VOUT

10V/div

COMP

500mV/div

200mA/div

t-100 s/divm

OPENLED

5V/div

200mV/div

VOUT

10V/div

200mA/div

TPS61161-Q1

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FB VOLTAGE FB VOLTAGE

vs vs

EASYSCALE STEP PWM DUTY CYCLE

Figure 6. Figure 7.

OUTPUT RIPPLE at PWM DIMMING SWITCHING WAVEFORM

Figure 8. Figure 9.

START-UP OPEN LED PROTECTION

Figure 10. Figure 11.

Product Folder Link(s): TPS61161-Q1

ILED +VFB

RSET

TPS61161-Q1

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DETAILED DESCRIPTION

OPERATION

The TPS61161 is a high efficiency, high output voltage boost converter in small package size, The device is ideal

for driving up to 10 white LED in series. The serial LED connection provides even illumination by sourcing the

same output current through all LEDs, eliminating the need for expensive factory calibration. The device

integrates 40-V/0.7-A switch FET and operates in pulse width modulation (PWM) with 600kHz fixed switching

frequency. For operation see the block diagram. The duty cycle of the converter is set by the error amplifier

output and the current signal applied to the PWM control comparator. The control architecture is based on

traditional current-mode control; therefore, a slope compensation is added to the current signal to allow stable

operation for duty cycles larger than 50%. The feedback loop regulates the FB pin to a low reference voltage

(200mV typical), reducing the power dissipation in the current sense resistor.

SOFT START-UP

Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is

enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps, each step takes 213 µs. This

ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5 ms after the

COMP voltage ramps, the current limit of the switch is set to half of the normal current limit spec. During this

period, the input current is kept below 400 mA (typical). See the start-up waveform of a typical example,

Figure 10.

OPEN LED PROTECTION

Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61161

monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the switch FET

and shuts down the IC as soon as the SW voltage exceeds the Vovp threshold and the FB voltage is less than

half of regulation voltage for 8 clock cycles. As a result, the output voltage falls to the level of the input supply.

The device remains in shutdown mode until it is enabled by toggling the CTRL pin logic. To allow the use of

inexpensive low-voltage output capacitor, the TPS61161 has different open lamp protection thresholds to prevent

the internal 40V FET from breaking down. The threshold is set at 38 V. The devices can be selected according to

the number of external LEDs and their maximum forward voltage.

SHUTDOWN

The TPS61161 enters shutdown mode when the CTRL voltage is logic low for more than 2.5 ms. During

shutdown, the input supply current for the device is less than 1 µA (max). Although the internal FET does not

switch in shutdown, there is still a dc current path between the input and the LEDs through the inductor and

Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to

ensure that the LEDs remain off in shutdown. However, in the typical application with two or more LEDs, the

forward voltage is large enough to reverse bias the Schottky and keep leakage current low.

CURRENT PROGRAM

The FB voltage is regulated by a low 0.2V reference voltage. The LED current is programmed externally using a

current-sense resistor in series with the LED string. The value of the RSET is calculated using Equation 1:

(1)

Where

ILED = output current of LEDs

VFB = regulated voltage of FB

RSET = current sense resistor

The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.

Product Folder Link(s): TPS61161-Q1

CTRL

low

high

200mVxdutycycle

Insertbattery

CTRL

low

high

Insertbattery

Programming

code

FBramp Shutdowndelay

EnterESmode

Timingwindow Programmingcode

50mV 50mV

EnterESmode

PWMsignal

Startup

delay

PWM

mode

Startupdelay

FBramp

Programmedvalue

(ifnotprogrammed, 200mVdefault )

Shutdown

delay

Shutdown

Startupdelay

FBramp

mode ESdetectdelay

ESdetecttime

VFB +Duty 200 mV

TPS61161-Q1

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LED BRIGHTNESS DIMMING MODE SELECTION

The CTRL pin is used for the control input for both dimming modes, PWM dimming and 1 wire dimming. The

dimming mode for the TPS61161 is selected each time the device is enabled. The default dimming mode is

PWM dimming. To enter the 1 wire mode, the following digital pattern on the CTRL pin must be recognized by

the IC every time the IC starts from the shutdown mode.

1. Pull CTRL pin high to enable the TPS61161, and to start the 1 wire detection window.

2. After the EasyScale detection delay (tes_delay, 100 µs) expires, drive CTRL low for more than the EasyScale

detection time (tes_detect, 260 µs).

3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window

(tes_win, 1 ms) expires. EasyScale detection window starts from the first CTRL pin low to high transition.

The IC immediately enters the 1-wire mode once the above three conditions are met. The EasyScale

communication can start before the detection window expires. Once the dimming mode is programmed, it can

not be changed without another start up. This means the IC needs to be shutdown by pulling the CTRL low for

2.5 ms and restarts. See the Dimming Mode Detection and Soft Start (Figure 12) for a graphical explanation.

Figure 12. Dimming Mode Detection and Soft Start PWM Brightness Dimming

PWM BRIGHTNESS DIMMING

When the CTRL pin is constantly high, the FB voltage is regulated to 200 mV typically. However, the CTRL pin

allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The

relationship between the duty cycle and FB voltage is given by Equation 2.

(2)

Where

Duty = duty cycle of the PWM signal

200 mV = internal reference voltage

As shown in Figure 13, the IC chops up the internal 200-mV reference voltage at the duty cycle of the PWM

signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the

error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for

brightness dimming, only the WLED dc current is modulated, which is often referred as analog dimming. This

eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and

duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, TPS61161

regulation voltage is independent of the PWM logic voltage level which often has large variations.

Product Folder Link(s): TPS61161-Q1

VBG

200mV

Error

Amplifier

CTRL

TPS61161-Q1

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For optimum performance, use the PWM dimming frequency in the range of 5 kHz to 100 kHz. The requirement

of minimum dimming frequency comes from the EasyScale detection delay and detection time specification in the

dimming mode selection. Since the CTRL pin is logic only pin, adding external RC filter applied to the pin does

not work.

Figure 13. Block Diagram of Programmable FB Voltage Using PWM Signal

To use lower PWM dimming, add an external RC network connected to the FB pin as shown in the additional

typical application (Figure 18).

DIGITAL 1 WIRE BRIGHTNESS DIMMING

The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save

the processor power and battery life as it does not require a PWM signal all the time, and the processor can

enter idle mode if available.

The TPS61161 adopts the EasyScale™ protocol for the digital dimming, which can program the FB voltage to

any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo

logarithmic curve for the brightness step. See the Table 1 for the FB pin voltage steps. The default step is full

scale when the device is first enabled (VFB = 200 mV). The programmed reference voltage is stored in an internal

EasyScale™: 1-WIRE DIGITAL DIMMING

EasyScale is a simple but flexible one-pin interface to configure the FB voltage. The interface is based on a

master-slave structure, where the master is typically a microcontroller or application processor. Figure 14 and

Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte.

The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two

address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The

Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale

compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit

transmission rate. It can automatically detect bit rates between 1.7 kbit/s and up to 160 kbit/s.

Product Folder Link(s): TPS61161-Q1

DATA IN

Start

DATA OUT ACK

RFA A1 A0 D4 D3 D2 D1 D0DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

Device Address DATABYTE

EOS Start EOS

Start

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Table 1. Selectable FB Voltage

FB voltage D4 D3 D2 D1 D0

(mV)

0 0 0 0 0 0 0

1 5 0 0 0 0 1

2 8 0 0 0 1 0

3 11 0 0 0 1 1

4 14 0 0 1 0 0

5 17 0 0 1 0 1

6 20 0 0 1 1 0

7 23 0 0 1 1 1

8 26 0 1 0 0 0

9 29 0 1 0 0 1

10 32 0 1 0 1 0

11 35 0 1 0 1 1

12 38 0 1 1 0 0

13 44 0 1 1 0 1

14 50 0 1 1 1 0

15 56 0 1 1 1 1

16 62 1 0 0 0 0

17 68 1 0 0 0 1

18 74 1 0 0 1 0

19 80 1 0 0 1 1

20 86 1 0 1 0 0

21 92 1 0 1 0 1

22 98 1 0 1 1 0

23 104 1 0 1 1 1

24 116 1 1 0 0 0

25 128 1 1 0 0 1

26 140 1 1 0 1 0

27 152 1 1 0 1 1

28 164 1 1 1 0 0

29 176 1 1 1 0 1

30 188 1 1 1 1 0

31 200 1 1 1 1 1

Figure 14. EasyScale Protocol Overview

Product Folder Link(s): TPS61161-Q1

LowBit

(Logic0)

HighBit

(Logic1)

tLow tHigh tLOW tHigh

EasyScaleTiming,withoutacknowledgeRFA =0

DA7

tStart

StaticHigh StaticHigh

DATA IN

tStart

TEOS TEOS

DA0

RFA

AddressByte DATA Byte

EasyScaleTiming,withacknowledgeRFA =1

StaticHigh

tACKN

Acknowledge

true,DataLine

pulleddownby

device

DATA IN

DATA OUT Acknowledge

false,nopull

down

Controllerneedsto

PullupDataLineviaa

resistortodetect ACKN

ACKN

DA7

StaticHigh

TEOS tvalACK

DA0

RFA

tStart tStart

AddressByte DATA Byte

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Table 2. EasyScale Bit Description

BIT TRANSMISSION

BYTE NAME DESCRIPTION

NUMBER DIRECTION

7 DA7 0 MSB device address

6 DA6 1

5 DA5 1

Device 4 DA4 1

Address IN

Byte 3 DA3 0

72 hex 2 DA2 0

1 DA1 1

0 DA0 0 LSB device address

7 (MSB) RFA Request for acknowledge. If high, acknowledge is applied by device

6 A1 0 Address bit 1

5 A0 0 Address bit 0

4 D4 Data bit 4

Data byte IN

3 D3 Data bit 3

2 D2 Data bit 2

1 D1 Data bit 1

0 (LSB) D0 Data bit 0

Acknowledge condition active 0, this condition will only be applied in case RFA bit is

set. Open drain output, Line needs to be pulled high by the host with a pullup

ACK OUT resistor. This feature can only be used if the master has an open drain output stage.

In case of a push pull output stage Acknowledge condition may not be requested!

Figure 15. EasyScale™— Bit Coding

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All bits are transmitted MSB first and LSB last. Figure 15 shows the protocol without acknowledge request (Bit

RFA = 0), Figure 15 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data

byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2 µs) before

the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is

needed prior to the device address byte. The transmission of each byte is closed with an End of Stream

condition for at least tEOS (2 µs).

The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and

tHIGH. It can be simplified to:

High Bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 15.

Low Bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 15.

The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on

the relation between tHIGH and tLOW, the logic 0 or 1 is detected.

The acknowledge condition is only applied if:

• Acknowledge is requested by a set RFA bit.

• The transmitted device address matches with the device address of the device.

• 16 bits is received correctly.

If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512 µs

maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal

ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master

controller keeps the line low in this period. The master device can detect the acknowledge condition with its input

by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the

acknowledge condition ends.

Note that the acknowledge condition may only be requested in case the master device has an open drain output.

For a push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500 µA is

recommended to for such cases as:

• an accidentally requested acknowledge

• to protect the internal ACKN-MOSFET

UNDERVOLTAGE LOCKOUT

An undervoltage lockout prevents operation of the device at input voltages below typical 2.2 V. When the input

voltage is below the undervoltage threshold, the device is shutdown and the internal switch FET is turned off. If

the input voltage rises by undervoltage lockout hysteresis, the IC restarts.

THERMAL SHUTDOWN

An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.

The device is released from shutdown automatically when the junction temperature decreases by 15°C.

Product Folder Link(s): TPS61161-Q1

é+

´´

)

VVV

(FL

ininfout

Iout_max +Vin ǒIlim *IPń2Ǔ h

Vout

Iin_DC +Vout Iout

Vin h

TPS61161-Q1

www.ti.com

APPLICATION INFORMATION

MAXIMUM OUTPUT CURRENT

The overcurrent limit in a boost converter limits the maximum input current and thus maximum input power for a

given input voltage. Maximum output power is less than maximum input power due to power conversion losses.

Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current

output. The current limit clamps the peak inductor current; therefore, the ripple has to be subtracted to derive

maximum dc current. The ripple current is a function of switching frequency, inductor value and duty cycle. The

following equations take into account of all the above factors for maximum output current calculation.

(3)

Where:

Ip= inductor peak to peak ripple

L = inductor value

Vf= Schottky diode forward voltage

Fs = switching frequency

Vout = output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across LEDs.

(4)

Where:

Iout_max = maximum output current of the boost converter

Ilim = over current limit

η= efficiency

For instance, when VIN is 3.0 V, 8 LEDs output equivalent to VOUT of 26 V, the inductor is 22 µH, the Schottky

forward voltage is 0.2 V; and then the maximum output current is 65 mA in typical condition. When VIN is 5 V, 10

LEDs output equivalent to VOUT of 32 V, the inductor is 22 µH, the Schottky forward voltage is 0.2 V; and then

the maximum output current is 85 mA in typical condition.

INDUCTOR SELECTION

The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These

factors make it the most important component in power regulator design. There are three important inductor

specifications, inductor value, dc resistance and saturation current. Considering inductor value alone is not

enough.

The inductor value determines the inductor ripple current. Choose an inductor that can handle the necessary

peak current without saturating, according to half of the peak-to-peak ripple current given by Equation 3, pause

the inductor dc current given by:

(5)

Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation

level, its inductance can decrease 20% to 35% from the 0-A value depending on how the inductor vendor defines

saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM when the

inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter’s

maximum output current, causes large input voltage ripple and reduces efficiency. Large inductance value

provides much more output current and higher conversion efficiency. For these reasons, a 10-µH to 22-µH

inductor value range is recommended. A 22-µH inductor optimized the efficiency for most application while

maintaining low inductor peak to peak ripple. Table 3 lists the recommended inductor for the TPS61161. When

recommending inductor value, the factory has considered –40% and +20% tolerance from its nominal value.

Product Folder Link(s): TPS61161-Q1

Cout +ǒVout *VinǓIout

Vout Fs Vripple

Vripple_ESR +Iout RESR

TPS61161-Q1

www.ti.com

TPS61161 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode

control. If the inductor value is lower than 10 µH, the slope compensation may not be adequate, and the loop can

be unstable. Therefore, customers need to verify the inductor in their application if it is different from the

recommended values.

Table 3. Recommended Inductors for TPS61161

L DCR MAX SATURATION CURRENT SIZE

PART NUMBER VENDOR

(µH) (Ω) (mA) (L × W × H mm)

LQH3NPN100NM0 10 0.3 750 3×3×1.5 Murata

VLCF5020T-220MR75-1 22 0.4 750 5×5×2.0 TDK

CDH3809/SLD 10 0.3 570 4×4×1.0 Sumida

A997AS-220M 22 0.4 510 4×4×1.8 TOKO

SCHOTTKY DIODE SELECTION

The high switching frequency of the TPS61161 demands a high-speed rectification for optimum efficiency.

Ensure that the diode average and peak current rating exceeds the average output current and peak inductor

current. In addition, the diode’s reverse breakdown voltage must exceed the open LED protection voltage. The

ONSemi MBR0540 and the ZETEX ZHCS400 are recommended for TPS61161.

COMPENSATION CAPACITOR SELECTION

The compensation capacitor C3 (see the block diagram), connected from COMP pin to GND, is used to stabilize

the feedback loop of the TPS61161. Use a 220-nF ceramic capacitor for C3.

INPUT AND OUTPUT CAPACITOR SELECTION

The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This

ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a

capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by

(6)

where, Vripple = peak-to-peak output ripple. The additional output ripple component caused by ESR is calculated

using:

(7)

Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or

electrolytic capacitors are used.

Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging, and ac signal. For

example, larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switching

frequency. So the effective capacitance is significantly lower. The dc bias can also significantly reduce

capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore,

leave the margin on the voltage rating to ensure adequate capacitance at the required output voltage.

The capacitor in the range of 1 µF to 4.7 µF is recommended for input side. The output requires a capacitor in

the range of 0.47 µF to 10 µF. The output capacitor affects the loop stability of the boost regulator. If the output

capacitor is below the range, the boost regulator can potentially become unstable. For example, if use the output

capacitor of 0.1 µF, a 470 nF compensation capacitor has to be used for the loop stable.

The popular vendors for high value ceramic capacitors are:

TDK (http://www.component.tdk.com/components.php)

Murata (http://www.murata.com/cap/index.html)

Product Folder Link(s): TPS61161-Q1

CTRL

GND

Rset

Vin

CTRL

COMP

GND

C1 Vin

LEDsIN

LEDsOut

Minimizethe

areaofthis

trace

Placeenough

VIAsaround

thermalpadto

enhancethermal

performance

PD(max) +125°C*TA

RqJA

TPS61161-Q1

www.ti.com

LAYOUT CONSIDERATIONS

As for all switching power supplies, especially those high frequency and high current ones, layout is an important

design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.

To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of

high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the

length and area of all traces connected to the SW pin and always use a ground plane under the switching

regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output

capacitor, contains high current rising and falling in nanosecond and should be kept as short as possible. The

input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the IC

supply ripple. Figure 16 shows a sample layout.

Figure 16. Sample Layout

THERMAL CONSIDERATIONS

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This

restriction limits the power dissipation of the TPS61161. Calculate the maximum allowable dissipation, PD(max),

and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined

using Equation 8:

(8)

where, TAis the maximum ambient temperature for the application. RθJA is the thermal resistance

junction-to-ambient given in Power Dissipation Table.

The TPS61161 comes in a thermally enhanced QFN package. This package includes a thermal pad that

improves the thermal capabilities of the package. The RθJA of the QFN package greatly depends on the PCB

layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using

thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB

Attachment application report (SLUA271).

Product Folder Link(s): TPS61161-Q1

Vin 3 V to 5 V

10 Hm

1 Fm

Rset

10 W

VIN SW

GND

CTRL

COMP

0.47 Fm

20mA

220 nF

TPS61160 (TBD)

ON/OFF

DIMMING

CONTROL

L1:

C1: Murata GRM188R61A105K

C2: Murata GRM188R61E474K

D1:

Murata LQH3NPN100NM0

ONsemi MBR0540T1

10 Hm

1 Fm

Rset

10 W

VIN SW

GND

CTRL

COMP

0.47 Fm

TPS61160 (TBD)

ON/OFF

DIMMING

CONTROL

80 kW

10 kW

100 kW

0.1 Fm

220 nF

PWM Signal: 1.8 V; 200 Hz

LED Current = 1.8 V x (1 - d)/ (8 x Rset)

L1:

C1: Murata GRM188R61A105K

C2: Murata GRM188R61E474K

D1:

Murata LQH3NPN100NM0

ONsemi MBR0540T1

Vin3Vto5V

22 HmD1

Rset

10 W

VIN SW

GND

CTRL

COMP

1 Fm

20mA

220nF

TPS61161

ON/OFF

DIMMING

CONTROL

1 Fm

L1: TDKVLCF5020T-220MR75-1

C1:MurataGRM188R61A105K

C2: MurataGRM21BR71H105K

D1:ONsemiMBR0540T1

TPS61161-Q1

www.ti.com

ADDITIONAL TYPICAL APPLICATIONS

Figure 17. Li-Ion Driver for 6 White LEDs

Figure 18. Li-Ion Driver for 6 White LEDs With External PWM Dimming Network

Figure 19. Li-Ion Driver for 8 White LEDs

Product Folder Link(s): TPS61161-Q1

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TPS61161QDRVRQ1 ACTIVE SON DRV 6 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS61161-Q1 :

•Catalog: TPS61161

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

PACKAGE OPTION ADDENDUM

www.ti.com 6-Oct-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS61161QDRVRQ1 SON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jun-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS61161QDRVRQ1 SON DRV 6 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jun-2012

Pack Materials-Page 2

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