Electrical characteristics ST10F273M
136/186 Doc ID 13453 Rev. 3
IPD3
Power down supply current(11)
(RTC on, 32 kHz oscillator on, main voltage
regulator off)
TA = 25°C – 200 µA
ISB1
Standby supply current(13)
(RTC off, oscillators off, VDD off, VSTBY on)
VSTBY = 5.5 V
TA = TJ = 25°C –250µA
VSTBY = 5.5 V
TA = TJ = 125°C –500µA
ISB2
Standby supply current(13)
(RTC on, 32 kHz oscillator on, main VDD off,
VSTBY on)
VSTBY = 5.5 V
TA = TJ = 25°C –250µA
VSTBY = 5.5 V
TA = TJ = 125°C –500µA
ISB3
Standby supply current(8)(13)
(VDD transient condition) ––2.5mA
1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is imposed by the external circuitry.
2. Port 5 leakage values are granted for not selected A/D converter channel. One channels is always selected (by default,
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
3. Consult your vendor to know which version of the on-chip oscillator amplifier is enabled (Low-Power or Wide-Swing).
The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 38 for a scheme of the input
circuitry.
4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
for CS output and the open drain function is not enabled.
5. The maximum current may be drawn while the respective signal line remains inactive.
6. The minimum current must be drawn in order to drive the respective signal line active.
7. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure Figure 39 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all
outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: This implies that I/O current is not considered.
The device is doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Convers ion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
8. Not 100% tested, guaranteed by design characterization.
9. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 39 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: This implies that I/O current is not considered. The
device is doing the following:
Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Convers ion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
10. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 38 below. These parameters are tested and at maximum CPU clock with all outputs disconnected
and all inputs at VIL or VIH, RSTIN pin at VIH1Min.
Table 57. DC characteristics (continued)
Symbol Parameter Test condition Limit values Unit
Min Max