UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 Economy Primary Side Controller PRELIMINARY FEATURES DESCRIPTION * User Programmable Soft Start With Active Low Shutdown * User Programmable Maximum Duty Cycle * Accessible 5V Reference * Undervoltage Lockout The UCC3809 family of BCDMOS economy low power integrated circuits contains all the control and drive circuitry required for off-line and isolated DC-to-DC fixed frequency current mode switching power supplies with minimal external parts count. Internally implemented circuits include undervoltage lockout featuring startup current less than 100A, a user accessible voltage reference, logic to ensure latched operation, a PWM comparator, and a totem pole output stage to sink or source peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state. * Operation to 1MHz * 0.4A Source/0.6A Sink FET Driver * Low 100A Startup Current Oscillator frequency and maximum duty cycle are programmed with two resistors and a capacitor. The UCC3809 family also features full cycle soft start. The family has UVLO thresholds and hysteresis levels for off-line and DC-to-DC systems as shown in the table below. PART NUMBER UCCX809-1 UCCX809-2 TURN ON THRESHOLD 10V 15V TURN OFF THRESHOLD 8V 8V BLOCK DIAGRAM UDG-97080-1 1/98 UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V IVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA IOUT (tpw < 1s and Duty Cycle < 10%). . . . . . . . -0.4A to 0.6A RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . -0.3V to REF + 0.3V IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15mA Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. UCC1809-X UCC2809-X UCC3809-X DIL-8 (Top View) D, N and J Packages Temperature Range Available Packages -55C to +125C J -40C to +85C N, D, J 0C to +70C N, D ELECTRICAL CHARACTERISTICS PARAMETER Supply Section VDD Clamp IVDD IVDD Starting Undervoltage Lockout Section Start Threshold (UCCx809-1) UVLO Hysteresis (UCCx809-1) Start Threshold (UCCx809-2) UVLO Hysteresis (UCCx809-2) Voltage Reference Section Output Voltage Line Regulation Load Regulation Comparator Section IFB Comparator Threshold OUT Propagation Delay (No Load) Soft Start Section ISS VSS Low Shutdown Threshold Oscillator Section Frequency Frequency Change with Voltage CT Peak Voltage CT Valley Voltage CT Peak to Peak Voltage Output Section Output VSAT Low Output VSAT High Output Low Voltage During UVLO Minimum Duty Cycle Maximum Duty Cycle Rise Time Fall Time Unless otherwise specified, VDD = 12V. TA = TJ. TEST CONDITIONS IVDD = 10mA No Load IREF = 0mA VDD = 10V to 15V IREF = 0mA to 5mA MIN TYP MAX UNIT 16 17.5 600 19 900 100 V A A 9.5 1.8 14.2 6.0 10 2 15 7 10.5 V V V V 4.75 5 2 2 5.25 Output Off 0.9 -100 0.95 50 -3 -6 0.46 0.5 90 100 0.1 3.33 1.67 1.67 VFB = 0.8V to 1.2V at Tr = 10ns VDD = 16v, VSS = 0V VDD = 7.5V, ISS = 200A RT1 = 10k, RT2 = 4.32k, CT = 1nF VDD = 10V to 15V 1.54 IOUT = 100mA (dc) IOUT = -40mA (dc), VDD - OUT IOUT = 20mA (dc) VFB = 2V COUT = 1nF COUT = 1nF 2 0.8 0.8 0 70 35 18 15.8 V mV mV 1 100 nA V ns -16 0.2 0.54 A V V 110 kHz %/V V V V 1.80 1.5 1.5 1.5 V V V % % ns ns UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 PIN DESCRIPTIONS FB: This pin is the summing node for current sense feedback, voltage sense feedback (by opto coupler) and slope compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250 on resistance NMOS FET during PWM off time and offers effective leading edge blanking set by the RC time constant of the feed back resistance from current sense resistor to FB input and the high frequency filter capacitor capacitance at this node to GND. GND: Reference ground and power ground for all functions. OUT: This pin is the high current power driver output. REF: The internal 5V reference output. This reference is buffered and is available on the REF pin. REF should be bypassed with a 0.47F ceramic capacitor. RT1: This pin connects to timing resistor RT1 and controls the positive ramp time of the internal oscillator (Tr = 0.69 * RT1 * CT). The positive threshold of the internal oscillator is sensed through inactive timing resis- tor RT2 which connects to pin RT2 and timing capacitor CT. RT2: This pin connects to timing resistor RT2 and controls the negative ramp time of the internal oscillator (Tf = 0.69 * RT2 * CT). The negative threshold of the internal oscillator is sensed through inactive timing resistor RT1 which connects to pin RT1 and timing capacitor CT. SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 6A current source. Under normal soft start SS is discharged to at least 0.4V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 5V voltage reference also goes low and IVDD < 100A. VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1F ceramic capacitor. APPLICATION DIAGRAM UDG-97149 Figure 1. Typical Appliction Diagram 3 UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 Figure 1 shows a typical isolated flyback converter utilizing the UCC3809. Note that the capacitors CREF and CVDD are local decoupling capacitors for the reference and IC input voltage, respectively. Both capacitors should be low ESR and ESL ceramic, placed as close to the IC pins as possible, and returned directly to the ground pin of the chip for best stability. VREF provides the internal bias to many of the IC functions and CREF should be at least 0.47F to prevent VREF from drooping. UDG-97195 Figure 2. UCC3809 Oscillator APPLICATION INFORMATION DMAX = 069 . * RT1 * CT * FOSC FB PIN The basic premise of the UCC3809 is that the voltage sense feedback signal originates from an optocoupler that is modulated by an external error amplifier located on the secondary side. This signal is summed with the current sense signal and any slope compensation at the FB pin and compared to a 1V threshold, as shown in the typical application circuit in Figure 1. Crossing this 1V threshold resets the PWM latch and modulates the output driver on-time much like the current sense comparator used in the UC3842. In the absence of a FB signal, the output will follow the programmed maximum on-time of the oscillator. When Q1 is on, CT charges via the Rdson of Q1 and RT1. During this charging process, the voltage of CT is sensed through RT2. Crossing the upper threshold (set at 2/3 VREF or 3.33V for a typical 5.0V reference) sets the CLK signal high, turning off Q1 and turning on Q2. CT now discharges through RT2 and the Rdson of Q2. CT discharges from 3.33 volts to the lower threshold (set at 1/3 VREF or 1.67V for a typical 5.0V reference) sensed through RT1. The CLK signal is reset low when CT crosses the 1.67 volt threshold, turning off Q2 and turning on Q1, initiating another charge cycle. When adding slope compensation, it is important to use a small capacitor to AC couple the oscillator waveform before summing this signal into the FB pin. By correctly selecting the emitter resistor of the optocoupler, the voltage sense signal can force the FB node to exceed the 1V threshold when the output that is being compared exceeds a desired level. Doing so drives the UCC3809 to zero percent duty cycle. OSCILLATOR The following equation sets the oscillator frequency: FOSC = (069 . * CT * (RT1 + RT 2)) 1 The recommended value for CT is 1nF for frequencies in the 100 kHz or less range and smaller CT for higher frequencies. The minimum recommended values of RT1 and RT2 are 10 k and 4.32 k, respectively. Using these values maintains a ratio of at least 20:1 between the Rdsons of the internal FETs and the external timing resistors, resulting in minimal change in frequency over temperature. Because of the oscillator's susceptibility to capacitive coupling, examine the oscillator frequency by looking at the common RT1-RT2-CT node on the circuit board as opposed to looking at pins 3 and 4 directly. For good noise immunity, RT1 and RT2 should be placed as close to pins 3 and 4 of the IC as possible. CT should be returned directly to the ground pin of the IC with minimal 4 UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 stray inductance and capacitance. SYNCHRONIZATION Both of the synchronization schemes shown in Figure 3 can be successfully implemented with the internal oscillator of the UCC3809. Both schemes allow access to the timing ramp needed for slope compensation and have minimal impact on the programmed maximum duty cycle. In the absence of a sync pulse, the PWM controller will run independently at the frequency set by RT1, RT2, and CT. This free running frequency must be approximately 15 to 20% lower than the sync pulse frequency to insure the free running oscillator does not cross the comparator threshold before the desired sync pulse. Option I uses the synchronization pulse to pull pin 3 low, triggering the internal 1.67 V comparator to reset the RS latch and initiate a charging cycle. The valley voltage of the CT waveform is higher when synchronized using this configuration, decreasing the ramp charge and discharge times, thereby increasing the operating frequency; otherwise the overall shape of the CT voltage waveform is unchanged. Option II uses the synchronization pulse to superimpose the sync voltage onto the peak of the CT waveform. This triggers the internal 3.33 V comparator, initiating a discharge cycle. The sync pulse is summed with the free running oscillator waveform at the CT node, resulting in a spike on top of the CT peak voltage. UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460 Figure 3. UCC3809 Synchronization Options 5