ANALOG DEVICES 16-Bit DSP DACPORT AD766 FEATURES Zero-Chip Interface to Digital Signal Processors Complete DACPORT On-Chip Voltage Reference Voltage and Current Outputs Serial, Twos-Compiement Input +3 V Output Sample Rates to 390 kSPS 94 dB Minimum Signal-to-Noise Ratio -81 dB Maximum Total Harmonic Distortion 15-Bit Monotonicity +5 V to +12 V Operation 16-Pin Plastic and Ceramic Packages Available in Commercial, Industrial, and Military Temperature Ranges APPLICATIONS Digital Signa! Processing Noise Cancellation Radar Jamming Automatic Test Equipment Precision Industrial Equipment Waveform Generation PRODUCT DESCRIPTION The AD766 16-bit DSP DACPORT provides a direct, three- wire interface to the serial ports of popular DSP processors, including the ADSP-2101, TMS320CXX, and DSP56001. No additional glue logic is required. The AD766 is also complete, offering on-chip serial-to-parallel input format conversion, a 16-bit current-steering DAC, voltage reference, and a voltage output op amp. The AD766 is fabricated in Analog Devices BiMOS II mixed-signal process which provides bipolar transis- tors, MOS transistors, and thin-film resistors for precision ana- log circuits in addition to CMOS devices for logic. The design and layout of the AD766 have been optimized for ac performance and are responsible for its guaranteed and tested 94 dB signal-to-noise ratio to 20 kHz and 79 dB SNR to 250 kHz. Laser-trimming the AD766s silicon chromium thin- film resistors reduces total harmonic distortion below 81 dB (at | kHz), a specification also production tested. An optional linearity trim pin allows elimination of midscale differential linearity error for even lower THD with small signals. The AD766s output amplifier provides a +3 V signal with a high slew rate, small glitch, and fast settling. The output ampli- fier is short circuit protected and can withstand indefinite shorts to ground. DACPORT is a registered trademark of Analog Devices, Inc. This is an abridged data sheet. To obtain the most recent version or complete data sheet, call our fax retrieval system at 1-800-446-6212. REV. A FUNCTIONAL BLOCK DIAGRAM e 6] vs Ls | | 15] TRIM [14] MsB ADJ 13] lout [12] AGND 11] SJ 70] Re 42] Vout NC = NO CONNECT CLK VV LE DATA REGISTER FRPP The serial interface consists of bit clock, data, and latch enable inputs. The twos-complement data word is clocked MSB first on falling clock edges into the serial-to-parallel converter, consistent with the serial protocols of popular DSP processors. The input clock can support data transfers up to 12.5 MHz. The falling edge of latch enable updates the internal DAC input register at the sample rate with the sixteen bits most recently clocked into the serial input register. The AD766 operates over a +5 V to +12 V power supply range. The digital supplies, +V, and V,, can be separatd from the analog signal supplies, + Vs and Vg, for reduced digital crosstalk. Separate analog and digital ground pins are also provided. An internal bandgap reference provides a precision voltage source to the output amp that is stable over temperature and time. Power dissipation is typically 120 mW with +5 V supplies and 300 mW with +12 V. The AD766 is available in commercial (0C to 70C), industrial (40C to 85C), and military (55C to 125C) grades. Commercial and industrial grade parts are available in a 16-pin plastic DIP; military parts processed to MIL-STD-883B are packaged in a 16-pin ceramic DIP. See Analog Devices Military Products Databook or current military data sheet for specifications for the military version. DIGITAL-TO-ANALOG CONVERTERS 3-83AD766 SPECIFICATION (Train tO Trax 5 V supplies, F; = 500 kSPS unless otherwise noted. No deglitchers or MSB trimming is used.) AD766J AD766A Parameter Min Typ Max Min Typ Max Units RESOLUTION 16 16 Bits DIGITAL INPUTS Via 2.0 +VL 2.0 +V, v Vit 0.8 0.8 Vv Tn: Vin = Vo 1.0 1.0 A I> Va = 0.4 -10 -10 pA SERIAL PORT TIMING Serial Clock Period (to. ) 95 115 ps Serial Clock HI (ty) 30 30 ns Serial Clock LO (tp) 30 70 ns Data Valid (toara) 40 40 ns Data Setup (ts) 15 20 ns Data Hold (ty) 15 20 ns Clock-to-Latch-Enable (trie) 80 100 ns Latch-Enable-to-Clock (ty erc) 1S 1S ns Latch Enable HI (ty g:31) 40 40 ns Latch Enable LO (ty gL) 40 80 ns ACCURACY! Gain Error +2.0 +2.0 % of FSR Gain Drift =25 +25 ppm of FSR/C Midscale Output Voltage Error +30 +30 mV Bipolar Zero Drift a4 +4 ppm of FSR/C Differential Linearity Error +0.001 +0.001 % of FSR Monotonicity 1S 15 Bits TOTAL HARMONIC DISTORTION Four = 1037 Hz' 0 dB ~88 -81 88 ~81 dB -20 dB 75 -65 ~75 65 dB 60 dB 37 27 37 ~27 dB Four = 49.07 kHz 0 dB -77 -72 -77 ~72 dB 20 dB -69 66 -69 66 dB -60 dB 25 -21 ~25 ~21 dB SIGNAL-TO-NOISE RATIO? 20 Hz to 20 kHz (Foyy = 1037 Hz)! 94 102 94 102 dB 20 kHz to 250 kHz (Fouy = 49.07 kHz) 19 83 79 83 dB SETTLING TIME (to +0.0015% of FSR) Voltage Output! 6 V Step 1.5 1.5 ps 1 LSB Step 1.0 1.0 ps Slew Rate 9 9 Vips Current Output 1 mA Step 10 2 to 100 2 Load 350 350 ns 1 kO Load 350 350 ns OUTPUT Voltage Output Configuration Bipolar Range +288 +3.0 +3.12 +2.88 +3.0 +3.12 v Output Current +8.0 +8.0 mA Output Impedance 0.1 0.1 2 Short Circuit Duration Indefinite to Common Indefinite te Common Current Output Configuration Bipolar Range +0.7 +10 +13 +0.7 +10 +13 mA Output Impedance (+ 30%) 1.7 1.7 kQ POWER SUPPLY Voltage: +V, and +V, 4.75 13.2 4.75 13.2 v -V, and Vs -13.2 4.75 13.2 ~4.75 v Current Case 1': Vg and V, = +5 V +1 12.0 15.0 12.0 15.0 mA -V, and -V, = -5V -I 12.0 ~15.0 12.0 -15.0 mA Case 2: Vg and V, = +12 V +I 10.5 10.5 mA -Vsand-V, = -12V -I -14 -14 mA Case 3*: V, and V; = +5 V +1 12 12 mA -Vgand-Vip=-1V- UI -14 -14 mA Power Dissipation: V, and V, = +5 V! 120 150 120 150 mW Vs and V_ = +12 V 300 300 mW V, and V; = +5 V, V, and -V, = -12 V* 225 225 mW 3-84 DIGITAL-TO-ANALOG CONVERTERS REV. AAD766 AD766J AD766A Parameter Min Typ Max Min Typ Max Units TEMPERATURE RANGE: Specified 0 +70 40 +85 C Storage 60 +100 -60 +100 C NOTES For A grade only, voltage outputs are guaranteed only if +V, = 7 V and -V, = ~7 V. Specified using external op amp, see Figure 3 for more details. Tested at full-scale input. For A grade only, power supplies must be symmetric, i.e., Vs = |-Vg| and +V, = |V_|. Each supply must independently meet this equality within +5%. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. kn Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE V_ toDGND ... 00... eee 0t0 13.2V VstoAGND .....00..000 0000 c cece eee 0 to 13.2 V Temperature Package -V, toDGND ...........000 000 eee -13.2V100V Model Range Option* ~VsgtoAGND .......0.2...-000.0.04 -13.2Vt00V AD766JN 0C to +70C N-16 Digital Inputs to DGND ................ -0.3 V to V, AD766AN 40C to +85C N-16 AGND to DGND ................- 0000005 +0.3V AD766SD/883B | 55C to +125C | D-16 Short Circuit Protection ........ Indefinite Short to Ground : : a . Soldering 6.0.00... 0c c ee cee eee +300C, 10 sec *N = Plastic DIP; D = Ceramic DIP. For outline information see Package Information section. *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. PIN DESIGNATIONS CONNECTION DIAGRAM Pin Function Description Vg cn VS rie] Ve 1 -Vs Analog Negative Power Supply pano [2 (pu ] TRIM 2 DGND Digital Ground 3 Vi Logic Positive Power Supply vB] [1a] mse aps 4 NC No Connection NC ] eS 3] lour s | CLK Clock Input ak [5 Fi] AGNo 6 LE Latch Enable Input LE i: sat 4] SJ 7 DATA Serial Data Input DATA GI REGISTER fio] Re 8 -Vi Logic Negative Power Supply _y Cel ] y 9 Vout Voltage Output . our 10 Ry Feedback Resistor NC = NO CONNECT 11 SJ Summing Junction 12 AGND Analog Ground 13 lout Current Output 14 MSB ADJ MSB Adjustment Terminal 15 TRIM MSB Trimming Potentiometer Terminal 16 Vs Analog Positive Power Supply ESD SENSITIVITY The AD766 features input protection circuitry consisting of large distributed diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the ea en AD766 has been classified as a Category 1 Device. . ( Proper ESD precautions are strongly recommended to avoid functional damage or performance aid faa degradation. Charges as high as 4000 volts readily accumulate on the human body and test eT RGME OTS TaIeTe equipment, and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam discharged to the destination socket before devices are removed. For further information on ESD precaution, refer to Analog Devices ESD Prevention Manual. REV.A DIGITAL-TO-ANALOG CONVERTERS 3-85