840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
1
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS840021I is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocksTM
family of high performance devices from ICS. The
ICS840021I uses a 25MHz crystal to synthesize
125MHz. The ICS840021I has excellent phase
jitter performance, over the 1.875MHz – 20MHz integration
range. The ICS840021I is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
FEATURES
•1 LVCMOS/LVTTL output, 15Ω output impedence
•Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
•Output frequency: 125MHz
•VCO range: 560MHz to 680MHz
•RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.48ps (typical) (3.3V)
Offset Noise Power
100Hz ............... -97.8 dBc/Hz
1kHz ..............-124.6 dBc/Hz
10kHz ..............-132.5 dBc/Hz
100kHz ..............-131.1 dBc/Hz
•Voltage supply modes:
VDD/VDDA = 3.3V
VDD/VDDA = 2.5V
•-40°C to 85°C ambient operating temperature
•Lead-Free package fully RoHS compliant
HiPerClockS™
ICS
ICS840021I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
VDDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
VDD
Q0
GND
nc
8
7
6
5
BLOCK DIAGRAM PIN ASSIGNMENT
OSC Phase
Detector VCO ÷5
÷25
(fixed)
XTAL_IN
XTAL_OUT
OE
Q0
25MHz
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
2
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
ADD
rewoP.nipylppusgolanA
2EOtupnIpulluP .delbanesituptuo0Q,HGIHnehW.nipelbanetuptuO
.slevelecafretniLTTVL/SOMCV
L.etatsZiHot0Qsecrof,WOLnehW
4,3 ,TUO_LATX
NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC
.tup
tuoehtsiTUO_LATX
5cndesunU.tcennocoN
6DNGrewoP.dnuorgylppusrewoP
70QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokco
lcdedne-elgniS
51 Ω.ecnedepmituptuo
8V
DD
rewoP.nipylppuseroC
:ETON
pulluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
C
DP
ecnaticapaCnoitapissiDrewoP V
DD
V,
ADD
V564.3=7Fp
V
DD
V,
ADD
V526.2=7Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
TUO
ecnadepmItuptuO 51 Ω
TABLE 3. CONTROL FUNCTION TABLE
stupnIlortnoCtuptuO
EO0Q
0Z-iH
1evitcA
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
3
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
egatloVylppuSgolanA 531.33.3564.3V
I
DD
tnerruCylppuSrewoP 56Am
I
ADD
tnerruCylppuSgolanA 01Am
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, V
O-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 101.7°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI V
DD
V3.3=2V
DD
3.0+V
V
DD
V5.2=7.1V
DD
3.0+V
V
LI
egatloVwoLtupnI V
DD
V3.3=3.0-8.0V
V
DD
V5.2=3.0-7.0V
I
HI
tnerruChgiHtupnIEOV
DD
V=
NI
V526.2roV564.3=5Aµ
I
LI
tnerruCwoLtupnIEOV
DD
V,V526.2roV564.3=
NI
V0=051-Aµ
V
HO
1ETON;egatloVhgiHtuptuO V
DD
V564.3=6.2V
V
DD
V526.2=8.1V
V
LO
1ETON;egatloVwoLtuptuOV
DD
V526.2roV564.3=5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
DD
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
.smargaid"tiucriCtseTdaoLtuptuO"
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 573.25.2526.2V
V
ADD
egatloVylppuSgolanA 573.25.2526.2V
I
DD
tnerruCylppuSrewoP 06Am
I
ADD
tnerruCylppuSgolanA 01Am
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
4
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 52zHM
)RSE(ecnatsiseRs
eireStnelaviuqE 05 Ω
ecnaticapaCtnuhS 7Fp
leveLevirD 1Wm
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 521zHM
t
)Ø(tij rettiJesahPSMR
1ETON;)modnaR( zHM02otzHM578.1:egnaRnoitargetnI84.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02002005sp
cdoelcyCytuDtuptuO 8425%
.tolPesioNesahPehtotreferesaelP:1ETON
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 521zHM
t
)Ø(tij rettiJesahPSMR
1ETON;)modnaR( zHM02otzHM578.1:egnaRnoitargetnI05.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02052055sp
cdoelcyCytuDtuptuO 8425%
.tolPesioNesahPehtotreferesaelP:1ETON
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
5
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 125MHZ (3.3V OR 2.5V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz (3.3V) = 0.48ps (typical)
1.875MHz to 20MHz (2.5V) = 0.50ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc
Hz
➤
➤
➤
Gigabit Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Gigabit Ethernet Filter to raw data
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
6
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
RMS PHASE JITTER OUTPUT RISE/FALL TIME
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
1.65V ± 5%
-1.65V ± 5%
Clock
Outputs
20%
80% 80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
x 100%
tPW
Q0
GND
VDD,
VDDA
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
SCOPE
Qx
LVCMOS
1.25V ± 5%
-1.25V ± 5%
GND
VDD,
VDDA
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
7
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
Figure 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS840021I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2
below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS840021I provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. VDD and VDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required.
Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each VDDA pin.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10μF
.01μF
3.3V or 2.5V
.01μF
VDD
C1
33p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
8
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A
shows a schematic example of the ICS840021I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 22pF and C2 = 33pF are recom-
mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy.
FIGURE 3A. ICS840021I SCHEMATIC EXAMPLE
FIGURE 3B. ICS840021I PC BOARD LAYOUT EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B
shows an example of ICS840021I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age. The footprints of other components in this example are listed
in the
Table 7.
There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
ecnerefeReziS
2C,1C2040
3C5080
5C,4C3060
3R,2R3060
tnenopmocstsil,7elbaT:ETON
.elpmaxetuoyalsihtninwohssezis
U1
ICS840021i
1
2
3
4
8
7
6
5
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q0
GND
NC
C1
22pF
C2
33pF
C4
0.1u
VDDA
R2
10
Q
R3
33
VDD
VDD
VDD=3.3V
OE
X1 LVCMOSC5
0.1u
C3
10uF
Zo = 50 Ohm
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
9
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS840021I is: 1961
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
10
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N8
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.201.3
ECISAB04.6
1E03.405.4
eCISAB56.0
L54
.057.0
α°0°8
aaa--01.0
840021AGI www.icst.com/products/hiperclocks.html REV. A MAY 19, 2005
11
Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
IGA120048SCIIA120POSSTdael8ebutC°58otC°04-
TIGA12004
8SCIIA120POSSTdael8leer&epat0052C°58otC°04-
FLIGA120048SCIDBTPOSST"eerF-daeL"dael8ebutC°58otC°04-
TFLIGA120048S
CIDBTPOSST"eerF-daeL"dael8leer&epat0052C°58otC°04-
.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntra
pehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
