AD national Semiconductor DS3884A BTL Handshake Transceiver General Description The 0S3884A is pin to pin and functionally compatible with the DS3884. The DS3884<A is a speed and power enhanced version of the DS3884. There are two minor differences be- tween the DS3884 and DS3884A. The external resistor used in the DS3884< is different from that used in the DS3884. REXT for the DS3884 is 6.2k while REXT for the DS3884A is 13k. The available filter settings for the DS3884A are 5 ns, 10 ns, 14 ns, 24 ns, while the settings for the DS3884 are 5 ns, 7.5 ns, 15 ns, and 25 ns. Features w Fast propagation delay (3 ns typ) @ 6-bit BTL transceiver m Selective receiver glitch filtering (FR1-FR3) Connection Diagrams a @ Controlled rise and fall time to reduce noise coupling to @ Built in Bandgap reference with separate QVoo and @ Exceeds 2 kV ESD testing (Human Body Model) @ Individual Bus-port ground pins @ Product offered in PLCC and POFP package styles February 1996 Meets 1194.1 Standard on Backplane Transceiver Log- ic (BTL) Supports live insertion Glitch free power-up/down protection Typically less than 5 pF bus-port capacitance Low Bus-port voltage swing (typically 1V) at 80 mA TTL compatible driver and control inputs Separate TTL 1/0 Open collector bus-port outputs allow Wired-OR connection adjacent lines QGND pins for precise receiver thrasholds JBAIBOSURL | SYPYUSPULH 119 Vrssesd a - zk o-w - zk QaQ-a Ezasrns8i See ge Ezas8b Serre Listti ft it} i ft | 44 43 42 41 40 39 38 37 36 35 34 fe S 435 2 1 44 43 42 41 40 Neti 33, NC nc-47 39;Ne p242 32B1 b248 38f Bt R243 31-B1 GND R2~49 37 B1 GND re DS3884AVF soe re DS3884AV ey GND 45 29B82 GND GND41 35) 62 GND Yoo 46 44PIN 28}~B3 Yoo 4 12 44PIN 34-63 cc cc 7 = D347 PQFP 27 | B3 GND 03 413 PLCC 33 83 GND rss (TOP VIEW) 26+ a4 rafr4 (TOP VIEW) s2b-e4 FR349 25B4 GND = FR3Z IS 319 84 GND D4q10 24-85 DATi6 30% 85 R4a4t1 23B5 GND R4117 299 85 GND 12 13 14 15 16 17 18 19 20 21 22 18 19 20 21 22 23 24 25 26 27 28 TrT?Priorrriedrged 'ipreirgor?gdgoggdre? ww wo wo Qo vo a gu oa ow oO Qo o 4 oj ao 2 oneoe = ZZ 32 la za oe artzzzz la =z a So 8s oO o 8s oS & 2 TL/F/11460-1 TL/F/11460-2 Order Number DS3884AV or DS3884AVF See NS Package V44A or VF44B TRESTATE is & of National i Ce 1996 National Semiconductor Corporation = TL/F/11480 | FARD-830M66/Printed in U.S. A. http://www.national.com M 6501126 0074654 434 aaLogic Diagram 01 RI FRI b2 R2 FR2 D3 R35 FRS 04 R4 DS RS 06 R6 DE PS2 TL/F/11460-3 http://www.national.com 2 M! 6501126 OO74b55 770General Description (continues The DS3884A is one in a series of transceivers designed specifically for the implementation of high performance Fu- turebus + and proprietary bus interfaces. The DS3884<A is a BTL 6-bit Handshake Transceiver designed to conform to JEEE 1194.1 (Backplane Transceiver LogicBTL) as speci- fied in the IEEE 896.2 Futurebus+ specification. Utilization of the DS3884A simplifies the implementation of all hand- shake signals which require Wired-OR glitch filtering. Three of the six bits have an additional parallel Wired-OR filtered receive output giving a total of nine receiver outputs. In Wired-OR applications, the glitch generated as drivers are released from the bus, is dependent upon the back- plane and parasitic wiring components causing the charac- teristics of the glitch to vary in pulse width and amplitude. To accommodate this variation the DS3884A features two pins defined as PS1 and PS2 which allow selection of a 5 ns, 10 ns, 14 ns and 24 ns filter setting to optimize glitch filter- ing for a given situation. The REXT pin is issued in conjunc- tion with the filtering circuitry and requires a 13 kf. resistor to ground. For additional information on Wired-OR glitch, reference Application Note AN-774. The DS3884A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with its collector to isolate the transistor output capacitance from the bus thus reducing the bus loading in the inactive state. The combined output capacitance of the driver and receiver input is typically less than 5 pF. The driver also has high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semicon- ductor, then developed by the IEEE to enhance the per- formance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus load- ing, a 1V nominal signal swing for reduced power consump- tion and receivers with precision thresholds for maximum noise immunity. The BTL standard eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The back- plane bus is intended to be operated with termination resis- tors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switch- ing. The devices unique driver circuitry meets a maximum slew rate of 0.5V/ns which allows controlled rise and fall times to teduce noise coupling to adjacent lines. The transceiver's high impedance control and driver inputs are fully TTL compatible. The receiver is a high speed comparator that utilizes a bandgap reference for precision threshold control allowing maximum noise immunity to the BTL 1V signaling level. Separate QVgc and QGND pins are provided to minimize the effects of high current switching noise. Output pins FR1-FR9 are the filtered outputs and R1-R6 are the unfil- tered outputs. All receiver outputs are fully TTL compatible. The DS3884A supports live insertion as defined for Future- bus+ through the LI (Live Insertion) pin. To implement live insertion the LI pin should be connected to the live insertion power connector. If this function is not supported the LI pin must be tied to the Voc pin. The DS3884A also provides power up/down glitch free protection during power se- quencing. The DS3884A has two types of power connections in addi- tion to the LI pin. They are the Logic Voc (Voc) and the Quiet Voc (QVcc). There are two Voc pins on the DS3884A that provide the supply voltage for the logic and control cir- Cuitry. Multiple connections are provided to reduce the ef- fects of package inductance and thereby minimize switching noise. As these pins are common to the Vcc bus internal to the device, a voltage difference should never exist between these pins and the voltage difference between Vcc and QVcc should never exceed +0.5V because of ESD circuit- ry. Additionally, the ESD circuitry between the Voc pins and all other pins except for BTL !/Os and LI pins requires that any voltage on these pins should not exceed the voltage on Voc + 0.5V. There are three different types of ground pins on the DS3884A. They are the logic ground (GND), BTL grounds (BI1GND-B6GND) and the Bandgap reference ground (QGND). All of these ground reference pins are isolated within the chip to minimize the effects of high current switch- ing transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not cary transient switching current. The GND and B1GND-B6GND should be connected to the nearest back- plane ground pin with the shortest possible path. Since many different grounding schemes could be impie- mented and ESD circuitry exist on the DS3884A, it is impor- tant to note that any voltage difference between ground pins, QGND, GND or B1GND-B6GND should not exceed +5V including power up/down sequencing. Additional transceivers included in the Futurebus+ family are; the DS3883A BTL 9-bit Transceiver, the DS3885 BTL Arbitration Transceiver with arbitration competition logic for the AB<7:0>/ABP signal lines, and the ODS3886A BTL 9-bit Latching Data Transceiver featuring edge triggered latches in the driver which may be bypassed during a fall-through mode and a transparent latch in the receiver. The 0S3875 Arbitration Controller included in the Future- bus+ family supports all the required and optional modes for Futurebus+ arbitration protocol. It is designed to be used in conjunction with the DS3884A and DS3885 trans- ceivers. The Logical Interface Futurebus+ Engine (LIFE) is a high performance Futurebus+ Protocol Controller designed for IEEE 896.1-1991. The LIFE will handle all handshaking sig- nals between the Futurebus+ and the local bus interface. The Protocol Controller supports the Futurebus+ com- pelled mode data transfer as both master and slave. The Protocol Controller can be configured to operate in compli- ance to IEEE 896.2 Profile B mode. The LIFE incorporates a DMA controller and 64-bit FIFOs for fast queuing. All of the transceivers are offered in 44-pin PLCC and PQFP high density package styles. 3 http:/Avww.national.com MB 6501126 OO74b5b LO? a a aa a a a aTypical Application 32/64/128/256 BIT DATA PATH ARBITRET ON LOGICAL INTERFACE Futurebus+ ENGINE (LIFE) S PROTOCOL/DATA PATH CONTROLLER CONTROLLER / a ~ a a v vy . x . DS38a3A OS3883A t = BIL 9-BIT XCVR BIL 9-BIT XCVR DS38B3A 0$3885 DSS8S4A OR OR OS3aa84A DS3884A 8TL 9-BIT XCVR ARBITRATION] | HANDSHAKE DS3886A 0S3886A HANDSHAKE] | HANDSHAKE oR XCvR XeVR BIL LATCHING ETL LATCHING XCVR XCVR DS38B6A DATA XCVR DATA XCVR BTL LATCHING DATA XCVR z z 4 + 4 4/8/16/32 DEVICES (DEPENDING ON DATA~ PATH WIDTH) 4 3 y 6 ? v8 a wi y? wv? > ARG ADORESS DATA FUTUREBUSt ARB# SYNC COMMAND STATUS SYNC SYNC ADDRESS/DATA PATH BACKPLANE TUF /11460-4 http://www.national.com MB 650)1cb OO74b57 S43 at eeAbsolute Maximum Ratings (note 1) If Milltary/Aerospace specified devices are required, Please contact the National Semiconductor Sales Storage Temperature Range 65C to + 150C Lead Temperature (Soldering, 4 seconds) 260C Office/Distributors for availability and specifications. Supply Voltage 6.5V Recommended Operating Control Input Voltage 6.5V Conditions Driver Input and Receiver Output 5.5V Supply Voltage, Voc 4.8V-5.5V Receiver Input Current 15mA Bus Termination Voltage (V7) 2.06V-2.14V Bus Termination Voltage 2.4V Operating Free Air Temperature OC to 70C Power Dissipation at 25C PLCC 2.5W PQFP 1.3W Derate PLCC Package 20 mW/C Derate POFP Package 11.1 mwW/*C DC Electrical Characteristics (notes 2 and 3) Ta = 0 to +70C, Vog = 5V +10% Symbol | Parameter Conditions | Min | Typ | Max | Units DRIVER AND CONTROL INPUT: (Dn, DE*, PS1 and PS2) Vinw Minimum Input High Voltage 2.0 v Vit Maximum Input Low Voltage 0.8 v \ Input Leakage Current Vin = Voc = 5.5V 100 pA iw Input High Current Vin = 2.4V 40 pA Ne Input Low Current Vin = 0.5V 100 pA Voi Input Diode Clamp Voltage IcLamp = ~12mA 1.2 v DRIVER OUTPUT/RECEIVER INPUT: (Bn) VoLB Nowe om Bus Voltage in - save OV, 0.75 1.0 4 Vv lotaz Output Low Bus Current Dn = 0.5V, DE* = 2.4V, Bn = 0.75V 100 pA !OHBZ Output High Bus Current Dn = 0.5V, DE* = 2.4V, Bn = 2.1V 100 pA lote Output Low Bus Current Dn = 0.5V, DE* = OV, Bn = 0.75V 220 pA loHB Output High Bus Current Dn = 0.5V, DE* = OV, Bn = 2.1V 350 pA VTH Receiver Input Threshold DE* = 2.4V 1.47 1.55 1.62 v VoLp Positive Clamp Voltage Voc = Max or OV, Ign = 1MA 2.4 3.4 45 Vv Voc = Max or OV, Ign = 10 mA 2.9 3.9 5.0 v VcLN Negative Clamp Voltage IcLAMP = 12mA 1.2 v RECEIVER OUTPUT: (FRn and Rn) Vou Voltage Output High Bn = 1.1V, DE* = 2.4V,loy = 2mA 2.4 3.2 Vv Voi Voltage Output Low Bn = 2.1V, DE* = 2.4V, lo, = 24mA 0.35 0.5 Vv Bn = 2.1V, DE* = 2.4V, ig. = 8mA 0.35 0.4 Vv los Output Short Circuit Current Bn = 1.1V, DE* = 2.4V (Note 4) -40 70 100 mA SUPPLY CURRENT loc Supply Current: Includes Voc, DE* = 0.5V, AllOn = 2.4V 50 70 mA QVec and L DE* = 2.4V, AlBn = 2.1V 50 70 mA ho Live Insertion Current DE* = 2.4V, Ali Dn = 0.5V 1 3 mA DE* = 0.5V, All Dn = 2.4V 2 5 mA Note 1: Absolute Maximum Ratings ara those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tabte of Electrical Characteristics provide conditions for actual device operation. a a MH 6501126 0074658 4ST http://www.national.comDC Electrical Characteristics (notes 2 and 3) Ta = 0 to +70C, Vog = 5V 10% (Continued) Note 2: All input and/or output pins shall not exceed Voc plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and power- down. This p: the ESD trom being di: d due to ive currents flowing trom the input and/or output pins to Veg and Voc. There is a dioda between each input and/or output to Voc which is forward blased when incorrect sequencing is applied. Altematively, a current limiting resistor can be used when pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50 mA. Exception, LI and Bn pins do not have power sequencing requirements with respect to Vog and QVic. Furthermore, the difference between Voc and QVoc should never be greater than 0.5V at any time including power-up. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions.: Voc = 5V and Ta = 25C unless otherwise stated. Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second. Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package. AC Electrical Characteristics 1, = oc to + 70C, Vog = 5V 10% (Note 6) Symbol | Parameter | Conditions | Min | Typ Max | Units DRIVER teHL Dn to Bn Prop. Delay DE* = 0V 1 3 5 ns teLH Figures 7, 2) 1 3 5 ns {PHL DE* to Bn Enable Time Dn = 3V 2 4 6 ns tPLH Disable Time | igures 7,3) 2 4 6 ns t Transition TimeRise/Fall (Figures 1, 2) 1 2 3.5 ns ty 20% to 80% 1 2 3.5 ns SR prow Fate is Calculated (Note 11) 05 vine tekew Skew between Drivers in (Note 7) 1 3 ns the Same Package RECEIVER tPHL Bn to Rn Prop. Delay DE* = 3V 2 4 5 ns teu Figures 4, 5) ns tskew Skew between Receivers in (Note 7) 1 3 ns Same Package FILTERED RECEIVER tpHL Bn to FRn Prop. Delay PS1=0V PS2=0V DE* = 3V 6 42 16 ns (Figures 4,5), Rexy = 13k PS1 = 0V PS2=3V DE* = 3V Figures 4, 5), Rey = 13k " 16 a ns PS1=3V PS2=0V DE* = 3V (Figures 4,5), Rey = 13k 8 | 21 27 ns PS1=3V PS2=3V DE* = 3V (Figures 4, 5), Rext = 13k 25 33 45 ns teLH Bn to FRn Prop. Delay DE* = 3V (Figures 4, 5) (Note 8) 2 5 7 ns Rext = 13 ka ter Glitch Rejection PS1=0V PS2=0V DE* = 3Vv 5 9 16 ns Figures 4, 6), Rey = 13k PS1 =0V PS2=3V DE* = 3V (Figures 4,6), Rext = 13k 10 18 18 ns PS1 =3V PS2=0V DE* = 3V (Figures 4,6), Rexr = 13k 14 8 24 ns = = ee PS1=3V PS2=3V DE* = 3V 24 34 42 ns Figures 4,6), Reyt = 13k http://www.national.com 6 MM 6501126 OO74b59 316 a a a ea tana aNAC Electrical Characteristics 1, = oc to + 70C, Vog = 5V 10% (Note 6) (Continued) Symbol | Parameter | Conditions Min Typ | Max | Units FILTERED RECEIVER TIMING REQUIREMENTS ts | P&n to Bn Set-Up Time | (Figure 7), Reyt = 13k9 | 250 | | ns PARAMETERS NOT TESTED Coutput Capacitance at Bn (Note 9) 5 pF tna Noise Rejection (Note 10) 1 ns Note 6: Input waveforms shall have a rise/fall time of 3 ns. Note 7: tae is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions. Note & Filtered receiver tp_}y is independent of filter setting. Note 9: The parameter is tested using TOR techniques described in P1194.0 BTL Backplane Design Guide. Note 10: This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width. Note 11: Futurebus+ transceivers are required to limit bus signal rise and falt times to no faster than 0.5V/ns, measured between 1.3V and 1.8V {approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.50 tied to +2.1V DC. Pin Descriptions Number of Input/ Pin Name Pins Output Description B1-B6 6 1/0 BTL receiver input and driver output B1GND-B6GND 6 NA Driver output ground reduces bounce due to high current switching of driver outputs (Note 12) DE* 1 I Driver Enable Low D1-D6 6 I TTL Driver Input FR1-FR3 3 oO TTL Filtered Receiver Output GND 3 NA Ground reference for switching circuits. (Note 12) Li 1 NA Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 13) NC 4 NA No Connect PS1, PS2 2 | Pulse Width Selection pin determines glitch filter setting (Note 14) R1-R6 6 0 TTL Receiver Output REXT 1 NA External Resistor pin. External resistor is used for internal biasing of filter circuitry. The 13 kN. resistor shall be connected between REXT and GND. The resistor shall have a tolerance of 1% and a temperature coefficient of 100 ppm/C or better. QGND 2 NA Ground reference for receiver input bandgap reference and non-switching circuits (Note 12) Woo 1 NA Voc supply for bandgap reference and non- switching circuits (Note 13) Voc 2 NA Voc supply for switching circuits (Note 13) Note 12: the multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then raduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low inductance (i.., ground plane with power pins and many signal pins connected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset between their grounds will degrade the noise margin. Note 13: The same considerations for ground are used for Voc in reducing lead inductance (see Note 12). QVcc and Veg should be tied togather extemally. if live insertion is not supported, the LI pin can be tied together with QVcc and Vic. Note 14: See AC characteristics for filter setting. 7 http://www.national.com MM 6501126 OO74bL0 033 a aa aTruth Table Glitch Filter Table DE* Dn PS1 PS2 Filter Setting x L L 5ns x L H 10 ns H H L 14ns L H H 24ns Note 1: X: High or low logic state Note 2: L: Low state Note 3H: High state Note 4: L-H: Low to high transition TUF/11480-6 TLF/11460-5 FIGURE 1. Driver Propagation Delay Set-Up FIGURE 2. Driver: Dn to Bn Switch Position teu feHL 3 [s1] open | close R=Vkd TLFI11480-7 TL/F/11460-8 FIGURE 3. Driver: DE* to Bn FIGURE 4. Receiver Propagation Delay Set-Up ter Bn 2AV y Bn 1.58 1.55V 1A 3V Vo Rn, FRa Vo FRn vv------~+---~-------- TL/F/11460-9 TL/F/11460-10 FIGURE 5. Receiver: Bn to FRn, Bn to Rn FIGURE 6. Receiver: tar, FRn(min) = 2V ts 3V PS1, PS2 1,5 ov 2.1V 8n 1.55V 1.1V A TL/F/11460~11 FIGURE 7. Receiver: PSn to Bn http://www.national.com 8 MH 6501126 OO74bb1 174 a enePhysical Dimensions inches (millimeters) unless otherwise noted 0.650 +0.006 850 9.900 a 40.15 | 1 0.01740.004 16.51 9 [0.4320.10] PIN 1 IDENT asex 0-045 6 1 44 40 [1.14] Ne P 7 39 Le q Y ) 0 f d HH 9.02940.003 a FA ([0.7440.08} q A 0.61020.020 qu A [15.4920.51) TY? q q q D q n - SEATING PLANE 7 N29 /4 l oo Perera 7, 18 128 0.020 et | pend MIN TYP _| 0.050 [0.51] 0.690-0.005 1p 0.500 (1.27] 0.1050.015 > {17.53-0.13] Hr 19-79) [2.6720,3a) 0.165-0.180 [4.19-4.57] TYP [2] e.cfo.s0) ] wean Rev 44-Pin PLCC Order Number DS3884AV NS Package V44A 9 hitp://www.national.com M 65011eb OO74bbe S00 a aaa etPhysical Dimensions inches (millimeters) unless otherwise noted (Continued) (1112.40 0.40 ;---D 10.00 3 0.10 =f he o > = 7) o ce 33 28 23 = 0.8 TYP a = er a Z = ] <= PIN 1 INDEX = ) | FE a - 7 a N As rg 01.2 A 70.25 MAX + 45 X0.6 TOP EJECTOR MARK 0.53 WAX c SEE DETAIL E 030 <9 3-0 ax 0.05 <A, AS 0.15 BOTTOM EJECTOR MARK n 0.340.1 TYP DETAIL E e}o0.2@j cf s-2@[0Q] TYPICAL, SCALE: 30X 1.75% 0-19 *0-19 0.80 + 0.05 m13 TYP po SEATING PLANE: f Sta ic 3 Lab 1.20 TYP 5 wall 0~7 TYP 0.80 0.05 44-Pin PQFP Order Number DS3884AVF NS Package VF44B 0.25 MIN TYP 0.58 0.20 TYP F448 (REV A) LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor ration Eur Hong Kong Ltd. Japan Ltd. 1111 West Bardin Road Fax: +49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308 Atfington, TX 76017 Tel: 1(800) 272-9959 Fax 1(800) 737-7018 Email: europe.su @nsc.com Deutsch Tel: +49 (0) 180-530 85 85 English Tel: +49 (0) 190-532 7B 32 Francais Tel: +49 (0) 180-592 93 58 Haliano Tel: +49 (0) 180-534 16 80 Ocean Centre, 5 Canton Ad. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Fax. 81-043-299-2408 http: //www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National raserves the right al any time without notice to change said circuitry and specifications. /O M@ 6501126 OO74bb3 847 a... aac ta aaa a