AD9174-FMC-EBZ - ANALOG DEVICES

Dual, 16-Bit, 12.6 GSPS

RF DAC and Direct Digital Synthesizer

Data Sheet AD9174

Rev. B Document Feedback

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FEATURES

Supports multiband wireless applications

3 bypassable, complex data input channels per RF DAC

3.08 GSPS maximum complex input data rate per input

channel

1 independent NCO per input channel

Proprietary, low spurious and distortion design

2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output

SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output

Flexible 8-lane, 15.4 Gbps JESD204B interface

Supports single-band and multiband use cases

Supports 12-bit high density mode for increased data

throughput

Multiple chip synchronization

Supports JESD204B Subclass 1

Selectable interpolation filter for a complete set of input

data rates

1×, 2×, 3×, 4×, 6×, and 8× configurable data channel

interpolation

1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation

Final 48-bit NCO that operates at the DAC rate to support

frequency synthesis up to 6 GHz

Transmit enable function allows extra power saving and

downstream circuitry protection

High performance, low noise PLL clock multiplier

Supports 12.6 GSPS DAC update rate

Observation ADC clock driver with selectable divide ratios

Low power

2.54 W with 2 DACs at 12 GSPS, DAC PLL on

10 mm × 10 mm, 144-ball BGA_ED with metal enhanced

thermal lid, 0.80 mm pitch

APPLICATIONS

Wireless communications infrastructure

Multiband base station radios

Microwave/E-band backhaul systems

Instrumentation, automatic test equipment (ATE)

Radars and jammers

GENERAL DESCRIPTION

The AD9174 is a high performance, dual, 16-bit digital-to-analog

converter (DAC) that supports DAC sample rates up to 12.6 GSPS.

The device features an 8-lane, 15.4 Gbps JESD204B data input

port, a high performance, on-chip DAC clock multiplier, and

digital signal processing capabilities targeted at single-band and

multiband direct to radio frequency (RF) wireless applications.

The AD9174 features three complex data input channels per RF

DAC datapath. Each input channel is fully bypassable. Each data

input channel (or channelizer) includes a configurable gain

stage, an interpolation filter, and a channel numerically controlled

oscillator (NCO) for flexible, multiband frequency planning.

The AD9174 supports an input data rate of up to a 3.08 GSPS

complex (inphase/quadrature (I/Q)), or up to 6.16 GSPS non-

complex (real), and is capable of allocating multiple complex input

data streams to the assigned channels for individual processing.

Each group of three channelizers is summed into a respective

main datapath for additional processing when needed. Each main

datapath includes an interpolation filter and one 48-bit main NCO

ahead of the RF DAC core. Using the modulator switch, the outputs

of a main datapath can be either routed to DAC0 alone for

operating as a single DAC, or routed to both DAC0 and DAC1

for operating as a dual, intermediate frequency DAC (IF DAC).

The AD9174 also supports ultrawide data rate modes that allow

bypassing the channelizers and main datapaths to provide

maximum data rates of up to 6.16 GSPS as a single, 16-bit DAC,

up to 3.08 GSPS as a dual, 16-bit DAC, or up to 4.1 GSPS as a

dual, 12-bit DAC.

Additionally, the main NCO blocks in the AD9174 contain a bank

of 31, 32-bit NCOs, each with an independent phase accumulator.

Combined with a 80 MHz serial peripheral interface (SPI) for

programming the NCOs, this bank allows a phase coherent, fast

frequency hopping (FFH) for applications where the NCO

frequencies are continuously adjusted during operation.

The AD9174 is available in a 144-ball BGA_ED package.

PRODUCT HIGHLIGHTS

1. A low power, multichannel, dual DAC design reduces

power consumption in higher bandwidth and multichannel

applications, while maintaining performance.

2. Supports single-band and multiband wireless applications

with three bypassable complex data channels per RF DAC,

or configurations that use the two main datapaths as two

wideband complex data channels when using the built in

modulator switch.

3. A maximum complex data rate (per I or Q) of up to 3.08 GSPS

with 16-bit resolution, and up to 4.1 GSPS with 12-bit

resolution. The AD9174 can be alternatively configured as

a dual DAC, with each DAC operating across an independent

JESD204B link, at the previously described data rates.

4. Ultrawide bandwidth single-DAC modes, supporting up to

6.16 GSPS data rates with 16-bit resolution.

AD9174 Data Sheet

Rev. B | Page 2 of 165

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

DC Specifications ......................................................................... 5

Digital Specifications ................................................................... 6

Maximum DAC Sampling Rate Specifications ......................... 6

Power Supply DC Specifications ................................................ 7

Serial Port and CMOS Pin Specifications ............................... 10

Digital Input Data Timing Specifications ............................... 11

JESD204B Interface Electrical and Speed Specifications ...... 12

Input Data Rates and Signal Bandwidth Specifications ........ 13

AC Specifications ........................................................................ 14

Absolute Maximum Ratings .......................................................... 16

Reflow Profile .............................................................................. 16

Thermal Characteristics ............................................................ 16

ESD Caution ................................................................................ 16

Pin Configuration and Function Descriptions ........................... 17

Typical Performance Characteristics ........................................... 20

Terminology .................................................................................... 28

Theory of Operation ...................................................................... 29

Serial Port Operation ..................................................................... 31

Data Format ................................................................................ 31

Serial Port Pin Descriptions ...................................................... 31

Serial Port Options ..................................................................... 32

JESD204B Serial Data Interface .................................................... 33

JESD204B Overview .................................................................. 33

Physical Layer ............................................................................. 37

Data Link Layer .......................................................................... 39

Syncing LMFC Signals ............................................................... 41

Transport Layer .......................................................................... 47

JESD204B Test Modes ............................................................... 48

JESD204B Error Monitoring ..................................................... 50

Digital Datapath ............................................................................. 53

Total Datapath Interpolation .................................................... 53

Channel Digital Datapath ......................................................... 55

Main Digital Datapath ............................................................... 58

NCO Only Mode ........................................................................ 62

Modulator Switch ....................................................................... 64

Interrupt Request Operation ........................................................ 68

Interrupt Service Routine .......................................................... 68

Analog Interface ............................................................................. 69

DAC Input Clock Configurations ............................................ 69

Clock Output Driver .................................................................. 71

Analog Outputs .......................................................................... 71

Applications Information .............................................................. 73

Hardware Considerations ......................................................... 73

Start-Up Sequence .......................................................................... 76

Outline Dimensions ..................................................................... 165

Ordering Guide ........................................................................ 165

REVISION HISTORY

7/2019—Rev. A to Rev. B

Changes to Digital Gain Section ................................................... 55

Changes to Table 37 ........................................................................ 56

Changes to Table 43 ........................................................................ 60

Changes to NCO Only Mode Section .......................................... 62

Changes to DAC Full-Scale Power Section ................................. 71

Changes to Table 56 ........................................................................ 79

Changes to Table 57 ........................................................................ 80

Changes to Table 62 ...................................................................... 105

5/2019—Rev. 0 to Rev. A

Change to Input Data Rate Per Input Channel Parameter,

Table 8 .............................................................................................. 12

Changes to Noise Spectral Density (NSD) Parameters,

Table 9 .............................................................................................. 13

Changes to Figure 16 Caption and Figure 17 Caption .............. 21

Change to Table 17 ......................................................................... 33

Changes to SYSREF± Sampling Section ...................................... 41

Changes to Subclass 1 Section ...................................................... 42

Changes to Figure 73 and Table 37 .............................................. 55

Change to Complex Modulator Switch Configurations

Sec tion .............................................................................................. 65

Changes to DAC On-Chip PL Section ........................................ 69

Change to M_DIVIDER_1 Bit Description, Table 52 ............... 75

Change to SPI_CHIPGRADE Register, Table 61 ....................... 82

Data Sheet AD9174

Rev. B | Page 3 of 165

Change to DATAPATH_NCO_SYNC_CFG Register,

Table 61 ............................................................................................. 85

Change to SPI_CHIPGRADE Register, Table 62 ........................ 94

Changes to DATAPATH_NCO_SYNC_CFG Register,

Table 62 ...........................................................................................114

Changes to DACPLL_CTRL1 Register, Table 62 ...................... 155

11/2018—Revision 0: Initial Version

AD9174 Data Sheet

Rev. B | Page 4 of 165

FUNCTIONAL BLOCK DIAGRAM

MDAC 0

PA PROTECT

AD9174

PA PROTECT

DAC 1

CLKIN+

DAC0±

CLKOUT+

CLKOUT–

CLKIN–

DAC1±

SYSREF+

SYSREF–

SERDES

JESD204B

CLOCK DISTRIBUTION

AND

CONTROL LOGIC

SYNCHRONIZATION

LOGIC

CLOCK

RECEIVER

DAC ALIGN

DETECT

CLOCK

DRIVER

CLOCK DIVIDER

÷1, ÷2, ÷3, ÷4

PLL

÷1, ÷2, ÷3

CLOCK

RECEIVER

SPI

SDIO

SDO

SCLK

SERDIN0±

SERDIN7±

IRQ0

YNCOUT1±

RAMP

UP/DOWN

GAIN

RAMP

UP/DOWN

GAIN

NCO

CHANNEL 0

GAIN

CHANNEL 1

GAIN

CHANNEL 2

GAIN

CHANNEL 3

GAIN

CHANNEL 4

GAIN

CHANNEL 5

GAIN

ISET

RESET

IRQ1

TXEN0

TXEN1

VREF

YNCOUT0±

16794-001

Figure 1.

Data Sheet AD9174

Rev. B | Page 5 of 165

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

RESOLUTION 16 Bit

ACCURACY

Integral Nonlinearity (INL) ±7 LSB

Differential Nonlinearity (DNL) ±7 LSB

ANALOG OUTPUTS (DAC0+, DAC0−, DAC1+, DAC1−)

Gain Error (with Internal ISET Reference) ±15 %

Full-Scale Output Current

Minimum RSET = 5 kΩ 14.2 16 17.8 mA

Maximum RSET = 5 kΩ 23.6 26 28.8 mA

Common-Mode Voltage 0 V

Differential Impedance 100 Ω

DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN−)

Differential Input Power RLOAD = 100 Ω differential on-chip

Minimum 0 dBm

Maximum 6 dBm

Differential Input Impedance1 100 Ω

Common-Mode Voltage AC-coupled 0.5 V

CLOCK OUTPUT DRIVER (CLKOUT+, CLKOUT−)

Differential Output Power

Minimum −9 dBm

Maximum 0 dBm

Differential Output Impedance 100 Ω

Common-Mode Voltage AC-coupled 0.5 V

Output Frequency 727.5 3000 MHz

TEMPERATURE DRIFT

Gain 10 ppm/°C

REFERENCE

Internal Reference Voltage 0.495 V

ANALOG SUPPLY VOLTAGES

AVDD1.0 0.95 1.0 1.05 V

AVDD1.8 1.71 1.8 1.89 V

DIGITAL SUPPLY VOLTAGES

DVDD1.0 0.95 1.0 1.05 V

DAVDD1.0 0.95 1.0 1.05 V

DVDD1.8 1.71 1.8 1.89 V

SERIALIZER/DESERIALIZER (SERDES) SUPPLY VOLTAGES

SVDD1.0 0.95 1.0 1.05 V

1 See the DAC Input Clock Configurations section for more details.

AD9174 Data Sheet

Rev. B | Page 6 of 165

DIGITAL SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = +25°C, which

corresponds to TJ = 51°C.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DAC UPDATE RATE

Minimum 2.91 GSPS

Maximum1 16-bit resolution, with interpolation 12.6 GSPS

16-bit resolution, no interpolation 6.16 GSPS

Adjusted2 16-bit resolution, with interpolation 3.08 GSPS

16-bit resolution, no interpolation 6.16 GSPS

DAC PHASE-LOCKED LOOP (PLL)

VOLTAGE CONTROLLED OSCILLATOR

(VCO) FREQUENCY RANGES

VCO Output Divide by 1 8.74 12.42 GSPS

VCO Output Divide by 2 4.37 6.21 GSPS

VCO Output Divide by 3 2.91 4.14 GSPS

PHASE FREQUENCY DETECT INPUT

FREQUENCY RANGE

25 770 MHz

DAC DEVICE CLOCK INPUT (CLKIN+,

CLKIN−) FREQUENCY RANGES

PLL Off 2.91 12.6 GHz

PLL On M divider set to divide by 1 25 770 MHz

M divider set to divide by 2 50 1540 MHz

M divider set to divide by 3 75 2310 MHz

M divider set to divide by 4 100 3080 MHz

1 The maximum DAC update rate varies depending on the selected JESD204B mode and the lane rate for the given configuration used. The maximum DAC rate

according to lane rate and voltage supply levels is listed in Table 3.

2 The adjusted DAC update rate is calculated as fDAC, divided by the minimum required interpolation factor for a given mode or the maximum channel data rate for a

given mode. Different modes have different maximum DAC update rates, minimum interpolation factors, and maximum channel data rates, as shown in Table 13.

MAXIMUM DAC SAMPLING RATE SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

MAXIMUM DAC UPDATE RATE

SVDD1.0 = 1.0 V ± 5% Lane rate > 11 Gbps 11.67 GSPS

Lane rate ≤ 11 Gbps 12.37 GSPS

SVDD1.0 = 1.0 V ± 2.5% Lane rate > 11 Gbps 11.79 GSPS

Lane rate ≤ 11 Gbps1 12.6 GSPS

1 If using the on-chip PLL, the maximum DAC speed is limited to the maximum PLL speed of 12.42 GSPS, as listed in Table 2.

Data Sheet AD9174

Rev. B | Page 7 of 165

POWER SUPPLY DC SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

DUAL-LINK MODES

Mode 1 (L = 2, M = 4,

NP = 16, N = 16)

11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 32× total

interpolation (4×, 8×), 40 MHz tone at −3 dBFS, channel gain = −6 dB, channel

NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode

AVDD1.0 All supply levels set to nominal values 725 1020 mA

All supply levels set to 5% tolerance 775 1120 mA

AVDD1.8 110 130 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 1100 1670 mA

All supplies at 5% tolerance 1170 1850 mA

DVDD1.8 35 50 mA

SVDD1.0 All supply levels set to nominal values 290 510 mA

All supplies at 5% tolerance 305 560 mA

Total Power

Dissipation

2.37 3.38 W

Mode 4 (L = 4, M = 4,

NP = 16, N = 16)

11.7965 GSPS DAC rate, 491.52 MHz PLL reference clock, 24× total

interpolation (3×, 8×), 40 MHz tone at −3 dBFS, channel gain = −6 dB, channel

NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode

AVDD1.0 725 mA

AVDD1.8 110 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply 1150 mA

DVDD1.8 35 mA

SVDD1.0 425 mA

Total Power

Dissipation

2.56 W

Mode 0 (L = 1, M = 2,

NP = 16, N = 16)

5.89824 GSPS DAC rate, 184.32 MHz PLL reference clock, 16× total

interpolation (2×, 8×), 40 MHz tone at −3 dBFS, channel NCO disabled,

main NCO = 1.8425 GHz, SYNCOUTx± in LVDS mode

AVDD1.0 All supply levels set to nominal values 400 670 mA

All supplies at 5% tolerance 425 745 mA

AVDD1.8 110 130 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 570 960 mA

All supplies at 5% tolerance 610 1070 mA

DVDD1.8 35 50 mA

SVDD1.0 175 340 mA

Total Power

Dissipation

1.40 2.15 W

AD9174 Data Sheet

Rev. B | Page 8 of 165

Parameter Test Conditions/Comments Min Typ Max Unit

Mode 3 (L = 2, M = 2,

NP = 16, N = 16)

11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 24× total

interpolation (3×, 8×), 40 MHz tone at −3 dBFS, channel NCO disabled,

main NCO = 2.655 GHz, SYNCOUTx± in LVDS mode

AVDD1.0 All supply levels set to nominal values 725 mA

All supplies at 5% tolerance 775 mA

AVDD1.8 110 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 1020 mA

All supplies at 5% tolerance 1070 mA

DVDD1.8 35 mA

SVDD1.0 All supply levels set to nominal values 245 mA

All supplies at 5% tolerance 250 mA

Total Power

Dissipation

2.25 W

Mode 9 (L = 4, M = 2,

NP = 16, N = 16)

12 GSPS DAC rate, 187.5 MHz PLL reference clock, 8× total interpolation

(1×, 8×), 10 MHz tone at−3 dBFS, channel NCO disabled, main NCO =

3.072 GHz, SYNCOUTx± in LVDS mode

AVDD1.0 All supply levels set to nominal values 740 1030 mA

All supplies at 5% tolerance 785 1135 mA

AVDD1.8 110 130 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 1010 1580 mA

All supplies at 5% tolerance 1070 1740 mA

DVDD1.8 35 50 mA

SVDD1.0 All supply levels set to nominal values 530 840 mA

All supplies at 5% tolerance 550 910 mA

Total Power

Dissipation

2.54 3.63 W

Mode 2 (L = 3, M = 6,

NP = 16, N = 16)

12 GSPS DAC rate, 375 MHz PLL reference clock, 48× total interpolation

(6×, 8×), 30 MHz tone at −3 dBFS, channel gain = −11 dB, channel NCOs =

20 MHz, main NCO = 2.1 GHz

AVDD1.0 All supply levels set to nominal values 735 1030 mA

All supplies at 5% tolerance 785 1135 mA

AVDD1.8 110 130 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply mA

All supply levels set to nominal values 1370 1800 mA

All supplies at 5% tolerance 1460 1980 mA

DVDD1.8 35 50 mA

SVDD1.0 All supply levels set to nominal values 410 680 mA

All supplies at 5% tolerance 430 755 mA

Total Power

Dissipation

2.77 3.69 W

SINGLE-LINK MODES

Mode 20 (L = 8, M = 1,

NP = 16, N = 16)

6 GSPS DAC rate, 187.5 MHz PLL reference clock, 1× total interpolation

(1×, 1×), 1.8 GHz tone at −3 dBFS, channel and main NCOs disabled

AVDD1.0 All supply levels set to nominal values 400 670 mA

All supplies at 5% tolerance 430 745 mA

AVDD1.8 75 100 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 390 700 mA

All supplies at 5% tolerance 410 810 mA

DVDD1.8 35 50 mA

SVDD1.0 All supply levels set to nominal values 525 820 mA

All supplies at 5% tolerance 550 880 mA

Data Sheet AD9174

Rev. B | Page 9 of 165

Parameter Test Conditions/Comments Min Typ Max Unit

Total Power

Dissipation

1.51 2.34 W

Mode 12 (L = 8, M = 2,

NP = 12, N = 12)

4 GSPS DAC rate, 187.5 MHz PLL reference clock, 1× total interpolation

(1×, 1×), 1 GHz tone at −3 dBFS, channel and main NCOs disabled

AVDD1.0 All supply levels set to nominal values 300 550 mA

All supplies at 5% tolerance 315 620 mA

AVDD1.8 75 100 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 320 630 mA

All supplies at 5% tolerance 350 725 mA

DVDD1.8 35 50 mA

SVDD1.0 All supply levels set to nominal values 525 820 mA

All supplies at 5% tolerance 550 880 mA

Total Power

Dissipation

1.34 2.15 W

DUAL-LINK, MODE 3 (NCO

ONLY, SINGLE-CHANNEL

MODE, NO SERDES)

6 GSPS DAC rate, 300 MHz PLL reference clock, 8× total interpolation (1×, 8×),

no input tone (dc internal level = 0x50FF), channel NCO = 40 MHz, main

NCO = 1.8425 GHz

Mode 3

AVDD1.0

All supply levels set to nominal values 410 660 mA

All supplies at 5% tolerance 435 750 mA

AVDD1.8 110 130 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 500 780 mA

All supplies at 5% tolerance 515 950 mA

DVDD1.8 0.3 1 mA

SVDD1.0 All supply levels set to nominal values 5 100 mA

All supplies at 5% tolerance 3 120 mA

Total Power

Dissipation

1.11 1.671 W

DUAL-LINK, MODE 4 (NCO

ONLY, DUAL-CHANNEL

MODE, NO SERDES)

12 GSPS DAC rate, 500 MHz PLL reference clock, 32× total interpolation

(4×, 8×), no input tone (dc internal level = 0x2AFF), channel NCOs =

±150 MHz, main NCO = 2 GHz

Mode 4

AVDD1.0 All supply levels set to nominal values 750 1030 mA

All supplies at 5% tolerance 790 1130 mA

AVDD1.8 110 130 mA

DVDD1.0 Combined current consumption with the DAVDD1.0 supply

All supply levels set to nominal values 1200 1590 mA

All supplies at 5% tolerance 1300 1750 mA

DVDD1.8 0.3 1 mA

SVDD1.0 5 100 mA

Total Power

Dissipation

2.15 2.851 W

AD9174 Data Sheet

Rev. B | Page 10 of 165

SERIAL PORT AND CMOS PIN SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 5.

Parameter Symbol Test Comments/Conditions Min Typ Max Unit

WRITE OPERATION See Figure 51

Maximum SCLK Clock Rate fSCLK, 1/tSCLK 80 MHz

SCLK Clock High tPWH SCLK = 20 MHz 5.03 ns

SCLK Clock Low tPWL SCLK = 20 MHz 1.6 ns

SDIO to SCLK Setup Time tDS 1.154 ns

SCLK to SDIO Hold Time tDH 0.577 ns

CS to SCLK Setup Time tS 1.036 ns

SCLK to CS Hold Time tH −5.3 ps

READ OPERATION See Figure 50

SCLK Clock Rate fSCLK, 1/tSCLK 48.58 MHz

SCLK Clock High tPWH 5.03 ns

SCLK Clock Low tPWL 1.6 ns

SDIO to SCLK Setup Time tDS 1.158 ns

SCLK to SDIO Hold Time tDH 0.537 ns

CS to SCLK Setup Time tS 1.036 ns

SCLK to SDIO Data Valid Time tDV 9.6 ns

SCLK to SDO Data Valid Time tDV 13.7 ns

CS to SDIO Output Valid to High-Z Not shown in Figure 50 or

Figure 51

5.4 ns

CS to SDO Output Valid to High-Z Not shown in Figure 50 or

Figure 51

9.59 ns

INPUTS (SDIO, SCLK, CS, RESET, TXEN0, and TXEN1)

Voltage Input

High VIH 1.48 V

Low VIL 0.425 V

Current Input

High IIH ±100 nA

Low IIL ±100 nA

OUTPUTS (SDIO, SDO)

Voltage Output

High VOH

0 mA load 1.69 V

4 mA load 1.52 V

Low VOL

0 mA load 0.045 V

4 mA load 0.175 V

Current Output

High IOH 4 mA

Low IOL 4 mA

INTERRUPT OUTPUTS (IRQ0, IRQ1)

Voltage Output

High VOH 1.71 V

Low VOL 0.075 V

Data Sheet AD9174

Rev. B | Page 11 of 165

DIGITAL INPUT DATA TIMING SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 6.

Parameter Test Conditions/Comments Min Typ Max Unit

LATENCY1

Channel Interpolation Factor, Main Datapath

Interpolation Factor

LMFC_VAR_x = 12, LMFC_DELAY_x = 12,

unless otherwise noted

1×, 1×2 JESD204B Mode 10,3 Mode 183 420 DAC clock cycles

JESD204B Mode 11, Mode 19 440 DAC clock cycles

JESD204B Mode 12, Mode 19 590 DAC clock cycles

JESD204B Mode 203 700 DAC clock cycles

JESD204B Mode 21 750 DAC clock cycles

1, 22 JESD204B Mode 83 670 DAC clock cycles

JESD204B Mode 9 700 DAC clock cycles

1, 42 JESD204B Mode 83 1090 DAC clock cycles

JESD204B Mode 9 1140 DAC clock cycles

1, 62 JESD204B Mode 83 1460 DAC clock cycles

JESD204B Mode 9 1530 DAC clock cycles

1, 82 JESD204B Mode 3 1390 DAC clock cycles

JESD204B Mode 83 1820 DAC clock cycles

JESD204B Mode 9 1920 DAC clock cycles

1, 122 JESD204B Mode 83 2700 DAC clock cycles

JESD204B Mode 9 2840 DAC clock cycles

2, 62 JESD204B Mode 3, Mode 4 1970 DAC clock cycles

JESD204B Mode 5 1770 DAC clock cycles

2, 82 JESD204B Mode 0 2020 DAC clock cycles

JESD204B Mode 3, Mode 4 2500 DAC clock cycles

3, 62 JESD204B Mode 3, Mode 4 2880 DAC clock cycles

JESD204B Mode 5, Mode 6 2630 DAC clock cycles

3, 82 JESD204B Mode 3, Mode 4 3310 DAC clock cycles

JESD204B Mode 5, Mode 6 2980 DAC clock cycles

4, 62 JESD204B Mode 0, Mode 1, Mode 2 2410 DAC clock cycles

4, 82 JESD204B Mode 0, Mode 1, Mode 2 3090 DAC clock cycles

6, 62 JESD204B Mode 0, Mode 1, Mode 2 3190 DAC clock cycles

6, 82 JESD204B Mode 0, Mode 1, Mode 2 4130 DAC clock cycles

8, 62 JESD204B Mode 7 3300 DAC clock cycles

8, 82 JESD204B Mode 7 4270 DAC clock cycles

DETERMINISTIC LATENCY

Fixed 13 PCLK4

Variable 2 PCLK cycles

SYSREF± TO LMFC DELAY 0 DAC clock cycles

1 Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay.

2 The first value listed in this specification is the channel interpolation factor, and the second value is the main datapath interpolation factor.

3 LMFC_VAR_x = 7 and LMFC_DELAY_x = 4

4 PCLK is the internal processing clock for the AD9174 and equals the lane rate ÷ 40.

AD9174 Data Sheet

Rev. B | Page 12 of 165

JESD204B INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 7.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

JESD204B SERIAL INTERFACE RATE (SERIAL LANE RATE) 3 15.4 Gbps

JESD204B DATA INPUTS

Input Leakage Current TA = 25°C

Logic High Input level = 1.0 V ± 0.25 V 10 μA

Logic Low Input level = 0 V −4 μA

Unit Interval UI 333 66.7 ps

Common-Mode Voltage VRCM AC-coupled −0.05 +1.1 V

Differential Voltage R_VDIFF 110 1050 mV

Differential Impedance ZRDIFF At dc 80 100 120 Ω

SYSREF± INPUT

Differential Impedance 100 Ω

DIFFERENTIAL OUTPUTS (SYNCOUT0±, SYNCOUT1±)1 Driving 100 Ω differential load

Output Differential Voltage VOD 320 390 460 mV

Output Offset Voltage VOS 1.08 1.12 1.15 V

SINGLE-ENDED OUTPUTS (SYNCOUT0±, SYNCOUT1±) Driving 100 Ω differential load

Output Voltage

High VOH 1.69 V

Low VOL 0.045 V

Current Output

High IOH 0 mA

Low IOL 0 mA

1 IEEE Standard 1596.3 LVDS compatible.

Data Sheet AD9174

Rev. B | Page 13 of 165

INPUT DATA RATES AND SIGNAL BANDWIDTH SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 8.

Parameter1 Test Conditions/Comments Min Typ Max Unit

INPUT DATA RATE PER INPUT CHANNEL

Channel datapaths bypassed (1× interpolation), single-DAC

mode, 16-bit resolution

6160 MSPS

Channel datapaths bypassed (1× interpolation), dual DAC

mode, 16-bit resolution

3080 MSPS

Channel datapaths bypassed (1× interpolation), dual DAC

mode, 12-bit resolution

4100 MSPS

1 complex channel enabled 3080 MSPS

2 complex channels enabled 770 MSPS

3 complex channels enabled 385 MSPS

COMPLEX SIGNAL BANDWIDTH PER INPUT

CHANNEL

1 complex channel enabled (0.8 × fDATA) 1232 MHz

2 complex channels enabled (0.8 × fDATA) 616 MHz

3 complex channels enabled (0.8 × fDATA) 308 MHz

MAXIMUM NCO CLOCK RATE

Channel NCO 1540 MHz

Main NCO 12.6 GHz

MAXIMUM NCO SHIFT FREQUENCY RANGE

Channel NCO Channel summing node = 1.575 GHz, channel interpolation rate >

1×

−770 +770 MHz

Main NCO fDAC = 12.6 GHz, main interpolation rate > 1× −6.3 +6.3 GHz

MAXIMUM FREQUENCY SPACING

ACROSS INPUT CHANNELS

Maximum NCO output frequency × 0.8 1232 MHz

1 Values listed for these parameters are the maximum possible when considering all JESD204B modes of operation. Some modes are more limiting, based on other

parameters.

AD9174 Data Sheet

Rev. B | Page 14 of 165

AC SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =

20 mA, unless otherwise noted. For the minimum and maximum, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which

corresponds to TJ = 51°C.

Table 9.

Parameter Test Conditions/Comments Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

Single Tone, fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) −7 dBFS, shuﬄe enabled

fOUT = 100 MHz −81 dBc

fOUT = 500 MHz −80 dBc

fOUT = 950 MHz −75 dBc

fOUT = 1840 MHz −80 dBc

fOUT = 2650 MHz −75 dBc

fOUT = 3700 MHz −67 dBc

Single Tone, fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) −7 dBFS, shuffle enabled

fOUT = 100 MHz −85 dBc

fOUT = 500 MHz −85 dBc

fOUT = 950 MHz −78 dBc

fOUT = 1840 MHz −75 dBc

fOUT = 2650 MHz −69 dBc

Single Tone, fDAC = 3000 MSPS, Mode 10 (L = 8, M = 2) −7 dBFS, shuﬄe enabled

fOUT = 100 MHz −87 dBc

fOUT = 500 MHz −84 dBc

fOUT = 950 MHz −81 dBc

Single-Band Application—Band 3 (1805 MHz to

1880 MHz)

Mode 0, 2× to 8×, fDAC = 6000 MSPS,

368.64 MHz reference clock

SFDR Harmonics −7 dBFS, shuﬄe enabled

In-Band −82 dBc

Digital Predistortion (DPD) Band DPD bandwidth = data rate × 0.8 −80 dBc

Second Harmonic −82 dBc

Third Harmonic −80 dBc

Fourth and Fifth Harmonic −95 dBc

SFDR Nonharmonics −7 dBFS, shuﬄe enabled

In-Band −74 dBc

DPD Band −74 dBc

ADJACENT CHANNEL LEAKAGE RATIO

4-Channel WCDMA −1 dBFS digital backoff

fDAC = 1200 MSPS, Mode 1 (L = 2, M = 4) fOUT = 1840 MHz −70 dBc

OUT = 2650 MHz −68 dBc

OUT = 3500 MHz −66 dBc

fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) fOUT = 1840 MHz −71 dBc

OUT = 2650 MHz −66 dBc

THIRD-ORDER INTERMODULATION DISTORTION (IMD3) Two-tone test, −7 dBFS/tone, 1 MHz spacing

fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) fOUT = 1840 MHz −83 dBc

OUT = 2650 MHz −85 dBc

OUT = 3700 MHz −77 dBc

fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) fOUT = 1840 MHz −74 dBc

OUT = 2650 MHz −72 dBc

Data Sheet AD9174

Rev. B | Page 15 of 165

Parameter Test Conditions/Comments Min Typ Max Unit

NOISE SPECTRAL DENSITY (NSD) 0 dBFS, NSD measurement taken at 10% away

from fOUT, shuffle on

Single Tone, fDAC = 12000 MSPS

fOUT = 200 MHz −163 dBc/Hz

fOUT = 500 MHz −163 dBc/Hz

fOUT = 950 MHz −162 dBc/Hz

fOUT = 1850 MHz −160 dBc/Hz

fOUT = 2150 MHz −158 dBc/Hz

Single Tone, fDAC = 6000 MSPS

fOUT = 200 MHz −164 dBc/Hz

fOUT = 500 MHz −163 dBc/Hz

fOUT = 950 MHz −161 dBc/Hz

fOUT = 1850 MHz −157 dBc/Hz

fOUT = 2150 MHz −155 dBc/Hz

Single Tone, fDAC = 3000 MSPS

fOUT = 200 MHz −163 dBc/Hz

fOUT = 500 MHz −159 dBc/Hz

fOUT = 950 MHz −155 dBc/Hz

SINGLE-SIDEBAND PHASE NOISE OFFSET Loop filter component values according to

Figure 90 are as follows: C1 = 22 nF, R1 = 232 Ω,

C2 = 2.4 nF, C3 = 33 nF; PFD frequency =

500 MHz, fOUT = 1.8 GHz, fDAC = 12 GHz

1 kHz −97 dBc/Hz

10 kHz −105 dBc/Hz

100 kHz −114 dBc/Hz

600 kHz −126 dBc/Hz

1.2 MHz −133 dBc/Hz

1.8 MHz −137 dBc/Hz

6 MHz −148 dBc/Hz

DAC TO DAC OUTPUT ISOLATION Taken using the AD9174-FMC-EBZ evaluation

board

Dual Band—fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4)

OUT = 1840 MHz −77 dB

OUT = 2650 MHz −70 dB

OUT = 3700 MHz −68 dB

AD9174 Data Sheet

Rev. B | Page 16 of 165

ABSOLUTE MAXIMUM RATINGS

Table 10.

Parameter Rating

ISET, FILT_COARSE, FILT_BYP, FILT_VCM −0.3 V to AVDD1.8 + 0.3 V

SERDINx± −0.2 V to SVDD1.0 + 0.2 V

SYNCOUT0±, SYNCOUT1±, RESET,

TXEN0, TXEN1, IRQ0, IRQ1, CS,

SCLK, SDIO, SDO

−0.3 V to DVDD1.8 + 0.3 V

DAC0±, DAC1±, CLKIN±, CLKOUT±,

FILT_FINE

−0.2 V to AVDD1.0 + 0.2 V

SYSREF± −0.2 V to DVDD1.0 + 0.2 V

AVDD1.0, DVDD1.0, SVDD1.0 to GND −0.2 V to +1.2 V

AVDD1.8, DVDD1.8 to GND −0.3 V to 2.2 V

Maximum Junction Temperature (TJ)1 118°C

Storage Temperature Range −65°C to +150°C

Reflow 260°C

1 Some operating modes of the device may cause the device to approach or

exceed the maximum junction temperature during operation at supported

ambient temperatures. Removal of heat from the device may require

additional measures such as active airflow, heat sinks, or other measures.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

REFLOW PROFILE

The AD9174 reflow profile is in accordance with the JEDEC

JESD20 criteria for Pb-free devices. The maximum reflow

temperature is 260°C.

THERMAL CHARACTERISTICS

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

θJA is the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θJC is

the junction to case thermal resistance.

Thermal resistances and thermal characterization parameters are

specified vs. the number of PCB layers in different airflow velocities

(in m/sec). The use of appropriate thermal management tech-

niques is recommended to ensure that the maximum junction

temperature does not exceed the limits shown in Table 10.

Use the values in Table 11 in compliance with JEDEC 51-12.

Table 11. Simulated Thermal Resistance vs. PCB Layers1

PCB Type

Airflow

Velocity

(m/sec) θJA θ

JC_TOP θ

JC_BOT Unit

JEDEC

2s2p

Board

0.0 25.3 2.43 3.04 °C/W

1.0 22.6 N/A N/A °C/W

2.5 21.0 N/A N/A °C/W

12-Layer

PCB2

0.0 15.4 2.4 2.6 °C/W

1.0 13.1 N/A N/A °C/W

2.5 11.6 N/A N/A °C/W

1 N/A means not applicable.

2 Non JEDEC thermal resistance.

3 1SOP PCB with no vias in PCB.

4 1SOP PCB with 7 × 7 standard JEDEC vias.

ESD CAUTION

Data Sheet AD9174

Rev. B | Page 17 of 165

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

123456789101112

AGND SERDIN7+ SERDIN6+ SERDIN5+ SERDIN4+ GND GND SERDIN3+ SERDIN2+ SERDIN1+ SERDIN0+ GND

BGND SERDIN7– SERDIN6– SERDIN5– SERDIN4– GND GND SERDIN3– SERDIN2– SERDIN1– SERDIN0– GND

C SVDD1.0 SVDD1.0 GND GND SVDD1.0 DVDD1.8 SVDD1.0 SVDD1.0 GND GND SVDD1.0 SVDD1.0

DDVDD1.8 TXEN1 GND SVDD1.0 GND TXEN0 IRQ0 DVDD1.8

EDNC DNC DVDD1.8 SDO SCLK CS SDIO RESET IRQ1 DVDD1.8 DNC DNC

FGND GND GND DAVDD1.0 DVDD1.0 DVDD1.0 DVDD1.0 DVDD1.0 DAVDD1.0 GND GND GND

GGND GND GND GND GND GND GND GND GND GND GND GND

HSYSREF+ SYSREF– AVDD1.0 AVDD1.0 AVDD1.0 FILT_FINE FILT_

COARSE AVDD1.0 AVDD1.0 AVDD1.0 GND CLKIN–

JGND DNC GND GND GND AVDD1.0 FILT_BYP GND GND GND GND CLKIN+

KCLKOUT+ GND AVDD1.8 DNC AVDD1.8 FILT_VCM AVDD1.8 GND GND AVDD1.8 GND GND

LCLKOUT– GND AVDD1.8 GND GND AVDD1.8 AVDD1.8 GND GND AVDD1.8 GND ISET

MGND

GROUND SERDES INPUT

AVDD1.0 GND DAC1+ DAC1– GND GND DAC0– DAC0+ GND AVDD1.0 GND

1.0V ANALOG SUPPLY SYSREF±/SYNCOUTx±

1.8V ANALOG SUPPLY

DNC = DO NOT CONNECT

1.0V SERDES SUPPLY

DAC RF OUTPUTS

1.8V DIGITAL SUPPLY

1.0V DIGITAL SUPPLY CMOS I/O

1.0V DIGITAL/ANALOG SUPPLY

RF CLOCK PINS

DAC PLL LOOP FILTER PINS

REFERENCE

SYNCOUT1+ SYNCOUT1– SYNCOUT0– SYNCOUT0+

16794-002

Figure 2. Pin Configuration

Table 12. Pin Function Descriptions

Pin No. Mnemonic Description

1.0 V Supply

H3, H4, H5, H8 to H10, J6, M2, M11 AVDD1.0 1.0 V Clock and Analog Supplies. These pins supply the clock receivers, clock

distribution, the on-chip DAC clock multiplier, and the DAC analog core. Clean

power supply rail sources are required on these pins.

F5 to F8 DVDD1.0 1.0 V Digital Supplies. These pins supply power to the DAC digital circuitry.

Clean power supply rail sources are required on these pins.

F4, F9 DAVDD1.0 1.0 V Digital to Analog Supplies. These pins can share a supply rail with the

DVDD1.0 supply (electrically connected) but must have separate supply plane

and decoupling capacitors for the PCB layout to improve isolation for these

two pins. Clean power supply rail sources are required on these pins.

C1, C2, C5, C7, C8, C11, C12, D6 SVDD1.0 1.0 V SERDES Supplies to the JESD204B Data Interface. Clean power supply rail

sources are required on these pins.

1.8 V Supply

K3, K5, K7, K10, L3, L6, L7, L10 AVDD1.8 1.8 V Analog Supplies to the On-Chip DAC Clock Multiplier and the DAC

Analog Core. Clean power supply rail sources are required on these pins.

C6, D3, D10, E3, E10 DVDD1.8 1.8 V Digital Supplies to the JESD204B Data Interface and the Other

Input/Output Circuitry, Such as the SPI. Clean power supply rail sources are

required on these pins.

AD9174 Data Sheet

Rev. B | Page 18 of 165

Pin No. Mnemonic Description

Ground

A1, A6, A7, A12, B1, B6, B7, B12, C3, C4,

C9, C10, D5, D7, F1 to F3, F10 to F12,

G1 to G12, H11, J1, J3 to J5, J8 to J11,

K2, K8, K9, K11, K12, L2, L4, L5, L8, L9,

L11, M1, M3, M6, M7, M10, M12

GND Device Common Ground.

RF Clock

J12 CLKIN+

Positive Device Clock Input. This pin is the clock input for the on-chip DAC

clock multiplier, REFCLK, when the DAC PLL is on. This pin is also the clock

input for the DAC sample clock or device clock (DACCLK) when the DAC PLL is

off. AC couple this input. There is an internal 100 Ω resistor between this pin

and CLKIN−.

H12 CLKIN− Negative Device Clock Input.

K1 CLKOUT+

Positive Device Clock Output. This pin is the clock output of a divided down

DACCLK and is available with the DAC PLL on and off. The divide down ratios

are by 1, 2, 3, or 4.

L1 CLKOUT− Negative Device Clock Output.

System Reference

H1 SYSREF+

Positive System Reference Input. It is recommended to ac couple this pin, but

dc coupling is also acceptable. See the SYSREF± specifications for the dc

common-mode voltage.

H2 SYSREF−

Negative System Reference Input. It is recommended to ac couple this pin, but

dc coupling is also acceptable. See the SYSREF± specifications for the dc

common-mode voltage.

On-Chip DAC PLL Loop Filter

H6 FILT_FINE

On-Chip DAC Clock Multiplier and PLL Fine Loop Filter Input. If the PLL is not in

use, leave this pin floating and disable the PLL via the control registers.

H7 FILT_COARSE

On-Chip DAC Clock Multiplier and PLL Coarse Loop Filter Input. If the PLL is not

in use, leave this pin floating and disable the PLL via the control registers.

J7 FILT_BYP

On-Chip DAC Clock Multiplier and LDO Bypass. Add a high quality ceramic

bypass capacitor between 2 μF and 10 μF at this node. Ideally this capacitor is

10 μF X7R or better. If the PLL is not in use, leave this pin floating and disable

the PLL via the control registers.

K6 FILT_VCM

On-Chip DAC Clock Multiplier and VCO Common-Mode Input. If the PLL is not

in use, leave this pin floating and disable the PLL via the control registers.

SERDES Data Bits

A2 SERDIN7+ SERDES Data Bit 7, Positive.

B2 SERDIN7− SERDES Data Bit 7, Negative.

A3 SERDIN6+ SERDES Data Bit 6, Positive.

B3 SERDIN6− SERDES Data Bit 6, Negative.

A4 SERDIN5+ SERDES Data Bit 5, Positive.

B4 SERDIN5− SERDES Data Bit 5, Negative.

A5 SERDIN4+ SERDES Data Bit 4, Positive.

B5 SERDIN4− SERDES Data Bit 4, Negative.

A8 SERDIN3+ SERDES Data Bit 3, Positive.

B8 SERDIN3− SERDES Data Bit 3, Negative.

A9 SERDIN2+ SERDES Data Bit 2, Positive.

B9 SERDIN2− SERDES Data Bit 2, Negative.

A10 SERDIN1+ SERDES Data Bit 1, Positive.

B10 SERDIN1− SERDES Data Bit 1, Negative.

A11 SERDIN0+ SERDES Data Bit 0, Positive.

B11 SERDIN0− SERDES Data Bit 0, Negative.

Data Sheet AD9174

Rev. B | Page 19 of 165

Pin No. Mnemonic Description

Sync Output

D12 SYNCOUT0+ Positive Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or

CMOS selectable.

D11 SYNCOUT0− Negative Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or

CMOS selectable.

D1 SYNCOUT1+ Positive Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or

CMOS selectable.

D2 SYNCOUT1− Negative Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or

CMOS selectable.

Serial Port Interface

E4 SDO Serial Port Data Output (CMOS Levels with Respect to DVDD1.8).

E7 SDIO Serial Port Data Input/Output (CMOS Levels with Respect to DVDD1.8).

E5 SCLK Serial Port Clock Input (CMOS Levels with Respect to DVDD1.8).

E6 CS Serial Port Chip Select, Active Low (CMOS Levels with Respect to DVDD1.8).

E8 RESET Reset, Active Low (CMOS Levels with Respect to DVDD1.8).

Interrupt Request

D9 IRQ0 Interrupt Request 0. This pin is an open-drain, active low output (CMOS levels

with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this

pin from floating when inactive.

E9 IRQ1 Interrupt Request 1. This pin is an open-drain, active low output (CMOS levels

with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this

pin from floating when inactive.

CMOS Input/Outputs

D8 TXEN0

Transmit Enable for DAC0. The CMOS levels are determined with respect to

DVDD1.8.

D4 TXEN1

Transmit Enable for DAC1. The CMOS levels are determined with respect to

DVDD1.8.

DAC Analog Outputs

M9 DAC0+ DAC0 Positive Current Output.

M8 DAC0− DAC0 Negative Current Output.

M4 DAC1+ DAC1 Positive Current Output.

M5 DAC1− DAC1 Negative Current Output.

Reference

L12 ISET

Device Bias Current Setting Pin. Connect a 5 kΩ resistor from this pin to GND,

preferably with <0.1% tolerance and <±25 ppm/°C temperature coefficient.

Do Not Connect

E1, E2, E11, E12, J2, K4 DNC Do Not Connect. Do not connect to these pins.

AD9174 Data Sheet

Rev. B | Page 20 of 165

TYPICAL PERFORMANCE CHARACTERISTICS

–120

–100

–80

–60

–40

–20

0 500 1000 1500

SFDR (dBc)

OUT (MHz)

2000 2500 3000 3500

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-103

Figure 3. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 0),

6 GHz DAC Sample Rate, Channel Interpolation 2×, Main Interpolation 8×

SFDR (dBc)

OUT

(MHz)

–120

–100

–80

–60

–40

–20

0 500 1000 1500 2000 2500 3000 3500

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-104

Figure 4. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 0),

6 GHz DAC Sample Rate, Channel Interpolation 2×, Main Interpolation 8×

SFDR (dBc)

OUT

(MHz)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 500 1000 1500 2000 2500 3000 3500

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-105

Figure 5. Worst Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 0),

6 GHz DAC Sample Rate, Channel Interpolation 2×, Main Interpolation 8×

SFDR (dBc)

OUT

(MHz)

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-106

Figure 6. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 1),

12 GHz DAC Sample Rate, Channel Interpolation 4×,

Main Interpolation 8×

SFDR (dBc)

OUT

(MHz)

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-107

Figure 7. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 1),

12 GHz DAC Sample Rate, Channel Interpolation 4×,

Main Interpolation 8×

16794-108

–100

–80

–60

–40

–20

0 1000 2000 3000 4000

OUT

(MHz)

WORST SPUR (dBc)

5000 6000

MODE 1:

DAC

= 2949.12MHz

MODE 1:

DAC

= 9830.4MHz

MODE 1:

DAC

= 5898.24MHz

MODE 1:

DAC

= 11796.48MHz

MODE 2:

DAC

= 2949.12MHz

MODE 2:

DAC

= 9830.4MHz

MODE 2:

DAC

= 5898.24MHz

MODE 2:

DAC

= 11796.48MHz

MODE 9:

DAC

= 2949.12MHz

MODE 9:

DAC

= 9830.4MHz

MODE 9:

DAC

= 5898.24MHz

MODE 10:

DAC

= 2949.12MHz (dBc)

MODE 10:

DAC

= 5898.24MHz (dBc)

MODE 10:

DAC

= 9830.4MHz (dBc)

MODE 10:

DAC

= 11796.48MHz (dBc)

Figure 8. Worst Spur vs. fOUT over fDAC (All Modes), 0 dB Digital Scale

Data Sheet AD9174

Rev. B | Page 21 of 165

SFDR (dBc)

OUT

(MHz)

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-109

Figure 9. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 2),

12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8×

SFDR (dBc)

OUT (MHz)

0 1000 2000 3000 4000 5000 6000 7000

–120

–100

–80

–60

–40

–20

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-110

Figure 10. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 2),

12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8×

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 1000 2000 3000 4000 5000 6000 7000

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-111

Figure 11. Worst Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 2),

12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8×

–120

–100

–80

–60

–40

–20

0 500 1000 1500 2000

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-112

Figure 12. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12),

4 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 1×,

12-Bit Resolution

–120

–100

–80

–60

–40

–20

0 500 1000 1500 2000

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-113

Figure 13. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12),

4 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 1×,

12-Bit Resolution

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 500 1000 1500 2000

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-114

Figure 14. Worst Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12),

4 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 1×,

12-Bit Resolution

AD9174 Data Sheet

Rev. B | Page 22 of 165

–140

–120

–100

–80

–60

–40

–20

0 500 1000 1500 2000 2500 3000 3500 4000 4500

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-315

Figure 15. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12),

8 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation

2×, 12-Bit Resolution

–140

–120

–100

–80

–60

–40

–20

0 500 1000 1500 2000 2500 3000 3500 4000 4500

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-316

Figure 16.Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12),

8 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation

2×, 12-Bit Resolution

–

100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 500 1000 1500 2000 2500 3000 3500 4000 4500

SFDR (dBc)

OUT (MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-317

Figure 17. Worst Harmonic (SFDR) vs. FOUT over Digital Scale (Mode 12),

8 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation

2×, 12-Bit Resolution

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

SFDR (dBc)

fOUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-115

Figure 18. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 9),

12 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 8×

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

SFDR (dBc)

OUT (MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-516

Figure 19. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 9),

12 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 8×

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-416

Figure 20. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 10),

12 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 4×

Data Sheet AD9174

Rev. B | Page 23 of 165

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

SFDR (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-116

Figure 21. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 10),

12 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 4×

–120

–100

–80

–60

–40

–20

0 500 1000 1500 2000 2500 3000

IMD3 (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-117

Figure 22. IMD3 vs. fOUT over Digital Scale (Mode 0) 6 GHz DAC Sample

Rate, Channel Interpolation 2×, Main Interpolation 8×, 1 MHz Tone

Spacing

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 200 400 600 800 1000 1200 1400

IMD3 (dBc)

OUT (MHz)

DAC = 2949.12MHz

DAC = 5898.24MHz

16794-118

Figure 23. IMD3 vs. fOUT over fDAC (Mode 0), Channel Interpolation 2×,

Main Interpolation 8×, 1 MHz Tone Spacing

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 1000 2000 3000 4000 5000 6000 7000

IMD3 (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-119

Figure 24. IMD3 vs. fOUT over Digital Scale (Mode 1), 12 GHz DAC Sample Rate,

Channel Interpolation 4×, Main Interpolation 8×, 1 MHz Tone Spacing

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 1000 2000 3000 4000 5000 6000 7000

IMD3 (dBc)

OUT

(MHz)

DAC

= 2949.12MHz

DAC

= 5898.24MHz

DAC

= 9830.4MHz

DAC

= 11796.48MHz

16794-120

Figure 25. IMD3 vs. fOUT over fDAC (Mode 1), Channel Interpolation 4×,

Main Interpolation 8×, 1 MHz Tone Spacing, −7 dB Digital Scale

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10000 2000 3000 4000 5000 6000 7000

IMD3 (dBc)

OUT

(MHz)

0dBFS

–7dBFS

–12dBFS

–17dBFS

16794-121

Figure 26. IMD3 vs. fOUT over Digital Scale (Mode 2), 12 GHz DAC Sample Rate,

Channel Interpolation 4×, Main Interpolation 8×, 1 MHz Tone Spacing

AD9174 Data Sheet

Rev. B | Page 24 of 165

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 1000 2000 3000 4000 5000 6000 7000

fDAC = 2949.12MHz

fDAC = 5898.24MHz

fDAC = 9830.4MHz

fDAC = 11796.48MHz

IMD3 (dBc)

fOUT (MHz)

16794-122

Figure 27. IMD3 vs. fOUT over fDAC (Mode 2), Channel Interpolation 4×,

Main Interpolation 8×, 1 MHz Tone Spacing

IMD3 (dBc)

OUT

(MHz)

–120

–100

–80

–60

–40

–20

0 500 1000 1500 2000

–7dBFS

–12dBFS

–20dBFS

–17dBFS

16794-123

Figure 28. IMD3 vs. fOUT over Digital Scale (Mode 12), 4 GHz DAC Sample Rate,

Channel Interpolation 1×, Main Interpolation 1×, 1 MHz Tone Spacing,

12-Bit Resolution

–

120

–100

–80

–60

–40

–20

0 500 1000 1500 2000 2500 3000 3500 4000 4500

IMD3 (dBc)

OUT

(MHz)

16794-325

–7dBFS

–12dBFS

–17dBFS

–20dBFS

Figure 29. IMD3 vs. fOUT over Digital Scale (Mode 12), 8 GHz DAC Sampling

Rate, Channel Interpolation 1×, Main Interpolation 2×, 1 MHz Tone

Sapcing

IMD3 (dBc)

OUT

(MHz)

–120

–100

–80

–60

–40

–20

0 1000 2000 3000 4000 5000 6000 7000

–7dBFS

–12dBFS

–17dBFS

–20dBFS

16794-124

Figure 30. IMD3 vs. fOUT over Digital Scale (Mode 10), 12 GHz DAC Sample Rate,

Channel Interpolation 1×, Main Interpolation 4×, 1 MHz Tone Spacing

–170

–165

–160

–155

–150

–145

–140

–135

–

130

0 500 1000 1500 2000 2500

NSD (dBc/Hz)

fOUT (MHz)

SHUFFLE OFF

SHUFFLE ON

16794-201

Figure 31. Single-Tone NSD Measured at 70 MHz vs. fOUT, 11796.48 MHz

fDAC, 16-Bit Resolution, for Different Shuffle Options

–170

–165

–160

–155

–150

–145

–140

–135

–

130

0 500 1000 1500 2000 2500

NSD (dBc/Hz)

OUT

(MHz)

DAC

= 5898.24MHz

DAC

= 9830.4MHz

DAC

= 11796.48MHz

16794-202

Figure 32. NSD vs. fOUT over fDAC, 16-Bit Resolution, Shuffle On, Single Tone

Measured at 70 MHz

Data Sheet AD9174

Rev. B | Page 25 of 165

–170

–165

–160

–155

–150

–145

–140

–135

–

130

0 500 1000 1500 2000 2500

NSD (dBc/Hz)

OUT

(MHz)

DAC

= 5898.24MHz

DAC

= 9830.4MHz

DAC

= 11796.48MHz

16794-203

Figure 33. NSD vs. fOUT over fDAC, 16-Bit Resolution, Shuffle On, Single-Tone,

Measured at 10% Offset from fOUT

–170

–165

–160

–155

–150

–145

–140

–135

–

130

0 500 1000 1500 2000 2500

NSD (dBc/Hz)

OUT

(MHz)

SHUFFLE OFF

SHUFFLE ON

16794-304

Figure 34. NSD vs. fOUT, 11796.48 MHz fDAC, 12-Bit Resolution, for Different

Shuffle Options, Single-Tone, Measured at 70 MHz

NSD (dBc/Hz)

–170

–165

–160

–155

–150

–145

–140

–135

–

130

0 500 1000 1500 2000 2500

OUT

(MHz)

DAC

= 5898.24MHz

DAC

= 9830.4MHz

DAC

= 11796.48MHz

16794-205

Figure 35. NSD vs. fOUT over fDAC, 12-Bit Resolution, Shuffle On, Single-Tone,

Measured at 70 MHz

NSD (dBc/Hz)

–170

–165

–160

–155

–150

–145

–140

–135

–

130

0 500 1000 1500 2000 2500

fOUT

(MHz)

fDAC

= 5898.24MHz

fDAC

= 9830.4MHz

fDAC

= 11796.48MHz

16794-206

Figure 36. NSD vs. fOUT over fDAC, 12-Bit Resolution, Shuffle On, Single-Tone,

Measured at 10% Offset from fOUT

10010 1k 10k 100k 1M 10M 100M

16794-207

–180

–170

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

SSB PHASE NOISE (dBc)

FREQUENCY OFFSET (Hz)

PLL OFF (DIRECT CLOCK)

PLL ON (PFD = 122.88MHz)

PLL ON (PFD = 245.76MHz)

PLL ON (PFD = 368.64MHz)

PLL ON (PFD = 491.52MHz)

Figure 37. Single-Sideband (SSB) Phase Noise vs. Offset over fOUT, over PFD

Frequency, fDAC = 12 GHz, fOUT = 1.8 GHz, PLL On, PLL Reference Clock =

500 MHz

10010 1k 10k 100k 1M 10M 100M

16794-331

–180

–170

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

SSB PHASE NOISE (dBc)

FREQUENCY OFFSET (Hz)

OUT

= 900MHz

OUT

= 1.8GHz

OUT

= 3.6GHz

Figure 38. SSB Phase Noise vs. Frequency Offset over fOUT, fDAC = 12 GHz,

Direct Clock (PLL Off)

AD9174 Data Sheet

Rev. B | Page 26 of 165

–1

0 10000 20000 30000 40000 50000 60000 70000

16-BIT DNL (LSB)

CODE

DAC1

DAC0

16794-208

Figure 39. DNL, IOUTFS = 26 mA, 16-Bit Resolution

–5

–4

–3

–2

–1

0 10000 20000 30000 40000 50000 60000 70000

16-BIT INL (LSB)

CODE

DAC1

DAC0

16794-209

Figure 40. INL, IOUTFS = 26 mA, 16-Bit Resolution

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0 10000 20000 30000 40000 50000 60000 70000

16-BIT DNL (LSB)

Code

DAC1

DAC0

16794-210

Figure 41. DNL, IOUTFS = 20 mA, 16-Bit Resolution

–4

–3

–2

–1

0 10000 20000 30000 40000 50000 60000 70000

16-BIT INL (LSB)

CODE

DAC1

DAC0

16794-211

Figure 42. INL, IOUTFS = 20 mA, 16-Bit Resolution

CODE

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

0 10000 20000 30000 40000 50000 60000 70000

16-BIT DNL (LSB)

DAC1

DAC0

16794-212

Figure 43. DNL, IOUTFS = 15.6 mA, 16-Bit Resolution

–3

–2

–1

0 10000 20000 30000 40000 50000 60000 70000

16-BIT INL (LSB)

CODE

DAC1

DAC0

16794-213

Figure 44. INL, IOUTFS = 15.6 mA, 16-Bit Resolution

Data Sheet AD9174

Rev. B | Page 27 of 165

–0.13

–0.09

–0.05

–0.01

0.03

0.07

0.11

0.15

0 500 1000 1500 2000 2500 3000 3500 4000 4500

12-BIT DNL (LSB)

CODE

DAC1

DAC0

16794-214

Figure 45. DNL, IOUTFS = 20 mA, 12-Bit Resolution

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15

0.20

0 500 1000 1500 2000 2500 3000 3500 4000 4500

12-BIT INL (LSB)

CODE

DAC1

DAC0

16794-215

Figure 46. INL, IOUTFS = 20 mA, 12-Bit Resolution

AD9174 Data Sheet

Rev. B | Page 28 of 165

TERMINOLOGY

Integral Nonlinearity (INL)

INL is the maximum deviation of the actual analog output from

the ideal output, determined by a straight line drawn from zero

scale to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Offset Error

Offset error is the deviation of the output current from the ideal

value of 0 mA. For DACx+, a 0 mA output is expected when all

inputs are set to 0. For DACx−, a 0 mA output is expected when

all inputs are set to 1.

Gain Error

Gain error is the difference between the actual and ideal output

span. The actual span is determined by the difference between

the output when the input is at its minimum code and the

output when the input is at its maximum code.

Output Compliance Range

The output compliance range is the range of allowable voltages

at the output of a current output DAC. Operation beyond the

maximum compliance limits can cause either output stage

saturation or breakdown, resulting in nonlinear performance.

Temperature Dr ift

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either TMIN or TMAX. For offset

and gain drift, the drift is reported in ppm of full-scale range

(FSR) per degree Celsius. For reference drift, the drift is reported

in ppm per degree Celsius.

Settling Time

Settling time is the time required for the output to reach and

remain within a specified error band around its final value,

measured from the start of the output transition.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the peak amplitude

of the output signal and the peak spurious signal within the dc

to Nyquist frequency of the DAC. Typically, energy in this band

is rejected by the interpolation filters. This specification, therefore,

defines how well the interpolation filters work and the effect of

other parasitic coupling paths on the DAC output.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

the interpolation rate (fDATA), a digital filter can be constructed that

has a sharp transition band near fDATA/2. Images that typically

appear around the output data rate (fDAC) can be greatly suppressed.

Channel Datapath

The channel datapath, sometimes referred to as a channelizer, is

a complex (IQ) datapath. There are six channelizers within the

chip, with three channelizers summed in each main datapath.

The channelizers can be bypassed if unused, depending on the

mode of operation. When the channelizers are in use, a complex

(I/Q) input data stream is required. Each channel datapath

includes an independently controlled gain stage and a channel

NCO. A selectable channel interpolation block is configurable

according to the mode of operation. All channels must be set to

the same interpolation rate.

Main Datapath

The main datapath refers to the portion of the digital datapath after

the summing node in the chip, up to each of the main DAC analog

cores. Each of these main datapaths includes an optional PA

protection block with a feed forward to the ramp up/down gain

stage block for muting the DAC outputs before damaging a power

amplifier in the transmit path. There is a selectable main

interpolation block that is configurable (same setting for both main

interpolation blocks) depending on the mode of operation chosen.

Each main datapath also contains an individually programmable

main NCO per main DAC datapath that can be optionally used

depending on the mode of operation.

Adjacent Channel Leakage Ratio (ACLR)

ACLR is the ratio in decibels relative to the carrier (dBc)

between the measured power within a channel relative to its

adjacent channel.

Adjusted DAC Update Rate

The adjusted DAC update rate is the DAC update rate divided

by the smallest interpolating factor. For clarity on DACs with

multiple interpolating factors, the adjusted DAC update rate for

each interpolating factor may be given.

Physical (PHY) Lane

Physical Lane x refers to SERDINx±.

Logical Lane

Logical Lane x refers to physical lanes after optionally being

remapped by the crossbar block (Register 0x308 to Register 0x30B).

Link Lane

Link Lane x refers to logical lanes considered per link. When

paging Link 0 (Register 0x300[2] = 0), Link Lane x = Logical

Lane x. When paging Link 1 (Register 0x300[2] = 1, dual link

only), Link Lane x = Logical Lane x + 4.

Data Sheet AD9174

Rev. B | Page 29 of 165

THEORY OF OPERATION

The AD9174 is a 16-bit, dual RF DAC with a high speed JESD204B

SERDES interface, compliant with Subclass 0 and Subclass 1

operation. Figure 1 shows a functional block diagram of the

AD9174. Each DAC core has three individually bypassable

channels that support up to 1.575 GSPS of complex data rate

input per channel. The JESD204B interface can be configured

for either single-link or a dual-link operation, in which each of

the eight high speed serial ports can carry data at a maximum of

15.4 Gbps to the channel datapaths, referred to as channelizers.

Compared to either LVDS or CMOS interfaces, the SERDES

interface simplifies pin count, board layout, and input clock

requirements to the device.

The local clock for the SERDES interface is derived from the

device clock (CLKIN± pins) as required by the JESD204B

specification. The device clock either acts as a reference for the

on-chip PLL to provide a DAC clock, or the PLL can be bypassed

and the DAC clock can be provided directly from a high fidelity,

external clock source. The SERDES interface can be configured

to operate in one, two, three, four, or eight lane per link modes,

depending on the required input data rate. In dual-link operation,

each link can occupy a maximum of four lanes each.

The digital datapath of the AD9174 includes bypassable (1×)

interpolation blocks in both the channel datapaths and the main

datapaths. Depending on the desired mode, there are also 2×,

3×, 4×, 6×, and 8× interpolation options for the channel datapaths,

and 2×, 4×, 6×, 8×, and 12× interpolation options for the main

datapaths. See Table 13 for a summary of the various supported

processing modes, as well as the associated interpolation options.

Unless 1× interpolation (bypass) is selected, each channel digital

datapath allows the user to individually control the gain stages

and NCO blocks at each channel. The NCO blocks have a 48-bit

modulus NCO option to enable digital frequency shifts of signals

with near infinite precision. At the end of the three channelizer

datapaths, there is a summation node that combines the three

channelizers together at a maximum of 1.575 GSPS, sent as an

input to the respective main DAC datapaths for further digital

processing.

Each main DAC datapath contains an optional power amplifier

(PA) protection block, a main datapath interpolation block, a

main NCO with an optional modulus feature, and a ramp-up/

ramp-down gain block that is fed by the PA protection block.

Additionally, there is an optional calibration tone feature, as

well as four modulator switch modes that are part of the main

NCO block.

Each NCO can operate as a standalone NCO in direct digital

synthesis (DDS) mode. The level of the NCO tone can be either

individually assigned by providing digital data from the SERDES

interface, or collectively assigned to all NCOs using a SPI-

programmable register. The frequency can be individually

controlled.

The AD9174 is also capable of FFH, which allows quick hopping

between 31 additional NCOs, each operating at a 32-bit precision.

Various modes of operation exist where either coherence or

phase continuity can be maintained between hops. Only a single

SPI write is required to hop to the next frequency, assuming

each frequency tuning word (FTW) is preloaded.

The AD9174 is also capable of multichip synchronization that

can both synchronize multiple DACs and establish a constant

and deterministic latency (latency locking) path for the DACs.

The latency for each DAC remains constant to within several

DAC clock cycles from link establishment to link establishment.

An external alignment signal (SYSREF±) makes the AD9174

JESD204B Subclass 1 compliant. Several methods of SYSREF±

signal handling are available for use in the system.

An SPI port configures the various functional blocks and monitors

their status. The various functional blocks and the data interface

must be set up in a predetermined sequence for proper operation

(see the Start-Up Sequence section). Simple SPI initialization

routines set up the JESD204B link and are included in the

AD9174-FMC-EBZ evaluation board package. This data sheet

describes the various blocks of the AD9174 in detail. Descriptions

of the JESD204B interface, control parameters, and various

registers to set up and monitor the device are provided. The

recommended start-up routine reliably sets up the data link.

AD9174 Data Sheet

Rev. B | Page 30 of 165

Table 13. JESD204B Supported Operating Modes and Interpolation Combinations

Application

JESD204B Operation Modes Channel Datapath Main DAC Datapath Maximum

Instantaneous

Bandwidth

(MHz)3

Link

Modes

JESD204B

Modes

Lanes

per

Link

Channels

per DAC

Maximum

Channel Data

Rate (MSPS)1

Channel

Inter-

polation

Main Datapath

Interpolation

Maximum

DAC Rate

(GSPS)2

Channelizer Modes (All

Complex)

375 MHz

(N = 16 Bits)

Single-Channel Single,

dual

0 1 1 385 2× 8× 6.16 308

0 1 1 385 4×, 6× 6×, 8× 12.6 308

Dual-Channel Single,

dual

1 2 2 385 4×, 6× 6×, 8× 12.6 616

Triple-Channel Single,

dual

2 3 3 385 4×, 6× 6×, 8× 12.6 924

500 MHz

(N = 12 Bits)

Single-Channel Single,

dual

5 1 1 513 2× 6× 6.16 410.4

5 1 1 513 3× 6×, 8× 12.6 410.4

Dual-Channel Single,

dual

6 2 2 513 3× 6×, 8× 12.6

750 MHz

(N = 16 Bits)

Single-Channel Single,

dual

3 2 1 770 1× 8× 6.16 616

3 2 1 770 2×, 3× 6×, 8× 12.6 616

Dual-Channel Single,

dual

4 4 2 770 2×, 3× 6×, 8× 12.6 616

4 4 2 385 4× 8× 12.6 308

187 MHz

(N = 16 Bits)

Dual-Channel Single,

dual

7 1 2 192.5 8× 6×, 8× 12.6 154

Wideband Modes

(Complex or Real)

3000 MHz

(N = 16 Bits)

Complex Single 10, 11 8 1 3080 1× 2×, 4× 12.6 2464

Real, Dual-DAC Single 10, 11 8 1 3080 1× 1× 3.08 1540

Real, Single- or

Dual-DAC

Single,

dual

18, 19 4 1 3080 1× 1× 3.08 1540

1500 MHz

(N = 16 Bits)

Complex, Dual-

DAC

Single,

dual

8, 9 4 24 1540 1× 2×, 4×, 6×, 8×,

12×

12.6 24644

4000 MHz

(N = 12 Bits)

Complex Single 12 8 1 4100 1× 2×5 8.2 3280

Real, Dual-DAC Single 12 8 1 4100 1x 1x 4.1 2050

2000 MHz

(N = 12 Bits)

Complex, Dual-

DAC

Single,

dual

22 4 24 2050 1× 4×, 6× 12.6 32804

6000 MHz

(N = 16 Bits)

Real, Single-DAC Single 20, 21 8 1 6160 1× 1× 6.16 3080

1 The maximum data rate is calculated based on a maximum lane rate as listed in Table 7. The data rate is calculated based on the formula lane rate = (10/8)  NP  data rate 

(M/L), where the NP, M, and L values depend on the selected mode.

2 The maximum DAC rate per mode depends on the voltage tolerance as well as the lane rate for a given configuration, as listed in Table 3. The maximum possible lane

rate is according to Table 7.

3 For complex modes, instantaneous bandwidth (IBW) is the bandwidth that both I and Q occupy (referred to as the combined I/Q bandwidth). The bandwidth for

complex modes is in part limited by the bandwidth of the interpolation filters. When the interpolation filters are bypassed to configure the AD9174 in real only mode,

IBW = ½ × data rate.

4 With a correct modulator switch configuration, the AD9174 can be configured to operate as a wideband, dual-channel DAC, with each channel to include its own main

datapath NCO. In this case, the modulator switch is configured to act as a summing node that feeds complex data from two datapaths to a single DAC core.

5 Only supported when JESD204B is configured for Subclass 1 operation.

Data Sheet AD9174

Rev. B | Page 31 of 165

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communications

port that allows easy interfacing with many industry-standard

microcontrollers and microprocessors. The serial input/output

is compatible with most synchronous transfer formats, including

both the Motorola, Inc., SPI and Intel® SSR protocols. The interface

allows read and write access to all registers that configure the

AD9174. MSB first or LSB first transfer formats are supported.

The serial port interface can be configured as a 4-wire interface

or a 3-wire interface in which the input and output share a

single pin input/output (SDIO). Data can be transferred either

one byte at a time, with the address specified for each read/write

operation, or can be transferred in multibyte mode, with the

address incremented automatically at the end of each transfer

cycle, thus increasing link throughput when multiple read/write

operations to register addresses are sequential.

SCLK

SDIO

SDO

SPI

PORT

16794-009

Figure 47. Serial Port Interface Pins (144-Ball BGA_ED)

There are two phases to a communication cycle with the

AD9174. Phase 1 is the instruction cycle (the writing of an

instruction byte into the device), coincident with the first

16 SCLK rising edges. The instruction word provides the serial

port controller with information needed for Phase 2 of the

communication cycle, namely the data transfer cycle. The

instruction word defines the starting register address for the

following data transfer and flags, whether the upcoming data

transfer is a read operation or a write operation.

A logic high on the CS pin followed by a logic low resets the

serial port timing to the initial state of the instruction cycle.

From this state, the next 16 rising SCLK edges represent the

instruction bits of the current input/output operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one or more data bytes. Eight × N SCLK cycles are

required to transfer N bytes during the transfer cycle. The registers

update (latch) their data immediately upon writing to the last

bit of each transfer byte.

The FTW and NCO phase offsets change only when the

frequency tuning word load request bit (DDSM_FTW_

LOAD_REQ or DDSC_FTW_LOAD_REQ) is set.

DATA FORMAT

The instruction byte contains the information shown in Table 14.

Table 14. Serial Port Instruction Word

I15 (MSB) I[14:0]

R/W A[14:0]

R/W, Bit 15 of the instruction word, determines whether a read

or a write data transfer occurs after the instruction word write.

Logic 1 indicates a read operation, and Logic 0 indicates a write

operation.

A14 to A0, Bit I14 to Bit I0 of the instruction word, determine

the register that is accessed during the data transfer portion of

the communication cycle.

For multibyte transfers, A[14:0] is the starting address. The

remaining register addresses are generated by the device based

on the address increment bit. If the address increment bits are set

high (Register 0x000, Bit 5 and Bit 2), multibyte SPI writes start on

A[14:0] and increment by 1 every eight bits sent/received. If the

address increment bits are set to 0, the address decrements by 1

every eight bits.

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 80 MHz. All data input is registered on the rising edge

of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (CS)

An active low input starts and gates a communication cycle.

CS allows more than one device to be used on the same serial

communications lines. The SDIO pin goes to a high impedance

state when this input is high. During the communication cycle,

the chip select must stay low.

Serial Data Input/Output (SDIO)

This pin is a bidirectional data line. In 4-wire mode, this pin

acts as the data input and SDO acts as the data output.

AD9174 Data Sheet

Rev. B | Page 32 of 165

SERIAL PORT OPTIONS

The serial port can support both MSB first and LSB first data

formats. This functionality is controlled by the LSB first bit

(Register 0x000, Bit 6 and Bit 1). The default is MSB first

(LSBFIRST bit = 0).

When the LSB first bits = 0 (MSB first), the instruction and data

bits must be written from MSB to LSB. R/W is followed by A[14:0]

as the instruction word, and D[7:0] is the data-word. When the

LSB first bits = 1 (LSB first), the opposite is true. A[0:14] is

followed by R/W, which is subsequently followed by D[0:7].

The serial port supports a 3-wire or 4-wire interface. When the

SDO active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire

interface with a separate input pin (SDIO) and output pin (SDO) is

used. When the SDO active bits = 0, the SDO pin is unused and

the SDIO pin is used for both the input and the output.

Multibyte data transfers can be performed as well by holding

the CS pin low for multiple data transfer cycles (eight SCLKs)

after the first data transfer word following the instruction cycle.

The first eight SCLKs following the instruction cycle read from

or write to the register provided in the instruction cycle. For

each additional eight SCLK cycles, the address is either incre-

mented or decremented and the read/write occurs on the new

ADDRINC_M (Register 0x000, Bit 5 and Bit 2). When ADDRINC

or ADDRINC_M is 1, the multicycle addresses are incremented.

When ADDRINC or ADDRINC_M is 0, the addresses are decre-

mented. A new write cycle can always be initiated by bringing

CS high and then low again.

To prevent confusion and to ensure consistency between devices,

the chip tests the first nibble following the address phase, ignoring

the second nibble. This test is completed independently from the

LSB first bits and ensures that there are extra clock cycles following

the soft reset bits (Register 0x000, Bit 0 and Bit 7). This test of

the first nibble only applies when writing to Register 0x000.

R/W A14 A13 A3 A2 A1 A0 D7 D6 D5 D0D1D2D3

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CLK

SDIO

16794-010

Figure 48. Serial Register Interface Timing, MSB First,

A0 A1 A2 A12 A13 A14 D0 D1 D2 D7D6D5D4

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SCLK

SDIO

R/W

16794-011

Figure 49. Serial Register Interface Timing, LSB First,

SCLK

SDIO

DATA BIT n – 1DATA BIT n

16794-012

Figure 50. Timing Diagram for Serial Port Register Read

CLK

SDIO

INSTRUCTION BIT 14 INSTRUCTION BIT 0INSTRUCTION BIT 15

PWH

PWL

16794-013

Figure 51. Timing Diagram for Serial Port Register Write

Data Sheet AD9174

Rev. B | Page 33 of 165

JESD204B SERIAL DATA INTERFACE

JESD204B OVERVIEW

The AD9174 has eight JESD204B SERDES data ports that receive

the input sample data to the device. The eight JESD204B ports

can be combined to form either one (single-link) or two (dual-

link) identical JESD204B links. Each link can provide data to its

own datapath with its own set of channelizers.

Both single- and dual-link JESD204B modes align their individual

(local) clocks to the same system reference (SYSREF±) and device

clock (CLKIN±) signals. However, the SYNCOUT0± and

SYNCOUT1± signals are specific to their respective JESD204B

link, and in dual-link mode the two links can operate

independently from one another.

The JESD204B serial interface hardware is grouped into three

layers: the physical layer, the data link layer, and the transport layer.

Figure 52 shows the three communication layers implemented in

the AD9174 serial data interface to recover the clock and

deserialize, descramble, and deframe the data before it is sent to

each of the digital signal processing channelizers of the device.

The communication layers are described as follows:

 The physical layer establishes a reliable channel between

the transmitter and the receiver.

 The data link layer is responsible for unpacking the data

into octets and descrambling the data.

 The transport layer receives the descrambled JESD204B

frames and converts them to DAC samples.

A detailed description of each layer is provided in the subsequent

sections, including information for configuring each aspect of

the interface.

A number of JESD204B parameters (L, F, K, M, N, NP, S, HD)

defines how the data is packed and tells the device how to turn

the serial data into samples. These parameters are described in

detail in the Transport Layer section. The AD9174 also has a

descrambling option (see the Descrambler section for more

information). To increase the maximum data rate achievable by

the SERDES interface, the AD9174 has the ability to use a 12-bit

packing mode (NP = 12, N = 11 or 12) for applications that do

not require 16-bit data.

The AD9174 has multiple JESD204B modes, which include

single- and dual-link modes, and allow configuration of the

device depending on the number channels, number of DAC

cores, and link speed requirements. These modes and their

respective JESD204B link parameters are described in Table 15

and Table 16. Various combinations of channel interpolation

and main datapath interpolation are available, depending on the

mode. Table 13 lists all the possible link and interpolation

combinations available as well as the maximum supported data

rate for each mode.

The AD9174 has two DAC cores, each with its own analog output.

Each DAC core is supplied with data from as many as three

complex channelizers. The effective number of converters, as

seen by the JESD204B link, is the number of noncomplex

channels in the given mode of operation, as represented by the

M parameter of the JESD204B standard. Therefore, a single

noncomplex channel is represented by M = 1, a complex channel is

represented by M = 2, a group of two complex channels is

represented by M = 4, and so on. When the total datapath

interpolation is set to 1×, the complex channels are bypassed

and the data input is assumed to be noncomplex (real). In this

case only, M = 2 represents the actual number of DAC cores,

and the complex data is not required.

For a particular JESD204B mode of operation, the following

relationships exist:

Total Interpolation = Channel Interpolation ×

Main Interpolation

Data Rate = DAC Rate/Total Interpolation

Lane Rate = (M/L) × NP × (10/8) × Data Rate

where:

Lane Rate must be between 3 Gbps and 15.4 Gbps.

M, L, and NP are JESD204B link parameters for the chosen

JESD204B operating mode.

Achieving and maintaining synchronous operation between the

JESD204B transmitter and the JESD204B receiver is critical for

maintaining a reliable link. After the link is established, the stability

and phase relationship between the various system clocks becomes

important. If a particular clock slips relative to a common

reference, the link may be lost and may need to be reestablished.

Similarly, if a particular lane becomes asynchronous relative to

other lanes within the link, this link may be lost as well. To simplify

the process of establishing or reestablishing a link, the AD9174

designates an independent master synchronization signal for each

JESD204B link. The SYNCOUT0± and SYNCOUT1± pins are

used as the master flag signal for all the lanes in the particular link.

If the data arriving on the various lanes appears to be out of

synchronization, SYNCOUTx± is deasserted and the transmitter

is expected to stop sending data and instead begin sending

synchronization characters to all the lanes in that link until

resynchronization is achieved.

AD9174 Data Sheet

Rev. B | Page 34 of 165

DESERIALIZER

DATA LINK

LAYER

TRANSPORT

LAYER

SERDIN0±

SYSREF±

SERDIN7±

I DATA[15:0]

Q DATA[15:0]

COMPLEX DATA

PER CHANNELIZER

SYNCOUT1±

SYNCOUT0±

PHYSICAL

LAYER

DESERIALIZER

FRAME TO

SAMPLES

QBD/

DESCRAMBLER

16794-014

Figure 52. Functional Block Diagram of Serial Link Receiver

Table 15. Single-Link JESD204B Operating Modes

Parameter

Single-Link JESD204B Modes

0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22

L (Lane Count) 1 2 3 2 4 1 2 1 4 4 8 8 8 4 4 8 8 4

M (Converter Count) 2 4 6 2 4 2 4 4 2 2 2 2 2 1 1 1 1 2

F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 3 1 2 1 2 3

S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 8 2 4 4 8 4

NP (Total Number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 12

N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 12

K (Frames per Multiframe) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

HD (High Density User Data Format) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Table 16. Dual-Link JESD204B Operating Modes

Parameter

Dual-Link JESD204B Modes

0 1 2 3 4 5 6 7 8 9 18 19 22

L (Lane Count) 1 2 3 2 4 1 2 1 4 4 4 4 4

M (Converter Count) 2 4 6 2 4 2 4 4 2 2 1 1 2

F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 3

S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 4

NP (Total Number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 12

N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 12

K (Frames per Multiframe) 32 32 32 32 32 32 32 32 32 32 32 32 32

HD (High Density User Data Format) 1 1 1 1 1 1 1 1 1 1 1 1 1

Table 17. Data Structure per Lane for F = 1 JESD204B Operating Modes1

JESD204B Mode and Parameters Link Logical Lane Frame 0, Octet 0 Frame 1, Octet 0

L = 4, M = 2, S = 1, NP = 16, N = 16

Mode 8: N = 16

Lane 0 M0S0[15:8] M0S1[15:8]

Lane 1 M0S0[7:0] M0S1[7:0]

Lane 2 M1S0[15:8] M1S1[15:8]

Lane 3 M1S0[7:0] M1S1[7:0]

Mode 10 (L = 8, M = 2, S = 2, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S2[15:8]

Lane 1 M0S0[7:0] M0S2[7:0]

Lane 2 M0S1[15:8] M0S3[15:8]

Lane 3 M0S1[7:0] M0S3[7:0]

Lane 4 M1S0[15:8] M1S2[15:8]

Lane 5 M1S0[7:0] M1S2[7:0]

Lane 6 M1S1[15:8] M1S3[15:8]

Lane 7 M1S1[7:0] M1S3[7:0]

Data Sheet AD9174

Rev. B | Page 35 of 165

JESD204B Mode and Parameters Link Logical Lane Frame 0, Octet 0 Frame 1, Octet 0

Mode 18 (L = 4, M = 1, S = 2, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S2[15:8]

Lane 1 M0S0[7:0] M0S2[7:0]

Lane 2 M0S1[15:8] M0S3[15:8]

Lane 3 M0S1[7:0] M0S3[7:0]

Mode 20 (L = 8, M = 1, S = 4, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S4[15:8]

Lane 1 M0S0[7:0] M0S4[7:0]

Lane 2 M0S1[15:8] M0S5[15:8]

Lane 3 M0S1[7:0] M0S5[7:0]

Lane 4 M0S2[15:8] M0S6[15:8]

Lane 5 M0S2[7:0] M0S6[7:0]

Lane 6 M0S3[15:8] M0S7[15:8]

Lane 7 M0S3[7:0] M0S7[7:0]

1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.

Table 18. Data Structure per Lane for F = 2 JESD204B Operating Modes1

JESD204B Mode and Parameters Link Logical Lane

Frame 0 Frame 1

Octet 0 Octet 1 Octet 0 Octet 2

Mode 3 (L = 2, M = 2, S = 1, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0]

Lane 1 M1S0[15:8] M1S0[7:0] M1S1[15:8] M1S1[7:0]

Mode 4 (L = 4, M = 4, S = 1, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0]

Lane 1 M1S0[15:8] M1S0[7:0] M1S1[15:8] M1S1[7:0]

Lane 2 M2S0[15:8] M2S0[7:0] M2S1[15:8] M2S1[7:0]

Lane 3 M3S0[15:8] M3S0[7:0] M3S1[15:8] M3S1[7:0]

Mode 9 (L = 4, M = 2, S = 2, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S2[15:8] M0S2[7:0]

Lane 1 M0S1[15:8] M0S1[7:0] M0S3[15:8] M0S3[7:0]

Lane 2 M1S0[15:8] M1S0[7:0] M1S2[15:8] M1S2[7:0]

Lane 3 M1S1[15:8] M1S1[7:0] M1S3[15:8] M1S3[7:0]

Mode 11 (L = 8, M = 2, S = 4, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S4[15:8] M0S4[7:0]

Lane 1 M0S1[15:8] M0S1[7:0] M0S5[15:8] M0S5[7:0]

Lane 2 M0S2[15:8] M0S2[7:0] M0S6[15:8] M0S6[7:0]

Lane 3 M0S3[15:8] M0S3[7:0] M0S7[15:8] M0S7[7:0]

Lane 4 M1S0[15:8] M1S0[7:0] M1S4[15:8] M1S4[7:0]

Lane 5 M1S1[15:8] M1S1[7:0] M1S5[15:8] M1S5[7:0]

Lane 6 M1S2[15:8] M1S2[7:0] M1S6[15:8] M1S6[7:0]

Lane 7 M1S3[15:8] M1S3[7:0] M1S7[15:8] M1S7[7:0]

Mode 19 (L = 4, M = 1, S = 4, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S4[15:8] M0S4[7:0]

Lane 1 M0S1[15:8] M0S1[7:0] M0S5[15:8] M0S5[7:0]

Lane 2 M0S2[15:8] M0S2[7:0] M0S6[15:8] M0S6[7:0]

Lane 3 M0S3[15:8] M0S3[7:0] M0S7[15:8] M0S7[7:0]

Mode 21 (L = 8, M = 1, S = 8, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S8[15:8] M0S8[7:0]

Lane 1 M0S1[15:8] M0S1[7:0] M0S9[15:8] M0S9[7:0]

Lane 2 M0S2[15:8] M0S2[7:0] M0S10[15:8] M0S10[7:0]

Lane 3 M0S3[15:8] M0S3[7:0] M0S11[15:8] M0S11[7:0]

Lane 4 M0S4[15:8] M0S4[7:0] M0S12[15:8] M0S12[7:0]

Lane 5 M0S5[15:8] M0S5[7:0] M0S13[15:8] M0S13[7:0]

Lane 6 M0S6[15:8] M0S6[7:0] M0S14[15:8] M0S14[7:0]

Lane 7 M0S7[15:8] M0S7[7:0] M0S15[15:8] M0S15[7:0]

1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.

AD9174 Data Sheet

Rev. B | Page 36 of 165

Table 19. Data Structure per Lane for F = 3 JESD204B Operating Modes1

JESD204B Mode and Parameters

Link

Logical

Lane

Frame 0

Octet 0 Octet 1 Octet 2

Nibble 0 Nibble1 Nibble 0 Nibble1 Nibble 0 Nibble1

Mode 5 (L = 1, M = 2, S = 1, NP = 12,

N = 12)

Lane 0 M0S0[11:8] M0S0[7:4] M0S0[3:0] M1S0[11:8] M1S0[7:4] M1S0[3:0]

Mode 6 (L = 2, M = 4, S = 1, NP = 12,

N = 12)

Lane 0 M0S0[11:8] M0S0[7:4] M0S0[3:0] M1S0[11:8] M1S0[7:4] M1S0[3:0]

Lane 1 M2S0[11:8] M2S0[7:4] M2S0[3:0] M3S0[11:8] M3S0[7:4] M3S0[3:0]

Mode 22 (L = 4, M = 2, S = 4, NP = 12,

N = 12)

Lane 0 M0S0[11:8] M0S0[7:4] M0S0[3:0] M0S1[11:8] M0S1[7:4] M0S1[3:0]

Lane 1 M0S2[11:8] M0S2[7:4] M0S2[3:0] M0S3[11:8] M0S3[7:4] M0S3[3:0]

Lane 2 M1S0[11:8] M1S0[7:4] M1S0[3:0] M1S1[11:8] M1S1[7:4] M1S1[3:0]

Lane 3 M1S2[11:8] M1S2[7:4] M1S2[3:0] M1S3[11:8] M1S3[7:4] M1S3[3:0]

Mode 12 (L = 8, M = 2, S = 8, NP = 12,

N = 12)

Lane 0 M0S0[11:8] M0S0[7:4] M0S0[3:0] M0S1[11:8] M0S1[7:4] M0S1[3:0]

Lane 1 M0S2[11:8] M0S2[7:4] M0S2[3:0] M0S3[11:8] M0S3[7:4] M0S3[3:0]

Lane 2 M0S4[11:8] M0S4[7:4] M0S4[3:0] M0S5[11:8] M0S5[7:4] M0S5[3:0]

Lane 3 M0S6[11:8] M0S6[7:4] M0S6[3:0] M0S7[11:8] M0S7[7:4] M0S7[3:0]

Lane 4 M1S0[11:8] M1S0[7:4] M1S0[3:0] M1S1[11:8] M1S1[7:4] M1S1[3:0]

Lane 5 M1S2[11:8] M1S2[7:4] M1S2[3:0] M1S3[11:8] M1S3[7:4] M1S3[3:0]

Lane 6 M1S4[11:8] M1S4[7:4] M1S4[3:0] M1S5[11:8] M1S5[7:4] M1S5[3:0]

Lane 7 M1S6[11:8] M1S6[7:4] M1S6[3:0] M1S7[11:8] M1S7[7:4] M1S7[3:0]

1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.

Table 20. Data Structure per Lane for F = 4 JESD204B Operating Modes1

JESD204B Mode and

Parameters

Link Logical

Lane

Frame 0 Frame 1

Octet 0 Octet 1 Octet 2 Octet 3 Octet 0 Octet 1 Octet 2 Octet 3

Mode 0 (L = 1, M = 2, S = 1,

NP = 16, N = 16)

Lane 0 M0S0[15:8] M0S0[7:0] M1S0[15:8] M1S0[7:0] M0S1[15:8] M0S1[7:0] M1S1[15:8] M1S1[7:0]

Mode 1 (L = 2, M = 4, S = 1,

NP = 16, N = 16)

Lane 0 M0S0[15:8] M0S0[7:0] M1S0[15:8] M1S0[7:0] M0S1[15:8] M0S1[7:0] M1S1[15:8] M1S1[7:0]

Lane 1 M2S0[15:8] M2S0[7:0] M3S0[15:8] M3S0[7:0] M2S1[15:8] M2S1[7:0] M3S1[15:8] M3S1[7:0]

Mode 2 (L = 3, M = 6, S = 1,

NP = 16, N = 16)

Lane 0 M0S0[15:8] M0S0[7:0] M1S0[15:8] M1S0[7:0] M0S1[15:8] M0S1[7:0] M1S1[15:8] M1S1[7:0]

Lane 1 M2S0[15:8] M2S0[7:0] M3S0[15:8] M3S0[7:0] M2S1[15:8] M2S1[7:0] M3S1[15:8] M3S1[7:0]

Lane 2 M4S0[15:8] M4S0[7:0] M5S0[15:8] M5S0[7:0] M4S1[15:8] M4S1[7:0] M5S1[15:8] M5S1[7:0]

1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.

Table 21. Data Structure per Lane for F = 8 JESD204B Operating Modes1

JESD204B Mode and

Parameters

Link Logical

Lane

Frame 0

Octet 0 Octet 1 Octet 2 Octet 3 Octet 4 Octet 5 Octet 6 Octet 7

Mode 7 (L = 1, M = 4, S = 1,

NP = 16, N = 16)

Lane 0 M0S0[15:8] M0S0[7:0] M1S0[15:8] M1S0[7:0] M2S0[15:8] M2S0[7:0] M3S0[15:8] M3S0[7:0]

1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.

Data Sheet AD9174

Rev. B | Page 37 of 165

PHYSICAL LAYER

The physical layer of the JESD204B interface, hereafter referred

to as the deserializer, has eight identical channels. Each channel

consists of the termination, an equalizer, a clock and data recovery

(CDR) circuit, and the 1:40 demux function (see Figure 53).

EQUALIZER CDR 1:40

DESERIALIZER

FROM SERDES PLL

SPI

ONTROL

TERMINATIONSERDINx±

16794-015

Figure 53. Deserializer Block Diagram

JESD204B data is input to the AD9174 via the SERDINx±

differential input pins, per the JESD204B specification.

Interface Power-Up and Input Termination

Before using the JESD204B interface, it must be powered up by

setting Register 0x200, Bit 0 = 0. In addition, each physical lane

(PHY) that is not being used (SERDINx±) must be powered

down. To do so, set the corresponding Bit x for Physical Lane x

in Register 0x201 to 0 if the physical lane is being used, and to 1

if it is not being used.

The AD9174 autocalibrates the input termination to 100 Ω at

dc. This calibration routine is performed automatically when

the JESD204B interface blocks are configured and does not

require any additional SPI register writes.

Receiver Eye Mask

The AD9174 is compatible with the JESD204B specification

regarding the receiver eye mask and is capable of capturing data

that complies with the mask in Figure 54. Figure 54 shows the

receiver eye normalized to the data rate interval. The AD9174

also supports an increased insertion loss limit, as defined in the

Equalization section.

525

–55

–525

AMPLITUDE (mV)

01.000.35 0.5 0.65

TIME (UI)

RECEIVER EYE MASK

16794-016

Figure 54. Receiver Eye Mask

Clock Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks

can be derived from the following equations:

Data Rate = DAC Rate/Total Interpolation

Lane Rate = (M/L) × NP × (10/8) × Data Rate

Byte Rate = Lane Rate/10

This relationship comes from 8-bit/10-bit encoding, where each

byte is represented by 10 bits.

PCLK Rate = Byte Rate/4 = Lane Rate/40

The processing clock is used for a quad-byte decoder.

Frame Rate = Byte Rate/F

where F is defined as octets per frame per lane.

PCLK Factor = Frame Rate/PCLK Rate = 4/F

where:

M is the JESD204B parameter for converters per link, which is

the effective number of converters as seen by the JESD204B

interface (not necessarily equal to the number of DAC cores).

L is the JESD204B parameter for lanes per link.

F is the JESD204B parameter for octets per frame per lane.

NP is the JESD204B parameter for the total number of bits

per sample.

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES PLL uses integer N techniques to

achieve clock synthesis. The entire SERDES PLL is integrated

on chip, including the VCO and the loop filter. The SERDES

PLL is capable of providing quadrature clocks to allow a wide

range of data rates (3 Gbps to 15.4 Gbps) with no gaps. These

clocks are the input to the CDR block that is described in the

Clock and Data Recovery section.

AD9174 Data Sheet

Rev. B | Page 38 of 165

DAC PLL CLOCK

÷4 PCLK

GENERATOR CDR HALF

RATE CLOCKS

SERDES PLL

WITH INTERNAL VCO

LANE RATES

3Gbps TO 15.4Gbps

JESD204B MODE (REGISTER 0x110, BITS[4:0])

DATAPATH INTERPOLATION (REGISTER 0x111, BITS[7:4])

CHANNEL INTERPOLATION (REGISTER 0x111, BITS[3:0])

DIRECT DAC CLOC

16794-017

Figure 55. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block

The reference clock to the SERDES PLL is always running at a

frequency, fREF, that is equal to 1/40 of the lane rate (PCLK rate).

For more information about the SERDES circuitry setup and

relevant register writes, see the Start-Up Sequence section. The

SERDES PLL block automatically tunes to the appropriate divider

range for the lane rate based on the SERDES mode being used. It

takes the DAC clock generated by either the DAC PLL, if in use, or

from the direct clock being sourced at the CLKIN± pins, divides

the DAC clock frequency by 4, and uses the JESD204B parameters

corresponding to the mode and interpolation values programmed

in Register 0x110 and Register 0x111 to determine the proper

dividers for generating the PCLK frequency (lane rate ÷ 40), as

shown in Figure 55.

Confirm that the SERDES PLL is working by reading

has locked.

Clock and Data Recovery

The deserializer is equipped with a CDR circuit. Instead of

recovering the clock from the JESD204B serial lanes, the CDR

recovers the clocks from the SERDES PLL. The SERDES PLL in

turn uses the PCLK as its reference, where the PCLK is derived

from the DAC clock. It is thus critical to lock the JESD204B

transmitter clock to the device clock of the AD9174.

The CDR circuit synchronizes the phase used to sample the data on

each serial lane independently. This independent phase adjustment

per serial interface ensures accurate data sampling and eases the

implementation of multiple serial interfaces on a PCB.

Power-Down Unused PHYs

Any unused physical and enabled lanes consume extra power

unnecessarily. Each lane that is not being used (SERDINx±) must

be powered off by writing a 1 to the corresponding bit of PHY_PD

(Register 0x201).

Equalization

To compensate for signal integrity distortions for each PHY

channel due to PCB trace length and impedance, the AD9174

employs an easy to use, low power equalizer on each JESD204B

channel. The AD9174 equalizers operating at the maximum lane

rate of 15.4 Gbps can compensate for up to 16 dB of insertion loss.

This equalizer performance is shown in Figure 56 for 15.4 Gbps,

near the maximum baud rate for the AD9174. The channel must

also meet the insertion loss deviation (also known as spectral

ripple) requirement of the JESD204B specification (less than

1.5 dB from 50 MHz to 0.75 times the baud rate).

INSERTION LOSS (dB)

FREQUENCY (GHz)

7.5 11.25

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

–22

–24

3.75

EXAMPLE OF JESD204B

COMPLIANT CHANNEL

MINIMUM

ALLOWED CHANNEL

LOSS (JESD204B SPEC)

EXAMPLE OF AD9174

COMPATIBLE CHANNEL

MINIMUM ALLOWED

CHANNEL LOSS

AD9174

16794-018

Figure 56. Insertion Loss Allowed

To ensure the AD9174 compensates for the amount of insertion

loss in the system, set the equalizer block appropriately. Table 22

shows the settings for the equalizer boost, equalizer gain, and

feedback controls, depending on the level of insertion loss in

the system. The equalizer boost setting is programmed for each

PHY lane (2-bit control for each) being used in Register 0x240

and Register 0x241. Similarly, the equalizer gain settings are

programmed for each PHY lane (2-bit control for each) used in

programmed per PHY lane (5-bit control for each, one control

per register) in Register 0x244 to Register 0x24B.

Table 22. Equalizer Register Control Settings per PHY Control

Insertion Loss ≤11 dB >11 dB

Equalizer Boost 0x02 0x03

Equalizer Gain 0x01 0x03

Feedback 0x1F 0x1F

Data Sheet AD9174

Rev. B | Page 39 of 165

Figure 57 and Figure 58 are provided as points of reference for

hardware designers and show the insertion loss for various

lengths of well laid out stripline and microstrip transmission

lines, respectively. See the Hardware Considerations section for

specific layout recommendations for the JESD204B channel.

–40

–35

–30

–25

–20

–15

–10

–5

012345678910

ATTENUATION (dB)

FREQUENCY (GHz)

STRI PL I NE = 6"

STRI PL I NE = 10"

STRI PL I NE = 15"

STRI PL I NE = 20"

STRI PL I NE = 25"

STRI PL I NE = 30"

16794-019

Figure 57. Insertion Loss of 50 Ω Striplines on FR4

–40

–35

–30

–25

–20

–15

–10

–5

012345678910

TTENU

TION (dB)

FREQ UENC Y ( GHz)

6" MICROSTRIP

10" MICRO ST RIP

15" MICRO ST RIP

20" MICRO ST RIP

25" MICRO ST RIP

30" MICRO ST RIP

16794-020

Figure 58. Insertion Loss of 50 Ω Microstrips on FR4

DATA LINK LAYER

The data link layer of the AD9174 JESD204B interface accepts

the deserialized data from the PHYs and deframes and descrambles

the data so that data octets are presented to the transport layer

to be recombined into the original data samples ahead of the

DAC core. The architecture of the data link layer is shown in

Figure 59. The data link layer consists of a synchronization

FIFO for each lane, a crossbar switch, a deframer, and a

descrambler.

The AD9174 can be set up to receive data from either a single-

link or dual-link high speed JESD204B serial data interface.

When operating in dual-link mode, the data link layer abstracts

the interface to appear as two independent JESD204B links to

the user, each occupying a maximum of four lanes. In either

mode, all eight lanes of the JESD204B interface handle link

layer communications such as code group synchronization

(CGS), frame alignment, and frame synchronization.

The AD9174 decodes 8-bit/10-bit control characters, which

mark the edges of the frame and help maintain alignment

between serial lanes. Each AD9174 serial interface link can issue

a synchronization request by setting its SYNCOUTx± signals

low. The synchronization protocol follows Section 4.9 of the

JESD204B standard. When a stream of four consecutive /K/

symbols is received, the AD9174 deactivates the synchronization

request by setting the SYNCOUTx± signals high at the next

internal LMFC rising edge. Then, the AD9174 waits for the

transmitter to issue an initial lane alignment sequence (ILAS).

During the ILAS, all lanes are aligned using the /A/ to /R/

character transition as described in the JESD204B Serial Link

Establishment section. Elastic buffers hold early arriving lane

data until the alignment character of the latest lane arrives. At

this point, the buffers for all lanes are released and all lanes are

aligned (see Figure 60).

LANE 0 DESERIALIZED

ND DESCRAM BLED DA T

LANE 0 DATA CL OCK SERDIN0±

FIFO

SERDIN7±

FIFO

CROSS-

BAR

SWITCH

LANE 7 DESERIALIZED

ND DESCRAM BLED DA T

LANE 7 DATA CL OCK

PCLK

DATA LI NK LAYER

SPI CO NTROL

SYSREF±

SYNCOUTx±

DESCRAMBLE

8-BI T/1 0-BIT DE CODE

SYSTEM CLOCK

PHASE DETECT

LANE 0 OCTETS

LANE 7 OCTETS

QUAD-BYTE

DEFRAMER

QBD

16794-021

Figure 59. Data Link Layer Block Diagram

AD9174 Data Sheet

Rev. B | Page 40 of 165

L RECEIVE LANES

(LATEST ARRIVAL)

L ALIGNED

RECEIVE LANES

0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL

K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER

A = K28.3 LANE ALIGNMENT SYMBOL

F = K28.7 FRAME ALIGNMENT SYMBOL

R = K28.0 START OF MULTIFRAME

Q = K28.4 START OF LINK CONFIGURATION DATA

C = JESD204x LINK CONFIGURATION PARAMETERS

D = Dx.y DATA SYMBOL

4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL

L RECEIVE LANES

(EARLIEST ARRIVAL)

KKKKKKKRDD

KKKRDD DDARQC C

DDARQC C

DDARDD

KKKKKKKRDD DDARQC C DDARDD

16794-022

Figure 60. Lane Alignment During ILAS

JESD204B Serial Link Establishment

A brief summary of the high speed serial link establishment

process for Subclass 1 is provided. See Section 5.3.3 of the

JESD204B specification document for complete details.

Step 1—Code Group Synchronization

Each receiver must locate /K/ (K28.5) characters in its input

data stream. After four consecutive /K/ characters are detected

on all link lanes, the receiver block deasserts the SYNCOUTx±

signals to the transmitter block at the receiver LMFC edge.

The transmitter captures the change in the SYNCOUTx±

signals and at a future transmitter LMFC rising edge, starts

the ILAS.

Step 2—Initial Lane Alignment Sequence

The main purposes of this phase are to align all the lanes of the

link and to verify the parameters of the link.

Before the link is established, write each of the link parameters

to the receiver device to designate how data is sent to the

receiver block.

The ILAS consists of four or more multiframes. The last character

of each multiframe is a multiframe alignment character, /A/.

The first, third, and fourth multiframes are populated with

predetermined data values. Section 8.2 of the JESD204B

specifications document describes the data ramp that is expected

during the ILAS. The deframer uses the final /A/ of each lane to

align the ends of the multiframes within the receiver. The second

multiframe contains an /R/ (K.28.0), /Q/ (K.28.4), and then data

corresponding to the link parameters. Additional multiframes

can be added to the ILAS if needed by the receiver. By default,

the AD9174 uses four multiframes in the ILAS (this can be

changed in Register 0x478). If using Subclass 1, exactly four

multiframes must be used.

After the last /A/ character of the last ILAS, multiframe data

begins streaming. The receiver adjusts the position of the /A/

character such that it aligns with the internal LMFC of the

receiver at this point.

Step 3—Data Streaming

In this phase, data is streamed from the transmitter block to the

receiver block.

Optionally, data can be scrambled. Scrambling does not start

until the first octet following the ILAS.

The receiver block processes and monitors the data it receives

for errors, including the following:

 Bad running disparity (8-bit/10-bit error)

 Not in table (8-bit/10-bit error)

 Unexpected control character

 Bad ILAS

 Interlane skew error (through character replacement)

If any of these errors exist, they are reported back to the

transmitter in one of the following ways (see the JESD204B

Error Monitoring section for details):

 SYNCOUTx± signal assertion: resynchronization

(SYNCOUTx± signals pulled low) is requested at each

error for the last two errors. For the first three errors, an

optional resynchronization request can be asserted when

the error counter reaches a set error threshold.

 For the first three errors, each multiframe with an error in

it causes a small pulse on the respective SYNCOUTx± pins.

 Errors can optionally trigger an interrupt request (IRQ)

event, which can be sent to the transmitter.

For more information about the various test modes for verifying

the link integrity, see the JESD204B Test Modes section.

Data Sheet AD9174

Rev. B | Page 41 of 165

Lane First In/First Out (FIFO)

The FIFOs in front of the crossbar switch and deframer synchro-

nize the samples sent on the high speed serial data interface

with the deframer clock by adjusting the phase of the incoming

data. The FIFO absorbs timing variations between the data

source and the deframer, which allows up to two PCLK cycles of

drift from the transmitter. The FIFO_STATUS_REG_0 register

and FIFO_STATUS_REG_1 register (Register 0x30C and

whether the FIFOs are full or empty.

Lane FIFO IRQ

An aggregate lane FIFO error bit is also available as an IRQ

event. Use Register 0x020, Bit 2 to enable the lane FIFO error

bit, and then use Register 0x024, Bit 2 to read back its status and

reset the IRQ signal. See the Interrupt Request Operation

section for more information.

Crossbar Switch

physical lanes (SERDINx±) to logical lanes used by the SERDES

deframers.

Table 23. Crossbar Registers

Address Bits Logical Lane

0x308 [2:0] SRC_LANE0

0x308 [5:3] SRC_LANE1

0x309 [2:0] SRC_LANE2

0x309 [5:3] SRC_LANE3

0x30A [2:0] SRC_LANE4

0x30A [5:3] SRC_LANE5

0x30B [2:0] SRC_LANE6

0x30B [5:3] SRC_LANE7

Write each SRC_LANEy with the number (x) of the desired

physical lane (SERDINx±) from which to obtain data. By

default, all logical lanes use the corresponding physical lane as

their data source. For example, by default, SRC_LANE0 = 0.

Therefore, Logical Lane 0 obtains data from Physical Lane 0

(SERDIN0±). To use SERDIN4± as the source for Logical Lane 0

instead, the user must write SRC_LANE0 = 4.

Lane Inversion

can be used to ease routing of the SERDINx± signals. For each

Logical Lane x, set Bit x of Register 0x334 to 1 to invert it.

Deframer

The AD9174 consists of two quad-byte deframers (QBDs) paged

by the LINK_PAGE control in Register 0x300, Bit 2. The deframer

accepts the 8-bit/10-bit encoded data from the deserializer (via

the crossbar switch), decodes it, and descrambles it into JESD204B

frames before passing it to the transport layer to be converted to

DAC samples. The deframer processes four symbols (or octets)

per processing clock (PCLK) cycle.

The deframer uses the JESD204B parameters that the user has

programmed into the register map to identify how the data is

packed, and unpacks it. The JESD204B parameters are described in

detail in the Transport Layer section. Many of the parameters

are also needed in the transport layer to convert JESD204B

frames into samples.

Descrambler

The AD9174 provides an optional descrambler block using a self

synchronous descrambler with the following polynomial:

1 + x14 + x15.

Enabling data scrambling reduces spectral peaks that are

produced when the same data octets repeat from frame to

frame. It also makes the spectrum data independent so that

possible frequency selective effects on the electrical interface do

not cause data dependent errors. Descrambling of the data is

enabled by setting the SCR bit (Register 0x453, Bit 7) to 1.

SYNCING LMFC SIGNALS

The AD9174 requires a synchronization (sync) to align the

LMFC and other internal clocks before the SERDES links are

brought online. The synchronization is a one-shot sync, where

the synchronization process begins on the next edge of the

alignment signal following the assertion of the

SYSREF_MODE_ONESHOT control in Register 0x03A, Bit 1.

In Subclass 1, the SYSREF± rising edge acts as the alignment

edge. In Subclass 0, an internal processing clock acts as the

alignment edge. When a sync has completed, the

SYNC_ROTATION_DONE (Register 0x03A, Bit 4) bit is

asserted and remains asserted until another sync is requested.

After a synchronization occurs, the JESD204B link can be

enabled. In Subclass 1, the latency of the JESD204B system is

deterministic and allows synchronization across multiple

devices, if desired.

SYSREF± Signal

The SYSREF± signal is a differential source synchronous input

that synchronizes the LMFC signals in both the transmitter and

receiver in a JESD204B Subclass 1 system to achieve deterministic

latency.

The SYSREF± signal is a rising edge sensitive signal that is

sampled by the device clock rising edge. It is best practice that

the device clock and SYSREF± signals be generated by the same

source, such as the HMC7044 clock generator, so that the phase

alignment between the signals is fixed. When designing for

optimum deterministic latency operation, consider the timing

distribution skew of the SYSREF± signal in a multipoint link

system (multichip).

AD9174 Data Sheet

Rev. B | Page 42 of 165

The AD9174 supports a periodic SYSREF± signal. The periodicity

can be continuous, strobed, or gapped periodic. The SYSREF±

signal can be dc-coupled with a common-mode voltage of 0.6 V

to 2.2 V and differential swing of 200 mV p-p to 1 V p-p. When

dc-coupled, a small amount of common-mode current (up to

0.3 mA) is drawn from the SYSREF± pins. See Figure 61 and

Figure 62 for the SYSREF± internal circuit for dc-coupled and a

c-coupled configurations. Ensure that the SYSREF_INPUTMODE

bit (Register 0x084, Bit 6) is set to 1, dc-coupled, to prevent

overstress on the SYSREF± receiver pins.

10.3kΩ

240F

104Ω

SYSREF–

SYSREF+

104Ω

100Ω

240F

10.3kΩ130kΩ

130kΩ

VCM

16794-138

Figure 61. DC-Coupled SYSREF± Receiver Circuitry

10.3kΩ

240F

104Ω

SYSREF–

YSREF+

104Ω

100Ω

240F

10.3kΩ130kΩ

130kΩ

VCM

16794-139

Figure 62. AC-Coupled SYSREF± Receiver Circuitry

To avoid this common-mode current draw, the SYSREF± receiver

can be ac-coupled using a 50% duty cycle periodic SYSREF±

signal with ac coupling capacitors. If ac-coupled, the ac coupling

capacitors combine with the resistors shown in Figure 62 to

make a high-pass filter with an RC time constant of τ = RC.

Select C such that τ > 4/SYSREF± frequency. In addition, the

edge rate must be sufficiently fast to allow SYSREF± sampling

clocks to correctly sample the rising SYSREF± edge before the

next sample clock.

When ac coupling the SYSREF± inputs, ensure that the

SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0,

ac-coupled, to enable the internal receiver biasing circuitry and

prevent overstress on the SYSREF± receiver pins. AC coupling

allows a differential voltage swing from 200 mV to 1 V on the

SYSREF± pins.

SYSREF± Sampling

The SYSREF± signal is sampled by a divide by 4 version of the

DAC clock. Thus, the minimum pulse width of the SYSREF±

signal must exceed 4 DAC clock periods to ensure accurate

sampling. The delay between the SYSREF± and DAC clock

input signal does not need to be timing constrained.

By default, the first SYSREF± rising edge at the SYSREF± inputs

that is detected after asserting the SYSREF_MODE_ONESHOT

bit (Register 0x03A, Bit 1) begins the synchronization and aligns

the internal LMFC signal with the sampled SYSREF± edge.

captured SYSREF± edges are ignored after the SYSREF_MODE_

ONESHOT bit is asserted before the synchronization takes place.

For example, if SYSREF_COUNT is set to 3, the AD9174 does

not sync after the SYSREF_MODE_ONESHOT bit is asserted

until the arrival of the 4th SYSREF± edge.

SYSREF± Jitter IRQ

In Subclass 1, after the one-shot synchronization occurs, the

SYSREF± signal is monitored to ensure that the subsequent

SYSREF± edges do not deviate from the internal LMFC clock

by more than a target amount.

the error window allowed, in DAC clock units. If a SYSREF±

edge varies from the internal LMFC clock by more than the

number of DAC clock units set in SYSREF_ERR_WINDOW,

the IRQ_SYSREF_JITTER is asserted.

Table 24. SYSREF± Jitter Window Tolerance

SYSREF± Jitter Window

Tolerance (DAC Clock Cycles)

SYSREF_ERR_WINDOW

(Register 0x039, Bits[5:0])1

±½ 0x00

±4 0x04

±8 0x08

±12 0x0C

±16 0x10

±20 0x14

+24 0x18

±28 0x1C

1 The two least significant digits are ignored because the SYSREF± signal is

sampled with a divide by 4 version of the DAC clock. As a result, the jitter

window is set by this divide by 4 clock rather than the DAC clock. It is

recommended that at least a four-DAC clock SYSREF± jitter window be

chosen.

The IRQ_SYSREF_JITTER can be configured as described

in the Interrupt Request Operation section to indicate the

SYSREF± signal has varied, and to request the SPI sequence for

a sync be performed again.

Sync Procedure

The procedure for enabling the sync is as follows:

1. Set up the DAC and the SERDES PLL, and enable the CDR

(see the Start-Up Sequence section).

2. Set Register 0x03B to 0xF1 to enable the synchronization

circuitry. If using the soft on/off feature, set Register 0x03B

to 0xF3 to ramp the datapath data before and after the

synchronization.

Data Sheet AD9174

Rev. B | Page 43 of 165

3. If Subclass 1, configure the SYSREF± settings as follows:

a. Set Register 0x039 (SYSREF± jitter window). See Table 24

for settings.

b. Set Register 0x036 = SYSREF_COUNT. Leave the

setting as 0 to bypass.

4. Perform a one-shot sync.

a. Set Register 0x03A = 0x00. Clear one-shot mode if

already enabled.

b. Set Register 0x03A = 0x02. Enable one-shot sync

mode.

5. If Subclass 1, send a SYSREF± edge. If pulse counting,

multiple SYSREF± edges are required. Sending SYSREF±

edges triggers the synchronization.

6. Read back the SYNC_ROTATION_DONE bit

(Register 0x03A, Bit 4) to confirm the rotation occurred.

Resynchronizing LMFC Signals

If desired, the sync procedure can be repeated to realign the

LMFC clock to the reference signal by repeating Step 2 to

Step 6, described in the Sync Procedure section. When the

one-shot sync is armed (writing Register 0x03A = 0x02), the

SYNCOUTx± signals deassert to drop the JESD204B links and

reassert after the rotation completes.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout. Data traversing from one clock domain to a

different clock domain can lead to ambiguous delays in the

JESD204B link. These ambiguities lead to nonrepeatable

latencies across the link from power cycle to power cycle with

each new link establishment. Section 6 of the JESD204B

specification addresses the issue of deterministic latency with

mechanisms defined as Subclass 1 and Subclass 2.

The AD9174 supports JESD204B Subclass 0 and Subclass 1

operation, but not Subclass 2. Write the subclass to

Subclass 0

Subclass 0 mode provides deterministic latency to within

several PCLK cycles. It does not require any signal on the

SYSREF± pins, which can be left disconnected.

Subclass 0 still requires that all lanes arrive within the same LMFC

cycle and the dual DACs must be synchronized to each other.

Subclass 1

This mode gives deterministic latency and allows the link to be

synchronized to within a few DAC clock cycles. Across the full

operating range, for both supply and temperature, it is within

±2.5 DAC clock periods for a 6 GHz DAC clock rate or ±4 DAC

clock periods for a 12.6 GHz DAC clock rate. If both supply and

temperature stability are maintained, the link can be

synchronized to within ±1.5 DAC clock periods for a 6 GHz

DAC clock rate or ±2.5 DAC clock periods for a 12.6 GHz DAC

clock rate. Achieving this latency requires an external, low jitter

SYSREF± signal that is accurately phase aligned to the DAC clock.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system, as follows:

 The SYSREF± signal distribution skew within the system

must be less than the desired uncertainty.

 The total latency variation across all lanes, links, and

devices must be ≤12 PCLK periods, which includes both

variable delays and the variation in fixed delays from lane

to lane, link to link, and device to device in the system.

ILAS

FIXED DELAY

VARIABLE

DELAY

POWER CYCLE

VARIANCE

DATA

LMFC

LIGNED DAT

AT Rx OUTPUT

DATA AT

Tx INPUT DATA

DSP

CHANNEL

LOGIC DEVICE

(JESD204B Tx) JESD204B Rx

DAC

LINK DELAY = DELA

FIXED

+ DELA

VARIABLE

16794-023

Figure 63. JESD204B Link Delay = Fixed Delay + Variable Delay

AD9174 Data Sheet

Rev. B | Page 44 of 165

Link Delay

The link delay of a JESD204B system is the sum of the fixed and

variable delays from the transmitter, channel, and receiver as

shown in Figure 63.

For proper functioning, all lanes on a link must be read during

the same LMFC period. Section 6.1 of the JESD204B specifica-

tion states that the LMFC period must be larger than the maximum

link delay. For the AD9174, this is not necessarily the case. Instead,

the AD9174 use a local LMFC for each link (LMFCRx) that can

be delayed from the SYSREF± aligned LMFC. Because the

LMFC is periodic, this delay can account for any amount of

fixed delay. As a result, the LMFC period must only be larger

than the variation in the link delays, and the AD9174 can achieve

proper performance with a smaller total latency. Figure 64 and

Figure 65 show a case where the link delay is greater than an LMFC

period. The link delay can be accommodated by delaying LMFCRx.

ILAS DATA

POWER CYCLE

VARIANCE

LMFC

LIGNED DAT

EARLY ARRIVING

LMFC REFERENCE

LATE ARRIVING

LMFC REFERENCE

16794-024

Figure 64. Link Delay > LMFC Period Example

ILAS DATA

FRAME CLOCK

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

LMFC

LMFC_DELAY LMFC REFERENCE FOR ALL POWER CYCLES

16794-025

Figure 65. LMFC_DELAY_x to Compensate for Link Delay > LMFC

The method to select the LMFCDel (Register 0x304) and

LMFCVar (Register 0x306) variables is described in the Link

Delay Setup Example, with Known Delays section and the Link

Delay Setup Example, Without Known Delay section. The setting

for LMFCDel must not equal or exceed the number of PCLK

cycles per LMFC period in the current mode. Similarly, LMFCVar

must not exceed the number of PCLK cycles per LMFC period in

the current mode or be set to <12 (whichever value is smaller).

Setting LMFCDel appropriately ensures that all the corresponding

data samples arrive in the same LMFC period. Then, LMFCVar

is written into the receive buffer delay (RBD) to absorb all link

delay variation. This write ensures that all data samples arrived

before reading. By setting these to fixed values across runs and

devices, deterministic latency is achieved.

The RBD described in the JESD204B specification takes values

from one frame clock cycle to /K/ frame clock cycles, and the

RBD of the AD9174 takes values from 0 PCLK cycle to 12 PCLK

cycles. As a result, up to 12 PCLK cycles of total delay variation

can be absorbed. LMFCVar and LMFCDel are both in PCLK

cycles. The PCLK factor, or number of frame clock cycles per

PCLK cycle, is equal to 4/f. For more information on this

relationship, see the Clock Relationships section.

Two examples follow that show how to determine LMFCVar

and LMFCDel. After they are calculated, write LMFCDel into

to Register 0x306 for all devices in the system.

Link Delay Setup Example, with Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel.

The example shown in Figure 66 is demonstrated in the following

steps. This example is in Subclass 1 to achieve deterministic latency,

and the example uses the case for F = 2. Therefore, the number of

PCLK cycles per multiframe = 16. Because PCBFixed << PCLK

Period, PCBFixed is negligible in this example and not included

in the calculations.

1. Find the receiver delays using Table 6.

RxFixed = 13 PCLK cycles

RxVar = 2 PCLK cycles

2. Find the transmitter delays. The equivalent table in the

example JESD204B core (implemented on a GTH or GTX

gigabit transceiver on a Virtex-6 FPGA) states that the

delay is 56 ± 2 byte clock cycles.

3. Because the PCLK rate = ByteRate/4 as described in the

Clock Relationships section, the transmitter delays in

PCLK cycles are calculated as follows:

TxFixed = 54/4 = 13.5 PCLK cycles

TxVar = 4/4 = 1 PCLK cycle

4. Calculate MinDelayLane as follows:

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

= floor(13 + 13.5 + 0)

= floor(26.5)

MinDelayLane = 26

5. Calculate MaxDelayLane as follows:

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

= ceiling(13 + 2 + 13.5 + 1 + 0)

= ceiling(29.5)

MaxDelayLane = 30

6. Calculate LMFCVar as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (30 + 1) − (26 − 1) = 31 − 25

LMFCVar = 6 PCLK cycles

7. Calculate LMFCDel as follows:

LMFCDel = (MinDelay − 1) % (PCLKsperMF)

= ((26 − 1)) % 16

= 25 % 16

LMFCDel = 9 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the

system. Write LMFCVar to Register 0x306 for all devices in

the system.

Data Sheet AD9174

Rev. B | Page 45 of 165

FRAME CLOCK

LMFC

PCLK

DATADATA AT Tx FRAMER ILAS

LMFC

TOTAL FIXED LATENCY = 30 PCLK CYCLES

LMFC DELAY = 26 FRAME CLOCK CYCLES

PCB FIXED

DELAY

DATA

ALIGNED LANE DATA

AT Rx DEFRAMER OUTPUT ILAS

TOTAL VARIABLE

LATENCY = 4

PCLK CYCLES

Tx VAR

DELAY

Rx VAR

DELAY

16794-026

Figure 66. LMFC Delay Calculation Example

Link Delay Setup Example, Without Known Delay

If the system delays are not known, the AD9174 can read back

the link latency between LMFCRX for each link (with the

LMFCDel setting subtracted out) and the SYSREF± aligned

LMFC. This information is then used to calculate LMFCVar

and LMFCDel.

Figure 68 shows how DYN_LINK_LATENCY_0 (Register 0x302)

provides a readback showing the delay (in PCLK cycles) between

LMFCRX minus the LMFC_DELAY_x (fixed delay) setting set in

the SPI at that time and the transition from the ILAS to the first

data sample. By repeatedly power cycling and taking this measure-

ment, the minimum and maximum delays across power cycles

can be determined and used to calculate LMFCVar and

LMFCDel.

In Figure 68, for Link A, Link B, and Link C, the system

containing the AD9174 (including the transmitter) is power

cycled and configured 20 times. The AD9174 is configured as

described in the Sync Procedure section. Because the purpose

of this exercise is to determine LMFCDel and LMFCVar, the

LMFCDel value is programmed to 0 and the DYN_LINK_

LATENCY_0 value is read from Register 0x302. The variation

in the link latency over the 20 runs is shown in Figure 68,

described as follows:

 Link A gives readbacks of 6, 7, 0, and 1. The set of recorded

delay values rolls over the edge of a multiframe at the

boundary of K/PCLK factor = 8. Add the number of PCLK

cycles per multiframe = 8 to the readback values of 0 and 1

because they rolled over the edge of the multiframe. Delay

values range from 6 to 9.

 Link B gives delay values from 5 to 7.

 Link C gives delay values from 4 to 7.

The example shown in Figure 68 is demonstrated in the following

steps. This example is in Subclass 1 to achieve deterministic

latency, and the example uses the case for F = 1. Therefore, the

number of PCLK cycles per multiframe = 8.

1. Calculate the minimum of all delay measurements across

all power cycles, links, and devices as follows:

MinDelay = min(all Delay values) = 4

2. Calculate the maximum of all delay measurements across

all power cycles, links, and devices as follows:

MaxDelay = max(all Delay values) = 9

3. Set LFMCVar to the maximum of 12 PCLK cycles. If

latency is required to be minimized for a given application,

calculate the total delay variation (with 2 PCLK cycles of

guard band on each end) across all power cycles, links, and

devices as follows:

LMFCVar = (MaxDelay + 2) − (MinDelay − 2)

= (9 + 2) − (4 − 2) = 11 − 2 = 9 PCLK cycles

4. Calculate the minimum delay in PCLK cycles (with

2 PCLK cycles of guard band) across all power cycles, links,

and devices as follows:

LMFCDel = (MinDelay – 2) % (PCLKsperMF)

= (4 − 2) % 8

= 2 % 8 = 2 PCLK cycles

5. Write LMFCDel to Register 0x304 for all devices in the system.

Write LMFCVar to Register 0x306 for all devices in the system.

AD9174 Data Sheet

Rev. B | Page 46 of 165

ILAS DATA

SYSREF±

ALIGNED DATA

LMFC

DYN_LINK_LATENCY_x

16794-027

Figure 67. DYN_LINK_LATENCY_x Illustration

0123456701234567

DYN_LINK_LATENCY_x

ALIGNED DATA (LINK A)

DETERMINISTICALLY

DELAYED DATA

LMFC

ALIGNED DATA (LINK B)

ALIGNED DATA (LINK C)

FRAME CLOCK

LMFC

PCLK

DATAILAS

LMFC_DELAY = 6

(FRAME CLOCK CYCLES)

LMFC_VAR = 7

(PCLK CYCLES)

16794-028

Figure 68. Multilink Synchronization Settings, Derived Method Example

DELAY

BUFFER 1

DELAY

BUFFER 0 F2S_0

F2S_1

DAC A_I0[15:0]

DAC A_Q0[15:0]

PCLK_1

LANE 0 OCTETS

LANE 7 OCTETS

PCLK_0

SPI CONTROL

LANE 3 OCTETS

LANE 4 OCTETS

DAC B_I0[15:0]

DAC B_Q0[15:0]

TRANSPORT LAYER

(QBD)

SPI CONTROL

PCLK_0

PCLK_1

FIFO

16794-029

Figure 69. Transport Layer Block Diagram

Data Sheet AD9174

Rev. B | Page 47 of 165

TRANSPORT LAYER

The transport layer receives the descrambled JESD204B frames

and converts them to DAC samples based on the programmed

JESD204B parameters shown in Table 25. The device parameters

are defined in Table 26.

Table 25. JESD204B Transport Layer Parameters

Parameter Description

F Number of octets per frame per lane: 1, 2, 3, 4 or 8.

K Number of frames per multiframe: K = 32.

L Number of lanes per converter device (per link), as

follows: 1, 2, 3, 4 or 8.

M Number of converters per device (per link), as follows:

For real data modes, M is the number of real data

converters (if total interpolation is 1×). For complex

data modes, M is the number of complex data

subchannels, I or Q.

S Number of samples per converter, per frame: 1, 2,

4 or 8.

Table 26. JESD204B Device Parameters

Parameter Description

CF Number of control words per device clock per link.

Not supported, must be 0.

CS Number of control bits per conversion sample. Not

supported, must be 0.

HD High density user data format. This parameter is

always set to 1.

N Converter resolution.

N' (or NP) Total number of bits per sample.

Certain combinations of these parameters are supported by the

AD9174. See Table 28 and Table 29 for a list of supported single-

link and dual-link modes, respectively. Table 28 and Table 29

lists the JESD204B parameters for each of the modes. Table 27 lists

JESD204B parameters that have fixed values.

Table 27. JESD204B Parameters with Fixed Values

Parameter Value

K 32

CF 0

HD 1

CS 0

Table 28. Single-Link JESD204B Operating Modes

Parameter

Single-Link JESD204B Modes

0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22

L (Lane Count) 1 2 3 2 4 1 2 1 4 4 8 8 8 4 4 8 8 4

M (Converter Count) 2 4 6 2 4 2 4 4 2 2 2 2 2 1 1 1 1 2

F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 3 1 2 1 2 3

S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 8 2 4 4 8 4

NP (Total Number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 12

N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 12

Table 29. Dual-Link JESD204B Operating Modes

Parameter

Dual-Link JESD204B Modes

0 1 2 3 4 5 6 7 8 9 18 19 22

L (Lane Count) 1 2 3 2 4 1 2 1 4 4 4 4 4

M (Converter Count) 2 4 6 2 4 2 4 4 2 2 1 1 2

F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 3

S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 4

NP (Total number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 12

N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 12

AD9174 Data Sheet

Rev. B | Page 48 of 165

Configuration Parameters

The AD9174 modes refer to the link configuration parameters

for L, K, M, N, NP, S, and F. Table 30 provides the description

and addresses for these settings.

Table 30. Configuration Parameters

JESD204B

Setting Description Address

L − 1 Number of lanes minus 1. Register 0x453,

Bits[4:0]

F − 1 Number of ((octets per frame) per

lane) minus 1.

Bits[7:0]

K − 1 Number of frames per multiframe

minus 1.

Bits[4:0]

M − 1 Number of converters minus 1. Register 0x456,

Bits[7:0]

N − 1 Converter bit resolution minus 1. Register 0x457,

Bits[4:0]

NP − 1 Bit packing per sample minus 1. Register 0x458,

Bits[4:0]

S − 1 Number of ((samples per

converter) per frame) minus 1.

Bits[4:0]

HD High density format. Set to 1. Register 0x45A,

Bit 7

DID Device ID. Match the device ID

sent by the transmitter.

Bits[7:0]

BID Bank ID. Match the bank ID sent by

the transmitter.

Bits[7:0]

LID0 Lane ID for Lane 0. Match the Lane

ID sent by the transmitter on

Logical Lane 0.

Bits[4:0]

JESDV JESD204x version. Match the

version sent by the transmitter

(0x0 = JESD204A, 0x1 = JESD204B).

Bits[7:5]

The AD9174 truncates the output of the main digital datapath

to the value of N bits for the selected mode, which is then sent

to the DAC core. It is possible to send the value of NP number

of bits worth of data with the lower NP − N LSBs padded as 0s,

or to send the full NP number of bits data across the SERDES

lanes. In either case, the lower NP − N LSBs are truncated prior

to the DAC core.

Data Flow Through the JESD204B Receiver

The link configuration parameters determine how the serial bits

on the JESD204B receiver interface are deframed and passed on

to the DACs as data samples.

Deskewing and Enabling Logical Lanes

After proper configuration, the logical lanes are automatically

deskewed. All logical lanes are enabled or not based on the

number of lanes for the mode setting chosen in Register 0x110,

Bits[4:0]. The physical lanes are all powered up by default. To

disable power to physical lanes that are not being used, set Bit x

in Register 0x201 to 1 to disable Physical Lane x, and keep it at 0

to enable it. The logical lanes must be enabled and deskewed on

a per link basis using the LINK_PAGE control (Register 0x300,

Bit 2). Set Bit x in Register 0x46C to 1 to deskew Link Logical

Lane x for the selected link page.

JESD204B TEST MODES

PRBS Testing

The JESD204B receiver on the AD9174 includes a PRBS pattern

checker on the back end of the PHY layer. The pattern checker

supports PRBS7, PRBS15, and PRBS31 data patterns, as defined

in the JESD204B specifications. The PRBS pattern can be sourced

from an external JESD204B transmitter, such a field-programmable

gate array (FPGA), or alternatively generated by the internal PRBS7

generator as described in the Internal PRBS7 Generator section.

This functionality allows testing of the bit error rate (BER) on

each physical lane of the AD9174 as well as the JESD204B PHY

as a whole. Low BER during PRBS testing confirms proper clocking

and clock synchronization, and confirms that the intercon-

nections (traces, connectors, and cabling) between the JESD204B

transmitter and receiver is of sufficient quality. Although the

PHY PRBS pattern checker does not require that the JESD204B

link be fully established, the JESD204B mode on the AD9174

must be configured so that the physical lanes are properly clocked

and are ready to receive PRBS data. The PRBS data must not be

8-bit/10-bit encoded. PRBS pattern verification can be performed

on multiple lanes at once or on one lane at a time. The error

count for each failing JESD204B lane is reported independently.

The process for enabling the PRBS checker on the AD9174 is as

follows:

1. Start sending a PRBS7, PRBS15, or PRBS31 looped pattern,

either from a JESD204B transmitter, or from the internal

PRBS7 generator of the AD9174.

2. Select the appropriate PRBS pattern to be received by

writing to Register 0x316, Bits[3:2], as shown in Table 31.

3. Enable the PHY test for all lanes being tested by writing to

PHY_TEST_EN (Register 0x315). Each bit of Register 0x315

enables the PRBS test for the corresponding lane. For example,

writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0.

Any running JESD204B link is interrupted at this point.

4. Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0

to 1 then back to 0 to reset the status registers to the default

value.

5. Set PHY_PRBS_TEST_THRESHOLD_xBITS (Register 0x319

to Register 0x317, Bits[23:0]) as desired.

6. Write a 0 and then a 1 to PHY_TEST_START (Register 0x316,

Bit 1). The rising edge of PHY_TEST_START starts the test.

a. In some cases, it may be necessary to repeat Step 4 at

this point. Toggle PHY_TEST_RESET (Register 0x316,

Bit 0) from 0 to 1, then back to 0.

7. Wait to accumulate the desired number of bits, or at least

500 ms.

8. Stop the test by writing PHY_TEST_START (Register 0x316,

Bit 1) = 0.

Data Sheet AD9174

Rev. B | Page 49 of 165

9. Read the PRBS test results from the PRBS status registers:

a. Each bit of PHY_PRBS_PASS (Register 0x31D)

corresponds to one SERDES lane (0 = fail, 1 = pass).

The default value following a reset is pass. To confirm

that the reported results are not a false positive, force a

fail condition on one or all of the lanes before running

a lengthy BER test. Either temporarily disable some or

all of the lanes for which the test was previously enabled

and confirm that the test fails, or select a PRBS pattern

of the incorrect type in Step 2 to observe failures on all

lanes. Then, reconfigure the test appropriately and run

the test to accumulate BER results.

b. The number of PRBS errors seen on each failing lane

can be read by writing the lane number to check (0 to

7) in PHY_SRC_ERR_CNT (Register 0x316, Bits[6:4])

and reading the PHY_PRBS_ERR_CNT_xBITS

(Register 0x31A to Register 0x31C). The maximum

error count is 224 − 1. If all bits of Register 0x31A to

the selected lane is exceeded.

Table 31. PHY PRBS Pattern Selection

PHY_PRBS_PAT_SEL Setting (Register 0x316,

Bits[3:2]) PRBS Pattern

0b00 (default) PRBS7

0b01 PRBS15

0b10 PRBS31

Internal PRBS7 Generator

The AD9174 integrates one internal PRBS7 generator that can

be used to test the JESD204B PHYs without an external PRBS

data input from a JESD204B transmitter. Although this approach

only confirms the portion of the PHY internal to the AD9174, it

does confirm that both the PRBS checker and internal clock

domains are running and are configured correctly. The internal

PRBS test is ideally followed by a more thorough, external PHY

PRBS test, in which case the pattern is sourced by a JESD204B

transmitter device.

The process for configuring the internal PRBS7 generator on

the AD9174 is as follows:

1. Set the EQ_BOOST_PHYx bits (Register 0x240, Bits[7:0]

and Register 0x241, Bit[7:0]) to 0.

2. Set SEL_IF_PARDATAINV_DES_RC_CH bits

(Register 0x234, Bits[7:0]) to 0 to make sure lanes not

inverted.

3. Enable the loop back test for all lanes being tested by

writing to EN_LBT_DES_RC_CH (Register 0x250). Each

bit of Register 0x250 enables the loop back test for the

corresponding lane. For example, writing a 1 to Bit 0 enables

the test for Physical Lane 0.

4. For halfrate, set EN_LBT_HALFRATE_DES_RC

(Register 0x251, Bit 1) to 1. Otherwise, set this bit to 0.

5. Toggle INIT_LBT_SYNC_DES_RC (Register 0x251, Bit 0)

from 0 to 1 then back to 0.

6. Refer to the PRBS Testing section for information on how

to configure the PRBS checker for a PRBS7 test.

Transport Layer Testing

The JESD204B receiver in the AD9174 supports the short

transport layer (STPL) test as described in the JESD204B

standard. Use this test to verify the data mapping between the

JESD204B transmitter and receiver. To perform this test, this

function must be implemented and enabled in the logic device.

Before running the test on the receiver side, the link must be

established and running without errors.

The STPL test ensures that each sample from each converter is

mapped appropriately according to the number of converters

(M) and the number of samples per converter (S). As specified

in the JESD204B standard, the converter manufacturer specifies

the test samples that are transmitted. Each sample must have a

unique value. For example, if M = 2 and S = 2, four unique

samples are transmitted repeatedly until the test is stopped. The

expected sample must be programmed into the device and the

expected sample is compared to the received sample one sample

at a time until all are tested. The process for performing this test

on the AD9174 is described as follows:

1. Synchronize and establish a JESD204B link between the

transmitter and the AD9174.

2. Enable the STPL test at the JESD204B transmitter.

Depending on JESD204B mode, there may be up to six

data streams per link, to feed up to three complex sub-

channels (M = 6), and each frame can contain up to eight

samples (S = 8).

3. Configure the SHORT_TPL_REF_SP_MSB bits

(Register 0x32E) and the SHORT_TPL_REF_SP_LSB bits

(Register 0x32D) to match one of the samples within a

single frame. For N = 12 modes, the integer value of the

expected sample is multiplied by 16 (binary, 4-bit shift

operation).

4. If testing a dual-link JESD204B, set SHORT_TPL_LINK_SEL

(Register 0x32F, Bit 7) to select whether Link 0 (DAC0

datapath(s)) or Link 1 (DAC1 datapath(s)) is tested.

5. Set SHORT_TPL_CHAN_SEL (Register 0x32C, Bits[3:2])

to select the channel.

6. Set SHORT_TPL_IQ_PATH_SEL (Register 0x32F, Bit 6) to

select the I or Q stream of the channel under test.

7. Set SHORT_TPL_SP_SEL (Register 0x32C, Bits[7:4]) to

select which sample within each frame is expected to have

the value indicated in Step 3.

8. Set SHORT_TPL_TEST_EN (Register 0x32C, Bit 0) to 1.

9. Set SHORT_TPL_TEST_RESET (Register 0x32C, Bit 1) to

1, then back to 0.

10. Wait for the desired time. The desired time is calculated as

1/(sample rate × BER). For example, given BER = 1 × 10−10

and a sample rate = 1 GSPS, the desired time = 10 sec.

11. Read the test result at SHORT_TPL_FAIL (Register 0x32F,

Bit 0).

AD9174 Data Sheet

Rev. B | Page 50 of 165

12. Choose another sample for the same or another M to

continue with the test, until all samples for both converters

from one frame are verified.

Repeated CGS and ILAS Test

As per Section 5.3.3.8.2 of the JESD204B specification, the

AD9174 can check that a constant stream of /K28.5/ characters

is being received, or that CGS followed by a constant stream of

ILAS is being received.

To run a repeated CGS test, send a constant stream of /K28.5/

characters to the AD9174 SERDES inputs. Next, set up the

device and enable the links. Ensure that the /K28.5/ characters are

being received by verifying that SYNCOUT± is deasserted and

that CGS has passed for all enabled link lanes by reading

To run the CGS followed by a repeated ILAS sequence test,

follow the procedure to set up the links, but before performing

the last write (enabling the links), enable the ILAS test mode by

writing a 1 to Register 0x477, Bit 7. Then, enable the links. When

the device recognizes four CGS characters on each lane, it

deasserts the SYNCOUTx±. At this point, the transmitter starts

sending a repeated ILAS sequence.

Read Register 0x473 to verify that the initial lane synchronization

has passed for all enabled link lanes.

JESD204B ERROR MONITORING

Disparity, Not in Table, and Unexpected Control (K)

Character Errors

As per Section 7.6 of the JESD204B specification, the AD9174 can

detect disparity errors, not in table (NIT) errors, and unexpected

control character errors, and can optionally issue a sync request

and reinitialize the link when errors occur.

Several other interpretations of the JESD204B specification are

noted in this section. When three NIT errors are injected to one

lane and QUAL_RDERR (Register 0x476, Bit 4) = 1, the readback

values of the bad disparity error (BDE) count register is 1.

Reporting of disparity errors that occur at the same character

position of an NIT error is disabled. No such disabling is per-

formed for the disparity errors in the characters after an NIT

error. Therefore, it is expected behavior that an NIT error may

result in a BDE error.

Checking Error Counts

The error count can be checked for disparity errors, NIT errors,

and unexpected control character errors. The error counts are

on a per lane and per error type basis. Each error type and lane

has a register dedicated to it. To check the error count, the

following steps must be performed:

1. Choose and enable which errors to monitor by selecting

them in Register 0x480, Bits[5:3] to Register 0x487, Bits[5:3].

Unexpected K (UEK) character, BDE, and NIT error

monitoring can be selected for each lane by writing a 1 to

the appropriate bit, as described in Table 62. These bits are

enabled by default.

2. The corresponding error counter reset bits are in

Write a 1 to the corresponding bit to reset that error

counter.

3. Registers 0x488, Bits[2:0] to Register 0x48F, Bits[2:0] have

the terminal count hold indicator for each error counter. If

this flag is enabled, when the terminal error count of 0xFF

is reached, the counter ceases counting and holds that

value until reset. Otherwise, it wraps to 0x00 and continues

counting. Select the desired behavior and program the

corresponding register bits per lane.

Check for Error Count Over Threshold

To check for the error count over threshold, follow these steps:

1. Define the error counter threshold. The error counter

threshold can be set to a user defined value in Register 0x47C,

or left to the default value of 0xFF. When the error threshold is

reached, an IRQ is generated, SYNCOUTx± is asserted, or

both, depending on the mask register settings. This one error

threshold is used for all three types of errors (UEK, NIT,

and BDE).

2. Set the SYNC_ASSERT_MASK bits. The SYNCOUTx±

assertion behavior is set in Register 0x47D, Bits[2:0]. By

default, when any error counter of any lane is equal to

the threshold, it asserts SYNCOUTx± (Register 0x47D,

Bits[2:0] = 0b111). When setting the SYNC_ASSERT_MASK

bits, LINK_PAGE (Register 0x300, Bit 2) must be set to 1.

3. Read the error count reached indicator. Each error counter

has a terminal count reached indicator, per lane. This indica-

tor is set to 1 when the terminal count of an error counter

for a particular lane is reached. These status bits are located

in Register 0x490, Bits[2:0] to Register 0x497, Bits[2:0]. Bit 3

can be read back to indicate whether a particular lane is

active.

Error Counter and IRQ Control

For error counter and IRQ control, follow these steps:

1. Enable the interrupts. Enable the JESD204B interrupts. The

interrupts for the UEK, NIT, and BDE error counters are in

monitor when bringing up the link, such as lane deskewing,

initial lane sync, good check sum, frame sync, code group sync

(Register 0x4B8, Bits[4:0], and configuration mismatch

(Register 0x4B9, Bit 0). These bits are off by default but can

be enabled by writing 0b1 to the corresponding bit.

2. Read the JESD204B interrupt status. The interrupt status

bits are in Register 0x4BA, Bits[7:0] and Register 0x4BB,

Bit 0, with the status bit position corresponding to the

enable bit position.

Data Sheet AD9174

Rev. B | Page 51 of 165

3. It is recommended to enable all interrupts that are planned

to be used prior to bringing up the JESD204B link. When

the link is up, the interrupts can be reset and then used to

monitor the link status.

Monitoring Errors via SYNCOUTx±

When one or more disparity, NIT, or unexpected control

character errors occur, the error is reported on the SYNCOUTx±

pin as per Section 7.6 of the JESD204B specification. The

JESD204B specification states that the SYNCOUTx± signal is

asserted for exactly two frame periods when an error occurs. For

the AD9174, the width of the SYNCOUTx± pulse can be

programmed to ½, 1, or 2 PCLK cycles. The settings to achieve a

SYNCOUTx± pulse of two frame clock cycles are given in Table 32.

Table 32. Setting SYNCOUTx± Error Pulse Duration

1 These register settings assert the SYNCOUTx± signal for two frame clock

cycle pulse widths.

Unexpected Control Character, NIT, Disparity IRQs

For UEK character, NIT, and disparity errors, error count over

the threshold events are available as IRQ events. Enable these events

by writing to Register 0x4B8, Bits[7:5]. The IRQ event status can

be read at Register 0x4BA, Bits[7:5] after the IRQs are enabled.

See the Error Counter and IRQ Control section for information

on resetting the IRQ. See the Interrupt Request Operation

section for more information on IRQs.

Errors Requiring Reinitializing

A link reinitialization automatically occurs when four invalid

disparity characters or four NIT characters are received as per

Section 7.1 of the JESD204B specification. When a link

reinitialization occurs, the resync request is at least five frames

and nine octets long.

The user can optionally reinitialize the link when the error

count for disparity errors, NIT errors, or UEK character errors

reaches a programmable error threshold. The process to enable

the reinitialization feature for certain error types is as follows:

1. Choose and enable which errors to monitor by selecting

them in Register 0x480, Bits[5:3] to Register 0x487,

Bits[5:3]. UEK, BDE, and NIT error monitoring can be

selected for each lane by writing a 1 to the appropriate bit,

as described in Table 33. These are enabled by default.

2. Write a 0 to the corresponding bit to Register 0x480,

Bits[2:0] to Register 0x487, Bits[2:0] to take counter out of

reset.

3. Enable the sync assertion mask for each type of error by

writing to SYNC_ASSERT_MASK (Register 0x47D,

Bits[2:0]) according to Table 33.

4. Program the desired error counter threshold into

ERRORTHRES (Register 0x47C).

5. For each error type enabled in the SYNC_ASSERT_MASK

programmed threshold, SYNCOUTx± falls, issuing a sync

request. All error counts are reset when a link reinitialization

occurs. The IRQ does not reset and must be reset manually.

Table 33. Sync Assertion Mask (SYNC_ASSERT_MASK)

Addr. Bit No. Bit Name Description

0x47D 2 BDE Set to 1 to assert SYNCOUTx±

if the disparity error count

reaches the threshold

1 NIT Set to 1 to assert SYNCOUTx±

if the NIT error count reaches

the threshold

0 UEK Set to 1 to assert SYNCOUTx±

if the UEK character error

count reaches the threshold

CGS, Frame Sync, Checksum, and ILAS Monitoring

that each stage of the JESD204B link establishment has

occurred.

Bit x of CODE_GRP_SYNC (Register 0x470) is high if Link

Lane x received at least four K28.5 characters and passed code

group synchronization.

Bit x of FRAME_SYNC (Register 0x471) is high if Link Lane x

completed initial frame synchronization.

Bit x of GOOD_CHECKSUM (Register 0x472) is high if the

checksum sent over the lane matches the sum of the JESD204B

parameters sent over the lane during ILAS for Link Lane x. The

parameters can be added either by summing the individual fields

in registers or summing the packed register. The calculated

checksums are the lower eight bits of the sum of the following

fields: DID, BID, LID, SCR, L − 1, F − 1, K − 1, M − 1, N − 1,

SUBCLASSV, NP − 1, JESDV, S − 1, and HD.

Bit x of INIT_LANE_SYNC (Register 0x473) is high if Link

Lane x passed the initial lane alignment sequence.

CGS, Frame Sync, Checksum, and ILAS IRQs

Fail signals for CGS, frame sync, checksum, and ILAS are available

as IRQ events. Enable them by writing to Register 0x4B8,

Bits[3:0]. The IRQ event status can be read at Register 0x4BA,

Bits[3:0] after the IRQs are enabled. Write a 1 to Register 0x4BA,

Bit 0 to reset the CGS IRQ. Write a 1 to Register 0x4BA, Bit 1 to

reset the frame sync IRQ. Write a 1 to Register 0x4BA, Bit 2 to

reset the checksum IRQ. Write a 1 to Register 0x4BA, Bit 3 to

reset the ILAS IRQ.

See the Interrupt Request Operation section for more

information.

PCLK Factor

(Frames/PCLK)

SYNC_ERR_DUR (Register 0x312,

Bits[7:4]) Setting1

1 4 0 (default)

2 2 1

3 1.5 2

4 1 2

8 0.5 4

AD9174 Data Sheet

Rev. B | Page 52 of 165

Configuration Mismatch IRQ

The AD9174 has a configuration mismatch flag that is available

as an IRQ event. Use Register 0x4B9, Bit 0 to enable the mismatch

flag (it is enabled by default), and then use Register 0x4BB, Bit 0

to read back its status and reset the IRQ signal. See the Interrupt

Request Operation section for more information.

The configuration mismatch event flag is high when the link

configuration settings (in Register 0x450 to Register 0x45D) do

not match the JESD204B settings received by the device

(Register 0x400 to Register 0x40D).

This function is different from the good checksum flags in

ted checksum matches a calculated checksum based on the

transmitted settings. The configuration mismatch event ensures

that the transmitted settings match the configured settings.

Data Sheet AD9174

Rev. B | Page 53 of 165

DIGITAL DATAPATH

The AD9174 has two independent digital datapaths, each

typically supplying data samples to the respective DACx core.

However, there are modulator switch configurations that allow

additional ways to route the samples to either DAC0, DAC1, or

both DACs. See the Modulator Switch section for more details.

Each digital datapath consists of multiple channel datapaths

(channelizers) that sum into a single datapath (main datapath),

which in turn connects to its respective DAC core by default

(see Figure 1). The channelizers and the main datapaths are

fully bypassable, depending on the JESD204B mode selected by

the user. There are a variety of digital processing blocks

available within the channelizers and the main datapaths,

including interpolation filters, bypassable NCOs that allow

either digital I/Q modulation of samples or standalone (DDS)

operation, PA protection blocks (power detection and

protection (PDP) block), and digital gain blocks to ramp or set

the sample gain.

TOTAL DATAPATH INTERPOLATION

The AD9174 contains two stages of interpolation filters: one

stage is located within each channel datapath and is set to a single

value across all channels, and one stage is located within each main

datapath. The total interpolation for a complete digital datapath

can be determined by multiplying the channel interpolation

factor by the main datapath interpolation factor. The relationship

between the DAC sample rate and input data rate is shown in

the following equation:

Total Interpolation = Channel Interpolation ×

Main Interpolation

fDATA = fDAC/(Channel Interpolation × Main Interpolation)

Each of the various cascaded half-band interpolation filters

covers 80% of the total bandwidth (BW) occupied by the incoming

data. Therefore, if using interpolation (total interpolation > 1), the

available signal BW is 80% of the data rate. If the interpolation

stages are bypassed (total interpolation = 1), the available signal

BW is 50% of the data rate because complex data is not used.

The signal bandwidth is calculated as follows:

Signal BW = 0.8 × fDATA, if total interpolation > 1

Signal BW = 0.5 × fDATA, if total interpolation = 1

The interpolation values are programmed as shown in the Table 34.

Table 34. Interpolation Factor Register Settings

Interpolation

Factor

Main Datapath,

Bits[7:4]

Channel Datapath,

Bits[3:0]

1× 0x1 0x1

2× 0x2 0x2

3× Not applicable 0x3

4× 0x4 0x4

6× 0x6 0x6

8× 0x8 0x8

12× 0xC Not applicable

Table 35. Interpolation Modes and Useable Bandwidth

Total Interpolation

Available Signal

Bandwidth fDATA

1× (Bypass) 0.5 × fDATA f

DAC

2×, 4×, 6×, 8×, 12×,

16×, 18×, 24×,

32×, 36×, 48×, 64×

0.8 × fDATA fDAC/total interpolation

Filter Performance

The interpolation filters interpolate the incoming data samples

so that changes in the incoming data are minimized, while

suppressing any interpolation images.

The usable bandwidth, as shown in Table 35, is defined as the

frequency band over which the filters have a pass-band ripple of

less than ±0.001 dB and an image rejection of greater than 85 dB.

Conceptual drawings that shows the relative bandwidth of each

of the filters are shown in Figure 70 and Figure 71. The maximum

pass-band amplitude of all filters is the same. In Figure 70 and

Figure 71, the amplitudes are intentionally shown to be different

to improve understanding, and in reality the amplitude across

all filters is constant and uniform regardless of the interpolation

rate selected by the user.

–2000 –1000 0 1000 2000 3000 4000

FILTER RESPONSE

FREQUENCY (MHz)

1× (MAX DAC = 6GHz)

2× (MAX DAC = 8GHz, 12 BITS)

2× (MAX DAC = 6GHz, 16 BITS)

4× (MAX DAC = 12GHz)

6× (MAX DAC = 12GHz)

16794-030

Figure 70. Band Responses of Total Interpolation Rates for 1×, 2×, 4×, and 6×

at Each Respective Maximum Achievable DAC Rate and Resolution

AD9174 Data Sheet

Rev. B | Page 54 of 165

–1000 –750 –500 –250 0 250 500 750 1000

FILTER RESPONSE

FREQUENCY (MHz)

8×

12×

16×

18×

24×

32×

36×

48×

64×

16794-031

Figure 71. Band Responses of Total Interpolation Rates for 8×, 12×, 16×, 18×,

24×, 32×, 36×, 48×, and 64× at a 12 GHz DAC Rate

Data Sheet AD9174

Rev. B | Page 55 of 165

CHANNEL DIGITAL DATAPATH

2×

2×2×

3×

TO MAIN

DATAPATH

NCO

DIGITAL

GAIN

JESD204B

INTERFACE

1×

2×

2×2×

3×

NCO

DIGITAL

GAIN

2×

2×2×

3×

NCO

DIGITAL

GAIN

16794-033

Figure 72. Block Diagram of the Channel Digital Datapath per the Main DAC Output

Whether one or all of the channelizers in each datapath are

enabled is defined by the JESD204B mode selected by the

user. Each channelizer consists of a digital gain stage, complex

interpolation block, and a complex 48-bit modulus NCO. The

channelizers and the summing node can be fully bypassed (1×

interpolation selected). The interpolation rate selection is applied to

all channelizers and cannot be independently controlled.

However, the gain stage and complex NCO settings can all be

controlled independently. The controls for these blocks are

paged by the channel paging mask in the CHANNEL_PAGE

bits (Register 0x008, Bits[5:0]), as described in Table 36. Each

bit of the page mask corresponds to a channel datapath. The

channelizers can be either paged individually to apply settings

that are unique to a specific channel, or can be paged as a group

to address multiple channelizers using a single set of SPI writes.

Table 36. Channel Page Mask

CHANNEL_PAGE

(Register 0x008,

Bits[5:0])

Channel

Paged

Channel Datapath

Updated

0x01 (Bit 0) Channel 0 Channel 0 of DAC0

0x02 (Bit 1) Channel 1 Channel 1 of DAC0

0x04 (Bit 2) Channel 2 Channel 2 of DAC0

0x08 (Bit 3) Channel 3 Channel 0 of DAC1

0x10 (Bit 4) Channel 4 Channel 1 of DAC1

0x20 (Bit 5) Channel 5 Channel 2 of DAC1

Each of the digital blocks in the channels is described in more

detail in the following sections.

Digital Gain

Each channelizer has an independent gain control that allows

unique gain scaling for each complex data stream. The gain

code for each channel is 12-bit resolution, located in

by the following formulas:

0 ≤ Gain ≤ (212 − 1)/211

−∞ dB < dB Gain ≤ +6.018 dB

Gain = Gain Code  (1/2048)

dB Gain = 20  log10 (Gain)

Gain Code = 2048  Gain = 211 10(dB Gain/20)

The gain code control (CHNL_GAIN) is paged with the

channel page mask (CHANNEL_PAGE) in Register 0x008,

Bits[5:0].

Because the output of all three channels is summed ahead of the

main datapath, take extra care when setting the gain to avoid

sample clipping if the combined amplitude exceeds full scale

after being summed. For example, if all three channels are used

and all three data streams contain samples that are >1/3 full

scale, clipping may occur. In other words, at any specific point

in time, the sum of the samples at the output of all enabled

channels must be between −215 and +(215 − 1).

The digital gain feature is available in all JESD204B modes,

except when 1× channel interpolation is used because the

channel digital processing features are bypassed in that mode,

as shown in Figure 73.

AD9174 Data Sheet

Rev. B | Page 56 of 165

Channel Interpolation

The channel interpolation options available are bypass (1×), 2×,

3×, 4×, 6×, and 8×. Each of the half-band filters used for

interpolation has up to 80% bandwidths with 85 dB of stop

band rejection. The channel half-band cascaded configuration

is shown in Figure 73, with each of the useable bandwidths of

the channel interpolation filters listed in Table 37.

HB2

2×

HB0

2× HB1

2×

TB0

3×

16794-034

Figure 73. Channel Interpolation Half-Band Filter Block Diagram

Table 37. Channel Interpolation Useable Bandwidths and

Rejection

Half-Band

Filter

Bandwidth

(×fIN_FILTER1) (%) Stop Band Rejection (dB)

HB0 80 85

TB0 54 85

HB1 40 85

HB2 27 85

1 fIN_FILTER is the frequency at the input of the half-band filter.

Channel Digital Modulation

Each channelizer includes a 48-bit dual-modulus NCO to allow

I/Q modulation of each channel data to an independent carrier

frequency, each with its own phase offset control. The 48-bit

NCO can be configured into either integer or modulus (DDS)

mode. In modulus mode, the A/B ratio added to the integer FTW

of the NCO allows the frequency to be synthesized with near

infinite precision. See the 48-Bit Integer/Modulus NCO section

for more details. NCO mode is selected as shown in Table 38.

These controls are paged per the channel page masks in the

CHANNEL_PAGE bits (Register 0x008, Bits[5:0]).

Table 38. Channel Modulation Mode Selection

Modulation Mode

Modulation Type

Bit 6

Bit 2

None 0b0 0b0

48-Bit Integer NCO 0b1 0b0

48-Bit Dual Modulus NCO 0b1 0b1

The channel NCO blocks also contain sideband selection

controls as well as options for how the FTW and phase offset

controls are updated. The phase offset word control can be

calculated as follows:

−180° ≤ Degrees Offset ≤ +180°

Degrees Offset = 180°  (DDSC_NCO_PHASE_OFFSET/215)

where DDSC_NCO_PHASE_OFFSET is a 16-bit twos complement

value programmed in the registers listed in Table 39.

Table 39. Channel NCO Phase Offset Registers

Address Value Description

0x138 DDSC_NCO_PHASE_OFFSET[7:0] 8 LSBs of phase offset

0x139 DDSC_NCO_PHASE_OFFSET[15:8] 8 MSBs of phase offset

48-Bit Integer/Modulus NCO

The 48-bit integer/modulus NCO combines an NCO block, a

phase shifter, and a complex modulator to modulate the signal

onto a user defined carrier frequency, as shown in Figure 74. This

configuration allows output signals to be shifted anywhere

across the output spectrum up to ±fNCO/2 with very fine

frequency resolution.

The NCO produces a quadrature carrier to translate the input

signal to a new center frequency. A quadrature carrier is a pair

of sinusoidal waveforms of the same frequency, offset 90° from

each other. The frequency of the quadrature carrier is set using

the FTW. The quadrature carrier is mixed with the I and Q data

and then summed into the I and Q datapaths, as shown in

Figure 74.

Each of the channel 48-bit NCOs can be configured to run in

integer mode (that is, when only the FTW value defines the

NCO output frequency). The value of the FTW in part depends

on the clock speed at which the NCO block is running (fNCO,CLK).

For any channel NCO, the clock rate is equal to the rate of the

summing node (maximum of 1.575 GSPS) and can be

calculated by using the following formulas:

fNCO,CLK = fDATA  Channel Interpolation

fNCO,CLK = fDAC/Main Interpolation = fSUMMING_NODE

The FTWs for each individual NCO can be programmed

separately and are calculated by using the following formula:

−fNCO,CLK/2 ≤ fCARRIER < + fNCO,CLK/2

DDSC_FTW = (fCARRIER/fNCO,CLK) × 248

where:

DDSC_FTW is a 48-bit, twos complement number.

fCARRIER is the output frequency of the NCO.

fNCO,CLK is the sampling clock frequency of the NCO.

The frequency tuning word is set as shown in Table 40.

Table 40. Channel NCO FTW Registers

Address Value Description

0x132 DDSC_FTW[7:0] 8 LSBs of FTW

0x133 DDSC_FTW[15:8] Next eight bits of FTW

0x134 DDSC_FTW[23:16] Next eight bits of FTW

0x135 DDSC_FTW[31:24] Next eight bits of FTW

0x136 DDSC_FTW[39:32] Next eight bits of FTW

0x137 DDSC_FTW[47:40] 8 MSBs of FTW

Data Sheet AD9174

Rev. B | Page 57 of 165

Unlike other NCO control registers, the FTW registers are not

applied to the NCO block immediately upon writing the control

of DDSC_FTW_LOAD_REQ (Register 0x131, Bit 0). After an

update request, DDSC_FTW_LOAD_ACK (Register 0x131, Bit 1)

must indicate a status high to acknowledge that the FTW has

been updated.

The DDSC_SEL_SIDEBAND bit (Register 0x130, Bit 1 = 0b1)

is a convenience bit that controls whether the lower- or upper-

sideband of the modulated data is used, which is equivalent to

flipping the sign of the FTW.

INTERPOLATION

NCO

–1

COS(ωn + θ)

SIN(ωn + θ)

I DATA

Q DATA

DDSC_FTW[47:0]

DDSC_SEL_SIDEBAND

OUT_I

OUT_Q

–

DDSC_NCO_PHASE_OFFSET

[15:0]

16794-035

Figure 74. NCO Modulator Block Diagram

Channel Modulus NCO Mode (Direct Digital Synthesis

(DDS) Mode)

Each 48-bit channel NCO can also be used in a dual modulus

mode to create fractional frequencies beyond the 48-bit accuracy

that integer mode provides, which may be of interest in applications

where the NCO is running for prolonged periods of time without

being reset, thus possibly resulting in a noticeable phase drift

relative to other clocks in the system, even given the small

initial frequency error of the 48-bit, integer NCO. The modulus

mode is enabled by programming the DDSC_MODULUS_EN bit

in the DDSC_DATAPATH_CFG register to 1 (Register 0x130,

Bit 2 = 0b1).

The frequency ratio for the programmable modulus DDS is

very similar to that of the typical accumulator-based DDS. The

only difference is that N is not required to be a power of two (as

for integer NCOs) for the programmable modulus, but can be

an arbitrary integer. In practice, hardware constraints place

limits on the range of values for N. As a result, the modulus

extends the use of the NCO to applications that require exact

rational frequency synthesis. The underlying function of the

programmable modulus technique is to alter the accumulator

modulus.

Implementation of the programmable modulus function within

the AD9174 is such that the fraction, M/N, is expressible by the

following equation. The form of the equation implies a

compound frequency tuning word with X representing the

integer part and A/B representing the fractional part.

CARRIER

NCO CLK

fMB





where:

X is the FTW, programmed in Register 0x132 to Register 0x137.

A is programmed in Register 0x140 to Register 0x145.

B is programmed in Register 0x13A to Register 0x13F.

Because X, A, and B are 48-bit words, modulus mode allows the

user to set the NCO output frequency (fCARRIER) with a precision

of (fNCO,CLK)/2(2 × 48).

Programmable Modulus Example

Consider the case in which fNCO,CLK = 1500 MHz and the desired

value of fCARRIER is 150 MHz. This scenario synthesizes an output

frequency that is not a power of two submultiple of the sample

rate, namely fCARRIER = (1/10) fNCO,CLK, which is not possible with

a typical accumulator-based DDS. The frequency ratio, fCARRIER/

fNCO,CLK, leads directly to M and N, which are determined by

reducing the fraction (150,000,000/1,500,000,000) to its lowest

terms, that is,

M/N = 150,000,000/1,500,000,000 = 1/10

Therefore, M = 1 and N = 10.

After calculation, X = 28,147,497,671,065, A = 3, and B = 5.

Programming these values into the registers for X, A, and B

(X is programmed in Register 0x132 to Register 0x137 for

DDSC_FTWx, B is programmed in Register 0x13A to

programmed in Register 0x140 to Register 0x145 for DDSC_

ACC_DELTAx) causes the NCO to produce an output frequency

of exactly 150 MHz given a 1500 MHz sampling clock. For more

details, refer to the AN-953 Application Note.

NCO Reset

Resetting an NCO is useful when determining the start time

and phase of a particular NCO. Each Channel NCO can be

configured to reset in response to one of several events: a direct

request via SPI (Register 0x131, Bit 0), a change to one of the

FTW register values, or on the next SYSREF± rising edge. The

reset method is controlled by Register 0x131. See the detailed

description for Register 0x131 for more information.

Channel Summing Node

The outputs of the channelizers are combined at the summing

node junction before being routed to the respective main datapath.

The summation of any number of channels being used must not

exceed a value range of ±215 to avoid clipping (binary overflow)

of the 16-bit data samples that are summed into the main datapath.

The maximum data rate for each channel when the channel

interpolation is >1× is limited by the maximum speed of summing

node junction, namely 1.575 GSPS. If the channel datapaths are

bypassed (channel interpolation is 1×), the summing node

block is also bypassed, as shown in Figure 72. Bypassing the

channelizer(s) allows passing data to the main digital datapath

at a higher data rate. See Table 13 for JESD204B modes and the

corresponding maximum data rates.

AD9174 Data Sheet

Rev. B | Page 58 of 165

MAIN DIGITAL DATAPATH

1×

RAMP UP/DOWN

GAIN

2×

3×

2×

TO ANALOG

DAC CORE

FROM

CHANNELIZER

OUTPUT MUX

NCO

PROTECTION

16794-036

Figure 75. Block Diagram of the Main Digital Datapath per Main DAC Output

Each main digital datapath consists of a power amplifier (PA)

protection block, a set of complex interpolation filters, a 48-bit

complex main datapath NCO, and a ramp-up/ramp-down gain

stage. The main datapaths are bypassable (1× interpolation

selected), which bypasses all the digital processing blocks

included in the main datapath. The interpolation selection is set

to the same value for all main datapaths and cannot be

independently controlled. However, the PA protection block,

complex NCO settings, and gain ramp can all be configured

independently.

The controls for these blocks are paged by the main DAC

datapath paging mask, MAINDAC_PAGE (Register 0x008,

Bits[7:6]), as listed in Table 41. Each bit of the page mask

corresponds to a main DAC datapath. The datapaths can be

either paged individually to apply settings that are unique to a

specific main datapath, or can be paged as a group to address

both datapaths using a single set of SPI writes.

Table 41. Main DAC Datapath Page Mask

MAINDAC_PAGE

(Register 0x008,

Bits[7:6])

DAC

Paged

DAC Datapath

Updated

0x40 (Bit 6) DAC0 DAC0

0x80 (Bit 7) DAC1 DAC1

Each digital block in the main datapath is described in more

detail in the following sections.

Downstream Protection (PA Protection)

The AD9174 has several circuits designed to quickly reduce (or

squelch) the amplitude of the samples that are to arrive at either

DAC core, and thus protect PAs or other external system

components located downstream from the AD9174 outputs.

The DACx outputs can be either gradually ramped up or

ramped down, or turned on or off in response to the following

trigger signals, as shown in Figure 76:

 PDP_PROTECT. This signal asserts when the calculated

digital sample amplitude exceeds a programmable

threshold.

 INTERFACE_PROTECT. This signal asserts when specific

JESD204B errors occur.

 SPI_PROTECT. This signal asserts when the user writes

the SPI control register directly.

 BSM_PROTECT. This signal triggers the blanking state

machine (BSM) module, which flushes the datapath on the

rising edge of the TXEN0 or TXEN1 signal, which may come

from a SPI write or the external TXEN0 or TXEN1 pin.

A number of flags are raised in response to the trigger events,

that can also be routed to the IRQx I/O pins (IRQ0 and IRQ1),

to possibly shut down other external downstream components

or simply serve as indicators.

The DAC output on/off feature is similarly implemented

through a feedforward trigger signal to the ramp-up/ramp-

down digital gain block at the end of the main datapath before

the analog DAC core, which allows the DAC to be turned on or

off gradually (or quickly).

Data Sheet AD9174

Rev. B | Page 59 of 165

PDP

JESD204B

ERRORS

SPI

BSM

IRQ0/IRQ1

TXEN0/TXEN1

(LONG/SHORT) PDP_PROTECT

SPI_PROTECT

SPI_TXEN

TXEN

INTERFACE_PROTECT

FLUSH

DATAPATH

DAC

CORE

CHANNEL

SUMMER

CHANNEL

DATAPATHS

BYPASSED

MNCO

+RAMP UP/DOWN

GAIN

BSM_PROTECT

ERROR

TRIGGER

SOURCE

ENA_SPI_TXEN

16794-037

Figure 76. Block Diagram of Downstream Protection Triggers

+ Q

SHORT AVERAGE

FILTER

(2.6ns, 1.0µs) AT 12GHz

LONG AVERAGE

FILTER

(1.0µs, 1.0ms) AT 12GHz

SHORT_PA_THRESHOLD

DATAPATH

DATA SAMPLES

LONG_PA_THRESHOLD

LONG_PDP_PROTECT/

SHORT_PDP_PROTECT

16794-038

Figure 77. PDP Block Diagram

Power Detection and Protection (PDP) Block

The PDP block calculates the anticipated average power at the

DACx core output and prevents overrange signals from being

output from the AD9174, to avoid a potentially destructive

breakdown of power sensitive devices, such as PAs. The protection

block provides a signal, PDP_PROTECT, that can be used ramp

down the DAC output and/or be routed to an I/O pin to flag

external components to shut down.

The PDP block uses a separate path with a shorter latency than

the datapath to ensure that PDP_PROTECT is triggered before

the overrange signal reaches the analog DAC cores (with the

exception when the total interpolation is 1). The sum of I2 and

Q2 are calculated as a representation of the input signal power

(to improve response time, only the top six MSBs of data

samples are used). The calculated sample power values are

accumulated through a moving average filter with an output

that is the average of the input signal power across a certain

number of samples. There are two types of average filters with

different lengths: a short filter that detects high power pulses

that may result in voltage breakdown, and a long filter that

detects sustained high power signals that may last longer than

the thermal constant of the PA or another device.

When the output of the averaging filter is larger than the

threshold, the internal signal, PDP_PROTECT, goes high,

which can optionally be configured to trigger an IRQ flag and

turn off the DAC output through the ramp-up/ramp-down.

The PDP block function is illustrated in Figure 77.

The long and short averaging times are configured by the LONG_

PA_AVG_TIME (Register 0x585, Bits[3:0]) and the SHORT_

PA_AVG_TIME (Register 0x58A, Bits[1:0]) controls. Use the

following calculations to determine the average window size times:

Length of Long Average Window = 2LONG_PP_AVG_TIME + 9

Length of Short Average Window = 2SHORT_PA_AVG_TIME

AD9174 Data Sheet

Rev. B | Page 60 of 165

When the calculated average power exceeds a specified

threshold, a trigger signal is issued. The registers to program the

thresholds for the long and short average filters, along with their

respective detected power calculation readbacks, are listed in

Table 42.

Table 42. PDP Threshold and Power Calculation Controls

0x583 [7:0] LONG_PA_THRESHOLD[7:0]

0x584 [4:0] LONG_PA_THRESHOLD[12:8]

0x586 [7:0] LONG_PA_POWER[7:0]

0x587 [4:0] LONG_PA_POWER[12:8]

0x588 [7:0] SHORT_PA_THRESHOLD[7:0]

0x589 [4:0] SHORT_PA_THRESHOLD[12:8]

0x58B [7:0] SHORT_PA_POWER[7:0]

0x58C [4:0] SHORT_PA_POWER[12:8]

Main Datapath Interpolation

The interpolation options available within the main datapath

are bypass (1), 2, 4, 6, 8 and 12. Each of the half-band

filters used for interpolation have up to 80% bandwidths with

85 dB of stop band rejection. The channel half-band cascaded

configuration is shown in Figure 78, with each of the useable

bandwidths of the interpolation filters listed in Table 43.

HB3

2×

HB4

2×

TB1

3×

HB5

2×

16794-039

Figure 78. Main Datapath Interpolation Half-Band Filter Block Diagram

Table 43. Main Datapath Interpolation Useable Bandwidths

and Rejection

Half-Band Filter

Bandwidth

(×fIN_FILTER) Stop Band Rejection (dB)

HB3 80% 85

HB4 40% 85

TB1 27% 85

HB5 20% 85

Main Datapath Digital Modulation

The main datapath 48-bit NCOs architecture is largely identical

to the channelizer NCOs that were described in earlier sections.

Their operation is similar as well. However, unlike the channelizer

NCOs, the main datapath NCOs operate at a higher clock rate,

the same rate as the analog DAC cores (fDAC), which allows the

NCOs to generate frequencies across a wider range. See the

48-Bit Integer/Modulus NCO section for more details

NCO mode is selected as shown in Table 44. These controls are

paged per the main DAC page masks, MAINDAC_PAGE

(Register 0x008, Bits[7:6]).

Table 44. Main Modulation Mode Selection

Modulation Mode

Modulation Type

Bit 3

Bit 2

None 0b0 0b0

48-Bit Integer NCO 0b1 0b0

48-Bit Dual Modulus NCO 0b1 0b1

The main NCO blocks also contain sideband selection controls

as well as options for how the FTW and phase offset controls

are updated.

The phase offset word control can be calculated as follows:

−180° ≤ Degrees Offset ≤ +180°

Degrees Offset = 180°  (DDSM_NCO_PHASE_OFFSET/215)

where DDSM_NCO_PHASE_OFFSET is a 16-bit twos complement

value programmed in the registers listed in Table 45.

Table 45. Main Datapath NCO Phase Offset Registers

Address Value Description

0x11C DDSM_NCO_PHASE_OFFSET[7:0] 8 LSBs of phase offset

0x11D DDSM_NCO_PHASE_OFFSET [15:8] 8 MSBs of phase offset

48-Bit Integer/Modulus NCO

The main datapath NCOs use a similar architecture to the

channelizer NCOs, as shown in Figure 74. Because the main

datapath NCOs are clocked at the same rate as fDAC, this

configuration allows output signals to be placed anywhere in

the output spectrum up to ±fDAC/2 with very fine frequency

resolution.

The NCO produces a quadrature carrier to translate the input

signal to a new carrier frequency, similar to the channelizer

NCOs. Refer to the corresponding channelizer NCO section for

more details.

The FTW for the main datapath NCOs is calculated in the same

manner as the FTW for the channelizer NCOs. An important

distinction is that the clock rate of the main datapath NCOs

(fNCO,CLK) is equal to the DAC sample rate (fDAC, 12.6 GSPS

maximum). Calculate fNCO,CLK using the following formula:

fNCO,CLK = fDAC = fDATA × Channel Interpolation



Main

Interpolation

The FTWs for each individual NCO can be programmed

separately and are calculated using the following formula:

−fNCO,CLK /2 ≤ fCARRIER < + fNCO,CLK /2

DDSM_FTW = (fCARRIER /fNCO,CLK) × 248

where:

fCARRIER is the output frequency of the NCO.

fNCO,CLK is the sampling clock frequency of the NCO.

DDSC_FTW is a 48-bit, twos complement number.

The frequency tuning word is set as shown in Table 46.

Data Sheet AD9174

Rev. B | Page 61 of 165

Table 46. Main Datapath NCO FTW Registers

Address Value Description

0x114 DDSM_FTW[7:0] 8 LSBs of FTW

0x115 DDSM_FTW[15:8] Next 8 bits of FTW

0x116 DDSM_FTW[23:16] Next 8 bits of FTW

0x117 DDSM_FTW[31:24] Next 8 bits of FTW

0x118 DDSM_FTW[39:32] Next 8 bits of FTW

0x119 DDSM_FTW[47:40] 8 MSBs of FTW

Unlike other NCO control registers, the FTW registers are not

applied to the NCO block immediately on writing the control

rising edge of DDSM_FTW_LOAD_REQ (Register 0x113, Bit 0).

After an update request, DDSM_FTW_LOAD_ACK

(Register 0x113, Bit 1) must indicate a high status to

acknowledge that the FTW is updated.

The DDSC_SEL_SIDEBAND bit Register 0x112, Bit 1 = 0b1)

is a convenience bit that controls whether the lower or upper

sideband of the modulated data is used, which is equivalent to

flipping the sign of the FTW.

INTERPOLATION

NCO

–1

COS(ωn + θ)

SIN(ωn + θ)

I DATA

Q DATA

DDSM_FTW[47:0]

DDSM_SEL_SIDEBAND

OUT_I

OUT_Q

–

DDSM_NCO_PHASE_OFFSET

[15:0]

16794-040

Figure 79. NCO Modulator Block Diagram, Main Datapath Modulus NCO

Mode (DDS)

Each of the main datapath 48-bit NCOs can also be used in a

dual modulus mode to create fractional frequencies beyond the

48-bit accuracy. The modulus mode is enabled by programming

the DDSM_MODULUS_EN bit in the DDSM_DATAPATH_

CFG register to 1 (Register 0x112, Bit 2 = 0b1).

The main datapath modulus NCOs are of a similar architecture to

the channel modulus NCOs, and the X (FTW), A, and B values are

calculated in a similar manner:

CARRIER

NCO CLK





where:

X is the FTW, programmed in Register 0x114 to Register 0x119.

A is programmed in Register 0x12A to Register 0x12F.

B is programmed in Register 0x124 to Register 0x129.

For more details and examples, see the Channel Modulus NCO

Mode (Direct Digital Synthesis (DDS) Mode) section. The main

datapath NCOs operate at a higher clock rate (fNCO, CLK) than the

channel NCOs, and are addressed from a different set of SPI

registers.

NCO Reset

Resetting the main datapath NCOs can be useful when determ-

ining the start time and phase of an NCO. Each NCO can be

configured to reset in response to one of several events: a direct

request via SPI (Register 0x113, Bit 0), a change to one of the

FTW register values, or on the next SYSREF± rising edge. The

reset method is controlled by Register 0x113. See the detailed

description of Register 0x113 in Table 62 for more information.

Fast Frequency Hopping (FFH)

Each main datapath NCO in the AD9174 has several features

that allow FFH between preconfigured carrier frequencies. The

main 48-bit NCO is a general-purpose NCO, combined with a

bank of 31 FFH NCOs, with 32 bits each.

FFH NCO

Each FFH NCO is implemented within the main 48-bit NCO,

with an associated bank of 31 FTWs located in Register 0x806 to

words that are loaded into the hopping frequency register bank

when the particular NCO is reset. Any of the 32 FTWs can be

selected by a single register write to the HOPF_SEL bits in the

DDSM_HOPF_CTRL register (Register 0x800, Bits[4:0]). The

manner in which the phase of a particular NCO transitions as it

hops between carrier frequencies is determined by the NCO

frequency change mode. These modes include phase continuous

hopping, phase discontinuous hopping, and phase coherent

hopping. The hopping modes are controlled by Register 0x800,

Bits[7:6], as described in Table 47.

Table 47. NCO Frequency Change Mode

0b00 Phase continuous switch

0b01 Phase discontinuous switch (reset

NCO accumulator)

0b10 Phase coherent switch

In phase discontinuous mode, the FTW of the NCO is updated

and the phase accumulator is reset, resulting in an abrupt phase

change each time the NCO hops to a new frequency. The

discontinuous phase may result in an undesirable glitch at the

transition point. Alternatively, in phase continuous switching,

the frequency tuning word of the NCO is updated, while the

main phase accumulator maintains count throughout the

update, resulting in a smooth phase transition between carrier

frequencies.

AD9174 Data Sheet

Rev. B | Page 62 of 165

In phase coherent mode, a bank of 31 additional phase

accumulators is enabled, which maintains count regardless of

which accumulator value is applied to the main accumulator.

The result is that the phase of all 32 FTWs is known at all times

for each carrier frequency, thus allowing to maintain phase

coherency between hops, relative to Time 0 (the time when the

NCO was last reset). Therefore, it is recommended to preload

all FTWs and only then select the phase coherent switch mode

so that the NCO phase accumulators start at the same time.

To conserve power, each of the 31 additional NCOs is enabled only

when its corresponding FTW is programmed to a value other than

0x0. All NCO FTWs have a default value of 0x0. Note that the main

phase accumulator (corresponding to the 48-bit FTW, namely

FTW0), is concurrently enabled by the DDSM_NCO_EN bit in the

DDSM_DATAPATH_CFG register (Register 0x112, Bit 3 = 0b1).

Each of the 32-bit NCOs can be powered down at the convenience

of the user. If a 32-bit NCO is initially powered up, it is

recommended to first program the FTW to 0x0001 to flush the

accumulator from any residual values, and only then program

the FTW to 0x0000, which powers down the NCO output, but

not the accumulator. This method avoids the possibility of any

residual spurious tones appearing at the output of adjacent

NCOs during power-down, however unlikely.

Calibration NCO

In addition to the 48-bit NCO and the 31, 32-bit NCOs, there is

a 32-bit calibration NCO, which is also part of the main datapath

NCO block, shown in Figure 74. This NCO is separate from the

48-bit NCO, allowing a convenient method for generating a

calibration tone without the need to modify the configuration of

the main datapath. Similar to all other NCOs, this NCO can be

used in NCO only mode, or used to translate incoming data to a

new carrier frequency. Register 0x1E6, Bit 0 controls whether

the 32-bit calibration NCO is connected to the main datapath,

or whether the normal 48-bit main NCO is connected instead.

To use the 32-bit calibration NCO, first enable the calibration

NCO accumulator by setting Register 0x1E6, Bit 2 = 1. Then,

program the calibration NCO FTW in Register 0x1E2 to

be used instead of the main NCO by setting Register 0x1E6,

Bit 0 = 1. Similar to other NCOs, the calibration NCO can be

configured to operate in NCO only mode, which is enabled by

setting Register 0x1E6, Bit 1 = 1.

Set the amplitude of the tone can be set in Registers 0x148 and

details.

NCO ONLY MODE

The AD9174 NCOs can operate in standalone mode, where the

JESD204B link is disconnected (or disabled) and one or more NCO

tones are output from DAC0 and/or DAC1. The correct JESD204B

mode must still be selected to configure the corresponding

channelizer and/or main datapath clock domains. In NCO only

mode, a single-tone sine wave is generated by each NCO by

modulating the NCO output with dc samples that are generated

internally. The amplitude of the dc samples directly corresponds

to the amplitude of the NCO tone output by the DAC core. The

amplitude of each channel NCO can be controlled independently

by paging the correct channel register (Register 0x148 and

by paging Channel 0 for Channel NCO0 and Channel 1 for

Channel NCO1 (the dc word is shared between Channel NCOx

and the main NCOx channel).

The data source of the digital datapaths in NCO only mode is the

dc data word, meaning that whether the JESD204B link is

initially brought up or not, the data from the link is not passed

to the datapaths. However, the input to the datapaths is easily

switched between the dc data input and SERDES block input, by

either Register 0x130 or Register 0x1E6, depending on the data-

path. The connection can be made on-the-fly, assuming that a

JESD204B link is previously configured and proper data samples

are supplied. During the transition, sensitive external components

can be protected using the PA protection block as previously

described.

To use any of the NCOs in NCO only mode, the user can elect to

configure the AD9174 to operate in JESD204B Mode 0, Mode 1,

or Mode 2, depending on the desired number of channel NCOs.

Any other JESD204B mode can be selected instead, as long as

the NCO is not bypassed (interpolation = 1). To enable the

NCOs that connect to DAC1, a dual-link JESD204B mode can

be configured. It is not necessary to establish the JESD204B link

with an external source, such as an FPGA, and instead only a

few SPI register writes are needed to enable the necessary

JESD204B mode to set up the clock domains corresponding to

each NCO.

In general, NCO only mode is useful to bring up a transmitter

radio signal chain without requiring a digital data source initially,

or in applications where a sine wave output is all that is required

(also known as DDS mode), such as in local oscillator (LO)

generation or radar applications.

There is an additional optional calibration NCO block that can

be used as part of the initial system calibration without otherwise

making changes to the configuration of the digital datapath.

Data Sheet AD9174

Rev. B | Page 63 of 165

MDAC

CORE

PA PROTECT

RAMP

UP/DOWN

GAIN

NCO

CALIBRATION

32-BIT NCO

REG 0x1E2 TO REG 0x1E5

MAIN 48-BIT

NCO

REG 0x114 TO REG 0x119

NCO

DDSC_EN_DC_INPUT

REG 0x130, BIT 0

NCO

DC AMPLITUDE LEVEL

(REG 0x148 TO REG 0x149)

CHANNEL

GAIN

CHANNEL

GAIN

CHANNEL

GAIN

DDSM_EN_CAL_DC_INPUT

REG 0x1E6, BIT 1

DDSM_EN_CAL_ACC

REG 0x1E6, BIT 2

DDSM_EN_CAL_FREQ_TUNING

REG 0x1E6, BIT 0

DDSC_EN_DC_INPUT

REG 0x130, BIT 0

DDSC_EN_DC_INPUT

REG 0x130, BIT 0

16794-148

Figure 80. DC Amplitude Injection for NCO Only Mode Block Diagram

AD9174 Data Sheet

Rev. B | Page 64 of 165

MODULATOR SWITCH

For added flexibility, the final NCO block (NCO0 and NCO1, to

correspond to the DAC core they feed by default, in Configuration 0)

includes a modulator switch that allows the user to route the

desired I and/or Q sample to one or all DAC cores. NCOx are

located near the output of their respective main digital datapaths.

The switch has four configurations, as shown in Figure 81 through

Figure 84. Some configurations bypass the NCO altogether and

route the complex I and Q samples from each datapath to the DAC

core(s), whereas other modes route the output of the NCOs instead.

Of particular interest may be Configuration 2, shown in Figure 83,

where I samples are sent to DAC0 and Q samples are sent to DAC1,

to operate the AD9174 as a traditional IF DAC. Configuration 3

routing also depends on whether NCO1 and/or DAC1 is enabled.

The configurations are set via Register 0x112, Bits[5:4] and are

paged by the MAINDAC_PAGE register control.

NCO

DAC0 I DATA DAC0 NCO REAL DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA DAC1 NCO REAL DATA

TO DAC1 CORE

DAC0 MOD SWITCH CONFIGURATION

DAC1 MOD SWITCH CONFIGURATION

DAC1 Q DATA

16794-041

Figure 81. Configuration 0—DAC0 = I0, DAC1 = I1

÷2

NCO

DAC0 I DATA

÷2

SUM OF I NCO OUT DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

SUM OF Q NCO OUT DATA

TO DAC1 CORE

DAC0 MOD SWITCH CONFIGURATION

DAC1 MOD SWITCH CONFIGURATION

DAC1 Q DATA

16794-042

Figure 82. Configuration 1, CMPLX_MOD_DIV2_DISABLE = 0—DAC0 = I0 + I1, DAC1 = Q0 + Q1

NCO

DAC0 I DATA

TO DAC0 CORE

DAC0 Q DAT

NCO

DAC1 I DATA DAC0 Q DATA

TO DAC1 CORE

DAC0 MOD SWITCH CONFIGURATION

DAC1 MOD SWITCH CONFIGURATION

DAC1 Q DAT

16794-043

Figure 83. Configuration 2—DAC0 = I0, DAC1 = Q0

Data Sheet AD9174

Rev. B | Page 65 of 165

÷2

NCO

DAC0 I DATA

SUM OF NCOs REAL DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

NO DATA

TO DAC1 CORE

DAC0 MOD SWITCH CONFIGURATION

DAC1 MOD SWITCH CONFIGURATION

DAC1 Q DATA

ZERO DATA

16794-044

Figure 84. Configuration 3, CMPLX_MOD_DIV2_DISABLE = 0—DAC0 = I0 + I1, DAC1 = 0

AD9174 Data Sheet

Rev. B | Page 66 of 165

Complex Modulator Switch Configurations

The switch configurations described previously only support

complex samples with the NCO bypassed. To support complex

samples where the NCO is used, Configuration 3 can be

additionally reconfigured to operate on complex samples at the

output of the NCO(s), controlled by the EN_CMPLX_MOD bit

(Register 0x112, Bit 6). The specific configuration also depends

on whether NCO1 is enabled, as shown in Figure 85 and Figure 86.

To set up Configuration 3A, set the EN_CMPLX_MOD bit to 1

and set the switch to Configuration 3, with both NCO0 and

NCO1 enabled. The quadrature output of the NCO from each

main datapath is also routed to DAC1 (no longer sends zero

data out of DAC1 as in the default Configuration 3, shown in

Figure 84). If NCO1 is disabled and EN_CMPLX_MOD = 1,

the real output of NCO0 is sent to DAC0 and the quadrature

output of the NCO0 is set to DAC 1. This setup is similar to

Configuration 2, but with the samples picked up at the output of

NCO0 (see Figure 85 and Figure 86).

The divide by 2 block at the input of the mux switch can be

disabled using the CMPLX_MOD_DIV2_DISABLE bit in

6 dB lower than anticipated because the divide by 2 block is

enabled by default.

The complete list of SPI writes required to enable each

configuration is shown in Table 48.

÷2

NCO

DAC0 I DATA

÷2

SUM OF I NCO OUT DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

SUM OF Q NCO OUT DATA

TO DAC1 CORE

DAC0 MOD SWITCH MODE

DAC1 MOD SWITCH MODE

DAC1 Q DATA

16794-442

Figure 85. Configuration 3A, EN_CMPLX_MOD = 1, CMPLX_MOD_DIV2_DISABLE = 0, both Main NCOs Enabled—DAC0 = I0_NCO + I1_NCO, DAC1 = Q0_NCO +

Q1_NCO

NCO

DAC0 I DATA

DAC0 I NCO OUT DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA DAC0 Q NCO OUT DATA

TO DAC1 CORE

DAC0 MOD SWITCH MODE

DAC1 MOD SWITCH MODE

DAC1 Q DATA

16794-443

Figure 86. Configuration 3B, EN_CMPLX_MOD = 1, CMPLX_MOD_DIV2_DISABLE = 1, DAC 1 Main NCO Disabled—DAC0 = I0_NCO, DAC1 = Q0_NCO

Table 48. Required SPI Writes for Each Modulator Switch Configuration

Configuration

(EN_COMPLEX_MOD)

Bits[5:4] (DDSM_

MODE)

(Paged) Register 0x0FF,

Bit 1 (CMPLX_MOD_

DIV2_DISABLE)

NCO0

Enable

NCO1

Enable

Configuration 0 0 0 1 1 0

Configuration 1 0 1 0 0 0

Configuration 2 0 2 0 0 0

Configuration 3 0 3 1 1 0

Complex Configuration 3A 1 3 1 1 0

Complex Configuration 3B 1 3 1 0 1

Data Sheet AD9174

Rev. B | Page 67 of 165

Ramp-Up/Ramp-Down Gain Block

A ramp-up/ramp-down gain block is located at the output of

each main datapath and before the samples are routed to the

analog DAC core(s) for decoding. This block is an extension of

the PDP block, and together these blocks protect downstream

components from large signal peaks or sustained average power

that exceeds a user defined threshold.

Various trigger methods can be configured in the PA protection

block to trigger a gain ramp-down to mute the data being

transmitted out of the AD9174, as shown in Figure 76. The

ramp-up and ramp-down steps can be configured via the SPI in

ramp-down occurs in 32 steps over 2(CODE + 8) DAC clock periods.

This control can be configured individually for each of the DAC

ramp blocks via the MAINDAC_PAGE control in Register 0x008.

After the data is ramped down due to a trigger event, it can be

ramped back up in two different ways, assuming the trigger event

(error) was cleared. If the SPI protection control bit triggered

the interrupt for a ramp-down, the data can be ramped-up by

toggling Register 0x582, Bit 7 from 0 to 1, and then back to 0.

Alternatively, an option exists to mute the digital data during a

digital clock rotation if the ROTATE_SOFT_OFF_EN control

in Register 0x581, Bit 2 is set to 1. When this bit is set, a

synchronization logic rotation triggers the ramp-up/ramp-down

block to ramp the output down, rotates the digital clocks, and

then ramps the output back up. These actions occur only if Bit 1

of the ROTATION_MODE control in Register 0x03B is set to 1

to enable a datapath clock rotation when the synchronization logic

rotates.

AD9174 Data Sheet

Rev. B | Page 68 of 165

INTERRUPT REQUEST OPERATION

The AD9174 provides an interrupt request output signal (IRQ)

on Pin D9 (IRQ0) and Pin E9 (IRQ1) that can be used to notify an

external host processor of significant device events. The IRQ

output can be switched between the IRQ0 pin or the IRQ1 pin by

setting the corresponding bit for the IRQ signal in Register 0x028,

assertion of the interrupt, query the device to determine the

precise event that occurred. The IRQx pins are open-drain,

active low outputs. Pull the IRQx pins high, external to the

device. These pins can be tied to the interrupt pins of other

devices with open-drain outputs to wire. OR these pins

together.

Figure 87 shows a simplified block diagram of how the IRQx

blocks works. If IRQ_EN is low, the INTERRUPT_SOURCE

signal is set to 0. If IRQ_EN is high, any rising edge of EVENT

causes the INTERRUPT_SOURCE signal to be set high. If any

INTERRUPT_SOURCE signal is high, the IRQx pin is pulled

low. INTERRUPT_SOURCE can be reset to 0 by either an

IRQ_RESET signal or a DEVICE_RESET signal.

Depending on the STATUS_MODE signal, EVENT_STATUS

reads back an event signal or an INTERRUPT_SOURCE signal.

The AD9174 has several IRQ register blocks that can monitor

up to 86 events, depending on the device configuration. Certain

details vary by IRQ register block, as described in Table 49.

Table 50 shows the source registers of the IRQ_EN, IRQ_RESET,

and STATUS_MODE signals in Figure 87, as well as the address

where EVENT_STATUS is read back.

Table 49. IRQ Register Block Details

Event

Reported EVENT_STATUS

0x020 to 0x27 Per chip INTERRUPT_SOURCE if IRQ is

enabled; if not, it is an event

0x4B8 to 0x4BB;

0x470 to 0x473

Per link and

lane

INTERRUPT_SOURCE if IRQ is

enabled; if not, 0

INTERRUPT SERVICE ROUTINE

Interrupt request management starts by selecting the set of

event flags that require host intervention or monitoring. Enable

the events that require host action so that the host is notified

when they occur. For events requiring host intervention upon

IRQ activation, run the following routine to clear an interrupt

request:

1. Read the status of the event flag bits that are being monitored.

2. Disable the interrupt by writing 0 to IRQ_EN.

3. Read the event source.

4. Perform any actions that may be required to clear the cause

of the event. In many cases, no specific actions may be

required.

5. Verify that the event source is functioning as expected.

6. Clear the interrupt by writing 1 to IRQ_RESET.

7. Enable the interrupt by writing 1 to IRQ_EN.

IRQ_EN

EVENT

DEVICE_RESET

EVENT_STATUS

INTERRUPT_SOURCE

IRQ_EN

STATUS_MODE

0OTHER

INTERRUPT

SOURCES

IRQ

IRQ_RESET

16794-045

Figure 87. Simplified Schematic of IRQx Circuitry

Table 50. IRQ Register Block Address of IRQ Signal Details

Block

Address of IRQ Signals1

IRQ_EN IRQ_RESET STATUS_MODE EVENT_STATUS

0x020 to

0x023

0x020 to 0x023; R/W per chip 0x024 to 0x027; per chip STATUS_MODE= IRQ_EN 0x024 to 0x027; R per chip

0x4B8 to

0x4BB

0x4B8, 0x4B9; W per error type 0x4BA, 0x4BB; W per error type Not applicable, STATUS_MODE = 1 0x4BA, 0x4BB; W per chip

0x470 to

0x473

0x470 to 0x473; W per error type 0x470 to 0x473; W per link Not applicable, STATUS_MODE = 1 0x470 to 0x473; W per link

1 R is read, W is write, and R/W is read/write.

Data Sheet AD9174

Rev. B | Page 69 of 165

ANALOG INTERFACE

DAC INPUT CLOCK CONFIGURATIONS

The AD9174 DAC sample clock or device clock (DACCLK) can

be received directly through CLKIN± (Pin H12 and Pin J12) or

generated using an integer PLL/VCO, integrated on-chip, with the

reference clock provided through the same CLKIN± differential

input pins. The DACCLK serves as a reference for all the clock

domains within the AD9174.

The AD9174 uses a low jitter, differential clock receiver that is

capable of interfacing directly to a differential or single-ended

clock source. Because the input is self biased, with a nominal

impedance of 100 , it is recommended that the clock source be

ac-coupled to the CLKIN± input pins. Phase noise performance

can be improved with higher clock input levels (larger swing,

resulting in higher effective slew rate), up to the recommended

maximum limits. Because the DACCLK is the sampling clock

for data within the analog cores (DACx), the quality of the clock

signal at the AD9174 clock input pins is paramount and directly

impacts the analog ac performance of the DAC. Select a clock

source with phase noise and spur characteristics that meet the

target application requirements. Generally, the use of a

PLL/VCO or other clock multipliers, internal or external to the

DAC, also multiplies the resulting phase noise (jitter). The best

phase noise performance is typically achieved using an external

clock running at the desired DAC clock rate, with the PLL/VCO

bypassed.

In cases where low phase noise is not a critical requirement, the

PLL/VCO provides a convenient way to operate the AD9174 at

DAC clock rates as high as 12.4 GHz without the need for

complex, multigigahertz clocking solutions, The PLL reference

frequency at CLKIN± can be typically orders of magnitude

lower than the operating DACCLK rate. The PLL then generates

a control voltage for a downstream VCO, which in effect

multiplies the reference clock up to the desired DACCLK

frequency.

The typical phase noise performance when the AD9174 is directly

clocked and the input clock duty cycle correction is on (enabled by

default) is shown in Figure 88, compared with the phase noise due

to the on-chip PLL/VCO.

–180

–160

–140

–120

–100

–80

–60

–40

–20

10 100 1k 10k 100k 1M 10M 100M

PHASE NOISE (dBc)

FREQUENCY OFFSET (Hz)

PLL OFF (DIRECT CLOCK)

PLL ON (PFD = 491.52MHz)

16794-216

Figure 88. Phase Noise vs. Frequency Offset; Direct Clock and PLL Phase

Noise, 12 GHz DAC Sample Rate, 1.65 GHz Output Frequency

50Ω

CLK+

CLK–

170kΩ

PLL/VCO DCC0

DCC1 TO

DAC1

DAC0

–

OPTIMIZED INPUT

BIAS

16794-050

CLOCK/

PLL MUX

CLOCK/

PLL MUX

Figure 89. Clock Receiver Input Simplified Equivalent Circuit

AD9174 Data Sheet

Rev. B | Page 70 of 165

DAC On-Chip PLL

The AD9174 includes an integer PLL/VCO block that allows

generating a DAC clock (fDAC) from an external reference frequency

(fREF) between 25 MHz and 3080 MHz, applied to the CLKIN±

pins (see Figure 90). When using the on-chip PLL, select the

predivider (M) via Register 0x793, Bits[1:0] to internally divide

the reference frequency to be within the range of 25 MHz to

770 MHz of the phase frequency detector (PFD) circuitry block

input. Enable the DAC PLL synthesizer by setting Register 0x095,

Bit 0 to 0.

The internal VCO operates over a frequency range of 8.74 GHz

to 12.4 GHz, with additional divider settings if a lower DACCLK is

required by the application. The DAC clock rate is user

configurable to be the VCO frequency (8.74 GHz to 12.4 GHz),

the VCO frequency divided by 2 (4.37 GHz to 6.2 GHz), or the

VCO frequency divided by 3 (2.92 GHz to 4.1 GHz) by setting

instructions on how to program the PLL.

To generate the required VCO control voltage from the charge

pump (CP) output, the AD9174 DAC PLL requires an external

loop filter. The recommended filter is a passive low-pass filter of

a topology similar to the one shown in Figure 90. Generally, the

pass band width of the filter (bandwidth) trades off loop response

time during a frequency change with loop stability after the

initial frequency lock occurs. For proper filter layout and

component selection, which results in optimal performance for

most applications, refer to the documentation of the AD9174-

FMC-EBZ evaluation board. The user may however customize

the filter to fit a specific application, according to the PFD

frequency, reference clock phase noise, and DAC output phase

noise requirements. For example, to lower DACCLK jitter when

using the PLL, a higher PFD frequency minimizes the contribution

of in band noise from the PLL. Set the PLL filter bandwidth

such that the in band noise of the PLL intersects with the open-

loop noise of the VCO to minimize the contributions of both

blocks to the overall noise.

The best jitter performance is typically achieved when using an

external, high performance clock source.

The DAC PLL uses an integer type synthesizer to generate the

DACCLK for both DAC0 and DAC1, implying that the

generated DACCLK must be an integer multiple of the input

reference clock. The relationship between DAC clock and the

reference clock is as follows:

fDAC = (8 × N × fREF)/M/(Register 0x094, Bits[1:0] + 1)

where:

fDAC is the desired DAC clock rate.

N is the VCO feedback divider ratio, ranging from 2 to 50.

fREF is the reference clock.

M is the reference clock divider ratio. The valid values for

reference clock divider (predivider) are 1, 2, 3, or 4 by setting

The VCO automatic calibration is triggered by the falling edge

of Register 0x792, Bit 1 transitioning from a logic high to logic

low. A lock detector bit (Register 0x7B5, Bit 0) is provided to

indicate that the DAC PLL achieved lock. If Register 0x7B5,

Bit 0 = 1, the PLL has locked.

PFD CHARGE

PUMP

VCO

÷N ÷8

÷M

CLK

RCVR

÷2

÷L

CLKIN+ CLKIN–

CLK

DRIVER

CLKOUT+ CLKOUT+

DACCLK

N = 2 TO 50

M = 1, 2, 3, 4

PCB

OFF-CHIP FILTER

FILT_COARSE

REG 0x094, BITS[1:0]

REG 0x095, BIT 0

C2 C3

REG 0x799, BITS[5:0]

REG 0x799, BITS[7:6]

L = 1, 2, 3, 4

FILT_VCM

FILT_FINE

÷3

DAC

REG 0x793, BITS[1:0]

16794-051

Figure 90. DAC PLL and Clock Path Block Diagram

Data Sheet AD9174

Rev. B | Page 71 of 165

CLOCK OUTPUT DRIVER

The AD9174 is capable of generating a high quality, divided

down version of the DACCLK, which can be used to clock critical

system components, such as a companion ADC. The integer

clock divider supports divide ratios of 1, 2, 3, and 4 and can be

programmed by Register 0x799, Bits[7:6] to set the desired

output frequency. The 3 dB bandwidth of the clock driver is

between 727.5 MHz and 3 GHz, although frequencies outside

this range can be generated with some penalty to both power

and spurious performance at the clock output.

The clock driver does not have an impact on the performance

of the DACx analog outputs.

ANALOG OUTPUTS

The AD9174 provides two fully independent DAC cores, DAC0

and DAC1, each with a differential output. Figure 91 shows an

equivalent output circuit for a single DAC core. Each output is

internally terminated with a 100 Ω resistor (RINT) that eliminates

the need to resistively terminate the DAC output externally on

the PCB. To properly dc bias the output stage, two RF chokes,

one for each output branch, are required to provide a dc current

path for the standing current of each DACx output. The

inductance value of the choke depends on the desired output

frequency range. In general, a larger choke provides a lower

cutoff output frequency.

Due to parasitic capacitances and inductances at the output, a

constant 100 Ω termination impedance cannot be easily

maintained across the full operating frequency range of the

AD9174, which can be anywhere between dc and >6 GHz,

depending on the application. The output impedance of each

DAC can be determined through measurement. Generally,

when matching the DAC output to a typical single-ended 50 Ω

load, a 2:1 balun is recommended when operating below ~2 GHz.

A 1:1 balun is recommended when operating above ~2 GHz,

which also extends the 3 dB roll-off of the output beyond 4 GHz

with proper PCB layout techniques.

DAC Full-Scale Power

IOUTFS is the full-scale current output at the positive and negative

branch of the DACx output, denoted as IP and IN in Figure 91 to

Figure 93. The default full-scale current is set to 19.531 mA,

although it can be adjusted from 15.625 mA to 25.977 mA by

programming the appropriate value in Register 0x05A.

IOUTFS = 15.625 mA + FSC_CTRL × (25/256) (mA)

As shown in Figure 91 to Figure 93, the amount of power delivered

to an external load depends on multiple factors, such as the IOUTFS

setting, the internal impedance of the DAC, and the external

loading and parasitic inductances and capacitances that the PCB

and other components present at the output. The true power that

can be delivered to a load is determined by measurements.

Alternatively, the DAC output power can be estimated from the

DAC equivalent model, by making certain assumptions about

the parasitic loading presented by a particular PCB design. The

DAC output can be modeled as a pair of dc current sources that

continuously provide dc, set to IOUTFS/2, summed with a parallel

ac source set by the incoming data samples, namely DACCODE,

that are sampled to the analog output at the rate of DACCLK.

Together, the three current sources model the output switch

network internal to each analog output, which define the

instantaneous current out of the positive and negative branches

of each differential output (IP and IN, respectively).

Assuming that parasitic capacitances and inductances are

negligible (which may not always be the case, especially at

output frequencies above ~2 GHz), the output current

presented to the load can be calculated as follows:

IP = (DACCODE + 2N − 1) × ILSB

IN = ((2N − 1 – 1) – DACCODE) × ILSB

and,

ILOAD = (IP – IN) × RINT/(RINT + RLOAD)

where,

ILSB = IOUTFS/2N

DACCODE is a sample value between −2N − 1 and 2N – 1 − 1 (as a

signed decimal representation of twos complement data).

For a single-tone output (pure sinewave), the rms power

delivered to the load can be calculated as follows:

ILOAD(RMS) = ILOAD_MAX/√2

where ILOAD_MAX is the maximum load current delivered at the

maximum DACCODE, as calculated previously, and,

PLOAD (W) = (ILOAD(RMS))2 × RLOAD

PLOAD (dBm) = 10 × log(PLOAD(W ×1000))

MSB Shuffle

Depending on the analog signal level, some or all of the MSB

current sources from the DAC may be static (unused). Particularly

at lower signal levels, when most MSBs are static, any mismatch

errors specific to the few MSBs that are dynamic may appear as

a degradation to spurious performance at the analog outputs.

On average, spurious performance is improved when the active

MSBs are continuously remapped (or shuffled) and randomly

selected from the total number of available MSBs before sampling

at the DACx analog outputs. MSB shuffle is a form of error

averaging. Because the cumulative errors are pseudorandom,

the improved SFDR comes at the expense of higher NSD.

Shuffling is only feasible when there are spare MSBs available

that are otherwise static, so that they can be randomly switched

in. Therefore, the benefit from shuffling is diminished as the

number of dynamic MSBs is increased, such as for signals that

experience frequent peaks near the full-scale current of the

DAC. With a sinusoidal output at full-scale, for example, the

benefit from MSB shuffling is largely nonexistent when

compared to performance with traditional (thermometer)

encoding.

AD9174 Data Sheet

Rev. B | Page 72 of 165

As previously mentioned, MSB shuffling is a form of error

averaging. A particular AD9174 device, with its own auto-

calibration factors and unique production process variations,

may show improved spurious performance at some signal levels

with MSB shuffle disabled. However, when a statically meaningful

set of devices is considered, the overall spurious performance is

shown to improve, on average.

MSB shuffle can be enabled via the MSB_SHUFFLE_EN bit (Bit 4

of Register 0x151).

DC-Coupled Operation

In certain applications, it is desirable to dc couple the analog

outputs to an external device, such as a modulator or a

differential amplifier. The AD9174 analog outputs can be

dc-coupled without performance degradation, as long as the

common-mode voltage (the dc voltage common to both the

positive and negative branches of a particular analog output) is

kept below 100 mV. For ac-coupled operation, the outputs are

typically dc shorted to GND or 0 V through RF chokes or

particular balun configurations.

Elevating the common-mode voltage to between 100 mV and

300 mV leads to performance degradation. Increasing the

common-mode voltage beyond 300 mV may lead to long-

term, irreversible damage of the analog outputs.

Ideally, the common-mode voltage at the analog outputs is kept

near 0 V or GND, while the load impedance seen by the analog

outputs is matched to their internal impedance. Replacing the

RF chokes used in ac-coupled operation with 50 Ω resistors to

GND is not recommended because this results in an excessive

common-mode voltage, near 250 mV. Instead, tie the 50 Ω resistors

to a −0.6 V reference supply, thus maintaining proper dc bias at the

analog output devices internal to each DAC output.

It is possible to resistively match the 0 V common-mode output

voltage of the AD9174 to a nonzero common-mode input voltage

of a downstream device, such as the 0.5 V input common mode

typical to some modulators. This matching inevitably leads to a

loss in the maximum power that can be delivered to the down-

stream device, because some of the power is dissipated in the

resistive matching network.

2:1

1:1 50Ω

LOAD

50Ω

DC I

OUTFS

DC I

OUTFS

AC I

OUTFS

DAC

BALUN

CHOKE

DACx+

DACx–

OUTFS

= 15.625mA TO 25.977mA

16794-052

Figure 91. Equivalent DAC Output Circuit and Recommended DAC Output Network

2:1

1:1 50Ω

LOAD

50Ω

DC IOUTFS/2

AC IOUTFS/2

DAC

BALUN

CHOKE

DACx+

DC PATH

DACx–

IAC

IOUTFS = 15.625mA TO 25.977mA

16794-053

Figure 92. DACx Output, DC Path (AC-Coupled Operation)

50Ω

LOAD

2:1

1:1

50Ω

DC I

OUTFS

DC I

OUTFS

AC I

OUTFS

DAC

BALUN

CHOKE

DACx+

AC I

LOAD

AC I

LOAD

DACx–

AC PATH AC PATH

OUTFS

= 15.625mA TO 25.977mA

16794-054

Figure 93. DACx Output, AC Path (AC-Coupled Operation)

Data Sheet AD9174

Rev. B | Page 73 of 165

APPLICATIONS INFORMATION

HARDWARE CONSIDERATIONS

Power Supply Recommendations

All the AD9174 supply domains must remain as noise free as

possible for the best operation. Power supply noise has a frequency

component that affects performance, and is specified in V rms.

An LC filter on the output of the power supply is recommended

to attenuate the noise, and must be placed as close to the AD9174

as possible. The AVDD1.0 supply, which supplies the clock receiver

and DAC analog core circuitry, and the AVDD1.8 supply, which

powers the DAC output and DAC PLL blocks, are the most noise

sensitive supplies on the device. It is highly recommended that

AVDD1.0 and AVDD1.8 be supplied separately with ultralow

noise regulators, such as the ADP1763 and ADM7154 or better

to achieve the best phase noise performance possible. Noisier

regulators impose phase noise onto the DAC output.

The DVDD1.0 supply provides power to the digital datapath

blocks and the SVDD1.0 supply powers the SERDES circuitry

on the chip. The DVDD1.8 supply powers circuitry blocks

related to the SPI, SYNCOUTx± transmitter, SYSREF receiver,

IRQx, RESET, and TXENx circuitry.

Take note of the maximum power consumption numbers

shown in Table 4 to ensure the power supply design can tolerate

temperature and IC process variation extremes. The amount of

current drawn is dependent on the chosen use cases, and

specifications are provided for several use cases to illustrate

examples and contributions from individual blocks, and to

assist in calculating the maximum required current per supply.

Another consideration for the power supply design is peak

current handling capability. The AD9174 draws more current

in the main digital supply when synthesizing a signal with

significant amplitude variations, such as a modulated signal,

as compared to when in idle mode or synthesizing a dc signal.

Therefore, the power supply must be able to supply current

quickly to accommodate burst signals such as GSM, TDMA,

or other signals that have an on or off time domain response.

Because the amount of current variation depends on the signals

used, it is best to perform lab testing first to establish ranges. A

typical difference can be several hundred milliamperes.

Power and Ground Planes

Solid ground planes are recommended to avoid ground loops

and to provide a solid, uninterrupted ground reference for the

high speed transmission lines that require controlled impedances.

It is recommended that power planes be stacked between ground

layers for high frequency filtering. Doing so adds extra filtering

and isolation between power supply domains in addition to the

decoupling capacitors.

Do not use segmented power planes as a reference for controlled

impedances unless the entire length of the controlled impedance

trace traverses across only a single segmented plane. These and

additional guidelines for the topology of high speed transmission

lines are described in the JESD204B Serial Interface Inputs

(SERDIN0± to SERDIN7±) section.

For some applications, where highest performance and higher

output frequencies are required, the choice of PCB materials

significantly impacts results. For example, materials such as

polyimide or materials from the Rogers Corporation can be

used, for example, to improve tolerance to high temperatures

and improve performance. Rogers 4350 material is used for the

top three layers in some of the evaluation board designs:

between the top signal layer and the ground layer below it.

JESD204B Serial Interface Inputs (SERDIN0± to SERDIN7±)

When considering the layout of the JESD204B serial interface

transmission lines, there are many factors to consider to

maintain optimal link performance. Among these factors are

insertion loss, return loss, signal skew, and the topology of the

differential traces.

Insertion Loss

The JESD204B specification limits the amount of insertion loss

allowed in the transmission channel (see Figure 56). The AD9174

equalization circuitry allows significantly more loss in the channel

than is required by the JESD204B specification. It is still important

that the designer of the PCB minimize the amount of insertion

loss by adhering to the following guidelines:

 Keep the differential traces short by placing the AD9174 as

close to the transmitting logic device as possible and routing

the trace as directly as possible between the devices.

 Route the differential pairs on a single plane using a solid

ground plane as a reference. It is recommended to route

the SERDES lanes on the same layer as the AD9174 to

avoid vias being used in the SERDES lanes.

 Use a PCB material with a low dielectric constant (<4) to

minimize loss, if possible.

When choosing between the stripline and microstrip techniques,

keep in mind the following considerations: stripline has less loss

(see Figure 57 and Figure 58) and emits less EMI, but requires

the use of vias that can add complexity to the task of controlling

the impedance. The microstrip technique is easier to implement

(if the component placement and density allow routing on the

top layer) and eases the task of controlling the impedance.

AD9174 Data Sheet

Rev. B | Page 74 of 165

If using the top layer of the PCB is problematic or the advantages of

stripline are desirable, follow these recommendations:

 Minimize the number of vias.

 If possible, use blind vias to eliminate via stub effects and

use microvias to minimize via inductance.

 If using standard vias, use the maximum via length to

minimize the stub size. For example, on an 8-layer board,

use Layer 7 for the stripline pair (see Figure 94).

 For each via pair, place a pair of ground vias adjacent to them

to minimize the impedance discontinuity (see Figure 94).

LAYER 1

LAYER 2

LAYER 3

LAYER 4

LAYER 5

LAYER 6

LAYER 7

LAYER 8 MINIMIZE STUB EFFECT

GND

DIFF–

DIFF+

ADD GROUND VIAS

STANDARD VIA

16794-046

Figure 94. Minimizing Stub Effect and Adding Ground Vias for Differential

Stripline Traces

Return Loss

The JESD204B specification limits the amount of return loss

allowed in a converter device and a logic device but does not

specify return loss for the channel. However, make every effort

to maintain a continuous impedance on the transmission line

between the transmitting logic device and the AD9174.

Minimizing the use of vias, or eliminating them entirely,

reduces one of the primary sources for impedance mismatches

on a transmission line (see the Insertion Loss section). Maintain

a solid reference beneath (for microstrip) or above and below

(for stripline) the differential traces to ensure continuity in the

impedance of the transmission line. If the stripline technique is

used, follow the guidelines listed in the Insertion Loss section to

minimize impedance mismatches and stub effects.

Another primary source for impedance mismatch is at either

end of the transmission line, where care must be taken to match

the impedance of the termination to that of the transmission

line. The AD9174 handles this matching internally with a

calibrated termination scheme for the receiving end of the line.

See the Interface Power-Up and Input Termination section for

details on this circuit and the calibration routine.

Signal Skew

There are many sources for signal skew, but the two sources to

consider when laying out a PCB are interconnect skew within a

single JESD204B link and skew between multiple JESD204B

links. In each case, keeping the channel lengths matched to

within 10 mm (calculated by 12.5 mm × (12.5 Gbps/15.4 Gbps))

is adequate for operating the JESD204B link at speeds of up to

15.4 Gbps. This amount of channel length match is equivalent

to about 85% UI on the AD9174-FMC-EBZ evaluation board.

Managing the interconnect skew within a single link is

straightforward. Managing multiple links across multiple

devices is more complex. However, follow the 10 mm guideline

for length matching. The AD9174 can handle more skew than

the 85% UI due to the 6 PCLK buffer in the JESD204B receiver,

but matching the channel lengths as close as possible is still

recommended.

To p ol o g y

Structure the differential SERDINx± pairs to achieve 50  to

ground for each half of the pair. Stripline vs. microstrip trade-

offs are described in the Insertion Loss section. In either case, it

is important to keep these transmission lines separated from

potential noise sources, such as high speed digital signals and

noisy supplies. If using stripline differential traces, route them

using a coplanar method, with both traces on the same layer.

Although this method does not offer more noise immunity than

the broadside routing method (traces routed on adjacent

layers), it is easier to route and manufacture so that the

impedance continuity is maintained. Broadside vs. coplanar

differential transmitter (Tx) lines are shown in Figure 95.

Tx DIFF A

DIFF A

DIFF B

ACTIVE

Tx DIFF B Tx ACTIVE

BROADSIDE DIFFERENTIAL Tx LINES COPLANAR DIFFERENTIAL Tx LINES

16794-047

Figure 95. Broadside vs. Coplanar Differential Stripline Routing Techniques

When considering the trace width vs. copper weight and

thickness, the speed of the interface must be considered. At

multigigabit speeds, the skin effect of the conducting material

confines the current flow to the surface. Maximize the surface

area of the conductor by making the trace width wider to

reduce the losses. Additionally, loosely couple differential traces

to accommodate the wider trace widths. This coupling helps

reduce the crosstalk and minimize the impedance mismatch

when the traces must separate to accommodate components,

vias, connectors, or other routing obstacles. Tightly coupled vs.

loosely coupled differential traces are shown in Figure 96.

DIFF A

DIFF B

TIGHTLY COUPLED

DIFFERENTIAL Tx LINES

LOOSELY COUPLED

DIFFERENTIAL Tx LINES

16794-048

Figure 96. Tightly Coupled vs. Loosely Coupled Differential Traces

AC Coupling Capacitors

The AD9174 requires that the JESD204B input signals be

ac-coupled to the source. These capacitors must be 100 nF and

placed as close as possible to the transmitting logic device. To

minimize the impedance mismatch at the pads, select the

package size of the capacitor so that the pad size on the PCB

matches the trace width as closely as possible.

Data Sheet AD9174

Rev. B | Page 75 of 165

SYNCOUT±, SYSREF±, and CLK± Signals

The SYSREF± signal on the AD9174 is a low speed, LVDS,

differential signal. The SYNCOUTx± signals are LVDS or

CMOS selectable. When LVDS mode is selected, use controlled

impedance traces routed as 100  differential impedance and

50  to ground when routing these signals. As with the

SERDIN0± to SERDIN7± data pairs, it is important to keep

these signals separated from potential noise sources, such as

high speed digital signals and noisy supplies. Separate the

SYNCOUTx± signal from other noisy signals because noise on

the SYNCOUTx± may be interpreted as a request for /K/

characters. It is important to keep similar trace lengths for the

CLK± and SYSREF± signals from the clock source to each of

the devices on either end of the JESD204B links (see Figure 97).

If using a clock chip that can tightly control the phase of CLK±

and SYSREF±, the trace length matching requirements are

greatly reduced.

CLOCK SOURCE

(

AD9516-1

ADCLK925

)

LANE 0

LANE 1

LANE N – 1

LANE N

DEVICE CLOCK DEVICE CLOCK

SYSREF±SYSREF±

SYSREF± TRACE LENGTH SYSREF± TRACE LENGTH

DEVICE CLOCK TRACE LENGTHDEVICE CLOCK TRACE LENGTH

DEVICE

16794-049

Figure 97. SYSREF± Signal and Device Clock Trace Length

AD9174 Data Sheet

Rev. B | Page 76 of 165

START-UP SEQUENCE

Several steps are required to program the AD9174 to the proper

operating state after the device is powered up. This sequence is

divided into several steps, and is listed in Table 51 to Table 60,

along with an explanation of the purpose of each step. Private

registers are reserved but must be written for proper operation.

Blank cells or cells with a variable or bit field name (in all

capital letters) in Table 51 to Table 60 indicate that the value

depends on the result as described in the Description column.

Table 51. Power-Up and Required Register Writes

R/W Register Bits Value Description

W 0x000 [7:0] 0x81 Soft reset.

W 0x000 [7:0] 0x3C Release reset and set to 4-wire SPI (optional; leave at the default of the 3-wire SPI).

W 0x091 [7:0] 0x00 Power up clock receiver.

W 0x206 [7:0] 0x01 Take PHYs out of reset.

W 0x705 [7:0] 0x01 Enable boot loader.

W 0x090 [7:0] 0x00 Power on DACs and bias circuitry.

Table 52. DAC PLL Configuration

R/W Register Bits Value Description

W 0x095 [7:0] 0x00 or 0x01 Bypass PLL. Set to 0x00 to use internal DAC PLL. If the user plans to supply the DAC clock

directly, set this register to 0x01 and execute the following two register writes; then, skip

the remaining writes in this table.

W 0x790 [7:0] 0xFF or 0x00 Write this register to 0xFF if bypassing the PLL (Register 0x095 = 0x01). If using the PLL,

write this register to 0x00.

W 0x791 [7:0] 0x1F or 0x00 Write this register to 0xFF if bypassing the PLL (Register 0x095 = 0x01) and then skip the

remaining register writes in this table and continue to Table 53. If using the PLL, write this

W 0x796 [7:0] 0xE5 DAC PLL required write.

W 0x7A0 [7:0] 0xBC DAC PLL required write.

W 0x794 [5:0] DACPLL_CP Set DAC PLL charge pump current. The recommended setting is 0x08, but can range from

0x04 to 0x10 for different phase noise performance targets.

W 0x797 [7:0] 0x10 DAC PLL required write.

W 0x797 [7:0] 0x20 DAC PLL required write.

W 0x798 [7:0] 0x10 DAC PLL required write.

W 0x7A2 [7:0] 0x7F DAC PLL required write.

Pause Wait 100 ms.

W 0x799 DAC PLL divider settings.

[7:6] ADC_CLK_DIVIDER ADC driver/clock output divide ratio.

0b00 = ÷1.

0b01 = ÷2.

0b10 = ÷3.

0b11 = ÷4.

[5:0] N_DIVIDER Programmable N divider. N_DIVIDER = (fDAC  M_DIVIDER)/(8  reference clock).

W 0x793 DAC PLL divider settings.

[7:2] 0x06 Keep default value for these bits.

[1:0] M_DIVIDER_1 Programmable predivider M_DIVIDER_1 (in n − 1 notation). The relevant calculation is as

follows:

PFD Frequency = reference clock/M_DIVIDER

0b00 = ÷1.

0b01 = ÷2.

0b10 = ÷3.

0b11 = ÷4.

Data Sheet AD9174

Rev. B | Page 77 of 165

R/W Register Bits Value Description

W 0x094 [7:2] 0x00 Keep default value for these bits.

1 PLL_VCO_DIV3_EN

Enable PLL output clock to be divided by 3. If this bit is set to 1, DAC clock = PLL VCO

frequency/3.

0 PLL_VCO_DIV2_EN

Enable PLL output clock to be divided by 2. Either this bit or Bit 1 in this register can be set

to 1, but both bits cannot be set at the same time (there is no divide by 6 option).

0b0: DAC clock = PLL VCO frequency.

0b1: DAC clock = PLL VCO frequency/2.

W 0x792 [7:0] 0x02 Reset VCO.

W 0x792 [7:0] 0x00

Pause Wait 100 ms for PLL to lock.

R 0x7B5 0 0b1 Ensure PLL is locked by reading back a value of 1 for bit 0 of this register.

Table 53. Delay Lock Loop (DLL) Configuration

R/W Register Bits Value Description

W 0x0C0 [7:0] 0x00 Power-up delay line.

W 0x0DB [7:0] 0x00

W 0x0DB [7:0] 0x01 Update DLL settings to circuitry.

W 0x0DB [7:0] 0x00

W 0x0C1 [7:0] 0x68 or 0x48 Set DLL search mode. If fDAC is < 4.5 GHz, set this register to 0x48. Otherwise, set this register to 0x68.

W 0x0C1 [7:0] 0x69 or 0x49 Set DLL search mode. If fDAC is < 4.5 GHz, set this register to 0x49. Otherwise, set this register to 0x69.

W 0x0C7 [7:0] 0x01 Enable DLL read status.

R 0x0C3 0 0b1 Ensure DLL is locked by reading back a value of 1 for Bit 0 of this register.

Table 54. Calibration

R/W Register Bits Value Description

W 0x050 [7:0] 0x2A Optimized calibration setting register write.

W 0x061 [7:0] 0x68 Required calibration control register write.

W 0x051 [7:0] 0x82 Optimized calibration setting register write.

W 0x051 [7:0] 0x83 Required calibration control register write.

W 0x081 [7:0] 0x03 Required calibration control register write.

Table 55. JESD204B Mode Setup

R/W Register Bits Value Description

W 0x100 [7:0] 0x00 Power up digital datapath clocks when internal clocks are stable.

W 0x110 [5:0] JESD_MODE Bit 5 of the JESD_MODE bit field determines whether the device is operating in single link

or dual link modes. 0 = single-link mode; 1 = dual-link mode. Bits[4:0] determine the

SERDES JESD204B mode of operation chosen from the appropriate single-link or dual-link

modes in Table 15 or Table 16.

W 0x111 [7:4] DP_INTERP_MODE Main datapath interpolation mode. The valid interpolation options for this control is based on

the JESD_MODE selected in Register 0x110. Bit 7 of Register 0x110 equals 1 if the JESD_MODE,

DP_INTERP_MODE, and CH_INTERP_MODE settings are not a valid combination.

[3:0] CH_INTERP_MODE

Channel datapath interpolation mode. The valid interpolation options for this control is based

on the JESD_MODE selected in Register 0x110. Bit 7 of Register 0x110 equals 1 if the

JESD_MODE, DP_INTERP_MODE, and CH_INTERP_MODE settings are not a valid combination.

W 0x084 6 SYSREF_INPUTMODE SYSREF± signal input mode selection.

0b0 = ac-coupled.

0b1 = dc-coupled.

0 SYSREF_PD If using Subclass 0, this bit can be set to 1 to power down the SYSREF± receiver. If using

Subclass 1, keep at the default of 0.

W 0x312 [7:4] Set SYNCOUTx± error duration, depending on the selected mode.

AD9174 Data Sheet

Rev. B | Page 78 of 165

R/W Register Bits Value Description

W 0x300 3 LINK_MODE Corresponds to the mode selection made in Register 0x110.

0b0 = single-link mode.

0b1 = dual-link mode.

2 0b0 Select Link 0 for setup. This bit selects the link QBD being paged.

0b0 = Link 0 (QBD0).

0b1 = Link 1 (QBD1).

[1:0] LINK_EN Enables the links.

0b01 = single-link mode.

0b11 = dual link mode.

W 0x475 [7:0] 0x09 Soft reset the JESD204B quad-byte deframer.

W 0x453 7 SCR Set scrambling option for SERDES data.

0 = disable scrambling.

1 = enable scrambling.

[4:0] L−1 Write the L value (in n − 1 notation) for the selected JESD_MODE.

W 0x458 [7:5] SUBCLASSV For Subclass 0, set this bit to 0. For Subclass 1, set this bit to 1.

[4:0] NP_1 Write the NP value (in n − 1 notation) for the selected JESD_MODE.

W 0x475 [7:0] 0x01 Bring the JESD204B quad-byte deframer out of reset.

W 0x300 If running in dual link mode, repeat writes for Link 1 as follows. If running in single-link

mode, skip the remaining steps in this table.

3 LINK_MODE Corresponds to the mode selection made in Register 0x110.

0b0 = single-link mode.

0b1 = dual link mode.

2 0b1 Select Link 1 for setup. This bit selects which link QBD is being paged.

0b0 = Link 0 (QBD0).

0b1 = Link 1 (QBD1).

[1:0] 0b00 Keep links disabled until end of routine.

W 0x475 [7:0] 0x09 Soft reset the JESD204B quad-byte deframer.

W 0x453 7 SCR Set scrambling option for SERDES data.

0 = disable scrambling.

1 = enable scrambling.

W 0x458 [4:0] L_1 Write the L value (in n − 1 notation) for the selected JESD_MODE.

[7:5] SUBCLASSV For Subclass 0, set this bit to 0. For Subclass 1, set this bit to 1.

[4:0] NP_1 Write the NP value (in n − 1 notation) for the selected JESD_MODE.

W 0x475 [7:0] 0x01 Bring the JESD204B quad-byte deframer out of reset.

Data Sheet AD9174

Rev. B | Page 79 of 165

Table 56 lists optional registers to configure the channel datapaths if they are being configured for a specific application. If the channel

datapaths are bypassed (CH_INTERP_MODE = 1 for 1 channel interpolation), Table 56 can be skipped in the start-up sequence.

Table 56. Channel Datapath Setup: Digital Gain and Channel NCOs

R/W Register Bits Value Description

W 0x008 [5:0] CHANNEL_PAGE. Select the channels to be programmed at the same time (or repeat this block for each

channel to independently program values). Bit x of this control corresponds to the Channel x datapath.

W 0x146 [7:0] CHNL_GAIN[7:0]. Write LSBs of channel digital gain. Configure digital gain for selected channels in

Paging Register 0x008. Calculation: CHNL_GAIN = 211 × 10(dB Gain/20) where dB Gain is the gain value in

dB for the channel gain desired.

W 0x147 [7:0] CHNL_GAIN[11:8]. Write MSBs of channel digital gain. Calculations shown in Register 0x146.

W 0x130 6 Enable NCO for selected channels in paging Register 0x008.

0b0 = disable NCO.

0b1 = enable NCO.

2 Enable NCO modulus for selected channels in paging Register 0x008.

0b0 = disable NCO modulus.

0b1 = enable NCO modulus.

1 Select sideband from modulation result.

0b0 = upper sideband.

0b1 = lower sideband (spectral flip).

0 If dc test mode or NCO test mode is desired, set this bit to 1 to enable the test tone generation.

Otherwise, set this bit to the default value of 0.

Integer NCO mode calculation: DDSC_FTW = (fCARRIER/fNCO)  248, where fNCO = fDATA/CH_INTERP_MODE.

W 0x132 [7:0] Write DDSC_FTW[7:0].

W 0x133 [7:0] Write DDSC_FTW[15:8].

W 0x134 [7:0] Write DDSC_FTW[23:16].

W 0x135 [7:0] Write DDSC_FTW[31:24].

W 0x136 [7:0] Write DDSC_FTW[39:32].

W 0x137 [7:0] Write DDSC_FTW[47:40].

W 0x138 [7:0] Write DDSC_NCO_PHASE_OFFSET[7:0]. Calculation: DDSC_NCO_PHASE_OFFSET = (Degrees Offset/180)  215.

W 0x139 [7:0] Write DDSC_NCO_PHASE_OFFSET[15:8].

If using NCO modulus mode, also program modulus parameters. If not, skip this section. For modulus

NCO mode: (fCARRIER/fNCO) = (X + (A/B))/248 where DDSC_ACC_DELTA = A, DDSC_ACC_MODULUS = B, and

DDSC_FTW = X.

W 0x13A [7:0] Write DDSC_ACC_MODULUS[7:0].

W 0x13B [7:0] Write DDSC_ACC_MODULUS[15:8].

W 0x13C [7:0] Write DDSC_ACC_MODULUS[23:16].

W 0x13D [7:0] Write DDSC_ACC_MODULUS[31:24].

W 0x13E [7:0] Write DDSC_ACC_MODULUS[39:32].

W 0x13F [7:0] Write DDSC_ACC_MODULUS[47:40].

W 0x140 [7:0] Write DDSC_ACC_DELTA[7:0].

W 0x141 [7:0] Write DDSC_ACC_DELTA[15:8].

W 0x142 [7:0] Write DDSC_ACC_DELTA[23:16].

W 0x143 [7:0] Write DDSC_ACC_DELTA[31:24].

W 0x144 [7:0] Write DDSC_ACC_DELTA[39:32].

W 0x145 [7:0] Write DDSC_ACC_DELTA[47:40].

W 0x131 0 0b1 Update all NCO phase and FTW words.

AD9174 Data Sheet

Rev. B | Page 80 of 165

Table 57 lists optional registers to configure the main DAC datapaths if they are being configured for a specific application. If the main

DAC datapaths are bypassed (DP_INTERP_MODE = 1 for 1 channel interpolation), Table 57 can be skipped in the start-up sequence.

Table 57. Main DAC Datapath Setup: PA Protect and Main NCOs

R/W Register Bits Value Description

W 0x008 [7:6] MAINDAC_PAGE. Select the main DAC datapath to be programmed at the same time (or repeat this

block for each DAC datapath to independently program values). Bit x of this control corresponds to the

DAC x datapath.

W 0x112 3 Enable NCO for selected channels in paging Register 0x008.

0b0 = disable NCO.

0b1 = enable NCO.

2 Enable NCO modulus for selected channels in paging Register 0x008.

0b0 = disable NCO modulus.

0b1 = enable NCO modulus.

1 Select sideband from modulation result.

0b0 = upper sideband.

0b1 = lower sideband (spectral flip).

0 Set this bit to 0.

Integer NCO mode calculation: DDSM_FTW = (fCARRIER/fDAC)  248.

W 0x114 [7:0] Write DDSM_FTW[7:0].

W 0x115 [7:0] Write DDSM_FTW[15:8].

W 0x116 [7:0] Write DDSM_FTW[23:16].

W 0x117 [7:0] Write DDSM_FTW[31:24].

W 0x118 [7:0] Write DDSM_FTW[39:32].

W 0x119 [7:0] Write DDSM_FTW[47:40].

W 0x11C [7:0] Write DDSM_NCO_PHASE_OFFSET[7:0]. Calculation: DDSM_NCO_PHASE_OFFSET = (degrees offset/180) × 215.

W 0x11D [7:0] Write DDSM_NCO_PHASE_OFFSET[15:8].

If using NCO modulus mode, also program modulus parameters. If not, skip this section. For modulus

NCO mode: (fCARRIER/fDAC) = (X + (A/B))/248, where DDSM_ACC_DELTA = A, DDSM_ACC_MODULUS = B, and

DDSM_FTW = X.

W 0x124 [7:0] Write DDSM_ACC_MODULUS[7:0].

W 0x125 [7:0] Write DDSM_ACC_MODULUS[15:8].

W 0x126 [7:0] Write DDSM_ACC_MODULUS[23:16].

W 0x127 [7:0] Write DDSM_ACC_MODULUS[31:24].

W 0x128 [7:0] Write DDSM_ACC_MODULUS[39:32].

W 0x129 [7:0] Write DDSM_ACC_MODULUS[47:40].

W 0x12A [7:0] Write DDSM_ACC_DELTA[7:0].

W 0x12B [7:0] Write DDSM_ACC_DELTA[15:8].

W 0x12C [7:0] Write DDSM_ACC_DELTA[23:16].

W 0x12D [7:0] Write DDSM_ACC_DELTA[31:24].

W 0x12E [7:0] Write DDSM_ACC_DELTA[39:32].

W 0x12F [7:0] Write DDSM_ACC_DELTA[47:40].

W 0x113 0 0b1 Update all NCO phase and FTW words.

Data Sheet AD9174

Rev. B | Page 81 of 165

Table 58. JESD204B SERDES Required Interface Setup

R/W Register Bits Value Description

W 0x240 [7:0]

0xAA or

0xFF

EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤

11 dB, set to 0xAA; otherwise, set to 0xFF.

W 0x241 [7:0]

0xAA or

0xFF

EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤

11 dB, set to 0xAA; otherwise, set to 0xFF.

W 0x242 [7:0]

0x55 or

0xFF

EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤

11 dB, set to 0x55; otherwise, set to 0xFF.

W 0x243 [7:0]

0x55 or

0xFF

EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤

11 dB, set to 0x55; otherwise, set to 0xFF.

W 0x244 [7:0] 0x1F EQ settings.

W 0x245 [7:0] 0x1F EQ settings.

W 0x246 [7:0] 0x1F EQ settings.

W 0x247 [7:0] 0x1F EQ settings.

W 0x248 [7:0] 0x1F EQ settings.

W 0x249 [7:0] 0x1F EQ settings.

W 0x24A [7:0] 0x1F EQ settings.

W 0x24B [7:0] 0x1F EQ settings.

W 0x201 [7:0] Power down unused PHYs. Bit x corresponds to SERDINx± pin power-down.

W 0x203 If in single-link mode, set to 0x01. If in dual-link mode and using both SYNCOUTx± signals, set to 0x00.

1 0b0 Power up SYNCOUT0± driver by setting this bit to 0.

0 Power up SYNCOUT1± driver by setting this bit to 0 if using dual link and both SYNCOUTx± signals.

W 0x253 [7:0] 0x01 Set SYNCOUT0± to be LVDS output. For CMOS output on SYNCOUT0+, set Bit 0 to 0.

W 0x254 [7:0] 0x01 Set SYNCOUT1± to be LVDS output. For CMOS output on SYNCOUT1+, set Bit 0 to 0.

W 0x210 [7:0] 0x16 SERDES required register write.

W 0x216 [7:0] 0x05 SERDES required register write.

W 0x212 [7:0] 0xFF SERDES required register write.

W 0x212 [7:0] 0x00 SERDES required register write.

W 0x210 [7:0] 0x87 SERDES required register write.

W 0x216 [7:0] 0x11 SERDES required register write.

W 0x213 [7:0] 0x01 SERDES required register write.

W 0x213 [7:0] 0x00 SERDES required register write.

W 0x200 [7:0] 0x00 Power up the SERDES circuitry blocks.

Pause Wait 100 ms.

W 0x210 [7:0] 0x86 SERDES required register write.

W 0x216 [7:0] 0x40 SERDES required register write.

W 0x213 [7:0] 0x01 SERDES required register write.

W 0x213 [7:0] 0x00 SERDES required register write.

W 0x210 [7:0] 0x86 SERDES required register write.

W 0x216 [7:0] 0x00 SERDES required register write.

W 0x213 [7:0] 0x01 SERDES required register write.

W 0x213 [7:0] 0x00 SERDES required register write.

W 0x210 [7:0] 0x87 SERDES required register write.

W 0x216 [7:0] 0x01 SERDES required register write.

W 0x213 [7:0] 0x01 SERDES required register write.

W 0x213 [7:0] 0x00 SERDES required register write.

W 0x280 [7:0] 0x05 SERDES required register write.

W 0x280 [7:0] 0x01 Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration.

R 0x281 0 0b1 Ensure Bit 0 of this register reads back 1 to indicate the SERDSES PLL is locked.

AD9174 Data Sheet

Rev. B | Page 82 of 165

Crossbar mapping writes the SERDINx input pin that is the source for each given logical lane in these registers. A value of x corresponds

to mapping data from the SERDINx± pin to the logical lane of the control bit field. The values in Table 59 vary with different PCB layout

routing.

Table 59. Transport Layer Setup, Synchronization, and Enable Links

R/W Register Bits Value Description

W 0x308 [7:0] Crossbar setup. Program the physical lane value that is providing data (the source) for each of the

logical lanes. [5:3] = Logical Lane 1 source, [2:0] = Logical Lane 0 source.

W 0x309 [7:0] [5:3] = Logical Lane 3 source, [2:0] = Logical Lane 2 source.

W 0x30A [7:0] [5:3] = Logical Lane 5 source, [2:0] = Logical Lane 4 source.

W 0x30B [7:0] [5:3] = Logical Lane 7 source, [2:0] = Logical Lane 6 source.

W 0x306 [7:0] 0x0C If operating in Subclass 0, this register write is not needed.

W 0x307 [7:0] 0x0C If operating in Subclass 0, this register write is not needed.

W 0x304 [7:0] If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be

determined by following one of the deterministic latency methods (with or without known

delays), as mentioned in the Link Delay section.

W 0x305 [7:0] If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be

determined by following one of the deterministic latency methods (with or without known

delays), as mentioned in the Link Delay section.

W 0x03B [7:0] 0xF1 Enable the sync logic, and set the rotation mode to reset the synchronization logic upon a sync

reset trigger.

W 0x03A [7:0] 0x02 Set up sync for one-shot sync mode.

SYSREF± If operating in Subclass 1, send SYSREF± pulse edges to the device for synchronization alignment.

W 0x300 3 LINK_MODE Corresponds to the mode selection made in Register 0x110.

0b0 = single-link mode.

0b1 = dual-link mode.

2 0b0 Select Link 0 for setup. This bit selects which link QBD is being paged.

0b0 = Link 0 (QBD0).

0b1 = Link 1 (QBD1).

[1:0] LINK_EN Enables the links.

0b01 = single-link mode

0b11 = dual-link mode.

Table 60. Cleanup Registers

R/W Register Bits Value Description

W 0x085 [7:0] 0x13 Set to the default register value.

W 0x1DE [7:0] 0x00 Disable analog SPI. To debug and continue readback capability, write 0x03.

W 0x008 [7:0] 0xC0 Page all main DACs for TXEN control update.

W 0x596 [7:0] 0x0C SPI turn on TXENx feature.

Data Sheet AD9174

Rev. B | Page 83 of 165

Table 61. Register Summary

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x000 SPI_INTFCONFA SOFTRESET_M LSBFIRST_M ADDRINC_M SDOACTIVE_M SDOACTIVE ADDRINC LSBFIRST SOFTRESET 0x00 R/W

0x001 SPI_INTFCONFB SINGLEINS CSSTALL RESERVED 0x00 R/W

0x003 SPI_CHIPTYPE CHIP_TYPE 0x04 R

0x004 SPI_PRODIDL PROD_ID[7:0] 0x72 R

0x005 SPI_PRODIDH PROD_ID[15:8] 0x91 R

0x006 SPI_CHIPGRADE PROD_GRADE DEV_REVISION 0x04 R

0x008 SPI_PAGEINDX MAINDAC_PAGE CHANNEL_PAGE 0xFF R/W

0x00A SPI_

SCRATCHPAD

SCRATCHPAD 0x00 R/W

0x010 CHIP_ID_L CHIP_ID[7:0] 0x00 R

0x011 CHIP_ID_M1 CHIP_ID[15:8] 0x00 R

0x012 CHIP_ID_M2 CHIP_ID[23:16] 0x00 R

0x013 CHIP_ID_H CHIP_ID[31:24] 0x00 R

0x020 IRQ_ENABLE RESERVED EN_SYSREF_

JITTER

EN_DATA_

READY

EN_LANE_

FIFO

EN_PRBSQ EN_PRBSI 0x00 R/W

0x021 IRQ_ENABLE0 RESERVED EN_DAC0_

CAL_DONE

RESERVED EN_PAERR0 0x00 R/W

0x022 IRQ_ENABLE1 RESERVED EN_DAC1_

CAL_DONE

RESERVED EN_PAERR1 0x00 R/W

0x023 IRQ_ENABLE2 RESERVED EN_DLL_LOST EN_DLL_LOCK RESERVED EN_PLL_

LOST

EN_PLL_

LOCK

0x00 R/W

0x024 IRQ_STATUS RESERVED IRQ_SYSREF_

JITTER

IRQ_DATA_

READY

IRQ_

LANE_FIFO

IRQ_PRBSQ IRQ_PRBSI 0x00 R/W

0x025 IRQ_STATUS0 RESERVED IRQ_DAC0_

CAL_DONE

RESERVED IRQ_

PAERR0

0x00 R/W

0x026 IRQ_STATUS1 RESERVED IRQ_DAC1_

CAL_DONE

RESERVED IRQ_

PAERR1

0x00 R/W

0x027 IRQ_STATUS2 RESERVED IRQ_DLL_LOST IRQ_DLL_

LOCK

RESERVED IRQ_PLL_

LOST

IRQ_PLL_

LOCK

0x00 R/W

0x028 IRQ_OUTPUT_

MUX

RESERVED MUX_

SYSREF_

JITTER

MUX_

DATA_

READY

MUX_

LANE_FIFO

MUX_

PRBSQ

MUX_

PRBSI

0x00 R/W

0x029 IRQ_OUTPUT_

MUX0

RESERVED MUX_

DAC0_

CAL_DONE

RESERVED MUX_

PAERR0

0x00 R/W

0x02A IRQ_OUTPUT_

MUX1

RESERVED MUX_

DAC1_CAL_

DONE

RESERVED MUX_

PAERR1

0x00 R/W

0x02B IRQ_OUTPUT_

MUX2

RESERVED MUX_DLL_

LOST

MUX_DLL_

LOCK

RESERVED MUX_PLL_

LOST

MUX_PLL_

LOCK

0x00 R/W

0x02C IRQ_STATUS_

ALL

RESERVED IRQ_

STATUS_ALL

0x00 R/W

0x036 SYSREF_COUNT SYSREF_COUNT 0x00 R/W

0x039 SYSREF_ERR_

WINDOW

RESERVED SYSREF_ERR_WINDOW 0x00 R/W

0x03A SYSREF_MODE RESERVED SYNC_

ROTATION_

DONE

RESERVED SYSREF_

MODE_

ONESHOT

RESERVED 0x10 R/W

0x03B ROTATION_

MODE

SYNCLOGIC_

RESERVED PERIODIC_

RST_EN

NCORST_

AFTER_ROT_EN

RESERVED ROTATION_MODE 0xB0 R/W

0x03F TX_ENABLE RESERVED TXEN_

DATAPATH_

DAC1

TXEN_

DATAPATH_

DAC0

RESERVED 0x00 R/W

0x050 CAL_CLK_DIV RESERVED CAL_CLK_DIV 0x28 R/W

0x051 CAL_CTRL CAL_CTRL0 RESERVED CAL_CTRL1 CAL_START 0x82 R/W

0x052 CAL_STAT RESERVED CAL_ACTIVE CAL_FAIL_

CAL_FINISH 0x00 R/W

0x05A FSC1 FSC_CTRL[7:0] 0x28 R/W

0x061 CAL_DEBUG0 RESERVED CAL_CTRL2 CAL_CTRL3 RESERVED CAL_CTRL4 RESERVED 0x60 R/W

0x081 CLK_CTRL RESERVED CAL_CLK_

PD1

CAL_CLK_

PD0

0x00 R/W

0x083 NVM_CTRL0 NVM_CTRL0A RESERVED NVM_CTRL0B 0x02 R/W

0x084 SYSREF_CTRL RESERVED SYSREF_

INPUTMODE

RESERVED SYSREF_PD 0x00 R/W

AD9174 Data Sheet

Rev. B | Page 84 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x085 NVM_CTRL1 RESERVED NVM_CTRL1A RESERVED NVM_

CTRL1B

NVM_

CTRL1C

0x13 R/W

0x08D ADC_CLK_

CTRL0

RESERVED CLKOUT_SWING 0x00 R/W

0x08F ADC_CLK_

CTRL2

RESERVED PD_

CLKOUT_

DRIVER

0x00 R/W

0x090 DAC_

POWERDOWN

RESERVED DAC_PD1 DAC_PD0 0x03 R/W

0x091 ACLK_CTRL RESERVED ACLK_

POWER-

DOWN

0x01 R/W

0x094 PLL_CLK_DIV RESERVED PLL_VCO_

DIV3_EN

PLL_VCO_

DIV2_EN

0x00 R/W

0x095 PLL_BYPASS RESERVED PLL_

BYPASS

0x00 R/W

0x09A NVM_CTRL PD_BGR RESERVED 0x00 R/W

0x0C0 DELAY_LINE_PD RESERVED DLL_CTRL0B DLL_CTRL0A RESERVED DLL_PD 0x31 R/W

0x0C1 DLL_CTRL0 DLL_CTRL1C DLL_CTRL1B DLL_CTRL1A RESERVED DLL_

ENABLE

0x70 R/W

0x0C3 DLL_STATUS RESERVED DLL_LOCK 0x00 R/W

0x0C7 DLL_READ RESERVED DLL_

READ_EN

0x00 R/W

0x0CC DLL_FINE_

DELAY0

RESERVED DLL_FINE_DELAY0 0x00 R/W

0x0CD DLL_FINE_

DELAY1

RESERVED DLL_FINE_DELAY1 0x00 R/W

0x0DB DLL_UPDATE RESERVED DLL_

DELAY_

UPDATE

0x00 R/W

0x0FF MOD_SWITCH_

DEBUG

RESERVED CMPLX_

MOD_DIV2_

DISABLE

RESERVED 0x00 R/W

0x100 DIG_RESET RESERVED DIG_

DATAPATH_

0x01 R/W

0x110 JESD_MODE MODE_NOT_

IN_TABLE

COM_SYNC JESD_MODE 0x20 R/W

0x111 INTRP_MODE DP_INTERP_MODE CH_INTERP_MODE 0x84 R/W

0x112 DDSM_

DATAPATH_CFG

RESERVED EN_CMPLX_

MOD

DDSM_MODE DDSM_

NCO_EN

DDSM_

MODULUS_

DDSM_SEL_

SIDEBAND

EN_SYNC_

ALL_CHNL_

NCO_

RESETS

0x01 R/W

0x113 DDSM_FTW_

UPDATE

RESERVED DDSM_FTW_REQ_MODE RESERVED DDSM_

FTW_

LOAD_

SYSREF

DDSM_

FTW_

LOAD_ACK

DDSM_

FTW_

LOAD_REQ

0x00 R/W

0x114 DDSM_FTW0 DDSM_FTW[7:0] 0x00 R/W

0x115 DDSM_FTW1 DDSM_FTW[15:8] 0x00 R/W

0x116 DDSM_FTW2 DDSM_FTW[23:16] 0x00 R/W

0x117 DDSM_FTW3 DDSM_FTW[31:24] 0x00 R/W

0x118 DDSM_FTW4 DDSM_FTW[39:32] 0x00 R/W

0x119 DDSM_FTW5 DDSM_FTW[47:40] 0x00 R/W

0x11C DDSM_PHASE_

OFFSET0

DDSM_NCO_PHASE_OFFSET[7:0] 0x00 R/W

0x11D DDSM_PHASE_

OFFSET1

DDSM_NCO_PHASE_OFFSET[15:8] 0x00 R/W

0x124 DDSM_ACC_

MODULUS0

DDSM_ACC_MODULUS[7:0] 0x00 R/W

0x125 DDSM_ACC_

MODULUS1

DDSM_ACC_MODULUS[15:8] 0x00 R/W

0x126 DDSM_ACC_

MODULUS2

DDSM_ACC_MODULUS[23:16] 0x00 R/W

0x127 DDSM_ACC_

MODULUS3

DDSM_ACC_MODULUS[31:24] 0x00 R/W

0x128 DDSM_ACC_

MODULUS4

DDSM_ACC_MODULUS[39:32] 0x00 R/W

0x129 DDSM_ACC_

MODULUS5

DDSM_ACC_MODULUS[47:40] 0x00 R/W

0x12A DDSM_ACC_

DELTA0

DDSM_ACC_DELTA[7:0] 0x00 R/W

Data Sheet AD9174

Rev. B | Page 85 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x12B DDSM_ACC_

DELTA1

DDSM_ACC_DELTA[15:8] 0x00 R/W

0x12C DDSM_ACC_

DELTA2

DDSM_ACC_DELTA[23:16] 0x00 R/W

0x12D DDSM_ACC_

DELTA3

DDSM_ACC_DELTA[31:24] 0x00 R/W

0x12E DDSM_ACC_

DELTA4

DDSM_ACC_DELTA[39:32] 0x00 R/W

0x12F DDSM_ACC_

DELTA5

DDSM_ACC_DELTA[47:40] 0x00 R/W

0x130 DDSC_

DATAPATH_

CFG

RESERVED DDSC_NCO_

RESERVED DDSC_

MODULUS_

DDSC_

SEL_

SIDEBAND

DDSC_EN_

DC_INPUT

0x00 R/W

0x131 DDSC_FTW_

UPDATE

RESERVED DDSC_

FTW_

LOAD_

SYSREF

DDSC_

FTW_

LOAD_ACK

DDSC_

FTW_

LOAD_REQ

0x00 R/W

0x132 DDSC_FTW0 DDSC_FTW[7:0] 0x00 R/W

0x133 DDSC_FTW1 DDSC_FTW[15:8] 0x00 R/W

0x134 DDSC_FTW2 DDSC_FTW[23:16] 0x00 R/W

0x135 DDSC_FTW3 DDSC_FTW[31:24] 0x00 R/W

0x136 DDSC_FTW4 DDSC_FTW[39:32] 0x00 R/W

0x137 DDSC_FTW5 DDSC_FTW[47:40] 0x00 R/W

0x138 DDSC_PHASE_

OFFSET0

DDSC_NCO_PHASE_OFFSET[7:0] 0x00 R/W

0x139 DDSC_PHASE_

OFFSET1

DDSC_NCO_PHASE_OFFSET[15:8] 0x00 R/W

0x13A DDSC_ACC_

MODULUS0

DDSC_ACC_MODULUS[7:0] 0x00 R/W

0x13B DDSC_ACC_

MODULUS1

DDSC_ACC_MODULUS[15:8] 0x00 R/W

0x13C DDSC_ACC_

MODULUS2

DDSC_ACC_MODULUS[23:16] 0x00 R/W

0x13D DDSC_ACC_

MODULUS3

DDSC_ACC_MODULUS[31:24] 0x00 R/W

0x13E DDSC_ACC_

MODULUS4

DDSC_ACC_MODULUS[39:32] 0x00 R/W

0x13F DDSC_ACC_

MODULUS5

DDSC_ACC_MODULUS[47:40] 0x00 R/W

0x140 DDSC_ACC_

DELTA0

DDSC_ACC_DELTA[7:0] 0x00 R/W

0x141 DDSC_ACC_

DELTA1

DDSC_ACC_DELTA[15:8] 0x00 R/W

0x142 DDSC_ACC_

DELTA2

DDSC_ACC_DELTA[23:16] 0x00 R/W

0x143 DDSC_ACC_

DELTA3

DDSC_ACC_DELTA[31:24] 0x00 R/W

0x144 DDSC_ACC_

DELTA4

DDSC_ACC_DELTA[39:32] 0x00 R/W

0x145 DDSC_ACC_

DELTA5

DDSC_ACC_DELTA[47:40] 0x00 R/W

0x146 CHNL_GAIN0 CHNL_GAIN[7:0] 0x00 R/W

0x147 CHNL_GAIN1 RESERVED CHNL_GAIN[11:8] 0x08 R/W

0x148 DC_CAL_TONE0 DC_TEST_INPUT_AMPLITUDE[7:0] 0x00 R/W

0x149 DC_CAL_TONE1 DC_TEST_INPUT_AMPLITUDE[15:8] 0x00 R/W

0x14B PRBS PRBS_

GOOD_Q

PRBS_

GOOD_I

RESERVED PRBS_INV_Q PRBS_INV_I PRBS_MODE PRBS_RESET PRBS_EN 0x10 R/W

0x14C PRBS_ERROR_I PRBS_COUNT_I 0x00 R

0x14D PRBS_ERROR_Q PRBS_COUNT_Q 0x00 R

0x14E PRBS_CHANSEL RESERVED PRBS_CHANSEL 0x07 R/W

0x151 DECODE_MODE RESERVED MSB_SHUFFLE_

RESERVED 0x00 R/W

0x1DE SPI_ENABLE RESERVED SPI_EN1 SPI_EN0 0x03 R/W

0x1E2 DDSM_CAL_

FTW0

DDSM_CAL_FTW[7:0] 0x00 R/W

0x1E3 DDSM_CAL_

FTW1

DDSM_CAL_FTW[15:8] 0x00 R/W

0x1E4 DDSM_CAL_

FTW2

DDSM_CAL_FTW[23:16] 0x00 R/W

AD9174 Data Sheet

Rev. B | Page 86 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x1E5 DDSM_CAL_

FTW3

DDSM_CAL_FTW[31:24] 0x00 R/W

0x1E6 DDSM_CAL_

MODE_DEF

RESERVED DDSM_EN_

CAL_ACC

DDSM_EN_

CAL_DC_

INPUT

DDSM_EN_

CAL_

FREQ_

TUNE

0x00 R/W

0x1E7 DATAPATH_

NCO_

SYNC_CFG

RESERVED ALL_NCO_

SYNC_ACK

START_

NCO_SYNC

0x00 R/W

0x200 MASTER_PD RESERVED SERDES_

MASTER_PD

0x01 R/W

0x201 PHY_PD PHY_PD 0xEE R/W

0x203 GENERIC_PD RESERVED PD_

SYNCOUT0

PD_

SYNCOUT1

0x01 R/W

0x206 CDR_RESET RESERVED CDR_PHY_

RESET

0x00 R/W

0x210 CBUS_ADDR SERDES_CBUS_ADDR 0x00 R/W

0x212 CBUS_

WRSTROBE_PHY

SERDES_CBUS_WR0 0x00 R/W

0x213 CBUS_

WRSTROBE_

OTHER

RESERVED SERDES_

CBUS_WR1

0x00 R/W

0x216 CBUS_WDATA SERDES_CBUS_DATA 0x00 R/W

0x234 CDR_

BITINVERSE

SEL_IF_PARDATAINV_DES_RC_CH 0x66 R/W

0x240 EQ_BOOST_

PHY_3_0

EQ_BOOST_PHY3 EQ_BOOST_PHY2 EQ_BOOST_PHY1 EQ_BOOST_PHY0 0xFF R/W

0x241 EQ_BOOST_

PHY_7_4

EQ_BOOST_PHY7 EQ_BOOST_PHY6 EQ_BOOST_PHY5 EQ_BOOST_PHY4 0xFF R/W

0x242 EQ_GAIN_

PHY_3_0

EQ_GAIN_PHY3 EQ_GAIN_PHY2 EQ_GAIN_PHY1 EQ_GAIN_PHY0 0xFF R/W

0x243 EQ_GAIN_

PHY_7_4

EQ_GAIN_PHY7 EQ_GAIN_PHY6 EQ_GAIN_PHY5 EQ_GAIN_PHY4 0xFF R/W

0x244 EQ_FB_PHY_0 RESERVED EQ_PHY_0 0x19 R/W

0x245 EQ_FB_PHY_1 RESERVED EQ_PHY1 0x19 R/W

0x246 EQ_FB_PHY_2 RESERVED EQ_PHY2 0x19 R/W

0x247 EQ_FB_PHY_3 RESERVED EQ_PHY3 0x19 R/W

0x248 EQ_FB_PHY_4 RESERVED EQ_PHY4 0x19 R/W

0x249 EQ_FB_PHY_5 RESERVED EQ_PHY5 0x19 R/W

0x24A EQ_FB_PHY_6 RESERVED EQ_PHY6 0x19 R/W

0x24B EQ_FB_PHY_7 RESERVED EQ_PHY7 0x19 R/W

0x250 LBT_REG_

CNTRL_0

EN_LBT_DES_RC_CH 0x00 R/W

0x251 LBT_REG_

CNTRL_1

RESERVED EN_LBT_

HALFRATE_

DES_RC

INIT_LBT_

SYNC_

DES_RC

0x02 R/W

0x253 SYNCOUT0_

CTRL

RESERVED SEL_

SYNCOUT0

_MODE

0x00 R/W

0x254 SYNCOUT1_

CTRL

RESERVED SEL_

SYNCOUT1

_MODE

0x00 R/W

0x280 PLL_ENABLE_

CTRL

RESERVED LOLSTICKY-

CLEAR_

LCPLL_RC

LDSYNTH_

LCPLL_RC

SERDES_

PLL_

STARTUP

0x01 R/W

0x281 PLL_STATUS RESERVED SERDES_

PLL_LOCK

0x00 R

0x300 GENERAL_JRX_

CTRL_0

RESERVED LINK_MODE LINK_PAGE LINK_EN 0x00 R/W

0x302 DYN_LINK_

LATENCY_0

RESERVED DYN_LINK_LATENCY_0 0x00 R

0x303 DYN_LINK_

LATENCY_1

RESERVED DYN_LINK_LATENCY_1 0x00 R

0x304 LMFC_DELAY_0 RESERVED LMFC_DELAY_0 0x00 R/W

0x305 LMFC_DELAY_1 RESERVED LMFC_DELAY_1 0x00 R/W

0x306 LMFC_VAR_0 RESERVED LMFC_VAR_0 0x3F R/W

0x307 LMFC_VAR_1 RESERVED LMFC_VAR_1 0x3F R/W

0x308 XBAR_LN_0_1 RESERVED LOGICAL_LANE1_SRC LOGICAL_LANE0_SRC 0x08 R/W

0x309 XBAR_LN_2_3 RESERVED LOGICAL_LANE3_SRC LOGICAL_LANE2_SRC 0x1A R/W

0x30A XBAR_LN_4_5 RESERVED LOGICAL_LANE5_SRC LOGICAL_LANE4_SRC 0x2C R/W

Data Sheet AD9174

Rev. B | Page 87 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x30B XBAR_LN_6_7 RESERVED LOGICAL_LANE7_SRC LOGICAL_LANE6_SRC 0x3E R/W

0x30C FIFO_STATUS_

REG_0

LANE_FIFO_FULL 0x00 R

0x30D FIFO_STATUS_

REG_1

LANE_FIFO_EMPTY 0x00 R

0x311 SYNCOUT_

GEN_0

RESERVED EOMF_

MASK_1

EOMF_

MASK_0

EOF_

MASK_1

EOF_

MASK_0

0x00 R/W

0x312 SYNCOUT_

GEN_1

SYNC_ERR_DUR RESERVED 0x00 R/W

0x315 PHY_PRBS_

TEST_EN

PHY_TEST_EN 0x00 R/W

0x316 PHY_PRBS_

TEST_CTRL

RESERVED PHY_SRC_ERR_CNT PHY_PRBS_PAT_SEL PHY_TEST_

START

PHY_TEST_

RESET

0x00 R/W

0x317 PHY_PRBS_

TEST_

THRESHOLD_

LOBITS

PHY_PRBS_THRESHOLD_LOBITS 0x00 R/W

0x318 PHY_PRBS_

TEST_

THRESHOLD_

MIDBITS

PHY_PRBS_THRESHOLD_MIDBITS 0x00 R/W

0x319 PHY_PRBS_

TEST_

THRESHOLD_

HIBITS

PHY_PRBS_THRESHOLD_HIBITS 0x00 R/W

0x31A PHY_PRBS_

TEST_ERRCNT_

LOBITS

PHY_PRBS_ERR_CNT_LOBITS 0x00 R

0x31B PHY_PRBS_

TEST_ERRCNT_

MIDBITS

PHY_PRBS_ERR_CNT_MIDBITS 0x00 R

0x31C PHY_PRBS_

TEST_ERRCNT_

HIBITS

PHY_PRBS_ERR_CNT_HIBITS 0x00 R

0x31D PHY_PRBS_

TEST_STATUS

PHY_PRBS_PASS 0xFF R

0x31E PHY_DATA_

SNAPSHOT_

CTRL

RESERVED PHY_GRAB_

MODE

PHY_GRAB_

DATA

0x00 R/W

0x31F PHY_

SNAPSHOT_

DATA_BYTE0

PHY_SNAPSHOT_DATA_BYTE0 0x00 R

0x320 PHY_

SNAPSHOT_

DATA_BYTE1

PHY_SNAPSHOT_DATA_BYTE1 0x00 R

0x321 PHY_

SNAPSHOT_

DATA_BYTE2

PHY_SNAPSHOT_DATA_BYTE2 0x00 R

0x322 PHY_

SNAPSHOT_

DATA_BYTE3

PHY_SNAPSHOT_DATA_BYTE3 0x00 R

0x323 PHY_

SNAPSHOT_

DATA_BYTE4

PHY_SNAPSHOT_DATA_BYTE4 0x00 R

0x32C SHORT_TPL_

TEST_0

SHORT_TPL_SP_SEL SHORT_TPL_CHAN_SEL SHORT_TPL_

TEST_RESET

SHORT_TPL_

TEST_EN

0x00 R/W

0x32D SHORT_TPL_

TEST_1

SHORT_TPL_REF_SP_LSB 0x00 R/W

0x32E SHORT_TPL_

TEST_2

SHORT_TPL_REF_SP_MSB 0x00 R/W

0x32F SHORT_TPL_

TEST_3

SHORT_TPL_

LINK_SEL

SHORT_TPL_

IQ_SAMPLE_

SEL

RESERVED SHORT_

TPL_FAIL

0x00 R/W

0x334 JESD_BIT_

INVERSE_CTRL

JESD_BIT_INVERSE 0x00 R/W

0x400 DID_REG DID_RD 0x00 R

0x401 BID_REG BID_RD 0x00 R

0x402 LID0_REG RESERVED ADJDIR_RD PHADJ_RD LL_LID0 0x00 R

0x403 SCR_L_REG SCR_RD RESERVED L_RD_1 0x00 R

0x404 F_REG F_RD_1 0x00 R

0x405 K_REG RESERVED K_RD_1 0x00 R

0x406 M_REG M_RD_1 0x00 R

AD9174 Data Sheet

Rev. B | Page 88 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x407 CS_N_REG CS_RD RESERVED N_RD_1 0x00 R

0x408 NP_REG SUBCLASSV_RD NP_RD_1 0x00 R

0x409 S_REG JESDV_RD_1 S_RD_1 0x00 R

0x40A HD_CF_REG HD_RD RESERVED CF_RD 0x00 R

0x40B RES1_REG RES1_RD 0x00 R

0x40C RES2_REG RES2_RD 0x00 R

0x40D CHECKSUM0_

REG

LL_FCHK0 0x00 R

0x40E COMPSUM0_

REG

LL_FCMP0 0x00 R

0x412 LID1_REG RESERVED LL_LID1 0x00 R

0x415 CHECKSUM1_

REG

LL_FCHK1 0x00 R

0x416 COMPSUM1_

REG

LL_FCMP1 0x00 R

0x41A LID2_REG RESERVED LL_LID2 0x00 R

0x41D CHECKSUM2_

REG

LL_FCHK2 0x00 R

0x41E COMPSUM2_

REG

LL_FCMP2 0x00 R

0x422 LID3_REG RESERVED LL_LID3 0x00 R

0x425 CHECKSUM3_

REG

LL_FCHK3 0x00 R

0x426 COMPSUM3_

REG

LL_FCMP3 0x00 R

0x42A LID4_REG RESERVED LL_LID4 0x00 R

0x42D CHECKSUM4_

REG

LL_FCHK4 0x00 R

0x42E COMPSUM4_

REG

LL_FCMP4 0x00 R

0x432 LID5_REG RESERVED LL_LID5 0x00 R

0x435 CHECKSUM5_

REG

LL_FCHK5 0x00 R

0x436 COMPSUM5_

REG

LL_FCMP5 0x00 R

0x43A LID6_REG RESERVED LL_LID6 0x00 R

0x43D CHECKSUM6_

REG

LL_FCHK6 0x00 R

0x43E COMPSUM6_

REG

LL_FCMP6 0x00 R

0x442 LID7_REG RESERVED LL_LID7 0x00 R

0x445 CHECKSUM7_

REG

LL_FCHK7 0x00 R

0x446 COMPSUM7_

REG

LL_FCMP7 0x00 R

0x450 ILS_DID DID 0x00 R/W

0x451 ILS_BID BID 0x00 R/W

0x452 ILS_LID0 RESERVED ADJDIR PHADJ LID0 0x00 R/W

0x453 ILS_SCR_L SCR RESERVED L_1 0x87 R/W

0x454 ILS_F F_1 0x00 R/W

0x455 ILS_K RESERVED K_1 0x1F R/W

0x456 ILS_M M_1 0x01 R/W

0x457 ILS_CS_N CS RESERVED N_1 0x0F R/W

0x458 ILS_NP SUBCLASSV NP_1 0x0F R/W

0x459 ILS_S JESDV S_1 0x01 R/W

0x45A ILS_HD_CF HD RESERVED CF 0x80 R

0x45B ILS_RES1 RES1 0x00 R/W

0x45C ILS_RES2 RES2 0x00 R/W

0x45D ILS_CHECKSUM FCHK0 0x00 R/W

0x46C LANE_DESKEW ILD7 ILD6 ILD5 ILD4 ILD3 ILD2 ILD1 ILD0 0x00 R

0x46D BAD_DISPARITY BDE7 BDE6 BDE5 BDE4 BDE3 BDE2 BDE1 BDE0 0x00 R

0x46E NOT_IN_TABLE NIT7 NIT6 NIT5 NIT4 NIT3 NIT2 NIT1 NIT0 0x00 R

0x46F UNEXPECTED_

KCHAR

UEK7 UEK6 UEK5 UEK4 UEK3 UEK2 UEK1 UEK0 0x00 R

0x470 CODE_GRP_

SYNC

CGS7 CGS6 CGS5 CGS4 CGS3 CGS2 CGS1 CGS0 0x00 R

0x471 FRAME_SYNC FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 0x00 R

Data Sheet AD9174

Rev. B | Page 89 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x472 GOOD_

CHECKSUM

CKS7 CKS6 CKS5 CKS4 CKS3 CKS2 CKS1 CKS0 0x00 R

0x473 INIT_LANE_

SYNC

ILS7 ILS6 ILS5 ILS4 ILS3 ILS2 ILS1 ILS0 0x00 R

0x475 CTRLREG0 RESERVED SOFTRST FORCE-

SYNCREQ

RESERVED REPL_FRM_

ENA

0x01 R/W

0x476 CTRLREG1 RESERVED QUAL_RDERR RESERVED FCHK_N 0x14 R/W

0x477 CTRLREG2 ILS_MODE RESERVED REPDATATEST QUETESTERR AR_ECNTR RESERVED 0x00 R/W

0x478 KVAL KSYNC 0x01 R/W

0x47C ERRORTHRES ETH 0xFF R/W

0x47D SYNC_ASSERT_

MASK

RESERVED SYNC_ASSERT_MASK 0x07 R/W

0x480 ECNT_CTRL0 RESERVED ECNT_ENA0 ECNT_RST0 0x3F R/W

0x481 ECNT_CTRL1 RESERVED ECNT_ENA1 ECNT_RST1 0x3F R/W

0x482 ECNT_CTRL2 RESERVED ECNT_ENA2 ECNT_RST2 0x3F R/W

0x483 ECNT_CTRL3 RESERVED ECNT_ENA3 ECNT_RST3 0x3F R/W

0x484 ECNT_CTRL4 RESERVED ECNT_ENA4 ECNT_RST4 0x3F R/W

0x485 ECNT_CTRL5 RESERVED ECNT_ENA5 ECNT_RST5 0x3F R/W

0x486 ECNT_CTRL6 RESERVED ECNT_ENA6 ECNT_RST6 0x3F R/W

0x487 ECNT_CTRL7 RESERVED ECNT_ENA7 ECNT_RST7 0x3F R/W

0x488 ECNT_TCH0 RESERVED ECNT_TCH0 0x07 R/W

0x489 ECNT_TCH1 RESERVED ECNT_TCH1 0x07 R/W

0x48A ECNT_TCH2 RESERVED ECNT_TCH2 0x07 R/W

0x48B ECNT_TCH3 RESERVED ECNT_TCH3 0x07 R/W

0x48C ECNT_TCH4 RESERVED ECNT_TCH4 0x07 R/W

0x48D ECNT_TCH5 RESERVED ECNT_TCH5 0x07 R/W

0x48E ECNT_TCH6 RESERVED ECNT_TCH6 0x07 R/W

0x48F ECNT_TCH7 RESERVED ECNT_TCH7 0x07 R/W

0x490 ECNT_STAT0 RESERVED LANE_ENA0 ECNT_TCR0 0x00 R

0x491 ECNT_STAT1 RESERVED LANE_ENA1 ECNT_TCR1 0x00 R

0x492 ECNT_STAT2 RESERVED LANE_ENA2 ECNT_TCR2 0x00 R

0x493 ECNT_STAT3 RESERVED LANE_ENA3 ECNT_TCR3 0x00 R

0x494 ECNT_STAT4 RESERVED LANE_ENA4 ECNT_TCR4 0x00 R

0x495 ECNT_STAT5 RESERVED LANE_ENA5 ECNT_TCR5 0x00 R

0x496 ECNT_STAT6 RESERVED LANE_ENA6 ECNT_TCR6 0x00 R

0x497 ECNT_STAT7 RESERVED LANE_ENA7 ECNT_TCR7 0x00 R

0x4B0 LINK_STATUS0 BDE0 NIT0 UEK0 ILD0 ILS0 CKS0 FS0 CGS0 0x00 R

0x4B1 LINK_STATUS1 BDE1 NIT1 UEK1 ILD1 ILS1 CKS1 FS1 CGS1 0x00 R

0x4B2 LINK_STATUS2 BDE2 NIT2 UEK2 ILD2 ILS2 CKS2 FS2 CGS2 0x00 R

0x4B3 LINK_STATUS3 BDE3 NIT3 UEK3 ILD3 ILS3 CKS3 FS3 CGS3 0x00 R

0x4B4 LINK_STATUS4 BDE4 NIT4 UEK4 ILD4 ILS4 CKS4 FS4 CGS4 0x00 R

0x4B5 LINK_STATUS5 BDE5 NIT5 UEK5 ILD5 ILS5 CKS5 FS5 CGS5 0x00 R

0x4B6 LINK_STATUS6 BDE6 NIT6 UEK6 ILD6 ILS6 CKS6 FS6 CGS6 0x00 R

0x4B7 LINK_STATUS7 BDE7 NIT7 UEK7 ILD7 ILS7 CKS7 FS7 CGS7 0x00 R

0x4B8 JESD_IRQ_

ENABLEA

EN_BDE EN_NIT EN_UEK EN_ILD EN_ILS EN_CKS EN_FS EN_CGS 0x00 R/W

0x4B9 JESD_IRQ_

ENABLEB

RESERVED EN_ILAS 0x00 R/W

0x4BA JESD_IRQ_

STATUSA

IRQ_BDE IRQ_NIT IRQ_UEK IRQ_ILD IRQ_ILS IRQ_CKS IRQ_FS IRQ_CGS 0x00 R/W

0x4BB JESD_IRQ_

STATUSB

RESERVED IRQ_ILAS 0x00 R/W

0x4BC IRQ_OUTPUT_

MUX_JESD

RESERVED MUX_JESD_

IRQ

0x00 R/W

0x580 BE_SOFT_OFF_

GAIN_CTRL

BE_SOFT_

OFF_GAIN_

RESERVED BE_GAIN_RAMP_RATE 0x00 R/W

0x581 BE_SOFT_OFF_

ENABLE

ENA_SHORT_

PAERR_

SOFTOFF

ENA_LONG_

PAERR_

SOFTOFF

RESERVED ENA_JESD_

ERR_

SOFTOFF

ROTATE_

SOFT_OFF_

TXEN_SOFT_

OFF_EN

SPI_SOFT_

OFF_EN

0xC6 R/W

0x582 BE_SOFT_ON_

ENABLE

SPI_SOFT_

ON_EN

LONG_LEVEL_

SOFTON_EN

RESERVED 0x40 R/W

0x583 LONG_PA_

THRES_LSB

LONG_PA_THRESHOLD[7:0] 0x00 R/W

0x584 LONG_PA_

THRES_MSB

RESERVED LONG_PA_THRESHOLD[12:8] 0x00 R/W

AD9174 Data Sheet

Rev. B | Page 90 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x585 LONG_PA_

CONTROL

LONG_PA_

ENABLE

RESERVED LONG_PA_AVG_TIME 0x00 R/W

0x586 LONG_PA_

POWER_LSB

LONG_PA_POWER[7:0] 0x00 R

0x587 LONG_PA_

POWER_MSB

RESERVED LONG_PA_POWER[12:8] 0x00 R

0x588 SHORT_PA_

THRES_LSB

SHORT_PA_THRESHOLD[7:0] 0x00 R/W

0x589 SHORT_PA_

THRES_MSB

RESERVED SHORT_PA_THRESHOLD[12:8] 0x00 R/W

0x58A SHORT_PA_

CONTROL

SHORT_PA_

ENABLE

RESERVED SHORT_PA_AVG_TIME 0x00 R/W

0x58B SHORT_PA_

POWER_LSB

SHORT_PA_POWER[7:0] 0x00 R

0x58C SHORT_PA_

POWER_MSB

RESERVED SHORT_PA_POWER[12:8] 0x00 R

0x58D TXEN_SM_0 RESERVED ENA_

TXENSM

0x50 R/W

0x596 BLANKING_

CTRL

RESERVED SPI_TXEN ENA_SPI_

TXEN

RESERVED 0x00 R/W

0x597 JESD_PA_INT0 JESD_PA_INT_CNTRL[7:0] 0x00 R/W

0x598 JESD_PA_INT1 RESERVED JESD_PA_

INT_

CNTRL[8]

0x00 R/W

0x599 TXEN_FLUSH_

CTRL0

RESERVED SPI_FLUSH_

0x01 R/W

0x705 NVM_LOADER_

RESERVED NVM_BLR_

0x00 R/W

0x790 DACPLL_

PDCTRL0

PLL_PD5 PLL_PD4 PLL_PD3 PLL_PD2 PLL_PD1 PLL_PD0 0x02 R/W

0x791 DACPLL_

PDCTRL1

RESERVED PLL_PD10 PLL_PD9 PLL_PD8 PLL_PD7 PLL_PD6 0x00 R/W

0x792 DACPLL_CTRL0 RESERVED D_CAL_

RESET

D_RESET_

VCO_DIV

0x02 R/W

0x793 DACPLL_CTRL1 RESERVED M_DIVIDER-1 0x18 R/W

0x794 DACPLL_CTRL2 RESERVED DACPLL_CP 0x04 R/W

0x795 DACPLL_CTRL3 RESERVED D_CP_CALBITS 0x08 R/W

0x796 DACPLL_CTRL4 PLL_CTRL0 RESERVED 0xD2 R/W

0x797 DACPLL_CTRL5 RESERVED PLL_CTRL1 0x20 R/W

0x798 DACPLL_CTRL6 RESERVED PLL_CTRL3 PLL_CTRL2 0x1C R/W

0x799 DACPLL_CTRL7 ADC_CLK_DIVIDER N_DIVIDER 0x08 R/W

0x7A0 DACPLL_CTRL9 RESERVED D_EN_VAR_

FINE_PRE

RESERVED D_EN_VAR_

COARSE_

PRE

RESERVED 0x90 R/W

0x7A2 DACPLL_

CTRL10

RESERVED D_REGULATOR_CAL_WAIT D_VCO_CAL_WAIT D_VCO_CAL_CYCLES RESERVED 0x35 R/W

0x7B5 PLL_STATUS RESERVED PLL_LOCK 0x00 R

0x800 DDSM_

HOPF_CTRL

HOPF_MODE RESERVED HOPF_SEL 0x00 R/W

0x806 DDSM_

HOPF_FTW1_0

HOPF_FTW1[7:0] 0x00 R/W

0x807 DDSM_

HOPF_FTW1_1

HOPF_FTW1[15:8] 0x00 R/W

0x808 DDSM_

HOPF_FTW1_2

HOPF_FTW1[23:16] 0x00 R/W

0x809 DDSM_

HOPF_FTW1_3

HOPF_FTW1[31:24] 0x00 R/W

0x80A DDSM_

HOPF_FTW2_0

HOPF_FTW2[7:0] 0x00 R/W

0x80B DDSM_

HOPF_FTW2_1

HOPF_FTW2[15:8] 0x00 R/W

0x80C DDSM_

HOPF_FTW2_2

HOPF_FTW2[23:16] 0x00 R/W

0x80D DDSM_

HOPF_FTW2_3

HOPF_FTW2[31:24] 0x00 R/W

0x80E DDSM_

HOPF_FTW3_0

HOPF_FTW3[7:0] 0x00 R/W

0x80F DDSM_

HOPF_FTW3_1

HOPF_FTW3[15:8] 0x00 R/W

Data Sheet AD9174

Rev. B | Page 91 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x810 DDSM_

HOPF_FTW3_2

HOPF_FTW3[23:16] 0x00 R/W

0x811 DDSM_

HOPF_FTW3_3

HOPF_FTW3[31:24] 0x00 R/W

0x812 DDSM_

HOPF_FTW4_0

HOPF_FTW4[7:0] 0x00 R/W

0x813 DDSM_

HOPF_FTW4_1

HOPF_FTW4[15:8] 0x00 R/W

0x814 DDSM_

HOPF_FTW4_2

HOPF_FTW4[23:16] 0x00 R/W

0x815 DDSM_

HOPF_FTW4_3

HOPF_FTW4[31:24] 0x00 R/W

0x816 DDSM_

HOPF_FTW5_0

HOPF_FTW5[7:0] 0x00 R/W

0x817 DDSM_

HOPF_FTW5_1

HOPF_FTW5[15:8] 0x00 R/W

0x818 DDSM_

HOPF_FTW5_2

HOPF_FTW5[23:16] 0x00 R/W

0x819 DDSM_

HOPF_FTW5_3

HOPF_FTW5[31:24] 0x00 R/W

0x81A DDSM_

HOPF_FTW6_0

HOPF_FTW6[7:0] 0x00 R/W

0x81B DDSM_

HOPF_FTW6_1

HOPF_FTW6[15:8] 0x00 R/W

0x81C DDSM_

HOPF_FTW6_2

HOPF_FTW6[23:16] 0x00 R/W

0x81D DDSM_

HOPF_FTW6_3

HOPF_FTW6[31:24] 0x00 R/W

0x81E DDSM_

HOPF_FTW7_0

HOPF_FTW7[7:0] 0x00 R/W

0x81F DDSM_

HOPF_FTW7_1

HOPF_FTW7[15:8] 0x00 R/W

0x820 DDSM_

HOPF_FTW7_2

HOPF_FTW7[23:16] 0x00 R/W

0x821 DDSM_

HOPF_FTW7_3

HOPF_FTW7[31:24] 0x00 R/W

0x822 DDSM_

HOPF_FTW8_0

HOPF_FTW8[7:0] 0x00 R/W

0x823 DDSM_

HOPF_FTW8_1

HOPF_FTW8[15:8] 0x00 R/W

0x824 DDSM_

HOPF_FTW8_2

HOPF_FTW8[23:16] 0x00 R/W

0x825 DDSM_

HOPF_FTW8_3

HOPF_FTW8[31:24] 0x00 R/W

0x826 DDSM_

HOPF_FTW9_0

HOPF_FTW9[7:0] 0x00 R/W

0x827 DDSM_

HOPF_FTW9_1

HOPF_FTW9[15:8] 0x00 R/W

0x828 DDSM_

HOPF_FTW9_2

HOPF_FTW9[23:16] 0x00 R/W

0x829 DDSM_

HOPF_FTW9_3

HOPF_FTW9[31:24] 0x00 R/W

0x82A DDSM_

HOPF_FTW10_0

HOPF_FTW10[7:0] 0x00 R/W

0x82B DDSM_

HOPF_FTW10_1

HOPF_FTW10[15:8] 0x00 R/W

0x82C DDSM_

HOPF_FTW10_2

HOPF_FTW10[23:16] 0x00 R/W

0x82D DDSM_

HOPF_FTW10_3

HOPF_FTW10[31:24] 0x00 R/W

0x82E DDSM_

HOPF_FTW11_0

HOPF_FTW11[7:0] 0x00 R/W

0x82F DDSM_

HOPF_FTW11_1

HOPF_FTW11[15:8] 0x00 R/W

0x830 DDSM_

HOPF_FTW11_2

HOPF_FTW11[23:16] 0x00 R/W

0x831 DDSM_

HOPF_FTW11_3

HOPF_FTW11[31:24] 0x00 R/W

0x832 DDSM_

HOPF_FTW12_0

HOPF_FTW12[7:0] 0x00 R/W

AD9174 Data Sheet

Rev. B | Page 92 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x833 DDSM_

HOPF_FTW12_1

HOPF_FTW12[15:8] 0x00 R/W

0x834 DDSM_

HOPF_FTW12_2

HOPF_FTW12[23:16] 0x00 R/W

0x835 DDSM_

HOPF_FTW12_3

HOPF_FTW12[31:24] 0x00 R/W

0x836 DDSM_

HOPF_FTW13_0

HOPF_FTW13[7:0] 0x00 R/W

0x837 DDSM_

HOPF_FTW13_1

HOPF_FTW13[15:8] 0x00 R/W

0x838 DDSM_

HOPF_FTW13_2

HOPF_FTW13[23:16] 0x00 R/W

0x839 DDSM_

HOPF_FTW13_3

HOPF_FTW13[31:24] 0x00 R/W

0x83A DDSM_

HOPF_FTW14_0

HOPF_FTW14[7:0] 0x00 R/W

0x83B DDSM_

HOPF_FTW14_1

HOPF_FTW14[15:8] 0x00 R/W

0x83C DDSM_

HOPF_FTW14_2

HOPF_FTW14[23:16] 0x00 R/W

0x83D DDSM_

HOPF_FTW14_3

HOPF_FTW14[31:24] 0x00 R/W

0x83E DDSM_

HOPF_FTW15_0

HOPF_FTW15[7:0] 0x00 R/W

0x83F DDSM_

HOPF_FTW15_1

HOPF_FTW15[15:8] 0x00 R/W

0x840 DDSM_

HOPF_FTW15_2

HOPF_FTW15[23:16] 0x00 R/W

0x841 DDSM_

HOPF_FTW15_3

HOPF_FTW15[31:24] 0x00 R/W

0x842 DDSM_

HOPF_FTW16_0

HOPF_FTW16[7:0] 0x00 R/W

0x843 DDSM_

HOPF_FTW16_1

HOPF_FTW16[15:8] 0x00 R/W

0x844 DDSM_

HOPF_FTW16_2

HOPF_FTW16[23:16] 0x00 R/W

0x845 DDSM_

HOPF_FTW16_3

HOPF_FTW16[31:24] 0x00 R/W

0x846 DDSM_

HOPF_FTW17_0

HOPF_FTW17[7:0] 0x00 R/W

0x847 DDSM_

HOPF_FTW17_1

HOPF_FTW17[15:8] 0x00 R/W

0x848 DDSM_

HOPF_FTW17_2

HOPF_FTW17[23:16] 0x00 R/W

0x849 DDSM_

HOPF_FTW17_3

HOPF_FTW17[31:24] 0x00 R/W

0x84A DDSM_

HOPF_FTW18_0

HOPF_FTW18[7:0] 0x00 R/W

0x84B DDSM_

HOPF_FTW18_1

HOPF_FTW18[15:8] 0x00 R/W

0x84C DDSM_

HOPF_FTW18_2

HOPF_FTW18[23:16] 0x00 R/W

0x84D DDSM_

HOPF_FTW18_3

HOPF_FTW18[31:24] 0x00 R/W

0x84E DDSM_

HOPF_FTW19_0

HOPF_FTW19[7:0] 0x00 R/W

0x84F DDSM_

HOPF_FTW19_1

HOPF_FTW19[15:8] 0x00 R/W

0x850 DDSM_

HOPF_FTW19_2

HOPF_FTW19[23:16] 0x00 R/W

0x851 DDSM_

HOPF_FTW19_3

HOPF_FTW19[31:24] 0x00 R/W

0x852 DDSM_

HOPF_FTW20_0

HOPF_FTW20[7:0] 0x00 R/W

0x853 DDSM_

HOPF_FTW20_1

HOPF_FTW20[15:8] 0x00 R/W

0x854 DDSM_

HOPF_FTW20_2

HOPF_FTW20[23:16] 0x00 R/W

0x855 DDSM_

HOPF_FTW20_3

HOPF_FTW20[31:24] 0x00 R/W

Data Sheet AD9174

Rev. B | Page 93 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x856 DDSM_

HOPF_FTW21_0

HOPF_FTW21[7:0] 0x00 R/W

0x857 DDSM_

HOPF_FTW21_1

HOPF_FTW21[15:8] 0x00 R/W

0x858 DDSM_

HOPF_FTW21_2

HOPF_FTW21[23:16] 0x00 R/W

0x859 DDSM_

HOPF_FTW21_3

HOPF_FTW21[31:24] 0x00 R/W

0x85A DDSM_

HOPF_FTW22_0

HOPF_FTW22[7:0] 0x00 R/W

0x85B DDSM_

HOPF_FTW22_1

HOPF_FTW22[15:8] 0x00 R/W

0x85C DDSM_

HOPF_FTW22_2

HOPF_FTW22[23:16] 0x00 R/W

0x85D DDSM_

HOPF_FTW22_3

HOPF_FTW22[31:24] 0x00 R/W

0x85E DDSM_

HOPF_FTW23_0

HOPF_FTW23[7:0] 0x00 R/W

0x85F DDSM_

HOPF_FTW23_1

HOPF_FTW23[15:8] 0x00 R/W

0x860 DDSM_

HOPF_FTW23_2

HOPF_FTW23[23:16] 0x00 R/W

0x861 DDSM_

HOPF_FTW23_3

HOPF_FTW23[31:24] 0x00 R/W

0x862 DDSM_

HOPF_FTW24_0

HOPF_FTW24[7:0] 0x00 R/W

0x863 DDSM_

HOPF_FTW24_1

HOPF_FTW24[15:8] 0x00 R/W

0x864 DDSM_

HOPF_FTW24_2

HOPF_FTW24[23:16] 0x00 R/W

0x865 DDSM_

HOPF_FTW24_3

HOPF_FTW24[31:24] 0x00 R/W

0x866 DDSM_

HOPF_FTW25_0

HOPF_FTW25[7:0] 0x00 R/W

0x867 DDSM_

HOPF_FTW25_1

HOPF_FTW25[15:8] 0x00 R/W

0x868 DDSM_

HOPF_FTW25_2

HOPF_FTW25[23:16] 0x00 R/W

0x869 DDSM_

HOPF_FTW25_3

HOPF_FTW25[31:24] 0x00 R/W

0x86A DDSM_

HOPF_FTW26_0

HOPF_FTW26[7:0] 0x00 R/W

0x86B DDSM_

HOPF_FTW26_1

HOPF_FTW26[15:8] 0x00 R/W

0x86C DDSM_

HOPF_FTW26_2

HOPF_FTW26[23:16] 0x00 R/W

0x86D DDSM_

HOPF_FTW26_3

HOPF_FTW26[31:24] 0x00 R/W

0x86E DDSM_

HOPF_FTW27_0

HOPF_FTW27[7:0] 0x00 R/W

0x86F DDSM_

HOPF_FTW27_1

HOPF_FTW27[15:8] 0x00 R/W

0x870 DDSM_

HOPF_FTW27_2

HOPF_FTW27[23:16] 0x00 R/W

0x871 DDSM_

HOPF_FTW27_3

HOPF_FTW27[31:24] 0x00 R/W

0x872 DDSM_

HOPF_FTW28_0

HOPF_FTW28[7:0] 0x00 R/W

0x873 DDSM_

HOPF_FTW28_1

HOPF_FTW28[15:8] 0x00 R/W

0x874 DDSM_

HOPF_FTW28_2

HOPF_FTW28[23:16] 0x00 R/W

0x875 DDSM_

HOPF_FTW28_3

HOPF_FTW28[31:24] 0x00 R/W

0x876 DDSM_

HOPF_FTW29_0

HOPF_FTW29[7:0] 0x00 R/W

0x877 DDSM_

HOPF_FTW29_1

HOPF_FTW29[15:8] 0x00 R/W

0x878 DDSM_

HOPF_FTW29_2

HOPF_FTW29[23:16] 0x00 R/W

AD9174 Data Sheet

Rev. B | Page 94 of 165

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x879 DDSM_

HOPF_FTW29_3

HOPF_FTW29[31:24] 0x00 R/W

0x87A DDSM_

HOPF_FTW30_0

HOPF_FTW30[7:0] 0x00 R/W

0x87B DDSM_

HOPF_FTW30_1

HOPF_FTW30[15:8] 0x00 R/W

0x87C DDSM_

HOPF_FTW30_2

HOPF_FTW30[23:16] 0x00 R/W

0x87D DDSM_

HOPF_FTW30_3

HOPF_FTW30[31:24] 0x00 R/W

0x87E DDSM_

HOPF_FTW31_0

HOPF_FTW31[7:0] 0x00 R/W

0x87F DDSM_

HOPF_FTW31_1

HOPF_FTW31[15:8] 0x00 R/W

0x880 DDSM_

HOPF_FTW31_2

HOPF_FTW31[23:16] 0x00 R/W

0x881 DDSM_

HOPF_FTW31_3

HOPF_FTW31[31:24] 0x00 R/W

Data Sheet AD9174

Rev. B | Page 95 of 165

Table 62. Register Details

Addr. Name Bits Bit Name Settings Description Reset Access

0x000 SPI_INTFCONFA 7 SOFTRESET_M Soft reset (mirror). Set this bit to mirror Bit 0. 0x0 R

6 LSBFIRST_M LSB first (mirror). Set this bit to mirror Bit 1. 0x0 R

5 ADDRINC_M Address increment (mirror). Set this bit to

mirror Bit 2.

0x0 R

4 SDOACTIVE_M SDO active (mirror). Set this bit to mirror Bit 3. 0x0 R

3 SDOACTIVE SDO active. Enables 4-wire SPI bus mode. 0x0 R/W

2 ADDRINC Address increment. When set, this bit

causes incrementing streaming addresses;

otherwise, descending addresses are

generated.

0x0 R/W

1 Streaming addresses are incremented.

0 Streaming addresses are decremented.

1 LSBFIRST LSB first. When set, this bit causes SPI input

and output data to be oriented as LSB first.

If this bit is clear, data is oriented as MSB first.

0x0 R/W

1 Shift LSB in first.

0 Shift MSB in first.

0 SOFTRESET Soft reset. This bit automatically clears to 0

after performing a reset operation. Setting

this bit initiates a reset. This bit autoclears

after the soft reset is complete.

0x0 R/W

1 Pulse the soft reset line.

0 Reset the soft reset line.

0x001 SPI_INTFCONFB 7 SINGLEINS Single instruction. 0x0 R/W

1 Perform single transfers.

0 Perform multiple transfers.

CSSTALL CS stalling. 0x0 R/W

0 Disable CS stalling.

1 Enable CS stalling.

[5:0] RESERVED Reserved. 0x0 R/W

0x003 SPI_CHIPTYPE [7:0] CHIP_TYPE Chip type. 0x4 R

0x004 SPI_PRODIDL [7:0] PROD_ID[7:0] Product ID. Updated once the bootloader

completes

0x72 R

0x005 SPI_PRODIDH [7:0] PROD_ID[15:8] Product ID. Updated once the bootloader

completes

0x91 R

0x006 SPI_CHIPGRADE [7:4] PROD_GRADE Product grade. 0x0 R

[3:0] DEV_REVISION Device revision. 0x4 R

0x008 SPI_PAGEINDX [7:6] MAINDAC_PAGE Sets the main DAC paging. Each high bit in

this field pages a DAC starting at the LSB.

Both main DACs can be paged and

programmed at the same time if desired.

0x3 R/W

[5:0] CHANNEL_PAGE Sets channel paging. Each high bit in this

field pages a complex channel starting at

the LSB. Multiple channels can be paged

and programmed at a time if desired.

0x3F R/W

0x00A SPI_SCRATCHPAD [7:0] SCRATCHPAD Scratch pad read/write register. 0x0 R/W

0x010 CHIP_ID_L [7:0] CHIP_ID[7:0] Chip ID serial number. 0x0 R

0x011 CHIP_ID_M1 [7:0] CHIP_ID[15:8] Chip ID serial number. 0x0 R

0x012 CHIP_ID_M2 [7:0] CHIP_ID[23:16] Chip ID serial number. 0x0 R

0x013 CHIP_ID_H [7:0] CHIP_ID[31:24] Chip ID serial number. 0x0 R

AD9174 Data Sheet

Rev. B | Page 96 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x020 IRQ_ENABLE [7:5] RESERVED Reserved. 0x0 R

4 EN_SYSREF_JITTER Enable SYSREF± jitter interrupt. 0x0 R/W

3 EN_DATA_READY Enable JESD204B receiver ready

(JRX_DATA_READY) low interrupt.

0x0 R/W

2 EN_LANE_FIFO Enable lane FIFO overflow/underflow

interrupt.

0x0 R/W

1 EN_PRBSQ Enable PRBS imaginary error interrupt. 0x0 R/W

0 EN_PRBSI Enable PRBS real error interrupt. 0x0 R/W

0x021 IRQ_ENABLE0 [7:4] RESERVED Reserved. 0x0 R

EN_DAC0_CAL_

DONE

Enable DAC0 calibration complete interrupt. 0x0 R/W

[2:1] RESERVED Reserved. 0x0 R/W

0 EN_PAERR0 Enable PA protection error interrupt for

DAC0.

0x0 R/W

0x022 IRQ_ENABLE1 [7:4] RESERVED Reserved. 0x0 R

EN_DAC1_CAL_

DONE

Enable DAC1 calibration complete interrupt. 0x0 R/W

[2:1] RESERVED Reserved. 0x0 R/W

0 EN_PAERR1 Enable PA protection error interrupt for

DAC1.

0x0 R/W

0x023 IRQ_ENABLE2 [7:6] RESERVED Reserved. 0x0 R

5 EN_DLL_LOST Enable DLL lock lost interrupt. 0x0 R/W

4 EN_DLL_LOCK Enable DLL lock interrupt. 0x0 R/W

[3:2] RESERVED Reserved. 0x0 R/W

1 EN_PLL_LOST Enable PLL lock lost interrupt. 0x0 R/W

0 EN_PLL_LOCK Enable PLL lock interrupt. 0x0 R/W

0x024 IRQ_STATUS [7:5] RESERVED Reserved. 0x0 R

4 IRQ_SYSREF_JITTER SYSREF± jitter too large. If EN_SYSREF_JITTER

is low, IRQ_SYSREF_JITTER shows the current

status. If EN_SYSREF_JITTER is high, IRQ_

SYSREF_JITTER latches and pulls the IRQx pin

low (x = the MUX_SYSREF_JITTER setting).

Writing a 1 to IRQ_SYSREF_JITTER when

latched clears the bit.

0x0 R/W

3 IRQ_DATA_READY JESD204x receiver data ready is low. If

EN_DATA_READY is low, IRQ_DATA_READY

shows the current status. If EN_DATA_

READY is high, IRQ_DATA_READY latches

and pulls the IRQx pin low (x = MUX_

DATA_READY setting). Writing a 1 to IRQ_

DATA_READY when latched clears the bit.

0x0 R/W

2 IRQ_LANE_FIFO Lane FIFO overflow/underflow. If EN_

LANE_FIFO is low, IRQ_LANE_FIFO shows

the current status. If EN_LANE_FIFO is

high, IRQ_LANE_FIFO latches and pulls the

IRQx pin low (x = MUX_LANE_FIFO

setting). Writing a 1 to IRQ_LANE_FIFO

when latched clears the bit.

0x0 R/W

1 IRQ_PRBSQ DAC1 PRBS error. If EN_PRBSQ is low,

IRQ_PRBSQ shows the current status. If

EN_PRBSQ is high, IRQ_PRBSQ latches and

pulls the IRQx pin low (x = MUX_PRBSQ

setting). Writing a 1 to IRQ_PRBSQ when

latched clears the bit.

0x0 R/W

Data Sheet AD9174

Rev. B | Page 97 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0 IRQ_PRBSI DAC0 PRBS error. If EN_PRBSI is low, IRQ_

PRBSI shows the current status. If EN_

PRBSI is high, IRQ_PRBSI latches and pulls

the IRQx pin low (x = MUX_PRBSI setting).

Writing a 1 to IRQ_PRBSI when latched

clears the bit.

0x0 R/W

0x025 IRQ_STATUS0 [7:4] RESERVED Reserved. 0x0 R

IRQ_DAC0_CAL_

DONE

DAC0 calibration done. If EN_DAC0_CAL_

DONE is low, IRQ_DAC0_CAL_DONE shows

the current status. If EN_DAC0_CAL_DONE

is high, IRQ_DAC0_CAL_DONE latches and

pulls the IRQx pin low (x = MUX_DAC0_

CAL_DONE setting). Writing a 1 to IRQ_

DAC0_CAL_DONE when latched clears the

bit.

0x0 R/W

[2:1] RESERVED Reserved. 0x0 R/W

0 IRQ_PAERR0 DAC0 PA error. If EN_PAERR0 is low, IRQ_

PAERR0 shows the current status. If EN_

PAERR0 is high, IRQ_PAERR0 latches and

pulls the IRQx pin low (x = MUX_PAERR0

setting). Writing a 1 to IRQ_PAERR0 when

latched clears the bit.

0x0 R/W

0x026 IRQ_STATUS1 [7:4] RESERVED Reserved. 0x0 R

IRQ_DAC1_CAL_

DONE

DAC1 calibration done. If EN_DAC0_CAL_

DONE is low, IRQ_DAC1_CAL_DONE shows

the current status. If EN_DAC1_CAL_DONE

is high, IRQ_DAC1_CAL_DONE latches and

pulls the IRQx pin low (x = MUX_DAC1_

CAL_DONE setting). Writing a 1 to IRQ_

DAC1_CAL_DONE when latched clears the

bit.

0x0 R/W

[2:1] RESERVED Reserved. 0x0 R/W

0 IRQ_PAERR1 DAC1 PA error. If EN_PAERR1 is low, IRQ_

PAERR1 shows the current status. If EN_

PAERR1 is high, IRQ_PAERR1 latches and

pulls the IRQx pin low (x = MUX_PAERR1

setting). Writing a 1 to IRQ_PAERR1 when

latched clears the bit.

0x0 R/W

0x027 IRQ_STATUS2 [7:6] RESERVED Reserved. 0x0 R

5 IRQ_DLL_LOST DLL lost. If EN_DLL_LOST is low, IRQ_DLL_

LOST shows the current status. If EN_DLL_

LOST is high, IRQ_DLL_LOST latches and

pulls the IRQx pin low (x = MUX_DLL_LOST

setting). Writing a 1 to IRQ_DLL_LOST

when latched clears the bit.

0x0 R/W

4 IRQ_DLL_LOCK DLL locked. If EN_DLL_LOCK is low, IRQ_

DLL_LOCK shows current status. If EN_DLL_

LOCK is high, IRQ_DLL_LOCK latches and

pulls the IRQx pin low (x = MUX_DLL_LOCK

setting). Writing a 1 to IRQ_DLL_LOCK when

latched clears the bit.

0x0 R/W

[3:2] RESERVED Reserved. 0x0 R/W

1 IRQ_PLL_LOST DAC PLL lock lost. If EN_PLL_LOST is low,

IRQ_PLL_LOST shows the current status. If

EN_PLL_LOST is high, IRQ_PLL_LOST latches

and pulls the IRQx pin low (x = MUX_PLL_

LOST setting). Writing a 1 to IRQ_PLL_

LOST when latched clears the bit.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 98 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0 IRQ_PLL_LOCK DAC PLL locked. If EN_PLL_LOCK is low, IRQ_

PLL_LOCK shows the current status. If EN_

PLL_LOCK is high, IRQ_PLL_LOCK latches

and pulls the IRQx pin low (x = MUX_PLL_

LOCK setting). Writing a 1 to IRQ_PLL_LOCK

when latched clears the bit.

0x0 R/W

0x028 IRQ_OUTPUT_MUX [7:5] RESERVED Reserved. 0x0 R

MUX_SYSREF_

JITTER

If EN_SYSREF_JITTER is set, this control

chooses the IRQx output pin on which the

event is triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

3 MUX_DATA_READY If EN_DATA_READY is set, this control

chooses the IRQx output pin on which the

event is triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

2 MUX_LANE_FIFO If EN_LANE_FIFO is set, this control chooses

the IRQx output pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

1 MUX_PRBSQ If EN_PRBSQ is set, this control chooses the

IRQx output pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

0 MUX_PRBSI If EN_PRBSI is set, this control chooses the

IRQx output pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

0x029 IRQ_OUTPUT_MUX0 [7:4] RESERVED Reserved. 0x0 R

MUX_DAC0_CAL_

DONE

If EN_DAC0_CAL_DONE is set, this control

chooses the IRQx output pin on which the

event is triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

[2:1] RESERVED Reserved. 0x0 R/W

0 MUX_PAERR0 If EN_PAERR0 is set, this control chooses

the IRQx output pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

0x02A IRQ_OUTPUT_MUX1 [7:4] RESERVED Reserved. 0x0 R

MUX_DAC1_CAL_

DONE

If EN_DAC1_CAL_DONE is set, this control

chooses the IRQx output pin on which the

event is triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

[2:1] RESERVED Reserved. 0x0 R/W

Data Sheet AD9174

Rev. B | Page 99 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0 MUX_PAERR1 If EN_PAERR1 is set, this control chooses

the IRQx output pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

0x02B IRQ_OUTPUT_MUX2 [7:6] RESERVED Reserved. 0x0 R

5 MUX_DLL_LOST If EN_DLL_LOST is set, this control chooses

the IRQx output pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

4 MUX_DLL_LOCK If EN_DLL_LOCK is set, this control chooses

the IRQx output pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

[3:2] RESERVED Reserved. 0x0 R/W

1 MUX_PLL_LOST If EN_PLL_LOST is set, this control chooses

the IRQx pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

0 MUX_PLL_LOCK If EN_PLL_LOCK is set, this control chooses

the IRQx pin on which the event is

triggered.

0x0 R/W

0 Route IRQ trigger signal to the IRQ0 pin.

1 Route IRQ trigger signal to the IRQ1 pin.

0x02C IRQ_STATUS_ALL [7:1] RESERVED Reserved. 0x0 R

0 IRQ_STATUS_ALL This bit is an OR of all the bits in

one to this bit clears any latched IRQx

signals in Register 0x24 to Register 0x27.

0x0 R/W

0x036 SYSREF_COUNT [7:0] SYSREF_COUNT Number of rising SYSREF± edges to ignore

before synchronization (pulse counting

mode).

0x0 R/W

0x039 SYSREF_ERR_

WINDOW

7 RESERVED Reserved. 0x0 R

[6:0]

SYSREF_ERR_

WINDOW

Amount of jitter allowed on the SYSREF±

input. SYSREF± jitter variations larger than

this trigger an interrupt. Units are in DAC

clocks.

0x0 R/W

0x03A SYSREF_MODE [7:5] RESERVED Reserved. 0x0 R

SYNC_ROTATION_

DONE

Synchronization logic rotation complete flag. 0x1 R

[3:2] RESERVED Reserved. 0x0 R

SYSREF_MODE_

ONESHOT

Enable one-shot synchronization rotation

mode.

0x0 R/W

00 Monitor mode. Status/error flag for IRQ_

SYSREF_JITTER is 1 if the SYSREF± edge is

outside the error window (Register 0x039,

Bits[6:0]).

01 Perform a single synchronization on the next

SYSREF±, then switch to monitor mode.

0 RESERVED Reserved. 0x0 R/W

AD9174 Data Sheet

Rev. B | Page 100 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x03B ROTATION_MODE 7 SYNCLOGIC_EN This bit must always be set to 1 (default) for

both Subclass 0 and Subclass 1 operations.

0x1 R/W

6 RESERVED Reserved. For proper operation, write this

bit to a 1.

0x0 R/W

5 PERIODIC_RST_EN Synchronization required setting. Always

set this bit to 1 for both Subclass 0 and

Subclass 1 operation.

0x1 R/W

NCORST_AFTER_

ROT_EN

Set this bit to 1 to reset all NCOs after digital

reset or synchronization rotation. Either this

control or the START_NCO_SYNC bit

(Register 0x1E7, Bit 0) can be used to reset

all the NCOs (main and channel

datapaths).

0x1 R/W

[3:2] RESERVED Reserved. 0x0 R

[1:0] ROTATION_MODE Selects the circuitry to be reset when a

synchronization rotation occurs. Certain

bits being set to 1 determine the actions

taken when a synchronization rotation is

performed. Bit 0 corresponds to a SERDES

clock reset and realignment. Bit 1 corres-

ponds to a datapath soft off/on gain, which

must only be used if PA protection is in use. If

PA protection is not used, set Bit 1 to 0.

0x0 R/W

0 No action, with either the SERDES clocks or

the datapath, occurs when a synchro-

nization rotation occurs.

1 The links drop and the SERDES clocks are

reset. It is recommended to set this bit high

so that when a synchronization rotation is

performed, the SERDES clocks realign

properly.

10 The datapath automatically uses the soft

on/off functionality to turn on and off the

datapath stream during a synchronization

rotation to avoid corrupted data from

being transmitted. Only use this feature if

the PA protection block is in use.

11 Both the SERDES clock reset and datapath

soft on/off feature are enabled.

0x03F TX_ENABLE [7:6] RESERVED Reserved. 0x0 R/W

TXEN_DATAPATH_

DAC1

Selects whether the datapath of DAC1 is

muted when the TXEN1 pin is brought low.

0x0 R/W

0 Datapath output is normal.

1 If TXEN1 = 0, the datapath output is

immediately zeroed. If TXEN1 = 1, the

datapath outputs normal operation.

TXEN_DATAPATH_

DAC0

Selects whether the datapath of DAC0 is

muted when the TXEN0 pin is brought low.

0x0 R/W

0 Datapath output is normal.

1 If TXEN0 = 0, the datapath output is

immediately zeroed. If TXEN0 = 1, the

datapath outputs normal operation.

[3:0] RESERVED Reserved. 0x0 R/W

0x050 CAL_CLK_DIV [7:4] RESERVED Reserved 0x2 R/W

[3:0] CAL_CLK_DIV Calibration register control. Set these bits

to 0xA for optimized calibration setting.

0x8 R/W

Data Sheet AD9174

Rev. B | Page 101 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x051 CAL_CTRL 7 CAL_CTRL0 Calibration setting. Set this bit to 1. 0x1 R/W

0 Reset the calibration engine.

1 Enable the calibration routine.

[6:3] RESERVED Reserved. 0x0 R/W

[2:1] CAL_CTRL1 Calibration mode selection. Set this bit

field to 1 for optimized calibration mode.

Paged by the MAINDAC_PAGE bits in

0x1 R/W

1 Set calibration control setting.

0 CAL_START Start calibration. After starting calibration, do

not write to any register from Register 0x051

to Register 0x061 until Register 0x052, Bit

2 reads low (indicating that the calibration

is no longer active). Paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x052 CAL_STAT [7:3] RESERVED Reserved. 0x0 R/W

2 CAL_ACTIVE Calibration active status flag. A readback

of 1 indicates the calibration routine is still

in progress. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R

1 CAL_FAIL_SEARCH Calibration failure flag. A readback of 1

indicates the calibration routine failed and is

possibly not valid. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R

0 CAL_FINISH Calibration complete flag. A readback of 1

indicates the calibration completed. This

control is paged by the MAINDAC_PAGE

bits in Register 0x008.

0x0 R

0x05A FSC1 [7:0] FSC_CTRL[7:0] Sets the full-scale (maximum) current that

is available from the DACx analog outputs.

This control is paged by the MAINDAC_

PAGE bits in Register 0x008. Full-scale

current = 15.625 mA + FSC_CTRL ×

(25/256) (mA).

0x28 R/W

0x061 CAL_DEBUG0 7 RESERVED Reserved. 0x0 R/W

6 CAL_CTRL2 Calibration control. Set this bit to 1 for

optimized calibration setting.

0x1 R/W

5 CAL_CTRL3 Calibration control. Set this bit to 1 for

optimized calibration setting.

0x1 R/W

4 RESERVED Reserved. 0x0 R/W

3 CAL_CTRL4 Calibration control. Set this bit to 1 for

optimized calibration setting.

0x0 R/W

[2:0] RESERVED Reserved. 0x0 R/W

0x081 CLK_CTRL [7:2] RESERVED Reserved. 0x0 R/W

1 CAL_CLK_PD1 After the calibration is complete for DAC1

(Register 0x052, Bit 0 = 1), set this bit high

to power down the calibration clock.

0x0 R/W

0 CAL_CLK_PD0 After the calibration is complete for DAC0

(Register 0x052, Bit 0 = 1), set this bit high

to power down the calibration clock.

0x0 R/W

0x083 NVM_CTRL0 7 NVM_CTRL0A NVM register control for the ring oscillator. 0x0 R/W

[6:2] RESERVED Reserved. 0x0 R

[1:0] NVM_CTRL0B NVM register control for the ring oscillator. 0x2 R/W

00 Divide by 8.

01 Divide by 16.

10 Divide by 32.

11 Divide by 64.

AD9174 Data Sheet

Rev. B | Page 102 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x084 SYSREF_CTRL 7 RESERVED Reserved. 0x0 R/W

SYSREF_

INPUTMODE

Sets the input mode type for the SYSREF±

pins.

0x0 R/W

0 AC couple SYSREF±.

1 DC couple SYSREF±.

[5:1] RESERVED Reserved. 0x0 R/W

0 SYSREF_PD Power down the SYSREF± receiver and

synchronization circuitry. If using Subclass 0,

set this bit to 1 because the SYSREF± pins

are not used.

0x0 R/W

0 SYSREF± receiver is powered on.

1 SYSREF± receiver is powered down.

0x085 NVM_CTRL1 7 RESERVED Reserved. 0x0 R

[6:4] NVM_CTRL1A NVM control. Set this control to 1 at the start

of the configuration sequence (as shown

in the Start-Up Sequence section) and set

to 0 at the end of the start-up routine

when no longer programming the device.

0x1 R/W

[3:2] RESERVED Reserved. 0x0 R

1 NVM_CTRL1B NVM control. Set this control to 1 at the start

of the configuration sequence (as shown in

the Start-Up Sequence section) and set to 0

at the end of the start-up routine when no

longer programming the device.

0x1 R/W

0 NVM_CTRL1C NVM control. Set this control to 0 at the start

of the configuration sequence (as shown in

the Start-Up Sequence section) and set to 1

at the end of the start-up routine when no

longer programming the device.

0x1 R/W

0x08D ADC_CLK_CTRL0 [7:5] RESERVED Reserved. 0x0 R

[4:0] CLKOUT_SWING Controls the swing level of the ADC clock

driver. Swing can be negative (inverts clock).

0x0 R/W

The calculation for Code 0 to Code 9 is as

follows:

ADC driver swing = 993 mV − CLKOUT_

SWING × 77 mV.

The calculation for Code 10 to Code 19 is

as follows:

ADC driver swing = (20 − CLKOUT_SWING ×

77 mV) − 1 V.

0x08F ADC_CLK_CTRL2 [7:1] RESERVED Reserved. 0x0 R

PD_CLKOUT_

DRIVER

Powers down the CLKOUT± output driver. 0x0 R/W

0x090 DAC_POWERDOWN [7:2] RESERVED Reserved. 0x0 R

1 DAC_PD1 Powers down DAC1. 0x1 R/W

0 Power up DAC1.

1 Power down DAC1.

0 DAC_PD0 Powers down DAC0. 0x1 R/W

0 Power up DAC0.

1 Power down DAC0.

0x091 ACLK_CTRL [7:1] RESERVED Reserved. 0x0 R/W

ACLK_

POWERDOWN

Analog clock receiver power-down. 0x1 R/W

Data Sheet AD9174

Rev. B | Page 103 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x094 PLL_CLK_DIV [7:2] RESERVED Reserved. 0x0 R

1 PLL_VCO_DIV3_EN Enable PLL output clock divide by 3. 0x0 R/W

0 PLL_VCO_DIV2_EN Enable PLL output clock divide by 2. 0x0 R/W

0 DAC clock = PLL VCO clock frequency.

1 DAC clock = PLL VCO clock frequency ÷ 2.

0x095 PLL_BYPASS [7:1] RESERVED Reserved. 0x0 R

0 PLL_BYPASS Enable direct clocking (bypassing the PLL

clock).

0x0 R/W

0 Use the internal PLL to generate the DAC

clock.

1 Bypass the PLL and directly clock with the

DAC clock frequency.

0x09A NVM_CTRL 7 PD_BGR Bias power-down. Set this bit to 1 to

power down the internal bias.

0x0 R/W

[6:0] RESERVED Reserved. 0x0 R/W

0x0C0 DELAY_LINE_PD [7:6] RESERVED Reserved. 0x0 R

5 DLL_CTRL0B DLL control. Set this bit to 0 to power up

the delay line during the device

configuration sequence.

0x1 R/W

4 DLL_CTRL0A DLL control. Set this bit to 0 to power up

the delay line during the device

configuration sequence.

0x1 R/W

[3:1] RESERVED Reserved. 0x0 R

0 DLL_PD Power down delay line. Set this bit to 0 to

power up the delay line during the device

configuration sequence.

0x1 R/W

0 Power up and enable the delay line.

1 Power down and bypass the delay line.

0x0C1 DLL_CTRL0 [7:6] DLL_CTRL1C DAC control setting. Set this control to 1

for optimal performance.

0x1 R/W

5 DLL_CTRL1B DLL control search mode. If the DAC

frequency is <4.5 GHz, set this bit to 0;

otherwise, set this bit to 1.

0x1 R/W

[4:3] DLL_CTRL1A DLL control search direction. Set this

control to 1 for optimal performance.

0x2 R/W

[2:1] RESERVED Reserved. 0x0 R

0 DLL_ENABLE DLL controller enable. 0x0 R/W

0 Disable DLL.

1 Enable DLL.

0x0C3 DLL_STATUS [7:1] RESERVED Reserved. 0x0 R

0 DLL_LOCK DLL lock indicator. This control reads back

1 if the DLL locks.

0x0 R

0x0C7 DLL_READ [7:1] RESERVED Reserved. 0x0 R

0 DLL_READ_EN Enable DLL readback status. A transition of

0 to 1 updates the lock status bit readback

in Register 0x0C3.

0x0 R/W

0x0CC DLL_FINE_DELAY0 [7:6] RESERVED Reserved. 0x0 R

[5:0] DLL_FINE_DELAY0 DLL delay control. 0x0 R/W

0x0CD DLL_FINE_DELAY1 [7:6] RESERVED Reserved. 0x0 R

[5:0] DLL_FINE_DELAY1 DLL delay control. 0x0 R/W

0x0DB DLL_UPDATE [7:1] RESERVED Reserved. 0x0 R

DLL_DELAY_

UPDATE

DLL update control. A transition from 0 to

1 updates the DLL circuitry with the

current register control settings.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 104 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x0FF MOD_SWITCH_

DEBUG

[7:2] RESERVED Reserved. 0x0 R

CMPLX_MOD_

DIV2_DISABLE

Disables the divide by 2 block in the mod-

ulator switch path. Set to 1 to bypass the

divide by 2 block. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0 RESERVED Reserved. 0x0 R

0x100 DIG_RESET [7:1] RESERVED Reserved. 0x0 R

0 DIG_DATAPATH_PD Holds all digital logic (SERDES digital,

digital clock generation, and digital

datapath) in reset until clock tree is stable.

0x1 R/W

0 Normal operating mode.

1 Holds the digital logic in reset. Must be

released (set to 0) after clocks to the chip

are stable (PLL and DLL blocks are locked)

to use the digital datapath.

0x110 JESD_MODE 7 MODE_NOT_IN_

TABLE

Programmed JESD204B mode and interpola-

tion mode combination is not valid. Select

a different combination.

0x0 R

6 COM_SYNC Combine the SYNCOUTx± signals in dual

link case.

0x0 R/W

[5:0] JESD_MODE Sets the JESD204B mode configuration.

See Table 13 for the JESD204B supported

operating modes and compatible interpola-

tion rates. Bit 5 of this control determines

single link (set to 0) or dual link (set to 1).

Bits[4:0] set the desired JESD204B mode

according to Table 13.

0x20 R/W

0x111 INTRP_MODE [7:4] DP_INTERP_MODE Sets main datapath interpolation rate. See

Table 13 for the JESD204B supported

operating modes and compatible JESD204B

modes and channel interpolation rates.

0x8 R/W

0x1 1×.

0x2 2×.

0x4 4×.

0x6 6×.

0x8 8×.

0xC 12×.

[3:0] CH_INTERP_MODE Sets channel interpolation rate. See Table 13

for the JESD204B supported operating

modes and compatible JESD204B modes

and main datapath interpolation rates.

0x4 R/W

0x1 1×.

0x2 2×.

0x3 3×.

0x4 4×.

0x6 6×.

0x8 8×.

Data Sheet AD9174

Rev. B | Page 105 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x112 DDSM_DATAPATH_

CFG

7 RESERVED Reserved. 0x0 R

6 EN_CMPLX_MOD

Modulator switch mode selection. This

control allows modifying Configuration 3 of

the modulator switch to allow complex (I/Q)

data from each NCO to pass to DACx. This

function depends on the settings applied to

Bits[5:4] in this register, Register 0x112. When

this bit is set high, Bits[5:4] of this register are

set to 0b11 (Modulator Switch Configuration

3). This control is paged by the MAINDAC_

PAGE bits in Register 0x008.

Switch configuration is as defined by

Bits[5:4].

With Bits[5:4] = 0b11 and the DAC1 main

NCO enabled, DAC0 = I0_NCO + I1_NCO,

DAC1 = Q0_NCO + Q1_NCO. With Bits[5:4] =

0b11 and the DAC1 main NCO disabled,

DAC0 = I0_NCO, DAC1 = Q0_NCO.

[5:4] DDSM_MODE

Modulator switch mode selection. This

control chooses the mode of operation for

the main datapath NCO being configured.

This control is paged by the MAINDAC_

PAGE bits in Register 0x008.

0x0 R/W

00 DAC0 = I0; DAC1 = I1.

01 DAC0 = I0 + I1; DAC1 = Q0 + Q1.

10 DAC0 = I0; DAC1 = Q0.

11 DAC0 = I0 + I1; DAC1 = 0.

3 DDSM_NCO_EN Main datapath modulation enable. If the

JESD204B mode chosen is a complex

mode (main datapath interpolation >1×),

this bit must be set to 1 for each main

datapath being used. If no modulation is

desired, set the FTW to be 0. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0 Disable main datapath NCO.

1 Enable main datapath NCO.

DDSM_

MODULUS_EN

Enable main datapath modulus DDS. This

control is paged by the MAINDAC_PAGE

bits in Register 0x008.

0x0 R/W

0 Disable modulus DDS.

1 Enable modulus DDS.

DDSM_SEL_

SIDEBAND

Selects upper or lower sideband from

modulation result. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0 Use upper sideband.

1 Use lower sideband = spectral flip.

EN_SYNC_ALL_

CHNL_NCO_RESETS

Selects the signal channel NCOS used for

resets and FTW updates. This control is

paged by the MAINDAC_PAGE bits in

0x1 R/W

0 Channel NCOs reset or update their FTW

based on channel NCO update requests.

1 Channel NCOs reset or update their FTW

based on main datapath NCO update

requests.

AD9174 Data Sheet

Rev. B | Page 106 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x113 DDSM_FTW_

UPDATE

7 RESERVED Reserved. 0x0 R

[6:4]

DDSM_FTW_REQ_

MODE

Frequency tuning word automatic update

mode. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

000

No automatic requests are generated

when the FTW registers are written.

001

Automatically generates a DDSM_FTW_

LOAD_REQ after DDSM_FTW Bits[7:0] are

written.

010

Automatically generates a DDSM_FTW_

LOAD_REQ after DDSM_FTW Bits[15:8] are

written.

011

Automatically generates a DDSM_FTW_

LOAD_REQ after DDSM_FTW Bits[23:16]

are written.

100

Automatically generates a DDSM_FTW_

LOAD_REQ after DDSM_FTW Bits[31:24]

are written.

101

Automatically generate a DDSM_FTW_

LOAD_REQ after DDSM_FTW Bits[39:32] is

written.

110

Automatically generates a DDSM_FTW_

LOAD_REQ after DDSM_FTW Bits[47:40]

are written.

3 RESERVED Reserved. 0x0 R

DDSM_FTW_

LOAD_SYSREF

Uses the next rising edge of SYSREF± to

trigger FTW load and reset. This bit also

loads the calibration tone FTW, as well as

the main NCO FTW on a rising edge

detection. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

DDSM_FTW_

LOAD_ACK

Frequency tuning word update acknow-

ledge. This bit reads back 1 if the FTW and

phase offset word is loaded properly. This

control is paged by the MAINDAC_PAGE bits

in Register 0x008.

0x0 R

0 FTW is not loaded.

1 FTW is loaded.

DDSM_FTW_

LOAD_REQ

Frequency tuning word update request

from the SPI. This bit also loads the calibra-

tion tone FTW, as well as the main NCO

FTW on a rising edge detection. This control

is paged by the MAINDAC_PAGE bits in

0x0 R/W

0 Clear DDSM_FTW_LOAD_ACK.

1 0 to 1 transition loads the FTW.

0x114 DDSM_FTW0 [7:0] DDSM_FTW[7:0] Sets the main datapath NCO FTW. If

DDSM_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSM_

FTW/248). If DDSM_MODULUS_EN is high,

the main datapath NCO frequency = fDAC ×

(DDSM_FTW + DDSM_ACC_DELTA/DDSM_

ACC_MODULUS)/248. DDSM_ACC_DELTA

must be >0. DDSM_ACC_DELTA must be

>DDSM_ACC_MODULUS. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

Data Sheet AD9174

Rev. B | Page 107 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x115 DDSM_FTW1 [7:0] DDSM_FTW[15:8] Sets the main datapath NCO FTW. If

DDSM_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSM_

FTW/248. If DDSM_MODULUS_EN is high,

the main datapath NCO frequency = fDAC ×

(DDSM_FTW + DDSM_ACC_DELTA/DDSM_

ACC_MODULUS)/ 248. DDSM_ACC_DELTA

must be > 0. DDSM_ACC_DELTA must be >

DDSM_ACC_MODULUS. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0x116 DDSM_FTW2 [7:0] DDSM_FTW[23:16] Sets the main datapath NCO FTW. If

DDSM_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSM_

FTW/248. If DDSM_MODULUS_EN is high,

the main datapath NCO frequency = fDAC ×

(DDSM_FTW + DDSM_ACC_DELTA/DDSM_

ACC_MODULUS)/248. DDSM_ACC_DELTA

must be > 0. DDSM_ACC_DELTA must be >

DDSM_ACC_MODULUS. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0x117 DDSM_FTW3 [7:0] DDSM_FTW[31:24] Sets the main datapath NCO FTW. If

DDSM_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSM_

FTW/248. If DDSM_MODULUS_EN is high,

the main datapath NCO frequency = fDAC ×

(DDSM_FTW + DDSM_ACC_DELTA/DDSM_

ACC_MODULUS)/248. DDSM_ACC_DELTA

must be > 0. DDSM_ACC_DELTA must be >

DDSM_ACC_MODULUS. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0x118 DDSM_FTW4 [7:0] DDSM_FTW[39:32] Sets the main datapath NCO FTW. If

DDSM_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSM_

FTW/248. If DDSM_MODULUS_EN is high,

the main datapath NCO frequency = fDAC ×

(DDSM_FTW + DDSM_ACC_DELTA/DDSM_

ACC_MODULUS)/248. DDSM_ACC_DELTA

must be > 0. DDSM_ACC_DELTA must be >

DDSM_ACC_MODULUS. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0x119 DDSM_FTW5 [7:0] DDSM_FTW[47:40] Sets the main datapath NCO FTW. If

DDSM_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSM_

FTW/248. If DDSM_MODULUS_EN is high,

the main datapath NCO frequency = fDAC ×

(DDSM_FTW + DDSM_ACC_DELTA/DDSM_

ACC_MODULUS)/248. DDSM_ACC_DELTA

must be > 0. DDSM_ACC_DELTA must be >

DDSM_ACC_MODULUS. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0x11C DDSM_PHASE_

OFFSET0

[7:0] DDSM_NCO_

PHASE_OFFSET[7:0]

Sets main datapath NCO phase offset. Code

is in 16-bit, twos complement format.

Degrees offset = 180 × (code/215. This

control is paged by the MAINDAC_PAGE

bits in Register 0x008.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 108 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x11D DDSM_PHASE_

OFFSET1

[7:0] DDSM_NCO_

PHASE_

OFFSET[15:8]

Sets main datapath NCO phase offset. Code

is in 16-bit, twos complement format.

Degrees offset = 180 × (code/215). This

control is paged by the MAINDAC_PAGE

bits in Register 0x008.

0x0 R/W

0x124 DDSM_ACC_

MODULUS0

[7:0] DDSM_ACC_

MODULUS[7:0]

Sets DDSM_ACC_MODULUS. If DDSM_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSM_FTW +

DDSM_ACC_DELTA/DDSM_ACC_

MODULUS)/248. DDSM_ACC_DELTA must be

>0. DDSM_ACC_DELTA must be > DDSM_

ACC_MODULUS. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x125 DDSM_ACC_

MODULUS1

[7:0] DDSM_ACC_

MODULUS[15:8]

Sets DDSM_ACC_MODULUS. If DDSM_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSM_FTW +

DDSM_ACC_DELTA/DDSM_ACC_

MODULUS)/248. DDSM_ACC_DELTA must be

>0. DDSM_ACC_DELTA must be

>DDSM_ACC_MODULUS. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0x126 DDSM_ACC_

MODULUS2

[7:0] DDSM_ACC_

MODULUS[23:16]

Sets DDSM_ACC_MODULUS. If DDSM_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSM_FTW +

DDSM_ACC_DELTA/DDSM_ACC_

MODULUS)/248. DDSM_ACC_DELTA must be

>0. DDSM_ACC_DELTA must be > DDSM_

ACC_MODULUS. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x127 DDSM_ACC_

MODULUS3

[7:0] DDSM_ACC_

MODULUS[31:24]

Sets DDSM_ACC_MODULUS. If DDSM_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSM_FTW +

DDSM_ACC_DELTA/DDSM_ACC_

MODULUS)/248. DDSM_ACC_DELTA must be

>0. DDSM_ACC_DELTA must be > DDSM_

ACC_MODULUS. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x128 DDSM_ACC_

MODULUS4

[7:0] DDSM_ACC_

MODULUS[39:32]

Sets DDSM_ACC_MODULUS. If DDSM_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSM_FTW +

DDSM_ACC_DELTA/DDSM_ACC_

MODULUS)/248. DDSM_ACC_DELTA must be

>0. DDSM_ACC_DELTA must be > DDSM_

ACC_MODULUS. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x129 DDSM_ACC_

MODULUS5

[7:0] DDSM_ACC_

MODULUS[47:40]

Sets DDSM_ACC_MODULUS. If DDSM_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSM_FTW +

DDSM_ACC_DELTA/DDSM_ACC_

MODULUS)/248. DDSM_ACC_DELTA must be

>0. DDSM_ACC_DELTA must be > DDSM_

ACC_MODULUS. This control is paged by

the MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x12A DDSM_ACC_DELTA0 [7:0]

DDSM_ACC_

DELTA[7:0]

Sets DDSM_ACC_DELTA. If DDSM_

MODULUS_EN is high, main datapath NCO

frequency = fDAC × (DDSM_FTW + DDSM_

ACC_DELTA/DDSM_ACC_MODULUS)/248.

DDSM_ACC_DELTA must be > 0. DDSM_

ACC_DELTA must be > DDSM_ACC_

MODULUS. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

Data Sheet AD9174

Rev. B | Page 109 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x12B DDSM_ACC_DELTA1 [7:0]

DDSM_ACC_

DELTA[15:8]

Sets DDSM_ACC_DELTA. If DDSM_

MODULUS_EN is high, main datapath NCO

frequency = fDAC × (DDSM_FTW + DDSM_

ACC_DELTA/DDSM_ACC_MODULUS)/248.

DDSM_ACC_DELTA must be > 0. DDSM_

ACC_DELTA must be > DDSM_ACC_

MODULUS. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x12C DDSM_ACC_DELTA2 [7:0]

DDSM_ACC_

DELTA[23:16]

Sets DDSM_ACC_DELTA. If DDSM_

MODULUS_EN is high, main datapath NCO

frequency = fDAC × (DDSM_FTW + DDSM_

ACC_DELTA/DDSM_ACC_MODULUS)/248.

DDSM_ACC_DELTA must be > 0. DDSM_

ACC_DELTA must be > DDSM_ACC_

MODULUS. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x12D DDSM_ACC_DELTA3 [7:0] DDSM_ACC_

DELTA[31:24]

Sets DDSM_ACC_DELTA. If DDSM_

MODULUS_EN is high, main datapath NCO

frequency = fDAC × (DDSM_FTW + DDSM_

ACC_DELTA/DDSM_ACC_MODULUS)/248.

DDSM_ACC_DELTA must be > 0. DDSM_

ACC_DELTA must be > DDSM_ACC_

MODULUS. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x12E DDSM_ACC_DELTA4 [7:0]

DDSM_ACC_

DELTA[39:32]

Sets DDSM_ACC_DELTA. If DDSM_

MODULUS_EN is high, main datapath NCO

frequency = fDAC × (DDSM_FTW + DDSM_

ACC_DELTA/DDSM_ACC_MODULUS)/248.

DDSM_ACC_DELTA must be > 0. DDSM_

ACC_DELTA must be > DDSM_ACC_

MODULUS. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x12F DDSM_ACC_DELTA5 [7:0]

DDSM_ACC_

DELTA[47:40]

Sets DDSM_ACC_DELTA. If DDSM_

MODULUS_EN is high, main datapath NCO

frequency = fDAC × (DDSM_FTW + DDSM_

ACC_DELTA/DDSM_ACC_MODULUS)/248.

DDSM_ACC_DELTA must be > 0. DDSM_

ACC_DELTA must be > DDSM_ACC_

MODULUS. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0 R/W

0x130 DDSC_ DATAPATH_

CFG

7 RESERVED Reserved. 0x0 R

6 DDSC_NCO_EN

Channel datapath modulation enable. If

the JESD204B mode chosen is a complex

mode (channel interpolation >1×), this bit

must be set to 1 for each channel datapath

being used. If no modulation is desired, set

the FTW to 0. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0 Disable channel NCO.

1 Enable channel NCO.

[5:3] RESERVED Reserved. 0x0 R/W

DDSC_MODULUS_

Enable channel modulus DDS. This control

is paged by the CHANNEL_PAGE bits in

0x0 R/W

0 Disable modulus DDS.

1 Enable modulus DDS.

AD9174 Data Sheet

Rev. B | Page 110 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

DDSC_SEL_

SIDEBAND

Selects upper or lower sideband from

modulation result. This control is paged by

the CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0 Use upper sideband.

1 Use lower sideband = spectral flip.

DDSC_EN_DC_

INPUT

Enable test tone generation by sending dc

to input level to channel DDS. Set the

amplitude in the DC_TEST_INPUT_

AMPLITUDE control (Register 0x148 and

the CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0 Disable test tone generation.

1 Enable test tone generation.

0x131 DDSC_FTW_UPDATE [7:3] RESERVED Reserved. 0x0 R

DDSC_FTW_

LOAD_SYSREF

Use next rising edge of SYSREF± to trigger

FTW load and reset. This control is paged by

the CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

DDSC_FTW_

LOAD_ACK

Frequency tuning word update acknow-

ledge bit. This bit reads back 1 if the FTW

and phase offset word is loaded properly.

This control is paged by the CHANNEL_

PAGE bits in Register 0x008.

0x0 R

0 FTW is not loaded.

1 FTW is loaded.

DDSC_FTW_

LOAD_REQ

Frequency tuning word update request

from the SPI. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0 No FTW update.

1 0 to 1 transition loads the FTW.

0x132 DDSC_FTW0 [7:0] DDSC_FTW[7:0] Sets the channel datapath NCO FTW. If

DDSC_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSC_

FTW/248). If DDSC_MODULUS_EN is high,

main datapath NCO frequency = fDAC ×

(DDSC_FTW + DDSC_ACC_DELTA/DDSC_

ACC_MODULUS)/248. DDSC_ACC_DELTA

must be > 0. DDSC_ACC_DELTA must be >

DDSC_ACC_MODULUS. This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

0x133 DDSC_FTW1 [7:0] DDSC_FTW[15:8] Sets the channel datapath NCO FTW. If

DDSC_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSC_

FTW/248). If DDSC_MODULUS_EN is high,

main datapath NCO frequency = fDAC ×

(DDSC_FTW + DDSC_ACC_DELTA/DDSC_

ACC_MODULUS)/248. DDSC_ACC_DELTA

must be > 0. DDSC_ACC_DELTA must be >

DDSC_ACC_MODULUS. This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

Data Sheet AD9174

Rev. B | Page 111 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x134 DDSC_FTW2 [7:0] DDSC_FTW[23:16] Sets the channel datapath NCO FTW. If

DDSC_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSC_

FTW/248). If DDSC_MODULUS_EN is high,

main datapath NCO frequency = fDAC ×

(DDSC_FTW + DDSC_ACC_DELTA/DDSC_

ACC_MODULUS)/248. DDSC_ACC_DELTA

must be > 0. DDSC_ACC_DELTA must be >

DDSC_ACC_MODULUS. This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

0x135 DDSC_FTW3 [7:0] DDSC_FTW[31:24] Sets the channel datapath NCO FTW. If

DDSC_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSC_

FTW/248). If DDSC_MODULUS_EN is high,

main datapath NCO frequency = fDAC ×

(DDSC_FTW + DDSC_ACC_DELTA/DDSC_

ACC_MODULUS)/248. DDSC_ACC_DELTA

must be > 0. DDSC_ACC_DELTA must be >

DDSC_ACC_MODULUS. This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

0x136 DDSC_FTW4 [7:0] DDSC_FTW[39:32] Sets the channel datapath NCO FTW. If

DDSC_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSC_

FTW/248). If DDSC_MODULUS_EN is high,

main datapath NCO frequency = fDAC ×

(DDSC_FTW + DDSC_ACC_DELTA/DDSC_

ACC_MODULUS)/248. DDSC_ACC_DELTA

must be > 0. DDSC_ACC_DELTA must be >

DDSC_ACC_MODULUS. This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

0x137 DDSC_FTW5 [7:0] DDSC_FTW[47:40] Sets the channel datapath NCO FTW. If

DDSC_MODULUS_EN is low, the main

datapath NCO frequency = fDAC × (DDSC_

FTW/248). If DDSC_MODULUS_EN is high,

main datapath NCO frequency = fDAC ×

(DDSC_FTW + DDSC_ACC_DELTA/DDSC_

ACC_MODULUS)/248. DDSC_ACC_DELTA

must be > 0. DDSC_ACC_DELTA must be >

DDSC_ACC_MODULUS. This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

0x138 DDSC_PHASE_

OFFSET0

[7:0] DDSC_NCO_

PHASE_OFFSET[7:0]

Sets the channel NCO phase offset. Code is in

16-bit, twos complement format. Degrees

offset = 180 × (code/215). This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

0x139 DDSC_PHASE_

OFFSET1

[7:0] DDSC_NCO_

PHASE_

OFFSET[15:8]

Sets the channel NCO phase offset. Code is in

16-bit, twos complement format. Degrees

offset = 180 × (code/215). This control is

paged by the CHANNEL_PAGE bits in

0x0 R/W

0x13A DDSC_ACC_

MODULUS0

[7:0] DDSC_ACC_

MODULUS[7:0]

Sets DDSC_ACC_MODULUS. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0.

DDSC_ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 112 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x13B DDSC_ACC_

MODULUS1

[7:0] DDSC_ACC_

MODULUS[15:8]

Sets DDSC_ACC_MODULUS. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0.

DDSC_ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x13C DDSC_ACC_

MODULUS2

[7:0] DDSC_ACC_

MODULUS[23:16]

Sets DDSC_ACC_MODULUS. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0. DDSC_

ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x13D DDSC_ACC_

MODULUS3

[7:0] DDSC_ACC_

MODULUS[31:24]

Sets DDSC_ACC_MODULUS. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0.

DDSC_ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x13E DDSC_ACC_

MODULUS4

[7:0] DDSC_ACC_

MODULUS[39:32]

Sets DDSC_ACC_MODULUS. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0.

DDSC_ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x13F DDSC_ACC_

MODULUS5

[7:0] DDSC_ACC_

MODULUS[47:40]

Sets DDSC_ACC_MODULUS. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0.

DDSC_ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x140 DDSC_ACC_DELTA0 [7:0]

DDSC_ACC_

DELTA[7:0]

Sets DDSC_ACC_DELTA. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0. DDSC_

ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x141 DDSC_ACC_

DELTA1

[7:0] DDSC_ACC_

DELTA[15:8]

Sets DDSC_ACC_DELTA. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0. DDSC_

ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

Data Sheet AD9174

Rev. B | Page 113 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x142 DDSC_ACC_DELTA2 [7:0]

DDSC_ACC_

DELTA[23:16]

Sets DDSC_ACC_DELTA. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0. DDSC_

ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x143 DDSC_ACC_DELTA3 [7:0]

DDSC_ACC_

DELTA[31:24]

Sets DDSC_ACC_DELTA. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0. DDSC_

ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x144 DDSC_ACC_DELTA4 [7:0]

DDSC_ACC_

DELTA[39:32]

Sets DDSC_ACC_DELTA. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0. DDSC_

ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x145 DDSC_ACC_DELTA5 [7:0]

DDSC_ACC_

DELTA[47:40]

Sets DDSC_ACC_DELTA. If DDSC_

MODULUS_EN is high, the main datapath

NCO frequency = fDAC × (DDSC_FTW +

DDSC_ACC_DELTA/DDSC_ACC_MODULUS)/

248. DDSC_ACC_DELTA must be > 0. DDSC_

ACC_DELTA must be > DDSC_ACC_

MODULUS. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

0x146 CHNL_GAIN0 [7:0] CHNL_GAIN[7:0] Sets the scalar channel gain value. This

control is paged by the CHANNEL_PAGE bits

in Register 0x008. Channel gain =

CHNL_GAIN/211.

0x0 R/W

0x147 CHNL_GAIN1 [7:4] RESERVED Reserved. 0x0 R

[3:0] CHNL_GAIN[11:8] Sets the scalar channel gain value. This

control is paged by the CHANNEL_PAGE bits

in Register 0x008. Channel gain =

CHNL_GAIN/211.

0x8 R/W

0x148 DC_CAL_TONE0 [7:0]

DC_TEST_INPUT_

AMPLITUDE[7:0]

DC test tone amplitude. This value sets the I

path and Q paths amplitudes independently.

Set these bits to 0x50FF for a full-scale

tone and ensure DDSC_EN_DC_INPUT in

is paged by the CHANNEL_PAGE control in

0x0 R/W

0x149 DC_CAL_TONE1 [7:0]

DC_TEST_INPUT_

AMPLITUDE[15:8]

DC test tone amplitude. This value sets the I

path and Q paths amplitudes independently.

Set to 0x50FF for a full-scale tone and ensure

that DDSC_EN_DC_INPUT (Register 0x130,

Bit 0) is set to 1. This control is paged by the

CHANNEL_PAGE bits in Register 0x008.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 114 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x14B PRBS 7 PRBS_GOOD_Q DAC1 good data indicator. 0x0 R

1 Correct PRBS sequence detected.

0 Incorrect sequence detected. Sticky; reset

to 1 by PRBS_RESET.

6 PRBS_GOOD_I DAC0 good data indicator. 0x0 R

0 Incorrect sequence detected. Sticky; reset

to 1 by PRBS_RESET.

1 Correct PRBS sequence detected.

5 RESERVED Reserved. 0x0 R

4 PRBS_INV_Q DAC1 data inversion. 0x1 R/W

0 Expect normal data.

1 Expect inverted data.

3 PRBS_INV_I DAC0 data inversion. 0x0 R/W

0 Expect normal data.

1 Expect inverted data.

2 PRBS_MODE Select which PRBS polynomial is used for

the datapath PRBS test.

0x0 R/W

0 7-bit: x7 + x6 + 1.

1 15-bit: x15 + x14 + 1.

1 PRBS_RESET Reset error counters. 0x0 R/W

0 Normal operation.

1 Reset counters.

0 PRBS_EN Enable PRBS checker. 0x0 R/W

0 Disable.

1 Enable.

0x14C PRBS_ERROR_I [7:0] PRBS_COUNT_I DAC0 PRBS error count. 0x0 R

0x14D PRBS_ERROR_Q [7:0] PRBS_COUNT_Q DAC1 PRBS error count. 0x0 R

0x14E PRBS_CHANSEL [7:3] RESERVED Reserved. 0x0 R

[2:0] PRBS_CHANSEL Selects the channel to which the PRBS_

GOOD_x and PRBS_COUNT_x bit field

readbacks correspond.

0x7 R/W

0 Select Channel 0 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 0, DAC0).

1 Select Channel 1 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 1, DAC0).

2 Select Channel 2 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 2, DAC0).

3 Select Channel 3 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 0, DAC1).

4 Select Channel 4 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 1, DAC1).

5 Select Channel 5 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 2, DAC1).

6 OR all channels for PRBS_GOOD_x, sum all

channels for PRBS_COUNT_x.

0x151 DECODE_MODE [7:5] RESERVED Reserved. 0x0 R

4 MSB_SHUFFLE_EN MSB shuffle control. Set =1 to enable

shuffling the MSBs, or set = 0 to disable

MSB shuffle and use the default (static)

thermometer encoding instead.

0x0 R/W

[3:0] RESERVED Reserved. 0x0 R

0x1DE SPI_ENABLE [7:2] RESERVED Reserved. 0x0 R

1 SPI_EN1 Enable SPI control. 0x1 R/W

0 SPI_EN0 Enable SPI control. 0x1 R/W

Data Sheet AD9174

Rev. B | Page 115 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x1E2 DDSM_CAL_FTW0 [7:0]

DDSM_CAL_

FTW[7:0]

FTW of the calibration accumulator. This

control is paged by the MAINDAC_PAGE bits

in Register 0x008.

0x0 R/W

0x1E3 DDSM_CAL_FTW1 [7:0]

DDSM_CAL_

FTW[15:8]

FTW of the calibration accumulator. This

control is paged by the MAINDAC_PAGE bits

in Register 0x008.

0x0 R/W

0x1E4 DDSM_CAL_FTW2 [7:0]

DDSM_CAL_

FTW[23:16]

FTW of the calibration accumulator. This

control is paged by the MAINDAC_PAGE bits

in Register 0x008.

0x0 R/W

0x1E5 DDSM_CAL_FTW3 [7:0]

DDSM_CAL_

FTW[31:24]

FTW of the calibration accumulator. This

control is paged by the MAINDAC_PAGE bits

in Register 0x008.

0x0 R/W

0x1E6 DDSM_CAL_MODE_

DEF

[7:3] RESERVED Reserved. 0x0 R

DDSM_EN_CAL_

ACC

Enable clock calibration accumulator. This bit

must be first set high, and then must load

the calibration FTW into Register 0x1E2 to

is paged by the MAINDAC_PAGE bits in

0x0 R/W

0 Disabled (does not clock the calibration

frequency accumulator).

1 Enables (turns on the clock to the

calibration frequency accumulator).

DDSM_EN_CAL_

DC_INPUT

Enable dc input to calibration DDS. This

control is paged by the MAINDAC_PAGE

bits in Register 0x008.

0x0 R/W

0 Mux in datapath signal to the input of the

final DDS.

1 Mux in dc to the input of the final DDS.

DDSM_EN_CAL_

FREQ_TUNE

Enable tuning of the signal to calibration

frequency for DAC0 only. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0 Disable calibration frequency tuning.

1 Enable calibration frequency tuning.

0x1E7 DATAPATH_NCO_

SYNC_CFG

[7:2] RESERVED Reserved. 0x0 R

ALL_NCO_SYNC_

ACK

Acknowledge signal that all the active NCOs

are loaded. This bit is the acknowledge

indicator for both the START_NCO_SYNC

bit (Bit 0 of this register) and the NCORST_

AFTER_ROT_EN bit (Register 0x03B, Bit 4)

method of resetting the NCOs. This control

is paged by the MAINDAC_PAGE bits in

0x0 R

0 START_NCO_SYNC Used to start the sync of the NCOs on a

rising edge of the SPI bit or SYSREF±

signal, depending on which is chosen as

the update trigger. Upon receiving a

trigger, the FTWs are loaded first, and then

a synchronization occurs. This control is

paged by the MAINDAC_PAGE bits in

0x0 R/W

0x200 MASTER_PD [7:1] RESERVED Reserved. 0x0 R

SERDES_MASTER_

Powers down the entire JESD204B receiver

analog (all eight channels and bias).

0x1 R/W

AD9174 Data Sheet

Rev. B | Page 116 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x201 PHY_PD [7:0] PHY_PD SPI override to power down the individual

PHYs. Bit 0 controls the SERDIN0± PHY.

0xEE R/W

Bit 1 controls the SERDIN1± PHY.

Bit 2 controls the SERDIN2± PHY.

Bit 3 controls the SERDIN3± PHY.

Bit 4 controls the SERDIN4± PHY.

Bit 5 controls the SERDIN5± PHY.

Bit 6 controls the SERDIN6± PHY.

Bit 7 controls the SERDIN7± PHY.

0x203 GENERIC_PD [7:2] RESERVED Reserved. 0x0 R

PD_SYNCOUT0 Powers down the SYNCOUT0± driver. 0x0 R/W

0 Enables the SYNCOUT0± output pins.

1 Powers down the SYNCOUT0± output pins.

PD_SYNCOUT1 Powers down the SYNCOUT1± driver. 0x1 R/W

0 Enables the SYNCOUT1± output pins.

1 Powers down the SYNCOUT1± output pins.

0x206 CDR_RESET [7:1] RESERVED Reserved. 0x0 R

0 CDR_PHY_RESET PHY reset control bit. Set this bit to 1 to

take the PHYs out of reset during device

operation.

0x0 R/W

0x210 CBUS_ADDR [7:0]

SERDES_CBUS_

ADDR

SERDES configuration control register to

set SERDES configuration address controls.

0x0 R/W

0x212 CBUS_WRSTROBE_

PHY

[7:0] SERDES_CBUS_

WR0

SERDES configuration control register to

commit the SERDES configuration controls

written.

0x0 R/W

0x213 CBUS_WRSTROBE_

OTHER

[7:1] RESERVED Reserved. 0x0 R

SERDES_CBUS_

WR1

SERDES configuration control register to

commit the SERDES configuration controls

written.

0x0 R/W

0x216 CBUS_WDATA [7:0]

SERDES_CBUS_

DATA

SERDES configuration control register to

set the SERDES configuration control data.

0x0 R/W

0x240 EQ_BOOST_PHY_

3_0

[7:6] EQ_BOOST_PHY3 Equalizer setting for PHY 3 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[5:4] EQ_BOOST_PHY2 Equalizer setting for PHY 2 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[3:2] EQ_BOOST_PHY1 Equalizer setting for PHY 1 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[1:0] EQ_BOOST_PHY0 Equalizer setting for PHY 0 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

0x234 CDR_BITINVERSE [7:0]

SEL_IF_

PARDATAINV_DES_

RC_CH

Output data inversion bit controls. Set Bit x

corresponding to PHY x to invert the bit

polarity.

0x66 R/W

0 Not inverted.

1 Inverted.

Data Sheet AD9174

Rev. B | Page 117 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x241 EQ_BOOST_PHY_

7_4

[7:6] EQ_BOOST_PHY7 Equalizer setting for PHY 7 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[5:4] EQ_BOOST_PHY6 Equalizer setting for PHY 6 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[3:2] EQ_BOOST_PHY5 Equalizer setting for PHY 5 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[1:0] EQ_BOOST_PHY4 Equalizer setting for PHY 4 based on

insertion loss of the system.

0x3 R/W

10 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

0x242 EQ_GAIN_PHY_3_0 [7:6] EQ_GAIN_PHY3 Equalizer gain for PHY 3 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[5:4] EQ_GAIN_PHY2 Equalizer gain for PHY 2 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[3:2] EQ_GAIN_PHY1 Equalizer gain for PHY 1 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[1:0] EQ_GAIN_PHY0 Equalizer gain for PHY 0 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

0x243 EQ_GAIN_PHY_7_4 [7:6] EQ_GAIN_PHY7 Equalizer gain for PHY 7 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[5:4] EQ_GAIN_PHY6 Equalizer gain for PHY 6 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[3:2] EQ_GAIN_PHY5 Equalizer gain for PHY 5 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

[1:0] EQ_GAIN_PHY4 Equalizer gain for PHY 4 based on

insertion loss of the system.

0x3 R/W

01 Insertion loss ≤ 11 dB.

11 Insertion loss > 11 dB.

0x244 EQ_FB_PHY_0 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY_0 SERDES equalizer setting for PHY0. Set this

control to 0x1F for optimal performance.

0x19 R/W

0x245 EQ_FB_PHY_1 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY1 SERDES equalizer setting for PHY1. Set this

control to 0x1F for optimal performance.

0x19 R/W

AD9174 Data Sheet

Rev. B | Page 118 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x246 EQ_FB_PHY_2 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY2 SERDES equalizer setting for PHY2. Set this

control to 0x1F for optimal performance.

0x19 R/W

0x247 EQ_FB_PHY_3 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY3 SERDES equalizer setting for PHY3. Set this

control to 0x1F for optimal performance.

0x19 R/W

0x248 EQ_FB_PHY_4 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY4 SERDES equalizer setting for PHY4. Set this

control to 0x1F for optimal performance.

0x19 R/W

0x249 EQ_FB_PHY_5 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY5 SERDES equalizer setting for PHY5. Set this

control to 0x1F for optimal performance.

0x19 R/W

0x24A EQ_FB_PHY_6 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY6 SERDES equalizer setting for PHY6. Set this

control to 0x1F for optimal performance.

0x19 R/W

0x24B EQ_FB_PHY_7 [7:5] RESERVED Reserved. 0x0 R

[4:0] EQ_PHY7 SERDES equalizer setting for PHY7. Set this

control to 0x1F for optimal performance.

0x19 R/W

0x250 LBT_REG_CNTRL_0 [7:0]

EN_LBT_DES_

RC_CH

Enable loopback test for desired physical

lanes per PHY, with Bit x corresponding to

PHY x.

0x0 R/W

0x251 LBT_REG_CNTRL_1 [7:2] RESERVED Reserved. 0x0 R

EN_LBT_

HALFRATE_DES_RC

Enables half rate mode for the loopback

test. If this bit is set to 1, the output data

rate = 2× the input clock frequency. If this

bit is set to 0, the output data rate = the

input clock frequency.

0x1 R/W

INIT_LBT_SYNC_

DES_RC

Initiate the loopback test by toggling this

bit from 0 to 1, then back to 0.

0x0 R/W

0x253 SYNCOUT0_CTRL [7:1] RESERVED Reserved. 0x0 R/W

SEL_SYNCOUT0_

MODE

This control determines the output driver

mode for the SYNCOUT0± pin operation.

Both SYNCOUT0± and SYNCOUT1± must

be set to the same mode of operation.

0x0 R/W

0 SYNCOUT0± is set to CMOS output.

1 SYNCOUT0± is set to LVDS output.

0x254 SYNCOUT1_CTRL [7:1] RESERVED Reserved. 0x0 R/W

SEL_SYNCOUT1_

MODE

This control determines the output driver

mode for the SYNCOUT1± pin operation.

Both SYNCOUT0± and SYNCOUT1± must

be set to the same mode of operation.

0x0 R/W

0 SYNCOUT1± is set to CMOS output.

1 SYNCOUT1± is set to LVDS output.

Data Sheet AD9174

Rev. B | Page 119 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x280 PLL_ENABLE_CTRL [7:3] RESERVED Reserved. 0x0 R

LOLSTICKYCLEAR_

LCPLL_RC

Clears out loss of lock bit. 0x0 R/W

LDSYNTH_LCPLL_

Pulse high to start VCO calibration

(without restarting the regulator or

remeasuring the temperature).

0x0 R/W

SERDES_PLL_

STARTUP

SERDES circuitry blocks are powered off

when this bit is set to 0. Set this bit to 1 at

the end of the SERDES configuration writes.

When this bit is set to 1, it powers up the

SERDES PLL blocks and starts the LDO and

calibration routine to lock the PLL auto-

matically to the appropriate lane rate based

on the JESD204B mode and interpolation

options programmed in the device. The

SERDES_PLL_LOCK bit (Register 0x281,

Bit 0) reads 1 when the PLL achieves lock.

0x1 R/W

0x281 PLL_STATUS [7:1] RESERVED Reserved. 0x0 R

0 SERDES_PLL_LOCK PLL is locked when this bit is high. 0x0 R

0x300 GENERAL_JRX_

CTRL_0

[7:4] RESERVED Reserved. 0x0 R

3 LINK_MODE

Reads back 0 when in single-link mode

and 1 when in dual-link mode.

0x0 R/W

2 LINK_PAGE Link paging. This bit selects which link

0x0 R/W

0 Page QBD0 for Link 0.

1 Page QBD1 for Link 1.

[1:0] LINK_EN These bits bring up the JESD204B digital

receiver when all link parameters are

programmed and all clocks are ready. Bit 0

applies to Link 0, whereas Bit 1 applies to

Link 1. Link 1 is only available in dual-link

mode.

0x0 R/W

0x302 DYN_LINK_

LATENCY_0

[7:6] RESERVED Reserved. 0x0 R

[5:0]

DYN_LINK_

LATENCY_0

Dynamic link latency, Link 0. Latency

between the LMFC receiver for Link 0 and

the last arriving LMFC boundary in units of

PCLK cycles.

0x0 R

0x303 DYN_LINK_

LATENCY_1

[7:6] RESERVED Reserved. 0x0 R

[5:0]

DYN_LINK_

LATENCY_1

Dynamic link latency, Link 1. Latency

between the LMFC receiver for Link 1 and

the last arriving LMFC boundary in units of

PCLK cycles.

0x0 R

0x304 LMFC_DELAY_0 [7:6] RESERVED Reserved. 0x0 R

[5:0] LMFC_DELAY_0 LMFC delay, Link 0. Delay from the LMFC

to the LMFC receiver for Link 0 in units of

PCLK cycles.

0x0 R/W

0x305 LMFC_DELAY_1 [7:6] RESERVED Reserved. 0x0 R

[5:0] LMFC_DELAY_1 LMFC delay, Link 1. Delay from the LMFC

to the LMFC receiver for Link 1 in units of

PCLK cycles.

0x0 R/W

0x306 LMFC_VAR_0 [7:6] RESERVED Reserved. 0x0 R

[5:0] LMFC_VAR_0 Variable delay buffer, Link 0. These bits set

when data is read from a buffer to be con-

sistent across links and power cycles (in units

of PCLK cycles). The maximum value is

0xC.

0x3F R/W

AD9174 Data Sheet

Rev. B | Page 120 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x307 LMFC_VAR_1 [7:6] RESERVED Reserved. 0x0 R

[5:0] LMFC_VAR_1 Variable delay buffer, Link 1. These bits set

when data is read from a buffer to be con-

sistent across links and power cycles (in units

of PCLK cycles). The maximum value is 0xC.

0x3F R/W

0x308 XBAR_LN_0_1 [7:6] RESERVED Reserved. 0x0 R

[5:3]

LOGICAL_LANE1_

SRC

Logical Lane 1 source. These bits select a

physical lane to be mapped onto Logical

Lane 1.

0x1 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

[2:0]

LOGICAL_LANE0_

SRC

Logical Lane 0 source. These bits select a

physical lane to be mapped onto Logical

Lane 0.

0x0 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

0x309 XBAR_LN_2_3 [7:6] RESERVED Reserved. 0x0 R

[5:3]

LOGICAL_LANE3_

SRC

Logical Lane 3 source. These bits select a

physical lane to be mapped onto Logical

Lane 3.

0x3 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

[2:0]

LOGICAL_LANE2_

SRC

Logical Lane 2 source. These bits select a

physical lane to be mapped onto Logical

Lane 2.

0x2 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

Data Sheet AD9174

Rev. B | Page 121 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x30A XBAR_LN_4_5 [7:6] RESERVED Reserved. 0x0 R

[5:3]

LOGICAL_LANE5_

SRC

Logical Lane 5 source. These bits select a

physical lane to be mapped onto Logical

Lane 5.

0x5 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

[2:0]

LOGICAL_LANE4_

SRC

Logical Lane 4 source. These bits select a

physical lane to be mapped onto Logical

Lane 4.

0x4 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

0x30B XBAR_LN_6_7 [7:6] RESERVED Reserved. 0x0 R

[5:3]

LOGICAL_LANE7_

SRC

Logical Lane 7 source. These bits select a

physical lane to be mapped onto Logical

Lane 7.

0x7 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

[2:0]

LOGICAL_LANE6_

SRC

Logical Lane 6 source. These bits select a

physical lane to be mapped onto Logical

Lane 6.

0x6 R/W

000 Data is from SERDIN0±.

001 Data is from SERDIN1±.

010 Data is from SERDIN2±.

011 Data is from SERDIN3±.

100 Data is from SERDIN4±.

101 Data is from SERDIN5±.

110 Data is from SERDIN6±.

111 Data is from SERDIN7±.

0x30C FIFO_STATUS_REG_0 [7:0] LANE_FIFO_FULL Bit x corresponds to FIFO full flag for data

from SERDINx±.

0x0 R

0x30D FIFO_STATUS_REG_1 [7:0] LANE_FIFO_EMPTY Bit x corresponds to FIFO empty flag for

data from SERDINx±.

0x0 R

AD9174 Data Sheet

Rev. B | Page 122 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x311 SYNCOUT_GEN_0 [7:4] RESERVED Reserved. 0x0 R

3 EOMF_MASK_1 Mask end of multiframe (EOMF) from

QBD1. Assert SYNCOUT1± based on the

loss of the multiframe synchronization.

0x0 R/W

0 Do not assert SYNCOUT1± on loss of

multiframe.

1 Assert SYNCOUT1± on loss of multiframe.

2 EOMF_MASK_0 Mask EOMF from QBD0. Assert

SYNCOUT0± based on the loss of the

multiframe synchronization.

0x0 R/W

0 Do not assert SYNCOUT0± on loss of

multiframe.

1 Assert SYNCOUT0± on loss of multiframe.

1 EOF_MASK_1 Mask EOF from QBD1. Assert SYNCOUT1±

based on loss of frame synchronization.

0x0 R/W

0 Do not assert SYNCOUT1± on loss of

frame.

1 Assert SYNCOUT1± on loss of frame.

0 EOF_MASK_0 Mask EOF from QBD0. Assert SYNCOUT0±

based on loss of frame synchronization.

0x0 R/W

0 Do not assert SYNCOUT0± on loss of

frame.

1 Assert SYNCOUT0± on loss of frame.

0x312 SYNCOUT_GEN_1 [7:4] SYNC_ERR_DUR Duration of SYNCOUTx± low for the

purposes of the synchronization error

report. Duration = (0.5 + code) PCLK

cycles. To most closely match the specified

value, set these bits as close as possible to

f/2 PCLK cycles. These bits are shared

between SYNCOUT0± and SYNCOUT1±.

0x0 R/W

[3:0] RESERVED Reserved. 0x0 R/W

0x315 PHY_PRBS_TEST_EN [7:0] PHY_TEST_EN Enable PHY BER by ungating the clocks. 0x0 R/W

0 PHY test disable.

1 PHY test enable.

0x316 PHY_PRBS_TEST_

CTRL

7 RESERVED Reserved. 0x0 R

[6:4] PHY_SRC_ERR_CNT 0x0 R/W

000 Report Lane 0 error count.

001 Report Lane 1 error count.

010 Report Lane 2 error count.

011 Report Lane 3 error count.

100 Report Lane 4 error count.

101 Report Lane 5 error count.

110 Report Lane 6 error count.

111 Report Lane 7 error count.

[3:2] PHY_PRBS_PAT_SEL Select PRBS pattern for PHY BER test. 0x0 R/W

00 PRBS7.

01 PRBS15.

10 PRBS31.

11 Not used.

1 PHY_TEST_START Starts and stops the PHY PRBS test. 0x0 R/W

0 Test not started.

1 Test started.

Data Sheet AD9174

Rev. B | Page 123 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0 PHY_TEST_RESET Resets PHY PRBS test state machine and

error counters.

0x0 R/W

0 Not reset.

1 Reset.

0x317 PHY_PRBS_TEST_

THRESHOLD_

LOBITS

[7:0] PHY_PRBS_

THRESHOLD_

LOBITS

Bits[7:0] of the 24-bit threshold value to

set the error flag for the PHY PRBS test.

0x0 R/W

0x318 PHY_PRBS_TEST_

THRESHOLD_

MIDBITS

[7:0] PHY_PRBS_

THRESHOLD_

MIDBITS

Bits[15:8] of the 24-bit threshold value to

set the error flag for the PHY PRBS test.

0x0 R/W

0x319 PHY_PRBS_TEST_

THRESHOLD_HIBITS

[7:0] PHY_PRBS_

THRESHOLD_

HIBITS

Bits[23:16] of the 24-bit threshold value to

set the error flag for the PHY PRBS test.

0x0 R/W

0x31A PHY_PRBS_TEST_

ERRCNT_LOBITS

[7:0] PHY_PRBS_ERR_

CNT_LOBITS

Bits[7:0] of the 24-bit reported PHY BER

error count from the selected lane.

0x0 R

0x31B PHY_PRBS_TEST_

ERRCNT_MIDBITS

[7:0] PHY_PRBS_ERR_

CNT_MIDBITS

Bits[15:8] of the 24-bit reported PHY BER

error count from the selected lane.

0x0 R

0x31C PHY_PRBS_TEST_

ERRCNT_HIBITS

[7:0] PHY_PRBS_ERR_

CNT_HIBITS

Bits[23:16] of the 24-bit reported PHY BER

error count from the selected lane.

0x0 R

0x31D PHY_PRBS_TEST_

STATUS

[7:0] PHY_PRBS_PASS Reports PHY BER pass/fail for each lane.

Bit x is high when Lane x passes.

0xFF R

0x31E PHY_DATA_

SNAPSHOT_CTRL

[7:2] RESERVED Reserved. 0x0 R

1 PHY_GRAB_MODE

This bit determines whether to use the

trigger to grab data.

0x0 R/W

0 Grab data when PHY_GRAB_DATA is set.

1 Grab data upon bit error.

0 PHY_GRAB_DATA Transitioning this bit from 0 to 1 causes

the logic to store current receive data from

one lane.

0x0 R/W

0x31F PHY_SNAPSHOT_

DATA_BYTE0

[7:0] PHY_SNAPSHOT_D

ATA_BY TE0

Current data received. Represents

PHY_SNAPSHOT_DATA[7:0].

0x0 R

0x320 PHY_SNAPSHOT_

DATA_BYTE1

[7:0] PHY_SNAPSHOT_D

ATA_BY TE1

Current data received. Represents

PHY_SNAPSHOT_DATA[15:8].

0x0 R

0x321 PHY_SNAPSHOT_

DATA_BYTE2

[7:0] PHY_SNAPSHOT_D

ATA_BY TE2

Current data received. Represents

PHY_SNAPSHOT_DATA[23:16].

0x0 R

0x322 PHY_SNAPSHOT_

DATA_BYTE3

[7:0] PHY_SNAPSHOT_D

ATA_BY TE3

Current data received. Represents

PHY_SNAPSHOT_DATA[31:24].

0x0 R

0x323 PHY_SNAPSHOT_

DATA_BYTE4

[7:0] PHY_SNAPSHOT_D

ATA_BY TE4

Current data received. Represents

PHY_SNAPSHOT_DATA[39:32].

0x0 R

AD9174 Data Sheet

Rev. B | Page 124 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x32C SHORT_TPL_TEST_0 [7:4]

SHORT_TPL_SP_

SEL

Short transport layer sample select. Selects

which sample to check from a specific

DAC.

0x0 R/W

0000 Sample 0.

0001 Sample 1.

0010 Sample 2.

0011 Sample 3.

0100 Sample 4.

0101 Sample 5.

0110 Sample 6.

0111 Sample 7.

1000 Sample 8.

1001 Sample 9.

1010 Sample 10.

1011 Sample 11.

1100 Sample 12.

1101 Sample 13.

1110 Sample 14.

1111 Sample 15.

[3:2]

SHORT_TPL_CHAN_

SEL

Short transport layer test channel select.

Selects which subchannel of the DACx

channelizer to test.

0x0 R/W

00 Channel 0.

01 Channel 1.

10 Channel 2.

SHORT_TPL_TEST_

RESET

Short transport layer test reset. Resets the

result of short transport layer test.

0x0 R/W

0 Not reset.

1 Reset.

SHORT_TPL_TEST_

Short transport layer test enable. Enable

short transport layer test.

0x0 R/W

0 Disable.

1 Enable.

0x32D SHORT_TPL_TEST_1 [7:0] SHORT_TPL_REF_

SP_LSB

Short transport layer reference sample,

LSB. This bit field is the lower eight bits of

the expected DAC sample during the short

transport layer test and is used to compare

with the received sample at the JESD204B

receiver output.

0x0 R/W

0x32E SHORT_TPL_TEST_2 [7:0]

SHORT_TPL_REF_

SP_MSB

Short transport layer test reference

sample, MSB. This bit field is the upper

eight bits of the expected DAC sample

during the short transport layer test and is

used to compare with the received sample

at the JESD204B receiver output.

0x0 R/W

Data Sheet AD9174

Rev. B | Page 125 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x32F SHORT_TPL_TEST_3 7 SHORT_TPL_LINK_

SEL

For running STPL on dual-link JESD204B

modes. Selects whether the STPL test is

performed on samples that are addressed to

the DAC0 channelizers/datapaths (Link 0), or

the DAC1 channelizers/datapaths (Link 1).

0x0 R/W

0 Link 0 samples are tested.

1 Link 1 samples are tested.

SHORT_TPL_IQ_

SAMPLE_SEL

Selects which data stream (path) to test for

a complex subchannel of the channelizer, I

or Q. For nonIQ JESD204B modes, select

the I path.

0x0 R/W

0 Select to test the I data stream.

1 Select to test the Q data stream.

[5:1] RESERVED Reserved. 0x0 R/W

0 SHORT_TPL_FAIL Short transport layer test fail. This bit

shows if the selected DAC sample matches

the expected sample for the short

transport layer test. If they match, the test

passes. Otherwise, the test fails.

0x0 R

0 Test pass.

1 Test fail.

0x334 JESD_BIT_INVERSE_

CTRL

[7:0] JESD_BIT_INVERSE Logical lane invert. Each bit of this control

inverses the JESD204B deserialized data

from one specific JESD204B receiver PHY.

Set Bit x high to invert the JESD204B

deserialized data on Logical Lane x.

0x0 R/W

0x400 DID_REG [7:0] DID_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x401 BID_REG [7:0] BID_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x402 LID0_REG 7 RESERVED Reserved. 0x0 R

6 ADJDIR_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

5 PHADJ_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[4:0] LL_LID0 Received ILAS LID configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x403 SCR_L_REG 7 SCR_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Scrambling is disabled.

1 Scrambling is enabled.

[6:5] RESERVED Reserved. 0x0 R

[4:0] L_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

00000 1 lane per converter device.

00001 2 lanes per converter device.

00010 3 lanes per converter device.

00011 4 lanes per converter device.

AD9174 Data Sheet

Rev. B | Page 126 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x404 F_REG [7:0] F_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 1 octet per frame.

1 2 octets per frame.

10 3 octets per frame.

11 4 octets per frame.

0x405 K_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] K_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

00000 Default value.

11111 32 frames per multiframe.

0x406 M_REG [7:0] M_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x407 CS_N_REG [7:6] CS_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

5 RESERVED Reserved. 0x0 R

[4:0] N_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x408 NP_REG [7:5] SUBCLASSV_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[4:0] NP_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x409 S_REG [7:5] JESDV_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

000 JESD204A.

001 JESD204B.

[4:0] S_RD_1 Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x40A HD_CF_REG 7 HD_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Low density mode.

1 High density mode.

[6:5] RESERVED Reserved. 0x0 R

[4:0] CF_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x40B RES1_REG [7:0] RES1_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x40C RES2_REG [7:0] RES2_RD Received ILAS configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x40D CHECKSUM0_REG [7:0] LL_FCHK0 Received checksum during ILAS on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

Data Sheet AD9174

Rev. B | Page 127 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x40E COMPSUM0_REG [7:0] LL_FCMP0 Computed checksum on Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x412 LID1_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] LL_LID1 Received ILAS LID configuration on Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x415 CHECKSUM1_REG [7:0] LL_FCHK1 Received checksum during ILAS on Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x416 COMPSUM1_REG [7:0] LL_FCMP1 Computed checksum on Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x41A LID2_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] LL_LID2 Received ILAS LID configuration on Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x41D CHECKSUM2_REG [7:0] LL_FCHK2 Received checksum during ILAS on Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x41E COMPSUM2_REG [7:0] LL_FCMP2 Computed checksum on Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x422 LID3_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] LL_LID3 Received ILAS LID configuration on Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x425 CHECKSUM3_REG [7:0] LL_FCHK3 Received checksum during ILAS on Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x426 COMPSUM3_REG [7:0] LL_FCMP3 Computed checksum on Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x42A LID4_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] LL_LID4 Received ILAS LID configuration on Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x42D CHECKSUM4_REG [7:0] LL_FCHK4 Received checksum during ILAS on Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x42E COMPSUM4_REG [7:0] LL_FCMP4 Computed checksum on Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x432 LID5_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] LL_LID5 Received ILAS LID configuration on Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x435 CHECKSUM5_REG [7:0] LL_FCHK5 Received checksum during ILAS on Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x436 COMPSUM5_REG [7:0] LL_FCMP5 Computed checksum on Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x43A LID6_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] LL_LID6 Received ILAS LID configuration on Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

AD9174 Data Sheet

Rev. B | Page 128 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x43D CHECKSUM6_REG [7:0] LL_FCHK6 Received checksum during ILAS on Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x43E COMPSUM6_REG [7:0] LL_FCMP6 Computed checksum on Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x442 LID7_REG [7:5] RESERVED Reserved. 0x0 R

[4:0] LL_LID7 Received ILAS LID configuration on Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x445 CHECKSUM7_REG [7:0] LL_FCHK7 Received checksum during ILAS on Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0x446 COMPSUM7_REG [7:0] LL_FCMP7 Computed checksum on Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0x450 ILS_DID [7:0] DID Device (link) identification number. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R/W

0x451 ILS_BID [7:0] BID Bank ID, extension to DID. This control is

paged by the LINK_PAGE control in

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0 R/W

0x452 ILS_LID0 7 RESERVED Reserved. 0x0 R

6 ADJDIR Direction to adjust the DAC LMFC. Link

information is received on Link Lane 0 as

specified in Section 8.3 of JESD204B. Only

Link 0 is supported. This control is paged

by the LINK_PAGE control in Register 0x300.

0x0 R/W

5 PHADJ Phase adjustment request to the DAC.

Only Link 0 is supported. This control is

paged by the LINK_PAGE control in Register

0x300.

0x0 R/W

[4:0] LID0 Lane identification number (within link).

This control is paged by the LINK_PAGE

control in Register 0x300. This signal must

only be programmed while the QBD is

held in soft reset (Register 0x475, Bit 3), and

must not be changed during normal

operation.

0x0 R/W

0x453 ILS_SCR_L 7 SCR Scramble enabled for the link. This control

is paged by the LINK_PAGE control in

0x1 R/W

0 Descrambling is disabled.

1 Descrambling is enabled.

[6:5] RESERVED Reserved. 0x0 R

[4:0] L_1 Number of lanes per converter (minus 1).

This control is paged by the LINK_PAGE

control in Register 0x300.

0x7 R/W

0x454 ILS_F [7:0] F_1 Number of octets per frame per lane

(minus 1). This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R/W

0x455 ILS_K [7:5] RESERVED Reserved. 0x0 R

[4:0] K_1 Number of frames per multiframe (minus 1).

This control is paged by the LINK_PAGE

control in Register 0x300.

0x1F R/W

11111 32 frames per multiframe.

Data Sheet AD9174

Rev. B | Page 129 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x456 ILS_M [7:0] M_1 Number of subchannels per link (minus 1).

This control is paged by the LINK_PAGE

control in Register 0x300.

0x1 R/W

0x457 ILS_CS_N [7:6] CS Number of control bits per sample. Only

Link 0 is supported. This control is paged

by the LINK_PAGE control in Register 0x300.

0x0 R

5 RESERVED Reserved. 0x0 R

[4:0] N_1 Converter resolution (minus 1). This

control is paged by the LINK_PAGE control

in Register 0x300.

0xF R/W

0x458 ILS_NP [7:5] SUBCLASSV Device subclass version. This control is

paged by the LINK_PAGE control in

0x0 R/W

000 Subclass 0.

001 Subclass 1.

[4:0] NP_1 Total number of bits per sample (minus 1).

This control is paged by the LINK_PAGE

control in Register 0x300.

0xF R/W

0x459 ILS_S [7:5] JESDV JESD204 version. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0 R/W

000 JESD204A.

001 JESD204B.

[4:0] S_1 Number of samples per converter per

frame cycle (minus 1). This control is paged

by the LINK_PAGE control in Register 0x300.

0x1 R/W

0x45A ILS_HD_CF 7 HD High density format, always set to 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x1 R

0 Low density mode.

1 High density mode.

[6:5] RESERVED Reserved. 0x0 R

[4:0] CF Number of control bits per sample. Only

Link 0 is supported. This control is paged

by the LINK_PAGE control in Register 0x300.

0x0 R

0x45B ILS_RES1 [7:0] RES1 Reserved field 1. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0 R/W

0x45C ILS_RES2 [7:0] RES2 Reserved field 2. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0 R/W

0x45D ILS_CHECKSUM [7:0] FCHK0 Calculated link configuration checksum. This

control is paged by the LINK_PAGE control

in Register 0x300. This signal must only be

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0 R/W

0x46C LANE_DESKEW 7 ILD7 Interlane deskew status for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

6 ILD6 Interlane deskew status for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

AD9174 Data Sheet

Rev. B | Page 130 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

5 ILD5 Interlane deskew status for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

4 ILD4 Interlane deskew status for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILD3 Interlane deskew status for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

2 ILD2 Interlane deskew status for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

1 ILD1 Interlane deskew status for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

0 ILD0 Interlane deskew status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

0x46D BAD_DISPARITY 7 BDE7 Bad disparity errors status for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < error threshold (ETH)[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 BDE6 Bad disparity errors status for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 BDE5 Bad disparity errors status for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 BDE4 Bad disparity errors status for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

3 BDE3 Bad disparity errors status for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

Data Sheet AD9174

Rev. B | Page 131 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

2 BDE2 Bad disparity errors status for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

1 BDE1 Bad disparity errors status for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

0 BDE0 Bad disparity errors status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

0x46E NOT_IN_TABLE 7 NIT7 Not in table errors status for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT6 Not in table errors status for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 NIT5 Not in table errors status for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 NIT4 Not in table errors status for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

3 NIT3 Not in table errors status for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

2 NIT2 Not in table errors status for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

1 NIT1 Not in table errors status for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

0 NIT0 Not in table errors status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

AD9174 Data Sheet

Rev. B | Page 132 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x46F UNEXPECTED_

KCHAR

7 UEK7 Unexpected K character errors status, Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 UEK6 Unexpected K character errors status, Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK5 Unexpected K character errors status, Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 UEK4 Unexpected K character errors status, Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

3 UEK3 Unexpected K character errors status, Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

2 UEK2 Unexpected K character errors status, Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

1 UEK1 Unexpected K character errors status, Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

0 UEK0 Unexpected K character errors status, Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

0x470 CODE_GRP_SYNC 7 CGS7 Code group synchronization status for

Lane 7. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

6 CGS6 Code group synchronization status for

Lane 6. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

5 CGS5 Code group synchronization status for

Lane 5. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

Data Sheet AD9174

Rev. B | Page 133 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

4 CGS4 Code group synchronization status for

Lane 4. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

3 CGS3 Code group synchronization status for

Lane 3. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CGS2 Code group synchronization status for

Lane 2. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

1 CGS1 Code group synchronization status for

Lane 1. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS0 Code group synchronization status for

Lane 0. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x471 FRAME_SYNC 7 FS7 Frame synchronization status for Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

6 FS6 Frame synchronization status for Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

5 FS5 Frame synchronization status for Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

4 FS4 Frame synchronization status for Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

3 FS3 Frame synchronization status for Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 FS2 Frame synchronization status for Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

AD9174 Data Sheet

Rev. B | Page 134 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

1 FS1 Frame synchronization status for Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 FS0 Frame synchronization status for Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x472 GOOD_CHECKSUM 7 CKS7 Computed checksum status for Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

6 CKS6 Computed checksum status for Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

5 CKS5 Computed checksum status for Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

4 CKS4 Computed checksum status for Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

3 CKS3 Computed checksum status for Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

2 CKS2 Computed checksum status for Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 CKS1 Computed checksum status for Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

0 CKS0 Computed checksum status for Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

Data Sheet AD9174

Rev. B | Page 135 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x473 INIT_LANE_SYNC 7 ILS7 Initial lane synchronization status for Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

6 ILS6 Initial lane synchronization status for Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

5 ILS5 Initial lane synchronization status for Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

4 ILS4 Initial lane synchronization status for Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

3 ILS3 Initial lane synchronization status for Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 ILS2 Initial lane synchronization status for Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

1 ILS1 Initial lane synchronization status for Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 ILS0 Initial lane synchronization status for Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x475 CTRLREG0 [7:4] RESERVED Reserved. 0x0 R/W

3 SOFTRST QBD soft reset. Active high synchronous

reset. Resets all hardware to power-on

state. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R/W

2 FORCESYNCREQ Command from application to assert a

synchronization request. Active high. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R/W

1 RESERVED Reserved. 0x0 R

0 REPL_FRM_ENA When this level input is set, it enables the

replacement of frames received in error.

This control is paged by the LINK_PAGE

control in Register 0x300. This signal must

only be programmed while the QBD is

held in soft reset (Register 0x475, Bit 3), and

must not be changed during normal

operation.

0x1 R/W

AD9174 Data Sheet

Rev. B | Page 136 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x476 CTRLREG1 [7:5] RESERVED Reserved. 0x0 R

4 QUAL_RDERR Error reporting behavior for concurrent

not in table (NIT) and running disparity

(RD) errors. This control is paged by the

LINK_PAGE control in Register 0x300. Set

this bit to 1. This signal must only be

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x1 R/W

0 NIT has no effect on RD error.

1 NIT error masks concurrent with RD error.

[3:1] RESERVED Reserved. 0x0 R/W

0 FCHK_N Checksum calculation method. This

control is paged by the LINK_PAGE control

in Register 0x300. This signal must only be

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0 R/W

0 Checksum is calculated by summing the

individual fields in the link configuration

table as defined in Section 8.3, Table 20 of

the JESD204B standard.

1 Checksum is calculated by summing the

registers containing the packed link

configuration fields (sum of Register 0x450

to Register 0x45A, modulo 256).

0x477 CTRLREG2 7 ILS_MODE Data link layer test mode is enabled when

this bit is set to 1. CGS pattern is followed

by a perpetual ILAS sequence. This control

is paged by the LINK_PAGE control in

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0 R/W

0 Normal mode.

1 CGS pattern is followed by a perpetual

ILAS sequence.

6 RESERVED Reserved. 0x0 R/W

5 REPDATATEST Repetitive data test enable using the

JTSPAT pattern. To enable the test, Bit 7 of

this register must = 0. This control is paged

by the LINK_PAGE control in Register 0x300.

This signal must only be programmed

while the QBD is held in soft reset

(Register 0x475, Bit 3), and must not be

changed during normal operation.

0x0 R/W

4 QUETESTERR Queue test error mode. This control is

paged by the LINK_PAGE control in

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0 R/W

0 When this bit = 0, simultaneous errors on

multiple lanes are reported as one error.

1 Selected when this bit = 1 and when

REPDATATEST = 1. Detected errors from all

lanes are trapped in a counter and

sequentially signaled on SYNCOUTx±.

Data Sheet AD9174

Rev. B | Page 137 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

3 AR_ECNTR Automatic reset of error counter. The error

counter that causes assertion of SYNCOUTx±

is automatically reset to 0 when AR_ECNTR =

1. All other counters are unaffected. This

control is paged by the LINK_PAGE control

in Register 0x300. This signal must only be

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0 R/W

[2:0] RESERVED Reserved. 0x0 R

0x478 KVAL [7:0] KSYNC Number of 4 × K multiframes during ILAS.

This control is paged by the LINK_PAGE

control in Register 0x300. This signal must

only be programmed while the QBD is

held in soft reset (Register 0x475, Bit 3), and

must not be changed during normal

operation.

0x1 R/W

0x47C ERRORTHRES [7:0] ETH Error counter threshold value. These bits

set when a SYNCOUTx± error or IRQx

interrupt is sent due to BD, NIT, or UEK

errors. This control is paged by the

LINK_PAGE control in Register 0x300. This

signal must only be programmed while

the QBD is held in soft reset

(Register 0x475, Bit 3), and must not be

changed during normal operation.

0xFF R/W

0x47D SYNC_ASSERT_

MASK

[7:3] RESERVED Reserved. 0x0 R

[2:0]

SYNC_ASSERT_

MASK

SYNCOUTx± assertion enable mask for BD,

NIT, and UEK error conditions. This control

is paged by the LINK_PAGE control in

assertion enable mask for BD, NIT, and UEK

error conditions, respectively. When an

error counter, in any lane, has reached the

error threshold count, ETH[7:0], and the

corresponding SYNC_ASSERT_MASK bit is

set, SYNCOUTx± is asserted. The mask bits

are as follows (the bit sequence is reversed

with respect to the other error count

controls and the error counters):

0x7 R/W

Bit 2 = bad disparity error (BDE).

Bit 1 = not in table error (NIT).

Bit 0 = unexpected K character error (UEK).

0x480 ECNT_CTRL0 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA0 Error counter enables for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST0 Reset error counters for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = bad disparity error (BDE).

Bit 1 = not in table error (NIT).

Bit 0 = unexpected K character error (UEK).

AD9174 Data Sheet

Rev. B | Page 138 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x481 ECNT_CTRL1 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA1 Error counter enables for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST1 Reset error counters for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x482 ECNT_CTRL2 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA2 Error counter enables for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST2 Reset error counters for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x483 ECNT_CTRL3 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA3 Error counter enables for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST3 Reset error counters for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

Data Sheet AD9174

Rev. B | Page 139 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x484 ECNT_CTRL4 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA4 Error counter enables for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST4 Reset error counters for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x485 ECNT_CTRL5 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA5 Error counter enables for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST5 Reset error counters for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x486 ECNT_CTRL6 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA6 Error counter enables for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST6 Reset error counters for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

AD9174 Data Sheet

Rev. B | Page 140 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x487 ECNT_CTRL7 [7:6] RESERVED Reserved. 0x0 R

[5:3] ECNT_ENA7 Error counter enables for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0] ECNT_RST7 Reset error counters for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x488 ECNT_TCH0 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH0 Terminal count hold enable of error counters

for Lane 0. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x489 ECNT_TCH1 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH1 Terminal count hold enable of error counters

for Lane 1. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

Data Sheet AD9174

Rev. B | Page 141 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x48A ECNT_TCH2 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH2 Terminal count hold enable of error counters

for Lane 2. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x48B ECNT_TCH3 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH3 Terminal count hold enable of error counters

for Lane 3. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x48C ECNT_TCH4 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH4 Terminal count hold enable of error counters

for Lane 4. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

AD9174 Data Sheet

Rev. B | Page 142 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x48D ECNT_TCH5 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH5 Terminal count hold enable of error counters

for Lane 5. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x48E ECNT_TCH6 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH6 Terminal count hold enable of error counters

for Lane 6. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x48F ECNT_TCH7 [7:3] RESERVED Reserved. 0x0 R

[2:0] ECNT_TCH7 Terminal count hold enable of error counters

for Lane 7. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7 R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

Data Sheet AD9174

Rev. B | Page 143 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x490 ECNT_STAT0 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA0 This output indicates if Lane 0 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR0 Terminal count reached indicator of error

counters for Lane 0. This control is paged

by the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the

corresponding counter terminal count

value of 0xFF is reached. If ECNT_TCHx is

set, the terminal count value for the

corresponding counter is held until the

counter is reset by the user; otherwise, the

counter rolls over and continues counting.

Counters of each lane are addressed as

follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x491 ECNT_STAT1 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA1 This output indicates if Lane 1 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR1 Terminal count reached indicator of error

counters for Lane 1. This control is paged

by the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the

corresponding counter terminal count

value of 0xFF is reached. If ECNT_TCHx is

set, the terminal count value for the

corresponding counter is held until the

counter is reset by the user; otherwise, the

counter rolls over and continues counting.

Counters of each lane are addressed as

follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x492 ECNT_STAT2 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA2 This output indicates if Lane 2 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR2 Terminal count reached indicator of error

counters for Lane 2. This control is paged

by the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the

user; otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

AD9174 Data Sheet

Rev. B | Page 144 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x493 ECNT_STAT3 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA3 This output indicates if Lane 3 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR3 Terminal count reached indicator of error

counters for Lane 3. This control is paged

by the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the

user; otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x494 ECNT_STAT4 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA4 This output indicates if Lane 4 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR4 Terminal count reached indicator of error

counters for Lane 4. This control is paged by

the LINK_PAGE control in Register 0x300. Set

these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the

user; otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x495 ECNT_STAT5 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA5 This output indicates if Lane 5 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR5 Terminal count reached indicator of error

counters for Lane 5. This control is paged by

the LINK_PAGE control in Register 0x300. Set

these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the

user; otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

Data Sheet AD9174

Rev. B | Page 145 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x496 ECNT_STAT6 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA6 This output indicates if Lane 6 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR6 Terminal count reached indicator of error

counters for Lane 6. This control is paged

by the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the

user; otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x497 ECNT_STAT7 [7:4] RESERVED Reserved. 0x0 R

3 LANE_ENA7 This output indicates if Lane 7 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

[2:0] ECNT_TCR7 Terminal count reached indicator of error

counters for Lane 7. This control is paged

by the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the

user; otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0 R

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x4B0 LINK_STATUS0 7 BDE0 Bad disparity errors status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT0 Not in table errors status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK0 Unexpected K character errors status for

Lane 0. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 ILD0 Interlane deskew status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

AD9174 Data Sheet

Rev. B | Page 146 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

3 ILS0 Initial lane synchronization status for Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS0 Computed checksum status for Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 FS0 Frame synchronization status for Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS0 Code group synchronization status for

Lane 0. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x4B1 LINK_STATUS1 7 BDE1 Bad disparity errors status for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT1 Not in table errors status for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK1 Unexpected K character errors status for

Lane 1. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 ILD1 Interlane deskew status for Lane 1. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILS1 Initial lane synchronization status for Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS1 Computed checksum status for Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 FS1 Frame synchronization status for Lane 1.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

Data Sheet AD9174

Rev. B | Page 147 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0 CGS1 Code group synchronization status for

Lane 1. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x4B2 LINK_STATUS2 7 BDE2 Bad disparity errors status for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT2 Not in table errors status for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK2 Unexpected K character errors status for

Lane 2. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 ILD2 Interlane deskew status for Lane 2. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILS2 Initial lane synchronization status for Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS2 Computed checksum status for Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 FS2 Frame synchronization status for Lane 2.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS2 Code group synchronization status for

Lane 2. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

AD9174 Data Sheet

Rev. B | Page 148 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x4B3 LINK_STATUS3 7 BDE3 Bad disparity errors status for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT3 Not in table errors status for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK3 Unexpected K character errors status for

Lane 3. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 ILD3 Interlane deskew status for Lane 3. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILS3 Initial lane synchronization status for Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS3 Computed checksum status for Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 FS3 Frame synchronization status for Lane 3.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS3 Code group synchronization status for

Lane 3. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x4B4 LINK_STATUS4 7 BDE4 Bad disparity errors status for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT4 Not in table errors status for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK4 Unexpected K character errors status for

Lane 4. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

Data Sheet AD9174

Rev. B | Page 149 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

4 ILD4 Interlane deskew status for Lane 4. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILS4 Initial lane synchronization status for Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS4 Computed checksum status for Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 FS4 Frame synchronization status for Lane 4.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS4 Code group synchronization status for

Lane 4. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x4B5 LINK_STATUS5 7 BDE5 Bad disparity errors status for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT5 Not in table errors status for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK5 Unexpected K character errors status for

Lane 5. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 ILD5 Interlane deskew status for Lane 5. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILS5 Initial lane synchronization status for Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS5 Computed checksum status for Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

AD9174 Data Sheet

Rev. B | Page 150 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

1 FS5 Frame synchronization status for Lane 5.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS5 Code group synchronization status for

Lane 5. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x4B6 LINK_STATUS6 7 BDE6 Bad disparity errors status for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT6 Not in table errors status for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK6 Unexpected K character errors status for

Lane 6. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 ILD6 Interlane deskew status for Lane 6. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILS6 Initial lane synchronization status for Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS6 Computed checksum status for Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 FS6 Frame synchronization status for Lane 6.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS6 Code group synchronization status for

Lane 6. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

Data Sheet AD9174

Rev. B | Page 151 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x4B7 LINK_STATUS7 7 BDE7 Bad disparity errors status for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

6 NIT7 Not in table errors status for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

5 UEK7 Unexpected K character errors status Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Error count < ETH[7:0] value.

1 Error count ≥ ETH[7:0] value.

4 ILD7 Interlane deskew status for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0 R

0 Deskew failed.

1 Deskew achieved.

3 ILS7 Initial lane synchronization status for Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

2 CKS7 Computed checksum status for Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Checksum is incorrect.

1 Checksum is correct.

1 FS7 Frame synchronization status for Lane 7.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0 CGS7 Code group synchronization status for

Lane 7. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R

0 Synchronization lost.

1 Synchronization achieved.

0x4B8 JESD_IRQ_ENABLEA 7 EN_BDE Bad disparity error counter. This control is

paged by the LINK_PAGE control in

0x0 R/W

6 EN_NIT Not in table error counter. This control is

paged by the LINK_PAGE control in

0x0 R/W

5 EN_UEK Unexpected K error counter. This control is

paged by the LINK_PAGE control in

0x0 R/W

4 EN_ILD Interlane deskew. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0 R/W

3 EN_ILS Initial lane synchronization. This control is

paged by the LINK_PAGE control in

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 152 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

2 EN_CKS Good checksum. This bit compares two

checksums: the checksum that the trans-

mitter sent over the link during the ILAS

and the checksum that the receiver

calculated from the ILAS data that the

transmitter sent over the link. The checksum

IRQ only looks at data sent by the trans-

mitter and not the checksum programmed

into Register 0x45D. This control is paged

by the LINK_PAGE control in Register 0x300.

0x0 R/W

1 EN_FS Frame synchronization. This control is

paged by the LINK_PAGE control in

0x0 R/W

0 EN_CGS Code group synchronization. This control

is paged by the LINK_PAGE control in

0x0 R/W

0x4B9 JESD_IRQ_ENABLEB [7:1] RESERVED Reserved. 0x0 R

0 EN_ILAS Configuration mismatch (checked for Lane 0

only). The ILAS IRQ compares the two sets

of ILAS data obtained by the receiver. The

first set of data is the ILAS data sent over

the JESD204B link by the transmitter. The

second set of data is the ILAS data

programmed into the receiver via the SPI

(Register 0x450 to Register 0x45D). If any

of the data differs, the IRQ is triggered. All

of the ILAS data, including the checksum,

is compared. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0 R/W

0x4BA JESD_IRQ_STATUSA 7 IRQ_BDE Bad disparity error counter. This control is

paged by the LINK_PAGE control in

0x0 R/W

6 IRQ_NIT Not in table error counter. This control is

paged by the LINK_PAGE control in

0x0 R/W

5 IRQ_UEK Unexpected K error counter. This control is

paged by the LINK_PAGE control in

0x0 R/W

4 IRQ_ILD Interlane deskew. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0 R/W

3 IRQ_ILS Initial lane synchronization. This control is

paged by the LINK_PAGE control in

0x0 R/W

2 IRQ_CKS Good checksum. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0 R/W

1 IRQ_FS Frame synchronization. This control is

paged by the LINK_PAGE control in

0x0 R/W

0 IRQ_CGS Code group synchronization. This control

is paged by the LINK_PAGE control in

0x0 R/W

0x4BB JESD_IRQ_STATUSB [7:1] RESERVED Reserved. 0x0 R

0 IRQ_ILAS Configuration mismatch (checked for Lane 0

only). This control is paged by the LINK_PAGE

control in Register 0x300.

0x0 R/W

Data Sheet AD9174

Rev. B | Page 153 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x4BC IRQ_OUTPUT_MUX_

JESD

[7:1] RESERVED Reserved. 0x0 R

0 MUX_JESD_IRQ

Selects which IRQ pin is connected to the

JESD204B IRQx sources.

0x0 R/W

0 Route the IRQ trigger signal to the IRQ0 pin.

1 Route the IRQ trigger signal to the IRQ1 pin.

0x580 BE_SOFT_OFF_

GAIN_CTRL

7 BE_SOFT_OFF_

GAIN_EN

Must be 1 to use soft off/on. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

[6:3] RESERVED Reserved. 0x0 R

[2:0]

BE_GAIN_RAMP_

RATE

Sets ramp rate. The gain ramps from 0 to 1

(or 1 to 0) in 32 steps over 2(CODE + 8) DAC

clock periods. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

0x581 BE_SOFT_OFF_

ENABLE

7 ENA_SHORT_

PAERR_SOFTOFF

Enable short PA error soft off. This control

is paged by the MAINDAC_PAGE control in

0x1 R/W

ENA_LONG_

PAERR_SOFTOFF

Enable long PA error soft off. This control is

paged by the MAINDAC_PAGE control in

0x1 R/W

[5:4] RESERVED Reserved. 0x0 R

ENA_JESD_ERR_

SOFTOFF

Enable JESD204B side error soft off. This

control is paged by the MAINDAC_PAGE

control in Register 0x008.

0x0 R/W

ROTATE_SOFT_

OFF_EN

When set to 1, the synchronization logic

rotation triggers the DAC output soft off.

control is paged by the MAINDAC_PAGE

control in Register 0x008.

0x1 R/W

TXEN_SOFT_OFF_E

When set to 1, a TXENx falling edge

triggers the DAC output soft off. This

control is paged by the MAINDAC_PAGE

control in Register 0x008.

0x1 R/W

0 SPI_SOFT_OFF_EN Force a soft off when gain is 1. This control

is paged by the MAINDAC_PAGE control in

0x0 R/W

0x582 BE_SOFT_ON_

ENABLE

7 SPI_SOFT_ON_EN Force a soft on when gain is 0. This control

is paged by the MAINDAC_PAGE control in

0x0 R/W

LONG_LEVEL_

SOFTON_EN

When set to 1, this bit enables the long

level soft on. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x1 R/W

[5:0] RESERVED Reserved. 0x0 R/W

0x583 LONG_PA_THRES_

LSB

[7:0] LONG_PA_

THRESHOLD[7:0]

Long average power threshold for

comparison. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

0x584 LONG_PA_THRES_

MSB

[7:5] RESERVED Reserved. 0x0 R

[4:0]

LONG_PA_

THRESHOLD[12:8]

Long average power threshold for

comparison. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 154 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x585 LONG_PA_CONTROL 7 LONG_PA_ENABLE Enable long average power calculation and

error detection. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

[6:4] RESERVED Reserved. 0x0 R

[3:0]

LONG_PA_AVG_

TIME

Sets length of long PA averaging time. This

control is paged by the MAINDAC_PAGE

control in Register 0x008. Averaging time =

29 + LONG_PA_AVG_TIME (PA clock periods).

A PA clock period is calculated by the

following:

0x0 R/W

If the main interpolation is >1×, PA clock

period = 4 × main interpolation × DAC

clock period.

If channel interpolation is >1×, PA clock

period = 8 × main interpolation × DAC

clock period.

Otherwise, PA clock period = 32 × DAC

clock period.

0x586 LONG_PA_POWER_

LSB

[7:0] LONG_PA_

POWER[7:0]

Long average power readback. Power

detected at data bus = I2 + Q2. The data

bus calculation only uses the 6 MSBs of the

I and Q data bus samples. This control is

paged by the MAINDAC_PAGE control in

0x0 R

0x587 LONG_PA_POWER_

MSB

[7:5] RESERVED Reserved. 0x0 R

[4:0]

LONG_PA_

POWER[12:8]

Long average power readback. Power

detected at data bus = I2 + Q2. The data

bus calculation only uses the 6 MSBs of the

I and Q data bus samples. This control is

paged by the MAINDAC_PAGE control in

0x0 R

0x588 SHORT_PA_THRES_

LSB

[7:0] SHORT_PA_

THRESHOLD[7:0]

Short average power threshold for

comparison. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

0x589 SHORT_PA_THRES_

MSB

[7:5] RESERVED Reserved. 0x0 R

[4:0]

SHORT_PA_

THRESHOLD[12:8]

Short average power threshold for

comparison. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

0x58A SHORT_PA_

CONTROL

7 SHORT_PA_ENABLE Enable short average power calculation and

error detection. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

[6:2] RESERVED Reserved. 0x0 R

[1:0]

SHORT_PA_AVG_

TIME

Sets length of short PA averaging. This

control is paged by the MAINDAC_PAGE

control in Register 0x008. Averaging time =

2SHORT_PA_AVG_TIME (PA clock periods). A PA

clock period is calculated by the following:

0x0 R/W

If the main interpolation is >1×, PA clock

period = 4 × main interpolation × DAC

clock period.

If channel interpolation is >1×, PA clock

period = 8 × main interpolation × DAC

clock period.

Otherwise, PA clock period = 32 × DAC

clock period.

Data Sheet AD9174

Rev. B | Page 155 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x58B SHORT_PA_POWER_

LSB

[7:0] SHORT_PA_

POWER[7:0]

Short average power readback. Power

detected at data bus = I2 + Q2. The data

bus calculation only uses the 6 MSBs of the

I and Q data bus samples. This control is

paged by the MAINDAC_PAGE control in

0x0 R

0x58C SHORT_PA_POWER_

MSB

[7:5] RESERVED Reserved. 0x0 R

[4:0]

SHORT_PA_

POWER[12:8]

Short average power readback. Power

detected at data bus = I2 + Q2. The data

bus calculation only uses the 6 MSBs of the

I and Q data bus samples. This control is

paged by the MAINDAC_PAGE control in

0x0 R

0x58D TXEN_SM_0 [7:1] RESERVED Reserved. 0x1 R/W

0 ENA_TXENSM Enable TXEN state machine. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x596 BLANKING_CTRL [7:4] RESERVED Reserved. 0x0 R

3 SPI_TXEN If ENA_SPI_TXEN (Bit 2 of this register) = 1,

the value of this register is the value of the

TXENx status. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

2 ENA_SPI_TXEN Enable TXENx control via the SPI by setting

this bit to 1. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

[1:0] RESERVED Reserved. 0x0 R

0x597 JESD_PA_INT0 [7:0]

JESD_PA_INT_

CNTRL[7:0]

Each bit enables a JESD204B PA interrupt. 0x0 R/W

Bit 8 = CGS.

Bit 7 = frame sync.

Bit 6 = good check sum.

Bit 5 = initial lane sync.

Bit 4 = interlane deskew.

Bit 3 = bad disparity error counter.

Bit 2 = NIT error counter.

Bit 1= UEK error counter.

Bit 0 = lane FIFO overflow or underflow.

0x598 JESD_PA_INT1 [7:1] RESERVED Reserved. 0x0 R

JESD_PA_INT_

CNTRL[8]

Each bit enables a JESD204B PA interrupt. 0x0 R/W

Bit 8 = CGS

Bit 7 = frame sync.

Bit 6 = good check sum.

Bit 5 = initial lane sync.

Bit 4 = interlane deskew.

Bit 3 = bad disparity error counter.

Bit 2 = NIT error counter.

Bit 1= UEK error counter.

Bit 0 = lane FIFO overflow or underflow.

0x599 TXEN_FLUSH_CTRL0 [7:1] RESERVED Reserved. 0x0 R

0 SPI_FLUSH_EN Enable datapath flush. This control is

paged by the MAINDAC_PAGE control in

0x1 R/W

0x705 NVM_LOADER_EN [7:1] RESERVED Reserved. 0x0 R

0 NVM_BLR_EN Enable bootloader. This bit self clears when

the boot loader completes or fails.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 156 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x790 DACPLL_PDCTRL0 7 PLL_PD5 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

[6:4] PLL_PD4 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

3 PLL_PD3 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value default (0).

0x0 R/W

2 PLL_PD2 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

1 PLL_PD1 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, write

this bit to 0.

0x1 R/W

0 PLL_PD0 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

0x791 DACPLL_PDCTRL1 [7:5] RESERVED Reserved. 0x0 R/W

4 PLL_PD10 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

3 PLL_PD9 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

2 PLL_PD8 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

1 PLL_PD7 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

0 PLL_PD6 PLL power-down control. Write this bit to 1

if bypassing the PLL. If using the PLL, keep

this value at default (0).

0x0 R/W

0x792 DACPLL_CTRL0 [7:2] RESERVED Reserved. 0x0 R

1 D_CAL_RESET Resets VCO calibration. 0x1 R/W

0 D_RESET_VCO_DIV Setting this high holds the VCO output

divider in reset. This has the effect of

turning off the input (and output) of the

ADC clock driver.

0x0 R/W

0x793 DACPLL_CTRL1 [7:2] RESERVED Reserved. 0x0 R

[1:0] M_DIVIDER−1 Programmable predivider value for PFD (in

n − 1 notation). M_DIVIDER = PLL

reference clock/PFD frequency. For

optimal spectral performance, choose an

M divider setting that selects a high PFD

frequency within the allowable PFD range.

0x0 R/W

0 Divide by 1.

1 Divide by 2.

10 Divide by 3.

11 Divide by 4.

0x794 DACPLL_CTRL2 [7:6] RESERVED Reserved. 0x0 R/W

[5:0] DACPLL_CP Charge pump current control. Charge

pump current = 100 μA + code × 100 μA.

0x4 R/W

0x795 DACPLL_CTRL3 [7:4] RESERVED Reserved. 0x0 R/W

[3:0] D_CP_CALBITS DAC PLL optimization control. 0x8 R/W

Data Sheet AD9174

Rev. B | Page 157 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x796 DACPLL_CTRL4 [7:4] PLL_CTRL0 DAC PLL optimization control. 0xD R/W

[3:0] RESERVED Reserved. 0x2 R/W

0x797 DACPLL_CTRL5 [7:6] RESERVED Reserved. 0x0 R/W

[5:0] PLL_CTRL1 DAC PLL optimization control. 0x20 R/W

0x798 DACPLL_CTRL6 7 RESERVED Reserved. 0x0 R

6 PLL_CTRL3 DAC PLL optimization control. 0x0 R/W

[5:0] PLL_CTRL2 DAC PLL optimization control. 0x1C R/W

0x799 DACPLL_CTRL7 [7:6] ADC_CLK_DIVIDER ADC clock output divider. 0x0 R/W

0 Divide by 1.

1 Divide by 2.

10 Divide by 3.

11 Divide by 4.

[5:0] N_DIVIDER Programmable divide by N value from

2 to 50. N_DIVIDER = (DAC frequency ×

M_DIVIDER)/(8 × reference clock frequency).

0x8 R/W

0x7A0 DACPLL_CTRL9 [7:6] RESERVED Reserved. 0x2 R/W

D_EN_VAR_FINE_

PRE

DAC PLL control. 0x0 R/W

[4:3] RESERVED Reserved. 0x2 R/W

D_EN_VAR_

COARSE_PRE

DAC PLL control. 0x0 R/W

[1:0] RESERVED Reserved. 0x0 R/W

0x7A2 DACPLL_CTRL10 7 RESERVED Reserved. 0x0 R

[6:5]

D_REGULATOR_

CAL_WAIT

DAC PLL optimization control. 0x1 R/W

[4:3] D_VCO_CAL_WAIT DAC PLL optimization control. 0x2 R/W

[2:1]

D_VCO_CAL_

CYCLES

DAC PLL optimization control. 0x2 R/W

0 RESERVED Reserved. 0x1 R/W

0x7B5 PLL_STATUS [7:1] RESERVED Reserved. 0x0 R

0 PLL_LOCK DAC PLL lock status. 0x0 R

0x800 DDSM_HOPF_CTRL [7:6]

DDSM_HOPF_

MODE

Frequency switch mode. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0 Phase continuous switch. Changes

frequency tuning word, and the phase

accumulator continues to accumulate to

the new FTW.

1 Phase discontinuous switch. Changes the

frequency tuning word and resets the

phase accumulator.

10 Phase coherent switch. This mode starts all

32 NCO phase accumulators to begin

counting simultaneously and all continue

counting regardless of which individual

NCO output is selected.

5 RESERVED Reserved. 0x0 R/W

[4:0] DDSM_HOPF_SEL Hopping frequency selection control.

Enter the number of the FTW (from FTW 0

to FTW31) to select the output of that

NCO. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 158 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x806 DDSM_HOPF_

FTW1_0

[7:0] DDSM_HOPF_

FTW1[7:0]

Hopping frequency FTW1. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x807 DDSM_HOPF_

FTW1_1

[7:0] DDSM_HOPF_

FTW1[15:8]

Hopping frequency FTW1. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x808 DDSM_HOPF_

FTW1_2

[7:0] DDSM_HOPF_

FTW1[23:16]

Hopping frequency FTW1. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x809 DDSM_HOPF_

FTW1_3

[7:0] DDSM_HOPF_

FTW1[31:24]

Hopping frequency FTW1. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x80A DDSM_HOPF_

FTW2_0

[7:0] DDSM_HOPF_

FTW2[7:0]

Hopping frequency FTW2. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x80B DDSM_HOPF_

FTW2_1

[7:0] DDSM_HOPF_

FTW2[15:8]

Hopping frequency FTW2. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x80C DDSM_HOPF_

FTW2_2

[7:0] DDSM_HOPF_

FTW2[23:16]

Hopping frequency FTW2. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x80D DDSM_HOPF_

FTW2_3

[7:0] DDSM_HOPF_

FTW2[31:24]

Hopping frequency FTW2. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x80E DDSM_HOPF_

FTW3_0

[7:0] DDSM_HOPF_

FTW3[7:0]

Hopping frequency FTW3. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x80F DDSM_HOPF_

FTW3_1

[7:0] DDSM_HOPF_

FTW3[15:8]

Hopping frequency FTW3. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x810 DDSM_HOPF_

FTW3_2

[7:0] DDSM_HOPF_

FTW3[23:16]

Hopping frequency FTW3. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x811 DDSM_HOPF_

FTW3_3

[7:0] DDSM_HOPF_

FTW3[31:24]

Hopping frequency FTW3. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x812 DDSM_HOPF_

FTW4_0

[7:0] DDSM_HOPF_

FTW4[7:0]

Hopping frequency FTW4. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x813 DDSM_HOPF_

FTW4_1

[7:0] DDSM_HOPF_

FTW4[15:8]

Hopping frequency FTW4. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x814 DDSM_HOPF_

FTW4_2

[7:0] DDSM_HOPF_

FTW4[23:16]

Hopping frequency FTW4. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x815 DDSM_HOPF_

FTW4_3

[7:0] DDSM_HOPF_

FTW4[31:24]

Hopping frequency FTW4. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x816 DDSM_HOPF_

FTW5_0

[7:0] DDSM_HOPF_

FTW5[7:0]

Hopping frequency FTW5. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x817 DDSM_HOPF_

FTW5_1

[7:0] DDSM_HOPF_

FTW5[15:8]

Hopping frequency FTW5. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x818 DDSM_HOPF_

FTW5_2

[7:0] DDSM_HOPF_

FTW5[23:16]

Hopping frequency FTW5. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

Data Sheet AD9174

Rev. B | Page 159 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x819 DDSM_HOPF_

FTW5_3

[7:0] DDSM_HOPF_

FTW5[31:24]

Hopping frequency FTW5. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x81A DDSM_HOPF_

FTW6_0

[7:0] DDSM_HOPF_

FTW6[7:0]

Hopping frequency FTW6. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x81B DDSM_HOPF_

FTW6_1

[7:0] DDSM_HOPF_

FTW6[15:8]

Hopping frequency FTW6. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x81C DDSM_HOPF_

FTW6_2

[7:0] DDSM_HOPF_

FTW6[23:16]

Hopping frequency FTW6. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x81D DDSM_HOPF_

FTW6_3

[7:0] DDSM_HOPF_

FTW6[31:24]

Hopping frequency FTW6. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x81E DDSM_HOPF_

FTW7_0

[7:0] DDSM_HOPF_

FTW7[7:0]

Hopping frequency FTW7. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x81F DDSM_HOPF_

FTW7_1

[7:0] DDSM_HOPF_

FTW7[15:8]

Hopping frequency FTW7. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x820 DDSM_HOPF_

FTW7_2

[7:0] DDSM_HOPF_

FTW7[23:16]

Hopping frequency FTW7. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x821 DDSM_HOPF_

FTW7_3

[7:0] DDSM_HOPF_

FTW7[31:24]

Hopping frequency FTW7. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x822 DDSM_HOPF_

FTW8_0

[7:0] DDSM_HOPF_

FTW8[7:0]

Hopping frequency FTW8. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x823 DDSM_HOPF_

FTW8_1

[7:0] DDSM_HOPF_

FTW8[15:8]

Hopping frequency FTW8. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x824 DDSM_HOPF_

FTW8_2

[7:0] DDSM_HOPF_

FTW8[23:16]

Hopping frequency FTW8. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x825 DDSM_HOPF_

FTW8_3

[7:0] DDSM_HOPF_

FTW8[31:24]

Hopping frequency FTW8. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x826 DDSM_HOPF_

FTW9_0

[7:0] DDSM_HOPF_

FTW9[7:0]

Hopping frequency FTW9. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x827 DDSM_HOPF_

FTW9_1

[7:0] DDSM_HOPF_

FTW9[15:8]

Hopping frequency FTW9. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x828 DDSM_HOPF_

FTW9_2

[7:0] DDSM_HOPF_

FTW9[23:16]

Hopping frequency FTW9. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x829 DDSM_HOPF_

FTW9_3

[7:0] DDSM_HOPF_

FTW9[31:24]

Hopping frequency FTW9. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x82A DDSM_HOPF_

FTW10_0

[7:0] DDSM_HOPF_

FTW10[7:0]

Hopping frequency FTW10. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x82B DDSM_HOPF_

FTW10_1

[7:0] DDSM_HOPF_

FTW10[15:8]

Hopping frequency FTW10. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 160 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x82C DDSM_HOPF_

FTW10_2

[7:0] DDSM_HOPF_

FTW10[23:16]

Hopping frequency FTW10. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x82D DDSM_HOPF_

FTW10_3

[7:0] DDSM_HOPF_

FTW10[31:24]

Hopping frequency FTW10. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x82E DDSM_HOPF_

FTW11_0

[7:0] DDSM_HOPF_

FTW11[7:0]

Hopping frequency FTW11. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x82F DDSM_HOPF_

FTW11_1

[7:0] DDSM_HOPF_

FTW11[15:8]

Hopping frequency FTW11. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x830 DDSM_HOPF_

FTW11_2

[7:0] DDSM_HOPF_

FTW11[23:16]

Hopping frequency FTW11. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x831 DDSM_HOPF_

FTW11_3

[7:0] DDSM_HOPF_

FTW11[31:24]

Hopping frequency FTW11. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x832 DDSM_HOPF_

FTW12_0

[7:0] DDSM_HOPF_

FTW12[7:0]

Hopping frequency FTW12. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x833 DDSM_HOPF_

FTW12_1

[7:0] DDSM_HOPF_

FTW12[15:8]

Hopping frequency FTW12. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x834 DDSM_HOPF_

FTW12_2

[7:0] DDSM_HOPF_

FTW12[23:16]

Hopping frequency FTW12. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x835 DDSM_HOPF_

FTW12_3

[7:0] DDSM_HOPF_

FTW12[31:24]

Hopping frequency FTW12. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x836 DDSM_HOPF_

FTW13_0

[7:0] DDSM_HOPF_

FTW13[7:0]

Hopping frequency FTW13. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x837 DDSM_HOPF_

FTW13_1

[7:0] DDSM_HOPF_

FTW13[15:8]

Hopping frequency FTW13. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x838 DDSM_HOPF_

FTW13_2

[7:0] DDSM_HOPF_

FTW13[23:16]

Hopping frequency FTW13. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x839 DDSM_HOPF_

FTW13_3

[7:0] DDSM_HOPF_

FTW13[31:24]

Hopping frequency FTW13. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x83A DDSM_HOPF_

FTW14_0

[7:0] DDSM_HOPF_

FTW14[7:0]

Hopping frequency FTW14. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x83B DDSM_HOPF_

FTW14_1

[7:0] DDSM_HOPF_

FTW14[15:8]

Hopping frequency FTW14. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x83C DDSM_HOPF_

FTW14_2

[7:0] DDSM_HOPF_

FTW14[23:16]

Hopping frequency FTW14. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x83D DDSM_HOPF_

FTW14_3

[7:0] DDSM_HOPF_

FTW14[31:24]

Hopping frequency FTW14. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x83E DDSM_HOPF_

FTW15_0

[7:0] DDSM_HOPF_

FTW15[7:0]

Hopping frequency FTW15. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

Data Sheet AD9174

Rev. B | Page 161 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x83F DDSM_HOPF_

FTW15_1

[7:0] DDSM_HOPF_

FTW15[15:8]

Hopping frequency FTW15. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x840 DDSM_HOPF_

FTW15_2

[7:0] DDSM_HOPF_

FTW15[23:16]

Hopping frequency FTW15. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x841 DDSM_HOPF_

FTW15_3

[7:0] DDSM_HOPF_

FTW15[31:24]

Hopping frequency FTW15. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x842 DDSM_HOPF_

FTW16_0

[7:0] DDSM_HOPF_

FTW16[7:0]

Hopping frequency FTW16. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x843 DDSM_HOPF_

FTW16_1

[7:0] DDSM_HOPF_

FTW16[15:8]

Hopping frequency FTW16. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x844 DDSM_HOPF_

FTW16_2

[7:0] DDSM_HOPF_

FTW16[23:16]

Hopping frequency FTW16. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x845 DDSM_HOPF_

FTW16_3

[7:0] DDSM_HOPF_

FTW16[31:24]

Hopping frequency FTW16. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x846 DDSM_HOPF_

FTW17_0

[7:0] DDSM_HOPF_

FTW17[7:0]

Hopping frequency FTW17. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x847 DDSM_HOPF_

FTW17_1

[7:0] DDSM_HOPF_

FTW17[15:8]

Hopping frequency FTW17. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x848 DDSM_HOPF_

FTW17_2

[7:0] DDSM_HOPF_

FTW17[23:16]

Hopping frequency FTW17. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x849 DDSM_HOPF_

FTW17_3

[7:0] DDSM_HOPF_

FTW17[31:24]

Hopping frequency FTW17. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x84A DDSM_HOPF_

FTW18_0

[7:0] DDSM_HOPF_

FTW18[7:0]

Hopping frequency FTW18. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x84B DDSM_HOPF_

FTW18_1

[7:0] DDSM_HOPF_

FTW18[15:8]

Hopping frequency FTW18. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x84C DDSM_HOPF_

FTW18_2

[7:0] DDSM_HOPF_

FTW18[23:16]

Hopping frequency FTW18. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x84D DDSM_HOPF_

FTW18_3

[7:0] DDSM_HOPF_

FTW18[31:24]

Hopping frequency FTW18. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x84E DDSM_HOPF_

FTW19_0

[7:0] DDSM_HOPF_

FTW19[7:0]

Hopping frequency FTW19. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x84F DDSM_HOPF_

FTW19_1

[7:0] DDSM_HOPF_

FTW19[15:8]

Hopping frequency FTW19. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x850 DDSM_HOPF_

FTW19_2

[7:0] DDSM_HOPF_

FTW19[23:16]

Hopping frequency FTW19. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x851 DDSM_HOPF_

FTW19_3

[7:0] DDSM_HOPF_

FTW19[31:24]

Hopping frequency FTW19. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 162 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x852 DDSM_HOPF_

FTW20_0

[7:0] DDSM_HOPF_

FTW20[7:0]

Hopping frequency FTW20. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x853 DDSM_HOPF_

FTW20_1

[7:0] DDSM_HOPF_

FTW20[15:8]

Hopping frequency FTW20. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x854 DDSM_HOPF_

FTW20_2

[7:0] DDSM_HOPF_

FTW20[23:16]

Hopping frequency FTW20. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x855 DDSM_HOPF_

FTW20_3

[7:0] DDSM_HOPF_

FTW20[31:24]

Hopping frequency FTW20. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x856 DDSM_HOPF_

FTW21_0

[7:0] DDSM_HOPF_

FTW21[7:0]

Hopping frequency FTW21. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x857 DDSM_HOPF_

FTW21_1

[7:0] DDSM_HOPF_

FTW21[15:8]

Hopping frequency FTW21. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x858 DDSM_HOPF_

FTW21_2

[7:0] DDSM_HOPF_

FTW21[23:16]

Hopping frequency FTW21. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x859 DDSM_HOPF_

FTW21_3

[7:0] DDSM_HOPF_

FTW21[31:24]

Hopping frequency FTW21. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x85A DDSM_HOPF_

FTW22_0

[7:0] DDSM_HOPF_

FTW22[7:0]

Hopping frequency FTW22. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x85B DDSM_HOPF_

FTW22_1

[7:0] DDSM_HOPF_

FTW22[15:8]

Hopping frequency FTW22. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x85C DDSM_HOPF_

FTW22_2

[7:0] DDSM_HOPF_

FTW22[23:16]

Hopping frequency FTW22. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x85D DDSM_HOPF_

FTW22_3

[7:0] DDSM_HOPF_

FTW22[31:24]

Hopping frequency FTW22. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x85E DDSM_HOPF_

FTW23_0

[7:0] DDSM_HOPF_

FTW23[7:0]

Hopping frequency FTW23. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x85F DDSM_HOPF_

FTW23_1

[7:0] DDSM_HOPF_

FTW23[15:8]

Hopping frequency FTW23. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x860 DDSM_HOPF_

FTW23_2

[7:0] DDSM_HOPF_

FTW23[23:16]

Hopping frequency FTW23. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x861 DDSM_HOPF_

FTW23_3

[7:0] DDSM_HOPF_

FTW23[31:24]

Hopping frequency FTW23. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x862 DDSM_HOPF_

FTW24_0

[7:0] DDSM_HOPF_

FTW24[7:0]

Hopping frequency FTW24. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x863 DDSM_HOPF_

FTW24_1

[7:0] DDSM_HOPF_

FTW24[15:8]

Hopping frequency FTW24. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x864 DDSM_HOPF_

FTW24_2

[7:0] DDSM_HOPF_

FTW24[23:16]

Hopping frequency FTW24. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

Data Sheet AD9174

Rev. B | Page 163 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x865 DDSM_HOPF_

FTW24_3

[7:0] DDSM_HOPF_

FTW24[31:24]

Hopping frequency FTW24. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x866 DDSM_HOPF_

FTW25_0

[7:0] DDSM_HOPF_

FTW25[7:0]

Hopping frequency FTW25. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x867 DDSM_HOPF_

FTW25_1

[7:0] DDSM_HOPF_

FTW25[15:8]

Hopping frequency FTW25. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x868 DDSM_HOPF_

FTW25_2

[7:0] DDSM_HOPF_

FTW25[23:16]

Hopping frequency FTW25. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x869 DDSM_HOPF_

FTW25_3

[7:0] DDSM_HOPF_

FTW25[31:24]

Hopping frequency FTW25. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x86A DDSM_HOPF_

FTW26_0

[7:0] DDSM_HOPF_

FTW26[7:0]

Hopping frequency FTW26. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x86B DDSM_HOPF_

FTW26_1

[7:0] DDSM_HOPF_

FTW26[15:8]

Hopping frequency FTW26. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x86C DDSM_HOPF_

FTW26_2

[7:0] DDSM_HOPF_

FTW26[23:16]

Hopping frequency FTW26. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x86D DDSM_HOPF_

FTW26_3

[7:0] DDSM_HOPF_

FTW26[31:24]

Hopping frequency FTW26. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x86E DDSM_HOPF_

FTW27_0

[7:0] DDSM_HOPF_

FTW27[7:0]

Hopping frequency FTW27. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x86F DDSM_HOPF_

FTW27_1

[7:0] DDSM_HOPF_

FTW27[15:8]

Hopping frequency FTW27. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x870 DDSM_HOPF_

FTW27_2

[7:0] DDSM_HOPF_

FTW27[23:16]

Hopping frequency FTW27. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x871 DDSM_HOPF_

FTW27_3

[7:0] DDSM_HOPF_

FTW27[31:24]

Hopping frequency FTW27. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x872 DDSM_HOPF_

FTW28_0

[7:0] DDSM_HOPF_

FTW28[7:0]

Hopping frequency FTW28. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x873 DDSM_HOPF_

FTW28_1

[7:0] DDSM_HOPF_

FTW28[15:8]

Hopping frequency FTW28. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x874 DDSM_HOPF_

FTW28_2

[7:0] DDSM_HOPF_

FTW28[23:16]

Hopping frequency FTW28. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x875 DDSM_HOPF_

FTW28_3

[7:0] DDSM_HOPF_

FTW28[31:24]

Hopping frequency FTW28. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x876 DDSM_HOPF_

FTW29_0

[7:0] DDSM_HOPF_

FTW29[7:0]

Hopping frequency FTW29. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x877 DDSM_HOPF_

FTW29_1

[7:0] DDSM_HOPF_

FTW29[15:8]

Hopping frequency FTW29. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

AD9174 Data Sheet

Rev. B | Page 164 of 165

Addr. Name Bits Bit Name Settings Description Reset Access

0x878 DDSM_HOPF_

FTW29_2

[7:0] DDSM_HOPF_

FTW29[23:16]

Hopping frequency FTW29. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x879 DDSM_HOPF_

FTW29_3

[7:0] DDSM_HOPF_

FTW29[31:24]

Hopping frequency FTW29. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x87A DDSM_HOPF_

FTW30_0

[7:0] DDSM_HOPF_

FTW30[7:0]

Hopping frequency FTW30. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x87B DDSM_HOPF_

FTW30_1

[7:0] DDSM_HOPF_

FTW30[15:8]

Hopping frequency FTW30. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x87C DDSM_HOPF_

FTW30_2

[7:0] DDSM_HOPF_

FTW30[23:16]

Hopping frequency FTW30. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x87D DDSM_HOPF_

FTW30_3

[7:0] DDSM_HOPF_

FTW30[31:24]

Hopping frequency FTW30. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x87E DDSM_HOPF_

FTW31_0

[7:0] DDSM_HOPF_

FTW31[7:0]

Hopping frequency FTW31. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x87F DDSM_HOPF_

FTW31_1

[7:0] DDSM_HOPF_

FTW31[15:8]

Hopping frequency FTW31. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x880 DDSM_HOPF_

FTW31_2

[7:0] DDSM_HOPF_

FTW31[23:16]

Hopping frequency FTW31. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

0x881 DDSM_HOPF_

FTW31_3

[7:0] DDSM_HOPF_

FTW31[31:24]

Hopping frequency FTW31. This control is

paged by the MAINDAC_PAGE control in

0x0 R/W

Data Sheet AD9174

Rev. B | Page 165 of 165

OUTLINE DIMENSIONS

PKG-005195

COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1.

05-10-2016-A

0.80

BSC

BOTTOM VIEW

TOP VIEW

SIDE VIEW

DETAIL A

10.10

10.00 SQ

9.90

9.80

9.70 SQ

9.60

1.71

1.56

1.41

8.80 SQ

REF

0.60

REF

0.15 REF

A1 BALL

CORNER

R 1.0

R 0.5~1.5

A1 BALL

CORNER INDICATOR

910 81112 7 564231

6.60 REF

0.38

0.34

0.30

0.40

0.35

0.30

0.87 REF

0.50

0.45

0.40

COPLANARITY

0.12

BALL DIAMETER

DETAIL A

SEATING

PLANE

Figure 98. 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

(BP-144-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9174BBPZ −40°C to +85°C 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-144-1

AD9174BBPZRL −40°C to +85°C 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-144-1

AD9174-FMC-EBZ Evaluation Board

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D16794-0-7/19(B)