SHARC+ Dual-Core DSP with ARM Cortex-A5 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SYSTEM FEATURES 17 mm x 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed ARM Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features SYSTEM CONTROL CORE 0 MEMORY Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices ADDITIONAL FEATURES Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for ARM TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications CORE 1 CORE 2 SECURITY AND PROTECTION S SYSTEM PROTECTION (SPU) S SYSTEM MEMORY PROTECTION UNIT (SMPU) FAULT MANAGEMENT ARM(R) TrustZone(R) SECURITY DUAL CRC WATCHDOGS PERIPHERALS SIGNAL ROUTING UNIT (SRU) 2x PRECISION CLOCK GENERATORS ASRC 4x PAIRS L1 CACHE (PARITY) 32 kB L1 I-CACHE 32 kB L1 D-CACHE L2 CACHE 256 kB (PARITY) L1 SRAM (PARITY) L1 SRAM (PARITY) 3 Mb (384 kB) SRAM/CACHE 3 Mb (384 kB) SRAM/CACHE 1x DAI FULL SPORT 1x PIN 0-3 BUFFER 20 1x S/PDIF Rx/Tx 2 3x I C 6 2x LINK PORTS 2x SPI + 1x QUAD SPI OTP MEMORY 3x UARTs THERMAL MONITOR UNIT (TMU) 1x EPPI PROGRAM FLOW SYSTEM CROSSBAR AND DMA SUBSYSTEM 8x TIMERS + 1x COUNTER SYS EVENT CORE 0 (GIC) SYS EVENT CORES 1-2 (SEC) ADC CONTROL MODULE (ACM) TRIGGER ROUTING (TRU) 2x CAN2.0 CLOCK GENERATION (CGU) L3 MEMORY INTERFACE SYSTEM L2 MEMORY CLOCK DISTRIBUTION UNIT (CDU) DDR3 DDR2 LPDDR1 SRAM (ECC) 8 Mb (1 MB) CLOCK, RESET, AND POWER DSP FUNCTIONS (FIR, IIR) 92-64 SD/SDIO/eMMC MLB 3-PIN 1x EMAC 8x SHARC(R) FLAGS ENCRYPTION/DECRYPTION RESET CONTROL (RCU) POWER MANAGEMENT (DPM) SYSTEM ACCELERATION G P I O 7 1 USB 2.0 HS MLB 6-PIN 16 6 DATA HADC (8 CHAN, 12-BIT) DEBUG UNIT 8-4 ARM(R) CoreSightTM WATCHPOINTS (SWU) Figure 1. Processor Block Diagram SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 (c)2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 TABLE OF CONTENTS System Features ....................................................... 1 ADSP-SC57x/ADSP-2157x Designer Quick Reference .... 45 Memory ................................................................ 1 Specifications ........................................................ 56 Additional Features .................................................. 1 Operating Conditions ........................................... 56 Table Of Contents .................................................... 2 Electrical Characteristics ....................................... 60 Revision History ...................................................... 2 HADC .............................................................. 64 General Description ................................................. 3 TMU ................................................................ 64 ARM Cortex-A5 Processor ...................................... 5 Absolute Maximum Ratings ................................... 65 SHARC Processor ................................................. 6 ESD Caution ...................................................... 65 SHARC+ Core Architecture .................................... 8 Timing Specifications ........................................... 66 System Infrastructure ........................................... 10 Output Drive Currents ....................................... 122 System Memory Map ........................................... 11 Test Conditions ................................................ 124 Security Features ................................................ 13 Environmental Conditions .................................. 126 Security Features Disclaimer .................................. 14 Safety Features ................................................... 14 ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments .................................................... 127 Processor Peripherals ........................................... 15 Numerical by Ball Number .................................. 127 System Acceleration ............................................ 19 Alphabetical by Pin Name ................................... 130 System Design .................................................... 20 Configuration of the 400-Ball CSP_BGA ................. 133 System Debug .................................................... 22 ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments .................................................... 134 Development Tools ............................................. 22 Additional Information ........................................ 23 Related Signal Chains .......................................... 23 ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions ...................................................... 24 400-Ball CSP_BGA Signal Descriptions ....................... 28 GPIO Multiplexing for 400-Ball CSP_BGA Package ....... 35 176-Lead LQFP Signal Descriptions ........................... 38 GPIO Multiplexing for 176-Lead LQFP Package ............ 43 Numerical by Lead Number ................................. 134 Alphabetical by Pin Name ................................... 136 Configuration of the 176-Lead LQFP Lead Configuration ................................................ 137 Outline Dimensions .............................................. 138 Surface-Mount Design ........................................ 139 Automotive Products ......................................... 140 Ordering Guide ................................................ 141 REVISION HISTORY 6/2018--Rev. A to Rev. B Changes to Program Trace Macrocell (PTM) Timing .... 120 Changes to System Features ........................................ 1 Changes to Test Conditions .................................... 124 Changes to Additional Features ................................... 1 Changes to Automotive Products ............................. 140 Changes to Table 2 and Table 3, General Description ....... 3 Changes to Ordering Guide .................................... 141 Changes to Operating Conditions .............................. 56 Deleted Package Information from Specifications .......... 56 Changes to Table 27 and Table 28, Clock Related Operating Conditions ........................................................... 58 Changes to Electrical Characteristics ........................... 60 Changes to Table 29, Table 32, and Table 33, Total Internal Power Dissipation .................................................. 62 Changes to Table 37, HADC Timing Specifications ........ 64 Rev. B | Page 2 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 GENERAL DESCRIPTION The ADSP-SC57x/ADSP-2157x processors are members of the SHARC(R) family of products. The ADSP-SC57x processor is based on the SHARC+(R) dual-core and the ARM(R) Cortex(R)-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products. By integrating a set of industry leading system peripherals and memory (see Table 1, Table 2, and Table 3), the ARM CortexA5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance. Table 2 provides comparison information for features that vary across the standard processors. Table 3 provides comparison information for features that vary across the automotive processors. Rev. B | Page 3 of 142 Table 1. Common Product Features Product Features DAI (includes SRU) Full SPORTs S/PDIF receive/transmit ASRCs PCGs Pin buffers I2C (TWI) Quad-data bit SPI Dual-data bit SPI CAN2.0 UARTs Enhanced PPI Up to 16-bit on BGA 12-bit on LQFP GP timer GP counter Watchdog timers ADC control module Hardware accelerators FIR/IIR Security cryptographic engine Multichannel 12-bit ADC | June 2018 ADSP-SC57x/ADSP-2157x 1 4 1 4 2 20 3 1 2 2 3 1 8 1 3 Yes Yes Yes 8-channel BGA; 4-channel LQFP ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 2. Comparison of ADSP-SC57x/ADSP-2157x Processor Features1 System Memory Processor Feature ARM Cortex-A5 (MHz, Max) ARM Core L1 Cache (I, D kB) ARM Core L2 Cache (kB) SHARC+ Core1 (MHz, Max) SHARC+ Core2 (MHz, Max) SHARC L1 SRAM (kB) L2 SRAM (Shared) (MB) DDR3/DDR2/LPDDR1 Controller (16-bit) USB 2.0 HS + PHY (Host/Device/OTG) EMAC Std/AVB + Timer IEEE 1588 SDIO/eMMC Link Ports GPIO Ports GPIO + DAI Pins Package Options 1 ADSPSC570 450 32, 32 256 450 N/A 1 x 384 1 ADSPSC571 500 32, 32 256 500 500 2 x 384 1 ADSPSC572 450 32, 32 256 450 N/A 1 x 384 1 ADSPSC573 500 32, 32 256 500 500 2 x 384 1 ADSP21571 N/A N/A N/A 500 500 2 x 384 1 ADSP21573 N/A N/A N/A 500 500 2 x 384 1 N/A N/A 1 1 N/A 1 N/A 10/100 N/A 1 Port A to D 64 + 20 176-LQFP N/A 10/100 N/A 1 Port A to D 64 + 20 176-LQFP 1 10/100/1000 1 2 Port A to F 92 + 20 400-BGA 1 10/100/1000 1 2 Port A to F 92 + 20 400-BGA N/A N/A N/A 1 Port A to D 64 + 20 176-LQFP N/A N/A N/A 2 Port A to F 92 + 20 400-BGA N/A means not applicable. Table 3. Comparison of ADSP-SC57x/ADSP-2157x Processor Features for Automotive 1 System Memory Processor Feature ARM Cortex-A5 (MHz, Max) ARM Core L1 Cache (I, D kB) ARM Core L2 Cache (kB) SHARC+ Core1 (MHz, Max) SHARC+ Core2 (MHz, Max) SHARC L1 SRAM (kB) L2 SRAM (Shared) (MB) DDR3/DDR2/LPDDR1 Controller (16-bit) USB 2.0 HS + PHY (Host/Device/OTG) EMAC Std/AVB + Timer IEEE 1588 SDIO/eMMC MLB 3-Pin/6-Pin Link Ports GPIO Ports GPIO + DAI Pins Package Options 1 ADSPSC570W 450 32, 32 256 450 N/A 1 x 384 1 ADSPSC571W 500 32, 32 256 500 500 2 x 384 1 ADSPSC572W 450 32, 32 256 450 N/A 1 x 384 1 ADSPSC573W 500 32, 32 256 500 500 2 x 384 1 ADSP21571W N/A N/A N/A 500 500 2 x 384 1 ADSP21573W N/A N/A N/A 500 500 2 x 384 1 N/A N/A 1 1 N/A 1 N/A 10/100 N/A 3-pin 1 Port A to D 64 + 20 176-LQFP N/A 10/100 N/A 3-pin 1 Port A to D 64 + 20 176-LQFP 1 10/100/1000 1 6-pin/3-pin 2 Port A to F 92 + 20 400-BGA 1 10/100/1000 1 6-pin/3-pin 2 Port A to F 92 + 20 400-BGA N/A N/A N/A 3-pin 1 Port A to D 64 + 20 176-LQFP N/A N/A N/A 6-pin/3-pin 2 Port A to F 92 + 20 400-BGA N/A means not applicable. Rev. B | Page 4 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 * Harvard L1 memory system with a memory management unit (MMU) ARM CORTEX-A5 PROCESSOR The ARM Cortex-A5 processor (see Figure 2) is a high performance processor with the following features: * ARM v7 debug architecture * Instruction cache unit (32 Kb) and data Level 1 (L1) cache unit (32 Kb) * Trace support through an embedded trace macrocell (ETM) interface * In order pipeline with dynamic branch prediction * Extension--vector floating-point unit (IEEE754) with trapless execution * ARM, Thumb, and ThumbEE instruction set support * Extension--media processing engine (MPE) with NEONTM technology * ARM TrustZone(R) security extensions * Extension--Jazelle(R) hardware acceleration TM EMBEDDED TRACE MACROCELL (ETM) INTERFACE CoreSight INTERFACE DEBUG CP15 DATA PROCESSING UNIT (DPU) DATA CACHE UNIT (DCU) (R) ARM Cortex-A5 PROCESSOR PREFETCH UNIT AND BRANCH PREDICTOR (PFU) DATA MICRO TLB DATA STORE BUFFER (STB) (R) NEONTM MEDIA PROCESSING ENGINE INSTRUCTION MICRO TLB INSTRUCTION CACHE UNIT (ICU) MAIN TRANSMISSION LOOKINSIDE BUFFER (TLB) 32 Kb 32 Kb BUS INTERFACE UNIT (BIU) (R) (R) ARM Cortex-A5 BUS MASTER PORT GENERIC INTERRUPT CONTROLLER (PrimeCell(R) PL390) L2 CACHE CONTROLLER (CoreLinkTM PL310) DATA MASTER PORTS SHARC PROCESSORS 256 Kb SYSTEM FABRIC TO OTHER CORES Figure 2. ARM Cortex-A5 Processor Block Diagram Rev. B | Page 5 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Generic Interrupt Controller (GIC), PL390 (ADSP-SC57x Only) L2 Cache Controller, PL310 (ADSP-SC57x Only) The Level 2 (L2) cache controller, PL310 (see Figure 2), works efficiently with the ARM Cortex-A5 processors that implement system fabric. The cache controller directly interfaces on the data and instruction interface. The internal pipelining of the cache controller is optimized to enable the processors to operate at the same clock frequency. The cache controller supports the following: The generic interrupt controller (GIC) is a centralized resource for supporting and managing interrupts. The GIC splits into the distributor block (GICPORT0) and the central processing unit (CPU) interface block (GICPORT1). Generic Interrupt Controller Port0 (GICPORT0) The GICPORT0 distributor block performs interrupt prioritization and distribution to the GICPORT1 CPU interface blocks that connect to the processors in the system. It centralizes all interrupt sources, determines the priority of each interrupt, and forwards the interrupt with the highest priority to the interface, for priority masking and preemption handling. * Two read/write 64-bit slave ports, one connected to the ARM Cortex-A5 instruction and data interfaces, and one connecting the ARM Cortex-A5 and SHARC+ cores for data coherency. * Two read/write 64-bit master ports for interfacing with the system fabric. Generic Interrupt Controller Port1 (GICPORT1) SHARC PROCESSOR The GICPORT1 CPU interface block performs priority masking and preemption handling for a connected processor in the system. GICPORT1 supports 8 software generated interrupts (SGIs) and 212 shared peripheral interrupts (SPIs). Figure 3 shows the SHARC processor integrates a SHARC+ SIMD core, L1 memory crossbar, I/D cache controller, L1 memory blocks, and the master/slave ports. Figure 4 shows the SHARC+ SIMD core block diagram. The SHARC processor supports a modified Harvard architecture in combination with a hierarchical memory structure. L1 memories typically operate at the full processor speed with little or no latency. B2 RAM B2 B1 RAM S P-CACHE B0 RAM B2 RAM SIMD Processor CCLK DOMAIN B0 (64) B3 RAM B1 (64) D-CACHE P-CACHE B2 (64) P-CACHE D-CACHE B3 (64) I-CACHE IO (32) IO (32) SLAVE PORT 1 INTERNAL MEMORY INTERFACE (IMIF) I/D CACHE CONTROL IO (32) IO (32) PM (64) DM (64) SLAVE PORT 2 (MDMA) SYSTEM FABRIC SYSCLK DOMAIN CORE MMR (32) DM (64) CMD (64) PM (64) MASTER PORT DATA (R) SHARC+ SIMD CORE CMI (64) PS (64/48) MASTER PORT INSTRUCTION INTERRUPT SEC Figure 3. SHARC Processor Block Diagram Rev. B | Page 6 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 S+ DEBUG TRACE SIMD Core BTB BP CEC FLAGS CONFLICT CACHE PM DATA 48 DMD/PMD 64 11-STAGE PROGRAM SEQUENCER PM ADDRESS 24 DAG1 16 x 32 DAG2 16 x 32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 PM DATA 64 TO IMIF USTAT PX DM DATA 64 MULTIPLIER MRF 80-BIT MRB 80-BIT SHIFTER ALU PEx DATA REGISTER Rx 16 x 40-BIT DATA SWAP PEy DATA REGISTER Sx 16 x 40-BIT ASTATx ASTATy STYKx STYKy ALU SHIFTER MULTIPLIER MSB 80-BIT MSF 80-BIT Figure 4. SHARC+ SIMD Core Block Diagram L1 Memory Figure 5 shows the ADSP-SC57x/ADSP-2157x memory map. Each SHARC+ core has a tightly coupled L1 SRAM of up to 3 Mb. Each SHARC+ core can access code and data in a single cycle from this memory space. The ARM Cortex-A5 core can also access this memory space with multicycle accesses. In the SHARC+ core private address space, both cores have L1 memory. SHARC+ core memory-mapped register (CMMR) address space is 0x00000000 through 0x0003FFFF in normal word (32-bit). Each block can be configured for different combinations of code and data storage. Of the 3 Mb SRAM, up to 1024 Kb/512 Kb can be configured for data memory (DM), program memory (PM), and instruction cache. Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the direct memory access (DMA) engine in a single cycle. Rev. B | Page 7 of 142 The SRAM of the processor can be configured as a maximum of 96k words of 32-bit data, 192k words of 16-bit data, 64k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 3 Mb. All of the memory can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words. Support of a 16-bit floating-point storage format doubles the amount of data that can be stored on chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM and PM buses, with each bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 The system configuration is flexible, but a typical configuration is 512 Kb DM, 128 Kb PM, and 128 Kb of instruction cache, with the remaining L1 memory configured as SRAM. Each addressable memory space outside the L1 memory can be accessed either directly or via cache. 0x FFFF FFFF RESERVED 0x C000 0000 DMC0 (1GB) 0x 8000 0000 SPI2 FLASH (512MB) 0x 6000 0000 The memory map in Table 4 gives the L1 memory address space and shows multiple L1 memory blocks offering a configurable mix of SRAM and cache. 0x 4C00 0000 L1 Master and Slave Ports 0x 4400 0000 Each SHARC+ core has two master ports and two slave ports to and from the system fabric. One master port fetches instructions. The second master port drives data to the system world. Slave port 1 together with slave port 2 (MDMA) run conflict free access to the individual memory blocks. For the slave port address, refer to the L1 memory address map in Table 4. 0x 4000 0000 0x 5000 0000 RESERVED 0x 4800 0000 SYSTEM MMR 0x 3000 0000 RESERVED 0x 28B8 FFFF SHARC2 L1 MULTI-MEMORY SPACE 0x 28A4 0000 RESERVED 0x 2838 FFFF SHARC1 L1 MULTI-MEMORY SPACE 0x 2824 0000 UNIFIED BYTE ADDRESS SPACE RESERVED L1 On-Chip Memory Bandwidth 0x 202B FFFF 0x 2028 0000 The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks, assuming no block conflicts. The total bandwidth is realized using both the DMD and PMD buses (2 x 64-bits CCLK speed and 2 x 32-bit SYSCLK speed). RESERVED 0x 2011 7FFF 0x 2824 0000 0x 201B FFFF RESERVED 0x 2018 0000 Instruction and Data Cache 0x 2010 FFFF L2 BOOT ROM 1 (0.25Mb) (SHARC(R) CORES) 0x 2010 8000 0x 2011 8000 0x 2011 0000 0x 2010 8000 0x 2010 0000 L2 BOOT ROM 2 (0.25Mb) (SHARC(R) CORES) L2 BOOT ROM 1 (0.25Mb) (SHARC(R) CORES) L2 BOOT ROM 0 (0.25Mb) (ARM(R) CORE 0) L2 SRAM (8Mb) 0x 2000 0000 0x 2000 0000 RESERVED 0x 0038 FFFF L1 BLOCK 3 SRAM (0.5Mb) 0x 0038 0000 RESERVED ARM(R) ADDRESS SPACE RESERVED 0x 0030 FFFF L1 BLOCK 2 SRAM (0.5Mb) 0x 0030 0000 RESERVED 0x 002D FFFF L1 BLOCK 1 SRAM (1Mb) 0x 002C 0000 0x 1000 1000 ARM(R) L2 CONFIG REGS (4KB) RESERVED 0x 1000 0000 System Event Controller (SEC) Input 0x 0025 FFFF RESERVED L1 BLOCK 0 SRAM (1Mb) 0x 0000 7FFF The output of the system event controller (SEC) controller is forwarded to the core event controller (CEC) to respond directly to all unmasked system-based interrupts. The SEC also supports nesting including various SEC interrupt channel arbitration options. The processor automatically stacks the arithmetic status (ASTATx and ASTATy) registers and mode (MODE1) register in parallel with the interrupt servicing for all SEC channels. Core Memory-Mapped Registers (CMMR) The core memory-mapped registers (CMMR) control the L1 instruction and data cache, BTB, L2 cache, parity error, system control, debug, and monitor functions. Rev. B | Page 8 of 142 0x 0024 0000 ARM(R) BOOT (32KB) 0x 0000 0000 SHARC(R) PRIVATE ADDRESS SPACE The ADSP-SC57x/ADSP-2157x processors also include a traditional instruction cache (I-cache) and two data caches (D-cache) (PM/DM caches) with parity support for all caches. These caches support one instruction access and two data accesses over the DM and PM buses, per CCLK cycle. The cache controllers automatically manage the configured L1 memory. The system can configure part of the L1 memory for automatic management by the cache controllers. The sizes of these caches are independently configurable from 0 kB to a maximum of 128 kB each. The memory not managed by the cache controllers is directly addressable by the processors. The controllers ensure the data coherence between the two data caches. The caches provide user-controllable features such as full and partial locking, range bound invalidation, and flushing. L2 BOOT ROM 2 (0.25Mb) (SHARC(R) CORES) RESERVED/CORE MMRs/ OTHER MEMORY ALIASES 0x 0000 0000 Figure 5. ADSP-SC57x/ADSP-2157x Memory Map SHARC+ CORE ARCHITECTURE The ADSP-SC57x/ADSP-2157x processors are code compatible at the assembly level with the ADSP-2148x, ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-2116x, and with the first-generation ADSP-2106x SHARC processors. The ADSP-SC57x/ADSP-2157x processors share architectural features with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-214xx, and ADSP-2116x SIMD SHARC processors, shown in Figure 4 and detailed in the following sections. | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Single-Instruction, Multiple Data (SIMD) Computational Engine The SHARC+ core contains two computational processing elements that operate as a single-instruction, multiple data (SIMD) engine. The processing elements are referred to as PEx and PEy data registers and each contain an arithmetic logic unit (ALU), multiplier, shifter, and register file. PEx is always active and PEy is enabled by setting the PEYEN mode bit in the mode control register (MODE1). SIMD mode allows the processors to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture efficiently executes math intensive DSP algorithms. In addition to all the features of previous generation SHARC cores, the SHARC+ core also provides a new and simpler way to execute an instruction only on the PEy data register. SIMD mode also affects the way data transfers between memory and the processing elements because to sustain computational operation in the processing elements requires twice the data bandwidth. Therefore, entering SIMD mode doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values transfer with each memory or register file access. Independent Parallel Computation Units Within each processing element is a set of pipelined computational units. The computational units consist of a multiplier, arithmetic/logic unit (ALU), and shifter. These units are arranged in parallel, maximizing computational throughput. These computational units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, IEEE 64-bit double-precision floating-point, and 32-bit fixed-point data formats. A multifunction instruction set supports parallel execution of the ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements per core. All processing operations take one cycle to complete. For all floating-point operations, the processor takes two cycles to complete in case of data dependency. Double-precision floating-point data take two to six cycles to complete. The processor stalls for the appropriate number of cycles for an interlocked pipeline plus data dependency check. Core Timer Each SHARC+ processor core also has a timer. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating system interrupts. Rev. B | Page 9 of 142 Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register register files (16 primary, 16 secondary), combined with the enhanced Harvard architecture of the processor, allow unconstrained data flow between computation units and internal memory. The registers in the PEx data register file are referred to as R0-R15 and in the PEy data register file as S0-S15. Context Switch Many of the registers of the processor have secondary registers that can activate during interrupt servicing for a fast context switch. The data, DAG, and multiplier result registers have secondary registers. The primary registers are active at reset, while control bits in MODE1 activate the secondary registers. Universal Registers General-purpose tasks use the universal registers. The four USTAT registers allow easy bit manipulations (set, clear, toggle, test, XOR) for all control and status peripheral registers. The data bus exchange register (PX) permits data to pass between the 64-bit PM data bus and the 64-bit DM data bus or between the 40-bit register file and the PM or DM data bus. These registers contain hardware to handle the data width difference. Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support For indirect addressing and implementing circular data buffers in hardware, the ADSP-SC57x/ADSP-2157x processor uses the two data address generators (DAGs). Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fast Fourier transforms (FFT). The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets and 16 secondary sets). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set Architecture (ISA) The flexible instruction set architecture (ISA), a 48-bit instruction word, accommodates various parallel operations for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory--all in a single instruction. Additionally, the double-precision floating-point instruction set is an addition to the SHARC+ core. | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Variable Instruction Set Architecture (VISA) In addition to supporting the standard 48-bit instructions from previous SHARC processors, the SHARC+ core processors support 16-bit and 32-bit opcodes for many instructions, formerly 48-bit in the ISA. This feature, called variable instruction set architecture (VISA), drops redundant or unused bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32bit instructions from both internal and external memories. VISA is not an operating mode; it is only address dependent (refer to memory map ISA/VISA address spaces in Table 7). Furthermore, it allows jumps between ISA and VISA instruction fetches. Single-Cycle Fetch of Instructional Four Operands The ADSP-SC57x/ADSP-2157x processors feature an enhanced Harvard architecture in which the DM bus transfers data and PM bus transfers both instructions and data. With the separate program memory bus, data memory buses, and on-chip instruction conflict cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction from the conflict cache, in a single cycle. data sharing, and exclusive data access to enable multiprocessor programming. To enhance the reliability of the application, L1 data RAMs support parity error detection logic for every byte. Additionally, the processors detect illegal opcodes. Core interrupts flag both errors. Master ports of the core also detect for failed external accesses. SYSTEM INFRASTRUCTURE The following sections describe the system infrastructure of the ADSP-SC57x/ADSP-2157x processors. System L2 Memory A system L2 SRAM memory of 8 Mb (1 MB) is available to both SHARC+ cores, the ARM Cortex-A5 core, and the system DMA channels (see Table 5). The L2 SRAM block is subdivided into eight banks to support concurrent access to the L2 memory ports. Memory accesses to the L2 memory space are multicycle accesses by both the ARM Cortex-A5 and SHARC+ cores. The memory space is used for various situations including * ARM Cortex-A5 to SHARC+ core data sharing and intercore communications * Accelerator and peripheral sources and destination memory to avoid accessing data in the external memory Core Event Controller (CEC) * A location for DMA descriptors The SHARC+ core generates various core interrupts (including arithmetic and circular buffer instruction flow exceptions) and SEC events (debug or monitor and software). The core event controller (CEC) is used to unmask interrupts for core processing (enabled in the IMASK register). * Storage for additional data for either the ARM Cortex-A5 or SHARC+ cores to avoid external memory latencies and reduce external memory bandwidth * Storage for incoming Ethernet traffic to improve performance Instruction Conflict Cache The processors include a 32-entry instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective--only the instructions that require fetches conflict with the PM bus data accesses cache. This cache allows full speed execution of core, looped operations, such as digital filter multiply accumulates, and FFT butterfly processing. The conflict cache serves for on-chip bus conflicts only. Branch Target Buffer (BTB)/Branch Predictor (BP) Implementation of a hardware-based branch predictor (BP) and branch target buffer (BTB) reduce branch delay. The program sequencer supports efficient branching using the BTB for conditional and unconditional instructions. Addressing Spaces In addition to traditionally supported long word, normal word, extended precision word, and short word addressing aliases, the processors support byte addressing for the data and instruction accesses. The enhanced ISA/VISA provides new instructions for accessing all sizes of data from byte space as well as converting word addresses to byte and byte to word addresses. Additional Features * Storage for data coefficient tables cached by the SHARC+ core See System Memory Protection Unit (SMPU) section for options in limiting access by specific cores and DMA masters. The ARM Cortex-A5 core has an L1 instruction and data cache, each of which is 32 kB in size. The core also has an L2 cache controller of 256 kB. When enabling the caches, accesses to all other memory spaces (internal and external) go through the cache. SHARC+ Core L1 Memory in Multiprocessor Space The ARM Cortex-A5 core can access the L1 memory of the SHARC+ core. See Table 6 for the L1 memory address in multiprocessor space. The SHARC+ core can access the L1 memory of the other SHARC+ core in the multiprocessor space. One Time Programmable Memory (OTP) The processors feature 7 Kb of one time programmable (OTP) memory which is memory map accessible. This memory can be programmed with custom keys and it supports secure boot and secure operation. I/O Memory Space The enhanced ISA/VISA of the ADSP-SC57x/ADSP-2157x processors provides a memory barrier instruction for data synchronization, exclusive data access support for multicore Rev. B | Page 10 of 142 Mapped I/Os include SPI2 memory address space (see Table 7). | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SYSTEM MEMORY MAP Table 4. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+(R) Addressing Memory Map (Private Address Space) Memory L1 Block 0 SRAM (1 Mb) L1 Block 1 SRAM (1 Mb) L1 Block 2 SRAM (0.5 Mb) L1 Block 3 SRAM (0.5 Mb) Long Word (64 Bits) 0x00048000- 0x0004BFFF 0x00058000- 0x0005BFFF 0x00060000- 0x00061FFF 0x00070000- 0x00071FFF Extended Precision/ ISA Code (48 Bits) 0x00090000- 0x00095554 0x000B0000- 0x000B5554 0x000C0000- 0x000C2AA9 0x000E0000- 0x000E2AA9 Normal Word (32 Bits) 0x00090000- 0x00097FFF 0x000B0000- 0x000B7FFF 0x000C0000- 0x000C3FFF 0x000E0000- 0x000E3FFF Short Word/ VISA Code (16 Bits) 0x00120000- 0x0012FFFF 0x00160000- 0x0016FFFF 0x00180000- 0x00187FFF 0x001C0000- 0x001C7FFF Byte Access (8 Bits) 0x00240000- 0x0025FFFF 0x002C0000- 0x002DFFFF 0x00300000- 0x0030FFFF 0x00380000- 0x0038FFFF Table 5. L2 Memory Addressing Map Memory1 L2 Boot ROM02 L2 RAM (8 Mb) L2 Boot ROM1 L2 Boot ROM23 Byte Address Space ARM Cortex-A5--Data Access and Instruction Fetch SHARC+--Data Access ARM: 0x00000000-0x00007FFF SHARC/DMA: 0x20100000-0x20107FFF 0x20000000-0x200FFFFF 0x20108000-0x2010FFFF 0x20110000-0x20117FFF Normal Word Address Space VISA Address Space ISA Address Space SHARC+ Data Access SHARC+ Instruction Fetch SHARC+ Instruction Fetch 0x08040000-0x08041FFF 0x08000000-0x0803FFFF 0x08042000-0x08043FFF 0x08044000-0x08045FFF 0x00B20000-0x00B23FFF 0x00B80000-0x00BFFFFF 0x00B00000-0x00B03FFF 0x00B40000-0x00B43FFF 0x00580000-0x00581555 0x005C0000-0x005EAAAA 0x00500000-0x00501555 0x00540000-0x00541555 1 All L2 RAM blocks are subdivided into eight banks. For ADSP-SC57x products, the L2 Boot ROM0 byte address space is 0x00000000-0x00007FFF. 3 L2 Boot ROM address for ADSP-2157x products. 2 Table 6. SHARC+(R) L1 Memory in Multiprocessor Space L1 memory of SHARC1 in multiprocessor space Address via Slave1 Port L1 memory of SHARC2 in multiprocessor space Address via Slave1 Port Memory Block Block 0 Block 1 Block 2 Block 3 Block 0 Block 1 Block 2 Block 3 Byte Address Space ARM Cortex-A5 and SHARC+ 0x28240000-0x2825FFFF 0x282C0000-0x282DFFFF 0x28300000-0x2830FFFF 0x28380000-0x2838FFFF 0x28A40000-0x28A5FFFF 0x28AC0000-0x28ADFFFF 0x28B00000-0x28B0FFFF 0x28B80000-0x28B8FFFF Normal Word Address Space SHARC+ 0x0A090000-0x0A097FFF 0x0A0B0000-0x0A0B7FFF 0x0A0C0000-0x0A0C3FFF 0x0A0E0000-0x0A0E3FFF 0x0A290000-0x0A297FFF 0x0A2B0000-0x0A2B7FFF 0x0A2C0000-0x0A2C3FFF 0x0A2E0000-0x0A2E3FFF Table 7. Memory Map of Mapped I/Os1 Byte Address Space ARM Cortex-A5--Data Access and Instruction Fetch SHARC+--Data Access SPI2 Memory 0x60000000-0x600FFFFF (512 MB) 0x60100000-0x602FFFFF 0x60300000-0x6FFFFFFF 0x70000000-0x7FFFFFFF 1 Normal Word Address Space SHARC+ Data Access 0x04000000-0x07FFFFFF Not applicable VISA Address Space SHARC+ Instruction Fetch 0x00F80000-0x00FFFFFF Not applicable Not applicable Not applicable ISA Address Space SHARC+ Instruction Fetch 0x00780000-0x007FFFFF Not applicable Not applicable The ARM Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space. Rev. B | Page 11 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 8. DMC Memory Map1 DMC0 (1 GB) 1 Byte Address Space ARM Cortex-A5--Data Access and Instruction Fetch SHARC+--Data Access 0x80000000-0x805FFFFF 0x80600000-0x809FFFFF 0x80A00000-0x80FFFFFF 0x81000000-0x9FFFFFFF 0xA0000000-0xBFFFFFFF Normal Word Address Space SHARC+ Data Access 0x10000000-0x17FFFFFF Not applicable VISA Address Space SHARC+ Instruction Fetch Not applicable Not applicable 0x00800000-0x00AFFFFF Not applicable Not applicable ISA Address Space SHARC+ Instruction Fetch 0x00400000-0x004FFFFF Not applicable Not applicable Not applicable Not applicable The ARM Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space. System Crossbars (SCBs) The DMA engine supports the following DMA operations: * A single linear buffer that stops on completion The system crossbars (SCBs) are the fundamental building blocks of a switch fabric style for on-chip system bus interconnection. The SCBs connect system bus masters to system bus slaves, providing concurrent data transfer between multiple bus masters and multiple bus slaves. A hierarchical model--built from multiple SCBs--provides a power and area efficient system interconnection. * A linear buffer with negative, positive, or zero stride length * A circular autorefreshing buffer that interrupts when each buffer becomes full * A similar circular buffer that interrupts on fractional buffers, such as at the halfway point * The 1D DMA uses a set of identical ping pong buffers defined by a linked ring of two-word descriptor sets, each containing a link pointer and an address The SCBs provide the following features: * Highly efficient, pipelined bus transfer protocol for sustained throughput * The 1D DMA uses a linked list of four-word descriptor sets containing a link pointer, an address, a length, and a configuration * Full-duplex bus operation for flexibility and reduced latency * Concurrent bus transfer support to allow multiple bus masters to access bus slaves simultaneously * The 2D DMA uses an array of one-word descriptor sets, specifying only the base DMA address * Protection model (privileged/secure) support for selective bus interconnect protection Direct Memory Access (DMA) The processors use direct memory access (DMA) to transfer data within memory spaces or between a memory space and a peripheral. The processors can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of processor activity. * The 2D DMA uses a linked list of multiword descriptor sets, specifying all configurable parameters Memory Direct Memory Access (MDMA) The processor supports various memory direct memory access (MDMA) operations, including, * Enhanced bandwidth MDMA channels with CRC protection (32-bit bus width, run on SYSCLK) * Enhanced bandwidth MDMA channel (32-bit bus width, runs on SYSCLK) DMA transfers can occur between memory and a peripheral or between one memory and another memory. Each memory to memory DMA stream uses two channels: the source channel and the destination channel. All DMA channels can transport data to and from all on-chip and off-chip memories. Programs can use two types of DMA transfers: descriptor-based or register-based. Register-based DMA allows the processors to program DMA control registers directly to initiate a DMA transfer. On completion, the DMA control registers automatically update with original setup values for continuous transfer. Descriptor-based DMA transfers require a set of parameters stored within memory to initiate a DMA sequence. Descriptor-based DMA transfers allow multiple DMA sequences to be chained together. Program a DMA channel to set up and start another DMA transfer automatically after the current sequence completes. Rev. B | Page 12 of 142 * Maximum bandwidth MDMA channel (64-bit bus width, runs on SYCLK) Extended Memory DMA Extended memory DMA supports various operating modes, such as delay line (which allows processor reads and writes to external delay line buffers and to the external memory), with limited core interaction and scatter/gather DMA (writes to and from noncontiguous memory blocks). Cyclic Redundant Code (CRC) Protection The cyclic redundant codes (CRC) protection modules allow system software to calculate the signature of code, data, or both in memory, the content of memory-mapped registers, or | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 periodic communication message objects. Dedicated hardware circuitry compares the signature with precalculated values and triggers appropriate fault events. System Event Controller (SEC) Both SHARC+ cores feature a system event controller. The SEC features include the following: For example, every 100 ms the system software initiates the signature calculation of the entire memory contents and compares these contents with expected, precalculated values. If a mismatch occurs, a fault condition is generated through the processor core or the trigger routing unit. * Comprehensive system event source management, including interrupt enable, fault enable, priority, core mapping, and source grouping * A distributed programming model where each system event source control and all status fields are independent of each other The CRC is a hardware module based on a CRC32 engine that computes the CRC value of the 32-bit data-words presented to it. The source channel of the memory to memory DMA (in memory scan mode) provides data. The data can be optionally forwarded to the destination channel (memory transfer mode). The main features of the CRC peripheral are as follows: * Determinism where all system events have the same propagation delay and provide unique identification of a specific system event source * A slave control port that provides access to all SEC registers for configuration, status, and interrupt and fault services * Memory scan mode * Global locking that supports a register level protection model to prevent writes to locked registers * Memory transfer mode * Data verify mode * Fault management including fault action configuration, time out, external indication, and system reset * Data fill mode * User-programmable CRC32 polynomial Trigger Routing Unit (TRU) * Bit and byte mirroring option (endianness) * Fault and error interrupt mechanisms * 1D and 2D fill block to initialize an array with constants * 32-bit CRC signature of a block of a memory or an MMR block The trigger routing unit (TRU) provides system level sequence control without core intervention. The TRU maps trigger masters (generators of triggers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to triggers in various ways. Common applications enabled by the TRU include, Event Handling The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing a higher priority event takes precedence over servicing a lower priority event. The processors provide support for four different types of events: * Automatically triggering the start of a DMA sequence after a sequence from another DMA channel completes * Software triggering * Synchronization of concurrent activities SECURITY FEATURES The following sections describe the security features of the ADSP-SC57x/ADSP-2157x processors. * An emulation event causes the processors to enter emulation mode, allowing command and control of the processors through the JTAG interface. * A reset event resets the processors. * An exceptions event occurs synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions triggered on the one side by the SHARC+ core, such as data alignment (SIMD or long word) or compute violations (fixed or floating point), and illegal instructions cause core exceptions. Conditions triggered on the other side by the SEC, such as error correcting codes (ECC), parity, watchdog, or system clock, cause system exceptions. ARM TrustZone The ADSP-SC57x processors provide TrustZone technology that is integrated into the ARM Cortex-A5 processors. The TrustZone technology enables a secure state that is extended throughout the system fabric. Cryptographic Hardware Accelerators The ADSP-SC57x/ADSP-2157x processors support standardsbased hardware accelerated encryption, decryption, authentication, and true random number generation. Support for the hardware accelerated cryptographic ciphers includes the following: * AES in ECB, CBC, ICM, and CTR modes with 128-bit, 192-bit, and 256-bit keys * An interrupts event occurs asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. * DES in ECB and CBC mode with 56-bit key * 3DES in ECB and CBC mode with 3x 56-bit key * ARC4 in stateful, stateless mode, up to 128-bit key Rev. B | Page 13 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Support for the hardware accelerated hash functions includes the following: * SHA-1 * SHA-2 with 224-bit and 256-bit digests * HMAC transforms for SHA-1 and SHA-2 * MD5 Public key accelerator (PKA) is available to offload computation intensive public key cryptography operations. Both a hardware-based nondeterministic random number generator and pseudorandom number generator are available. Secure boot is also available with 224-bit elliptic curve digital signatures ensuring integrity and authenticity of the boot stream. Optionally, ensuring confidentiality through AES-128 encryption is available. Employ secure debug to allow only trusted users to access the system with debug tools. CAUTION This product includes security features that can be used to protect embedded nonvolatile memory contents and prevent execution of unauthorized code. When security is enabled on this device (either by the ordering party or the subsequent receiving parties), the ability of Analog Devices to conduct failure analysis on returned devices is limited. Contact Analog Devices for details on the failure analysis limitations for this device. System Protection Unit (SPU) The system protection unit (SPU) guards against accidental or unwanted access to an MMR space of the peripheral by providing a write protection mechanism. The user can choose and configure the protected peripherals as well as configure which of the four system MMR masters (two SHARC+ cores, memory DMA, and CoreSight debug) the peripherals are guarded against. The SPU is also part of the security infrastructure. Along with providing write protection functionality, the SPU is employed to define which resources in the system are secure or nonsecure as well as block access to secure resources from nonsecure masters. SECURITY FEATURES DISCLAIMER To our knowledge, the Security Features, when used in accordance with the data sheet and hardware reference manual specifications, provide a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE SECURITY FEATURES CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. SAFETY FEATURES The ADSP-SC57x/ADSP-2157x processors are designed to support functional safety applications. While the level of safety is mainly dominated by the system concept, the following primitives are provided by the processors to build a robust safety concept. Multiparity Bit Protected SHARC+ Core L1 Memories In the SHARC+ core L1 memory space, whether SRAM or cache, multiple parity bits protect each word to detect the single event upsets that occur in all RAMs. Parity also protects the cache tags and BTB. Parity Protected ARM L1 Cache In the ARM Cortex-A5 L1 cache space, each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs. Parity also protects the cache tags. Error Correcting Codes (ECC) Protected L2 Memories Error correcting codes (ECC) correct single event upsets. A single error correct/double error detect (SEC/DED) code protects the L2 memory. By default, ECC is enabled, but it can be disabled on a per bank basis. Single-bit errors correct transparently. If enabled, dual-bit errors can issue a system event or fault. ECC protection is fully transparent to the user, even if L2 memory is read or written by 8-bit or 16-bit entities. Parity-Protected Peripheral Memories Parity protection is added to all peripheral memories: System Memory Protection Unit (SMPU) * ASRC The system memory protection unit (SMPU) provides memory protection against read and/or write transactions to defined regions of memory. There are SMPU units in the ADSPSC57x/ADSP-2157x processors for each memory space, except for SHARC L1 and SPI direct memory slave. * IIR The SMPU is also part of the security infrastructure. It allows the user to protect against arbitrary read and/or write transactions and allows regions of memory to be defined as secure and prevent nonsecure masters from accessing those memory regions. * CRYPTO * FIR * USB * CAN * EMAC * SDIO * MLB * TRACE Rev. B | Page 14 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Cyclic Redundant Code (CRC) Protected Memories While parity bit and ECC protection mainly protect against random soft errors in L1 and L2 memory cells, the cyclic redundant code (CRC) engines can protect against systematic errors (pointer errors) and static content (instruction code) of L1, L2, and even Level 3 (L3) memories (DDR2, LPDDR). The processors feature two CRC engines that are embedded in the memory to memory DMA controllers. The application code makes these connections using the signal routing unit (SRU), shown in Figure 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to interconnect under software control. This functionality allows easy use of the DAI associated peripherals for a wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. CRC checksums can be calculated or compared automatically during memory transfers, or one or multiple memory regions can be continuously scrubbed by a single DMA work unit as per DMA descriptor chain instructions. The CRC engine also protects data loaded during the boot process. The DAI includes the peripherals described in the following sections (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffers 20 and 19 can change the polarity of the input signals. Most signals of the peripherals belonging to different DAIs cannot be interconnected, with few exceptions. Signal Watchdogs The DAI_PINx pin buffers can also be used as GPIO pins. DAI input signals allow the triggering of interrupts on the rising edge, falling edge, or both. The eight general-purpose (GP) timers feature modes to monitor off-chip signals. The watchdog period mode monitors whether external signals toggle with a period within an expected range. The watchdog width mode monitors whether the pulse widths of external signals are within an expected range. Both modes help detect undesired toggling or lack of toggling of system level signals. System Event Controller (SEC) Besides system events, the system event controller (SEC) further supports fault management including fault action configuration as timeout, internal indication by system interrupt, or external indication through the SYS_FAULT pin and system reset. Memory Error Controller (MEC) See the Digital Audio Interface (DAI) chapter of the ADSPSC57x/ADSP-2157x SHARC+ Processor Hardware Reference for complete information on the use of the DAIs and SRUs. Serial Port (SPORT) The processors feature four synchronous full serial ports (SPORTs). These ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. These devices include Analog Devices AD19xx and ADAU19xx family of audio codecs, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Two data lines, a clock, and frame sync make up the serial ports. The data lines can be programmed to either transmit or receive data and each data line has a dedicated DMA channel. An individual full SPORT module consists of two independently configurable SPORT halves with identical functionality. Two bidirectional data lines--primary (0) and secondary (1)--are available per SPORT half and are configurable as either transmitters or receivers. Therefore, each SPORT half permits two unidirectional streams into or out of the same SPORT. This bidirectional functionality provides greater flexibility for serial communications. For full-duplex configuration, one half SPORT provides two transmit signals, while the other half SPORT provides the two receive signals. The frame sync and clock are shared. The memory error controller (MEC) manages memory parity/ECC errors and warnings from the cores and peripherals and sends out interrupts and triggers. PROCESSOR PERIPHERALS The following sections describe the peripherals of the ADSPSC57x/ADSP-2157x processors. Dynamic Memory Controller (DMC) The 16-bit dynamic memory controller (DMC) interfaces to * LPDDR1 (JESD209A) maximum frequency 200 MHz, DDRCLK (64 Mb to 2 Gb) Serial ports operate in the following six modes: * Standard DSP serial mode * DDR2 (JESD79-2E) maximum frequency 400 MHz, DDRCLK (256 Mb to 4 Gb) * Multichannel time division multiplexing (TDM) mode * I2S mode * DDR3 (JESD79-3E) maximum frequency 450 MHz, DDRCLK (512 Mb to 8 Gb) * Packed I2S mode * Left justified mode * DDR3L (1.5 V compatible only) maximum frequency 450 MHz, DDRCLK (512 Mb to 8 Gb) * Right justified mode See Table 8 for the DMC memory map. Asynchronous Sample Rate Converter (ASRC) Digital Audio Interface (DAI) The processors support one mirrored digital audio interface (DAI) unit. The DAI can connect various peripherals to any of the DAI pins (DAI_PIN20-DAI_PIN01). Rev. B | Page 15 of 142 The asynchronous sample rate converter (ASRC) contains four ASRC blocks. It is the same core in the AD1896 192 kHz stereo asynchronous sample rate converter. The ASRC provides up to 140 dB signal-to-noise ratio (SNR). The ASRC block performs | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 * ITU-656 status word error detection and correction for ITU-656 receive modes and ITU-656 preamble and status word decoding. synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The ASRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the ASRC can clean up audio data from jittery clock sources such as the S/PDIF receiver. * Optional packing and unpacking of data to/from 32 bits from/to 8 bits and 16 bits. If packing/unpacking is enabled, configure endianness to change the order of packing/unpacking of bytes or words. S/PDIF-Compatible Digital Audio Receiver/Transmitter * RGB888 can be converted to RGB666 or RGB565 for transmit modes. The Sony/Philips Digital Interface Format (S/PDIF) is a standard audio data transfer format that allows the transfer of digital audio signals from one device to another without converting them to an analog signal. There is one S/PDIF transmit/receive block on the processor. The digital audio interface carries three types of information: audio data, nonaudio data (compressed data), and timing information. The S/PDIF interface supports one stereo channel or compressed audio streams. The S/PDIF transmitter and receiver are AES3 compliant and support the sample rate from 24 KHz to 192 KHz. The S/PDIF receiver supports professional jitter standards. The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/ transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from various sources, such as the SPORTs, external pins, and the precision clock generators (PCGs), and are controlled by the SRU control registers. Precision Clock Generators (PCG) The precision clock generators (PCG) consist of two units located in the DAI block. The PCG can generate a pair of signals (clock and frame sync) derived from a clock input signal (CLKIN, SCLK0, or DAI pin buffer). Both units are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Enhanced Parallel Peripheral Interface (EPPI) The processors provide an enhanced parallel peripheral interface (EPPI) that supports data widths up to 16 bits for the BGA package and 12 bits for the LQFP package. The EPPI supports direct connection to thin film transistor (TFT) LCD panels, parallel ADCs and DACs, video encoders and decoders, image sensor modules, and other general-purpose peripherals. The features supported in the EPPI module include the following: * Programmable data length of 8 bits, 10 bits, 12 bits, 14 bits, and 16 bits per clock. * Various framed, nonframed, and general-purpose operating modes. Frame syncs can be generated internally or can be supplied by an external device. Rev. B | Page 16 of 142 * Various deinterleaving/interleaving modes for receiving or transmitting 4:2:2 YCrCb data. * Configurable LCD data enable output available on Frame Sync 3. Universal Asynchronous Receiver/Transmitter (UART) Ports The processors provide three full-duplex universal asynchronous receiver/transmitter (UART) ports, fully compatible with PC standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting fullduplex, DMA supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits as well as no parity, even parity, or odd parity. Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multidrop bus (MDB) systems. A frame is terminated by a configurable number of stop bits. The UART ports support automatic hardware flow control through the clear to send (CTS) input and request to send (RTS) output with programmable assertion first in, first out (FIFO) levels. To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a programmable interframe space. Serial Peripheral Interface (SPI) Ports The processors have three industry-standard SPI-compatible ports that allow the processors to communicate with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, 4-wire interface consisting of two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other SPI-compatible devices. An extra two (optional) data pins are provided to support quad-SPI operation. Enhanced modes of operation, such as flow control, fast mode, and dual-I/O mode (DIOM), are also supported. DMA mode allows for transferring several words with minimal central processing unit (CPU) interaction. With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible devices in master mode, slave mode, and multimaster environments. The SPI peripheral includes programmable baud rates, clock phase, and clock polarity. The peripheral can operate in a multimaster environment by interfacing with several other devices, | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 acting as either a master device or a slave device. In a multimaster environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices to interface with fast master devices by providing an SPI ready pin (SPI_RDY) which flexibly controls the transfers. * Frame status delivery to memory through DMA, including frame completion semaphores for efficient buffer queue management in software The baud rate and clock phase and polarities of the SPI port are programmable. The port has integrated DMA channels for both transmit and receive data streams. * Convenient frame alignment modes * Transmit DMA support for separate descriptors for MAC header and payload fields to eliminate buffer copy operations * 47 MAC management statistics counters with selectable clear on read behavior and programmable interrupts on half maximum value Link Port (LP) * Advanced power management Two 8-bit wide link ports (LPs) for the BGA package (one link port for the LQFP package) can connect to the link ports of other DSPs or peripherals. Link ports are bidirectional and have eight data lines, an acknowledge line, and a clock line. * Magic packet detection and wakeup frame filtering * Support for 802.3Q tagged VLAN frames * Programmable MDC clock rate and preamble suppression ADC Control Module (ACM) Interface The ADC control module (ACM) provides an interface that synchronizes the controls between the processors and an ADC. The analog-to-digital conversions are initiated by the processors, based on external or internal events. Audio Video Bridging (AVB) Support The 10/100/1000 EMAC supports the following audio video bridging (AVB) features: * Separate channels or queues for AV data transfer in 100 Mbps and 1000 Mbps modes) The ACM allows for flexible scheduling of sampling instants and provides precise sampling signals to the ADC. * IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for the additional transmit channels The ACM synchronizes the ADC conversion process, generating the ADC controls, the ADC conversion start signal, and other signals. The actual data acquisition from the ADC is done by an internal DAI routing of the ACM with the SPORT0 block. * Configuring up to two additional channels (Channel 1 and Channel 2) on the transmit and receive paths for AV traffic. Channel 0 is available by default and carries the legacy best effort Ethernet traffic on the transmit side. The processors interface directly to many ADCs without any glue logic required. * Separate DMA, transmit and receive FIFO for AVB latency class Ethernet Media Access Controller (EMAC) The processor features an ethernet media access controller (EMAC): 10/100/1000 AVB Ethernet with precision time protocol (IEEE 1588). The processors can directly connect to a network through embedded fast EMAC that supports 10Base-T (10 Mb/sec), 100Base-T (100 Mb/sec) and 1000Base-T (1 Gb/sec) operations. Some standard features of the EMAC are as follows: * Support and MII/RMII/RGMII protocols for external PHYs. * Programmable control to route received VLAN tagged non AV packets to channels or queues Precision Time Protocol (PTP) IEEE 1588 Support The IEEE 1588 standard is a precision clock synchronization protocol for networked measurement and control systems. The processors include hardware support for IEEE 1588 with an integrated precision time protocol synchronization engine (PTP_TSYNC). This engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the engine include the following: * RGMII support for the BGA package only * Full-duplex and half-duplex modes * Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards * Media access management (in half-duplex operation) * Flow control * Hardware assisted time stamping capable of up to 12.5 ns resolution * Station management, including the generation of MDC/MDIO frames for read/write access to PHY registers * Lock adjustment Some advanced features of the EMAC include the following: * Automatic detection of IPv4 and IPv6 packets, as well as PTP messages * Automatic checksum computation of IP header and IP payload fields of receive frames * Multiple input clock sources (SCLK0, RGMII, RMII, MII clock, and external clock) * Independent 32-bit descriptor driven receive and transmit DMA channels * Programmable pulse per second (PPS) output * Auxiliary snapshot to time stamp external events Rev. B | Page 17 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Controller Area Network (CAN) There are two controller area network (CAN) modules. A CAN controller implements the CAN 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to the capability to communicate reliably over a network. This is because the protocol incorporates CRC checking, message error tracking, and fault node confinement. The CAN controller offers the following features: * 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit) * Dedicated acceptance masks for each mailbox The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts down to zero from the programmed value, protecting the system from remaining in an unknown state where software that normally resets the timer stops running due to an external noise condition or software error. General-Purpose Counters (CNT) A 32-bit counter (CNT) is provided that can operate in generalpurpose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. Count direction is either controlled by a levelsensitive input pin or by two edge detectors. A third counter input can provide flexible zero marker support and can input the push button signal of thumbwheel devices. All three CNT0 pins have a programmable debouncing circuit. * Additional data filtering on the first two bytes * Support for both the standard (11-bit) and extended (29-bit) identifier (ID) message formats * Support for remote frames * Active or passive network support * Interrupts, including transmit and receive complete, error, and global An additional crystal is not required to supply the CAN clock because it is derived from a system clock through a programmable divider. Internal signals forwarded to a GP timer enable the timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmed count values are exceeded. Housekeeping Analog-to-Digital Converter (HADC) The housekeeping analog-to-digital converter (HADC) provides a general-purpose, multichannel successive approximation ADC. It supports the following set of features: Timers * 12-bit ADC core with built in sample and hold. The processors include several timers that are described in the following sections. * Eight single-ended input channels for the BGA package; four single-ended input channels for the LQFP package. * Throughput rates up to 1 MSPS. General-Purpose (GP) Timers (TIMER) * Single external reference with analog inputs between 0 V and 3.3 V. There is one general-purpose (GP) timer unit, providing eight GP programmable timers. Each timer has an external pin that can be configured either as PWM or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input on the TM_TMR[n] pins, an external TM_CLK input pin, or to the internal SCLK0. * Selectable ADC clock frequency including the ability to program a prescaler. * Adaptable conversion type; allows single or continuous conversion with option of autoscan. * Autosequencing capability with up to eight autoconversions in a single session. Each conversion can be programmed to select one to eight input channels. These timer units can be used in conjunction with the UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software autobaud detect function for the respective serial channels. The GP timers can generate interrupts to the processor core, providing periodic events for synchronization to either the system clock or to external signals. Timer events can also trigger other peripherals via the TRU (for instance, to signal a fault). Each timer can also be started and/or stopped by any TRU master without core intervention. Watchdog Timer (WDT) Three on-chip software watchdog timers (WDT) can be used by the ARM Cortex-A5 and/or SHARC+ cores. A software watchdog can improve system availability by forcing the processors to a known state, via a general-purpose interrupt, or a fault, if the timer expires before being reset by software. Rev. B | Page 18 of 142 * Six data registers (individually addressable) to store conversion values USB 2.0 On the Go (OTG) Dual-Role Device Controller (BGA Only) The USB supports high speed/full speed/low speed (HS/FS/LS) USB2.0 on the go (OTG). The USB 2.0 OTG dual-role device controller provides a low cost connectivity solution in industrial applications, as well as consumer mobile devices such as cell phones, digital still cameras, and MP3 players. The USB 2.0 controller allows these devices to transfer data using a point to point USB connection without the need for a PC host. The module can operate in a traditional USB peripheral only mode as well as the host mode presented in the OTG supplement to the USB 2.0 specification. | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 The USB clock is provided through a dedicated external crystal or crystal oscillator. The USB OTG dual-role device controller includes a phaselocked loop (PLL) with programmable multipliers to generate the necessary internal clocking frequency for the USB. Media Local Bus (MediaLB) The automotive model has a Microchip MediaLB (MLB) slave interface that allows the processors to function as a media local bus device. It includes support for both 3-pin and 6-pin media local bus protocols. The MLB 3-pin configuration supports speeds up to 1024 x FS. The MLB 6-pin configuration supports speed of 2048 x FS. The MLB also supports up to 64 logical channels with up to 468 bytes of data per MLB frame. The MLB interface supports MOST25, MOST50, and MOST150 data rates and operates in slave mode only. 2-Wire Controller Interface (TWI) The processors include three 2-wire interface (TWI) modules that provide a simple exchange method of control data between multiple devices. The TWI module is compatible with the widely used I2C bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (TWI_SCL) and data (TWI_SDA) and supports the protocol at speeds up to 400 kb/sec. The TWI interface pins are compatible with 5 V logic levels. reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin by pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half-port assignment and interrupt management. This includes masking, identification, and clearing of requests. These registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write one to set or write one to clear them individually. Mobile Storage Interface (MSI) The mobile storage interface (MSI) controller acts as the host interface for multimedia cards (MMC), secure digital memory cards (SD), and secure digital input/output cards (SDIO). The MSI controller has the following features: * Support for a single MMC, SD memory, and SDIO card * Support for 1-bit and 4-bit SD modes * Support for 1-bit, 4-bit, and 8-bit MMC modes * Support for eMMC 4.3 embedded NAND flash devices * An 11-signal external interface with clock, command, optional interrupt, and up to eight data lines * Integrated DMA controller * Card interface clock generation in the clock distribution unit (CDU) Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. * SDIO interrupt and read wait features General-Purpose I/O (GPIO) SYSTEM ACCELERATION Each general-purpose port pin can be individually controlled by manipulating the port control, status, and interrupt registers: The following sections describe the system acceleration blocks of the ADSP-SC57x/ADSP-2157x processors. * GPIO direction control register specifies the direction of each individual GPIO pin as input or output. * GPIO control and status registers have a write one to modify mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. * GPIO interrupt mask registers allow each individual GPIO pin to function as an interrupt to the processors. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. * GPIO interrupt sensitivity registers specify whether individual pins are level or edge sensitive and specify, if edge sensitive, whether the rising edge or both the rising and falling edges of the signal are significant. Pin Interrupts Finite Impulse Response (FIR) Accelerator The finite impulse response (FIR) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. The FIR accelerator can access all memory spaces and can run concurrently with the other accelerators on the processor. Infinite Impulse Response (IIR) Accelerator The infinite impulse response (IIR) accelerator consists of a 1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data, and one MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency. The IIR accelerator can access all memory spaces and run concurrently with the other accelerators on the processor. Every port pin on the processors can request interrupts in either an edge sensitive or a level sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO operation. Five system level interrupt channels (PINT0-PINT4) are Rev. B | Page 19 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SYSTEM DESIGN The following sections provide an introduction to system design features and power supply issues. Clock Management The processors provide three operating modes, each with a different performance and power profile. Control of clocking to each of the processor peripherals reduces power consumption. The processors do not support any low power operation modes. Control of clocking to each of the processor peripherals can reduce the power consumption. Reset Control Unit (RCU) Reset is the initial state of the whole processor, or the core, and is the result of a hardware or software triggered event. In this state, all control registers are set to default values and functional units are idle. Exiting a full system reset starts with the core ready to boot. The reset control unit (RCU) controls how all the functional units enter and exit reset. Differences in functional requirements and clocking constraints define how reset signals are generated. Programs must guarantee that none of the reset functions put the system into an undefined state or causes resources to stall. This is particularly important when the core resets (programs must ensure that there is no pending system activity involving the core when it is reset). From a system perspective, reset is defined by both the reset target and the reset source. The reset target is defined as the following: Frequencies generated by each CGU are derived from a common multiplier with different divider values available for each output. The CGU generates all on-chip clocks and synchronization signals. Multiplication factors are programmed to define the PLLCLK frequency. Programmable values divide the PLLCLK frequency to generate the core clock (CCLK), the system clocks, the DDR1/DDR2/ DDR3 clock (DCLK), and the output clock (OCLK). For more information on clocking, see the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference. Writing to the CGU control registers does not affect the behavior of the PLL immediately. Registers are first programmed with a new value and the PLL logic executes the changes so it transitions smoothly from the current conditions to the new conditions. System Crystal Oscillator and USB Crystal Oscillator The processor can be clocked by an external crystal (see Figure 6), a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If using an external clock, it must be a TTL-compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the SYS_CLKINx pin and the USB_CLKIN pin of the processor. When using an external clock, the SYS_XTALx pin and the USB_XTAL pin must be left unconnected. Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal can be used. * System reset--all functional units except the RCU are set to default states. SHARC(R) PROCESSOR TO PLL CIRCUITRY * Hardware reset--all functional units are set to default states without exception. History is lost. * Core only reset-- affects the core only. When in reset state, the core is not accessed by any bus master. The reset source is defined as the following: * System reset--can be triggered by software (writing to the RCU_CTL register) or by another functional unit such as the dynamic power management (DPM) unit or any of the SEC, TRU, or emulator inputs. SYS_CLKINx SYS_XTALx N * FOR OVERTONE OPERATION ONLY * Hardware reset--the SYS_HWRST input signal asserts active (pulled down). 18 pF* * Core only reset--affects only the core. The core is not accessed by any bus master when in reset state. 18 pF* NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18 pF MUST BE TREATED AS A MAXIMUM. * Trigger request (peripheral). Clock Generation Unit (CGU) Figure 6. External Crystal Connection The ADSP-SC57x/ADSP-2157x processors support two independent PLLs. Each PLL is part of a clock generation unit (CGU); see Figure 7. Each CGU can be either driven externally by the same clock source or each can be driven by separate sources. This provides flexibility in determining the internal clocking frequencies for each clock domain. Rev. B | Page 20 of 142 For fundamental frequency operation, use the circuit shown in Figure 6. A parallel resonant, fundamental frequency, microprocessor grade crystal is connected across the SYS_CLKINx pin and the SYS_XTALx pin. The on-chip resistance between the SYS_CLKINx pin and the SYS_XTALx pin is in the 500 k range. Further parallel resistors are typically not recommended. | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 The two capacitors and the series resistor, shown in Figure 6, fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 6 are typical values only. The capacitor values are dependent upon the load capacitance recommendations of the crystal manufacturer and the physical layout of the printed circuit board (PCB). The resistor value depends on the drive level specified by the crystal manufacturer. The user must verify the customized values based on careful investigations on multiple devices over the required temperature range. A third overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit, shown in Figure 6. A design procedure for third overtone operation is discussed in detail in "Using Third Overtone Crystals with the ADSP-218x DSP" (EE-168). The same recommendations can be used for the USB crystal oscillator. Clock Distribution Unit (CDU) The two CGUs each provide outputs which feed a clock distribution unit (CDU). The clock outputs CLKO0-CLKO9 are connected to various targets. For more information, refer to the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference. Table 9. Boot Modes SYS_BMODE[n] Setting1, 2 000 001 010 011 100 101 110 1 2 Boot Mode No boot SPI2 master SPI2 slave UART0 slave Reserved Reserved Link0 slave SYS_BMODE2 pin is applicable only for the BGA package. Link0 slave boot is supported only on the BGA package. Thermal Monitoring Unit (TMU) The thermal monitoring unit (TMU) provides on-chip temperature measurement for applications that require substantial power consumption. The TMU is integrated into the processor die and digital infrastructure using an MMR-based system access to measure the die temperature variations in real-time. TMU features include the following: * On-chip temperature sensing * Programmable over temperature and under temperature limits Power-Up * Programmable conversion rate SYS_XTALx oscillations (SYS_CLKINx) start when power is applied to the VDD_EXT pins. The rising edge of SYS_HWRST starts on-chip PLL locking (PLL lock counter). The deassertion must apply only if all voltage supplies and SYS_CLKINx oscillations are valid (refer to the Power-Up Reset Timing section). * Programmable clock source selection to run the sensor off an independent local clock * Averaging feature available Power Supplies Clock Out/External Clock The SYS_CLKOUT output pin has programmable options to output divided-down versions of the on-chip clocks. By default, the SYS_CLKOUT pin drives a buffered version of the SYS_ CLKIN0 input. Refer to the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference to change the default mapping of clocks. The processors have separate power supply connections for * Internal (VDD_INT) * External (VDD_EXT) * USB (VDD_USB) * HADC/TMU (VDD_HADC) * DMC (VDD_DMC) Booting The processors have several mechanisms for automatically loading internal and external memory after a reset. The boot mode is defined by the SYS_BMODE[n] input pins. There are two categories of boot modes. In master boot mode, the processors actively load data from serial memories. In slave boot modes, the processors receive data from external host devices. The boot modes are shown in Table 9. These modes are implemented by the SYS_BMODE[n] bits of the reset configuration register and are sampled during power-on resets and software initiated resets. In the ADSP-SC57x processors, the ARM Cortex-A5 (Core 0) controls the boot process, including loading all internal and external memory. Likewise, in the ADSP-2157x processors, the SHARC+ (Core 1) controls the boot function. The option for secure boot is available on all models. Rev. B | Page 21 of 142 All power supplies must meet the specifications provided in Operating Conditions section. All external supply pins must be connected to the same power supply. Power Management As shown in Table 10, the processors support four different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate specifications (see the Specifications section for processor operating conditions). If the feature or the peripheral is not used, refer to Table 25. | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Integrated Development Environments (IDEs) Table 10. Power Domains Power Domain All internal logic DDR3/DDR2/LPDDR USB HADC/TMU All other I/O (includes SYS, JTAG, and ports pins) For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers the CrossCore Embedded Studio integrated development environment (IDE). VDD Range VDD_INT VDD_DMC VDD_USB VDD_HADC VDD_EXT CrossCore Embedded Studio is based on the Eclipse framework. Supporting most Analog Devices processor families, it is the IDE of choice for processors, including multicore devices. The power dissipated by a processor is largely a function of the clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation. Target Board JTAG Emulator Connector The Analog Devices DSP tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processors to monitor and control the target board processor during emulation. The Analog Devices DSP tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor JTAG interface ensures the emulator does not affect target system loading or timing. For information on JTAG emulator operation, see the appropriate emulator hardware user's guide at SHARC Processors Software and Tools. SYSTEM DEBUG The processors include various features that allow easy system debug. These are described in the following sections. System Watchpoint Unit (SWU) The system watchpoint unit (SWU) is a single module that connects to a single system bus and provides transaction monitoring. One SWU is attached to the bus going to each system slave. The SWU provides ports for all system bus address channel signals. Each SWU contains four match groups of registers with associated hardware. These four SWU match groups operate independently but share common event (for example, interrupt and trigger) outputs. Debug Access Port (DAP) Debug access port (DAP) provides IEEE 1149.1 JTAG interface support through the JTAG debug. The DAP provides an optional instrumentation trace for both the core and system. It provides a trace stream that conforms to MIPI System Trace Protocol version 2 (STPv2). DEVELOPMENT TOOLS CrossCore Embedded Studio seamlessly integrates available software add ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information, visit www.analog.com/cces. EZ-KIT Lite Evaluation Board For processor evaluation, Analog Devices provides a wide range of EZ-KIT Lite(R) evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Various EZ-Extenders(R) are also available, which are daughter cards that deliver additional specialized functionality, including audio and video processing. For more information visit www.analog.com. EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in circuit. This permits users to download, execute, and debug programs for the EZKIT Lite system. It also supports in circuit programming of the on-board Flash(R) device to store user specific boot code, enabling standalone operation. With the full version of CrossCore Embedded Studio installed (sold separately), engineers can develop software for supported EZ-KITs or any custom system utilizing supported Analog Devices processors. Software Add Ins for CrossCore Embedded Studio Analog Devices offers software add ins which seamlessly integrate with CrossCore Embedded Studio to extend the capabilities and reduce development time. Add ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add ins are viewable through the CrossCore Embedded Studio IDE once the add in is installed. Analog Devices supports its processors with a complete line of software and hardware development tools, including an integrated development environment (CrossCore(R) Embedded Studio), evaluation products, emulators, and a variety of software add ins. Rev. B | Page 22 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Board Support Packages (BSPs) for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add ins called board support packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. Middleware Packages Analog Devices offers middleware add ins such as real-time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information, see the following web pages: * www.analog.com/ucos2 * www.analog.com/ucos3 The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the JTAG port of the DSP to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see "Analog Devices JTAG Emulation Technical Reference" (EE-68). ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSPSC57x/ADSP-2157x architecture and functionality. For detailed information on the core architecture and instruction set, refer to the SHARC+ Core Programming Reference. RELATED SIGNAL CHAINS * www.analog.com/ucfs * www.analog.com/ucusbd * www.analog.com/ucusbh * www.analog.com/lwip Algorithmic Modules To speed development, Analog Devices offers add ins that perform popular audio and video processing algorithms. These are available for use with CrossCore Embedded Studio. For more information visit www.analog.com. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG test access port (TAP). In circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the internal features of the processor via the TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The application signal chains page in the Circuits from the Lab(R) site (www.analog.com\circuits) provides the following: * Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications * Drill down links for components in each chain to selection guides and application information * Reference designs applying best practice design techniques Rev. B | Page 23 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x DETAILED SIGNAL DESCRIPTIONS Table 11 provides a detailed description of each pin. Table 11. ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions Signal Name ACM_A[n] ACM_T[n] C1_FLG[n] C2_FLG[n] CAN_RX CAN_TX CNT_DG Direction Output Input Output Output Input Output Input CNT_UD Input CNT_ZM Input DAI_PIN[nn] InOut DMC_A[nn] DMC_BA[n] Output Output DMC_CAS Output DMC_CK DMC_CK DMC_CKE DMC_CS[n] DMC_DQ[nn] DMC_LDM Output Output Output Output InOut Output DMC_LDQS InOut DMC_LDQS InOut DMC_ODT Output DMC_RAS Output DMC_RESET DMC_RZQ DMC_UDM Output InOut Output DMC_UDQS InOut Description ADC Control Signals. Function varies by mode. External Trigger n. Input for external trigger events. SHARC Core 1 Flag Pin. SHARC Core 2 Flag Pin. Receive. Typically an external CAN transceiver RX output. Transmit. Typically an external CAN transceiver TX input. Count Down and Gate. Depending on the mode of operation, this input acts either as a count down signal or a gate signal. Count down--this input causes the GP counter to decrement. Gate--stops the GP counter from incrementing or decrementing. Count Up and Direction. Depending on the mode of operation, this input acts either as a count up signal or a direction signal. Count up--this input causes the GP counter to increment. Direction--selects whether the GP counter is incrementing or decrementing. Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the pressing of a pushbutton. Pin n. The digital applications interface (DAI0) connects various peripherals to any of the DAI0_PINxx pins. Programs make these connections using the signal routing unit (SRU). Address n. Address bus. Bank Address n. Defines which internal bank an activate, read, write or precharge command is applied to on the dynamic memory. Bank Address n also defines which mode registers (MR, EMR, EMR2, and/or EMR3) load during the load mode register command. Column Address Strobe. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the CAS input of dynamic memory. Clock. Outputs DCLK to external dynamic memory. Clock (Complement). Complement of DMC_CK. Clock Enable. Active high clock enables. Connects to the CKE input of the dynamic memory. Chip Select n. Commands are recognized by the memory only when this signal is asserted. Data n. Bidirectional data bus. Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with write data. Input with read data. Can be single-ended or differential depending on register settings. Data Strobe for Lower Byte (Complement). Complement of DMC_LDQS. Not used in single-ended mode. On Die Termination. Enables dynamic memory termination resistances when driven high (assuming the memory is properly configured). ODT is enabled or disabled regardless of read or write commands. Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the RAS input of dynamic memory. Reset (DDR3 Only). External Calibration Resistor Connection. Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with write data. Input with read data. Can be single-ended or differential depending on register settings. Rev. B | Page 24 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 11. ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions (Continued) Signal Name DMC_UDQS Direction InOut DMC_VREF DMC_WE Input Output ETH_COL ETH_CRS Input Input ETH_MDC ETH_MDIO ETH_PTPAUXIN[n] Output InOut Input ETH_PTPCLKIN[n] ETH_PTPPPS[n] Input Output ETH_RXCLK_REFCLK ETH_RXCTL_RXDV InOut InOut ETH_RXD[n] ETH_RXERR ETH_TXCLK ETH_TXCTL_TXEN ETH_TXD[n] HADC_EOC_DOUT Input Input Input InOut Output Output HADC_VIN[n] HADC_VREFN Input Input HADC_VREFP Input JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST LP_ACK Input Input Output Input Input InOut LP_CLK InOut LP_D[n] MLB_CLK MLB_CLKN MLB_CLKOUT MLB_CLKP MLB_DAT InOut InOut InOut InOut InOut InOut Description Data Strobe for Upper Byte (Complement). Complement of DMC_UDQS. Not used in single-ended mode. Voltage Reference. Connects to half of the VDD_DMC voltage. Applies to the DMC0_VREF pin. Write Enable. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the WE input of dynamic memory. MII Collision Detect. Collision detect input signal valid only in MII. MII Carrier Sense. Asserted by the PHY when either the transmit or receive medium is not idle. Deasserted when both are idle. This signal is not used in RMII/RGMII modes. Management Channel Clock. Clocks the MDC input of the PHY for RMII/RGMII. Management Channel Serial Data. Bidirectional data bus for PHY control for RMII/RGMII. PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it in the auxiliary time stamp FIFO. PTP Clock Input. Optional external PTP clock input. PTP Pulse Per Second Output. When the advanced time stamp feature enables, this signal is asserted based on the PPS mode selected. Otherwise, this signal is asserted every time the seconds counter is incremented. RXCLK (10/100/1000) or REFCLK (10/100). RXCTL (10/100/1000) or RXDV (10/100). In RGMII mode, RX_CTL multiplexes receive data valid and receiver error. In RMII mode, RXDV is carrier sense and receive data valid (CRS_DV), multiplexed on alternating clock cycles. In MII mode, RXDV is receive data valid (RX_DV), asserted by the PHY when the data on ETH_RXD[n] is valid. Receive Data n. Receive data bus. Receive Error. Reference Clock. Externally supplied Ethernet clock TXCTL (10/100/1000) or TXEN (10/100). Transmit Data n. Transmit data bus. End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate bit in HADC_CTL. Analog Input at Channel n. Analog voltage inputs for digital conversion. Ground Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. External Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. JTAG Clock. JTAG test access port clock. JTAG Serial Data In. JTAG test access port data input. JTAG Serial Data Out. JTAG test access port data output. JTAG Mode Select. JTAG test access port mode select. JTAG Reset. JTAG test access port reset. Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output. When the link port is configured as a transmitter, ACK is an input. Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured as a transmitter, CLK is an output. Data n. Data bus. Input when receiving, output when transmitting. Single Ended Clock. Differential Clock (-). Single Ended Clock Out. Differential Clock (+). Single Ended Data. Rev. B | Page 25 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 11. ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions (Continued) Signal Name MLB_DATN MLB_DATP MLB_SIG MLB_SIGN MLB_SIGP MSI_CD MSI_CLK MSI_CMD MSI_D[n] MSI_INT Direction InOut InOut InOut InOut InOut Input Output InOut InOut Input PPI_CLK PPI_D[nn] PPI_FS1 InOut InOut InOut PPI_FS2 InOut PPI_FS3 InOut P_[nn] InOut SPI_CLK SPI_D2 SPI_D3 SPI_MISO InOut InOut InOut InOut SPI_MOSI InOut SPI_RDY SPI_SEL[n] SPI_SS InOut Output Input SPT_ACLK InOut SPT_AD0 InOut SPT_AD1 InOut SPT_AFS InOut SPT_ATDV Output SPT_BCLK InOut SPT_BD0 InOut Description Differential Data (-). Differential Data (+). Single Ended Signal. Differential Signal (-). Differential Signal (+). Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket. Clock. The clock signal applied to the connected device from the MSI. Command. Sends commands to and receive responses from the connected device. Data n. Bidirectional data bus. eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card interrupt output. An interrupt can be sampled even when the MSI clock to the card is switched off. Clock. Input in external clock mode, output in internal clock mode. Data n. Bidirectional data bus. Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the ADSPSC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the ADSPSC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI chapter of the ADSPSC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. Position n. General-purpose input/output. See the GP Ports chapter of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. Clock. Input in slave mode, output in master mode. Data 2. Transfers serial data in quad mode. Open-drain when ODM mode is enabled. Data 3. Transfers serial data in quad mode. Open-drain when ODM mode is enabled. Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual and quad modes. Open-drain when ODM mode is enabled. Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual and quad modes. Open-drain when ODM mode is enabled. Ready. Optional flow signal. Output in slave mode, input in master mode. Slave Select Output n. Used in master mode to enable the desired slave. Slave Select Input. Slave mode--acts as the slave select input. Master mode--optionally serves as an error detection input for the SPI when there are multiple masters. Channel A Clock. Data and frame sync are driven or sampled with respect to this clock. This signal can be either internally or externally generated. Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data or as an input to receive serial data. Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data or as an input to receive serial data. Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in multichannel transmit mode. It is asserted during enabled slots. Channel B Clock. Data and frame sync are driven or sampled with respect to this clock. This signal can be either internally or externally generated. Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data or as an input to receive serial data. Rev. B | Page 26 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 11. ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions (Continued) Signal Name SPT_BD1 Direction InOut SPT_BFS InOut SPT_BTDV Output SYS_BMODE[n] SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT Input Input Input Output SYS_FAULT InOut SYS_FAULT InOut SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TM_ACI[n] TM_ACLK[n] TM_CLK TM_TMR[n] TRACE_CLK TRACE_D[nn] TWI_SCL TWI_SDA UART_CTS UART_RTS UART_RX Input Output Output Output Input Input Input InOut Output Output InOut InOut Input Output Input UART_TX Output USB_CLKIN Input USB_DM USB_DP USB_ID InOut InOut Input USB_VBC Output USB_VBUS USB_XTAL InOut Output Description Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data or as an input to receive serial data. Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in multichannel transmit mode. It is asserted during enabled slots. Boot Mode Control n. Selects the boot mode of the processor. Clock/Crystal Input. Clock/Crystal Input. Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. Active-High Fault Output. Indicates internal faults or senses external faults depending on the operating mode. Active-Low Fault Output. Indicates internal faults or senses external faults depending on the operating mode. Processor Hardware Reset Control. Resets the device when asserted. Reset Output. Indicates the device is in the reset state. Crystal Output. Crystal Output. Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes. Alternate Clock n. Provides an additional time base for an individual timer. Clock. Provides an additional global time base for all GP timers. Timer n. The main input/output signal for each timer. Trace Clock. Clock output. Trace Data n. Unidirectional data bus. Serial Clock. Clock output when master, clock input when slave. Serial Data. Receives or transmits data. Clear to Send. Flow control signal. Request to Send. Flow control signal. Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. Transmit. Transmits output. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet specifications for frequency/tolerance information. Data -. Bidirectional differential data line. Data +. Bidirectional differential data line. OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A type plug is sensed (signifying that the USB controller is the A device). The input is high when a B type plug is sensed (signifying that the USB controller is the B device). VBUS Control. Controls an external voltage source to supply VBUS when in host mode. Can be configured as open-drain. Polarity is configurable as well. Bus Voltage. Connects to bus voltage in host and device modes. Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN. Rev. B | Page 27 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 400-BALL CSP_BGA SIGNAL DESCRIPTIONS * The pin name column identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a GPIO pin). The processor pin definitions are shown in Table 12 for the 400-ball CSP_BGA package. The columns in this table provide the following information: * The DAI pins and their associated signal routing units (SRUs) connect inputs and outputs of the DAI peripherals (SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio Interface (DAI) chapter of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for complete information on the use of the DAI and SRUs. * The signal name column includes the signal name for every pin and the GPIO multiplexed pin function, where applicable. * The description column provides a descriptive name for each signal. * The port column shows whether or not a signal is multiplexed with other signals on a GPIO port pin. Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions Signal Name ACM0_A0 ACM0_A1 ACM0_A2 ACM0_A3 ACM0_A4 ACM0_T0 C1_FLG0 C1_FLG1 C1_FLG2 C1_FLG3 C2_FLG0 C2_FLG1 C2_FLG2 C2_FLG3 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_UD CNT0_ZM DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 DAI0_PIN15 Description ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 External Trigger n SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Count Up and Direction CNT0 Count Zero Marker DAI0 Pin 1 DAI0 Pin 2 DAI0 Pin 3 DAI0 Pin 4 DAI0 Pin 5 DAI0 Pin 6 DAI0 Pin 7 DAI0 Pin 8 DAI0 Pin 9 DAI0 Pin 10 DAI0 Pin 11 DAI0 Pin 12 DAI0 Pin 13 DAI0 Pin 14 DAI0 Pin 15 Rev. B | Port F C C A B A E E F D B C F E C C C C D E D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Page 28 of 142 | June 2018 Pin Name PF_11 PC_14 PC_15 PA_14 PB_01 PA_15 PE_13 PE_01 PF_04 PD_06 PB_00 PC_14 PF_11 PE_15 PC_12 PC_13 PC_14 PC_15 PD_08 PE_13 PD_07 DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 DAI0_PIN15 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DAI0_PIN16 DAI0_PIN17 DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CK DMC0_CKE DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS Description DAI0 Pin 16 DAI0 Pin 17 DAI0 Pin 18 DAI0 Pin 19 DAI0 Pin 20 DMC0 Address 0 DMC0 Address 1 DMC0 Address 2 DMC0 Address 3 DMC0 Address 4 DMC0 Address 5 DMC0 Address 6 DMC0 Address 7 DMC0 Address 8 DMC0 Address 9 DMC0 Address 10 DMC0 Address 11 DMC0 Address 12 DMC0 Address 13 DMC0 Address 14 DMC0 Address 15 DMC0 Bank Address Input 0 DMC0 Bank Address Input 1 DMC0 Bank Address Input 2 DMC0 Column Address Strobe DMC0 Clock DMC0 Clock (complement) DMC0 Clock enable DMC0 Chip Select 0 DMC0 Data 0 DMC0 Data 1 DMC0 Data 2 DMC0 Data 3 DMC0 Data 4 DMC0 Data 5 DMC0 Data 6 DMC0 Data 7 DMC0 Data 8 DMC0 Data 9 DMC0 Data 10 DMC0 Data 11 DMC0 Data 12 DMC0 Data 13 DMC0 Data 14 DMC0 Data 15 DMC0 Data Mask for Lower Byte DMC0 Data Strobe for Lower Byte DMC0 Data Strobe for Lower Byte (complement) Rev. B | Page 29 of 142 | June 2018 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Pin Name DAI0_PIN16 DAI0_PIN17 DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CK DMC0_CKE DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE ETH0_COL ETH0_CRS ETH0_MDC ETH0_MDIO ETH0_PTPAUXIN0 ETH0_PTPAUXIN1 ETH0_PTPAUXIN2 ETH0_PTPAUXIN3 ETH0_PTPCLKIN0 ETH0_PTPPPS0 ETH0_PTPPPS1 ETH0_PTPPPS2 ETH0_PTPPPS3 ETH0_RXCLK_REFCLK ETH0_RXCTL_RXDV ETH0_RXD0 ETH0_RXD1 ETH0_RXD2 ETH0_RXD3 ETH0_RXERR ETH0_TXCLK ETH0_TXCTL_TXEN ETH0_TXD0 ETH0_TXD1 ETH0_TXD2 ETH0_TXD3 HADC0_EOC_DOUT HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI Description DMC0 On die termination DMC0 Row Address Strobe DMC0 Reset (DDR3 only) DMC0 External calibration resistor connection DMC0 Data Mask for Upper Byte DMC0 Data Strobe for Upper Byte DMC0 Data Strobe for Upper Byte (complement) DMC0 Voltage Reference DMC0 Write Enable EMAC0 MII Collision detect EMAC0 Carrier Sense/RMII Receive Data Valid EMAC0 Management Channel Clock EMAC0 Management Channel Serial Data EMAC0 PTP Auxiliary Trigger Input 0 EMAC0 PTP Auxiliary Trigger Input 1 EMAC0 PTP Auxiliary Trigger Input 2 EMAC0 PTP Auxiliary Trigger Input 3 EMAC0 PTP Clock Input 0 EMAC0 PTP Pulse Per Second Output 0 EMAC0 PTP Pulse Per Second Output 1 EMAC0 PTP Pulse Per Second Output 2 EMAC0 PTP Pulse Per Second Output 3 EMAC0 RXCLK (10/100/1000) or REFCLK (10/100) EMAC0 RXCTL (10/100/1000) or CRS (10/100) EMAC0 Receive Data 0 EMAC0 Receive Data 1 EMAC0 Receive Data 2 EMAC0 Receive Data 3 EMAC0 Receive Error EMAC0 Transmit Clock EMAC0 TXCTL (10/100/1000) or TXEN (10/100) EMAC0 Transmit Data 0 EMAC0 Transmit Data 1 EMAC0 Transmit Data 2 EMAC0 Transmit Data 3 HADC0 End of Conversion/Serial Data Out HADC0 Analog Input at channel 0 HADC0 Analog Input at channel 1 HADC0 Analog Input at channel 2 HADC0 Analog Input at channel 3 HADC0 Analog Input at channel 4 HADC0 Analog Input at channel 5 HADC0 Analog Input at channel 6 HADC0 Analog Input at channel 7 HADC0 Ground Reference for ADC HADC0 External Reference for ADC JTAG Clock JTAG Serial Data In Rev. B | Page 30 of 142 | June 2018 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed C B A A D D F F F A D E E B B A A A A B B B B B B B D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Pin Name DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE PC_06 PB_01 PA_11 PA_10 PD_14 PD_15 PF_06 PF_07 PF_05 PA_09 PD_08 PE_00 PE_01 PB_00 PB_01 PA_13 PA_12 PA_14 PA_15 PB_03 PB_04 PB_09 PB_07 PB_08 PB_06 PB_05 PD_09 HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions (Continued) Signal Name JTG_TDO JTG_TMS JTG_TRST LP0_ACK LP0_CLK LP0_D0 LP0_D1 LP0_D2 LP0_D3 LP0_D4 LP0_D5 LP0_D6 LP0_D7 LP1_ACK LP1_CLK LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 LP1_D6 LP1_D7 MLB0_CLK MLB0_CLKN MLB0_CLKOUT MLB0_CLKP MLB0_DAT MLB0_DATN MLB0_DATP MLB0_SIG MLB0_SIGN MLB0_SIGP MSI0_CD MSI0_CLK MSI0_CMD MSI0_D0 MSI0_D1 MSI0_D2 MSI0_D3 MSI0_D4 MSI0_D5 MSI0_D6 MSI0_D7 MSI0_INT PPI0_CLK PPI0_D00 PPI0_D01 Description JTAG Serial Data Out JTAG Mode Select JTAG Reset LP0 Acknowledge LP0 Clock LP0 Data 0 LP0 Data 1 LP0 Data 2 LP0 Data 3 LP0 Data 4 LP0 Data 5 LP0 Data 6 LP0 Data 7 LP1 Acknowledge LP1 Clock LP1 Data 0 LP1 Data 1 LP1 Data 2 LP1 Data 3 LP1 Data 4 LP1 Data 5 LP1 Data 6 LP1 Data 7 MLB0 Single-Ended Clock MLB0 Differential Clock (-) MLB0 Single-Ended Clock Out MLB0 Differential Clock (+) MLB0 Single-Ended Data MLB0 Differential Data (-) MLB0 Differential Data (+) MLB0 Single-Ended Signal MLB0 Differential Signal (-) MLB0 Differential Signal (+) MSI0 Card Detect MSI0 Clock MSI0 Command MSI0 Data 0 MSI0 Data 1 MSI0 Data 2 MSI0 Data 3 MSI0 Data 4 MSI0 Data 5 MSI0 Data 6 MSI0 Data 7 MSI0 eSDIO Interrupt Input EPPI0 Clock EPPI0 Data 0 EPPI0 Data 1 Rev. B | Port Not Muxed Not Muxed Not Muxed E E E E E E E E E E B B D D D D D D A D B Not Muxed B Not Muxed B Not Muxed Not Muxed B Not Muxed Not Muxed C F F E E E E F F F F C C D D Page 31 of 142 | June 2018 Pin Name JTG_TDO JTG_TMS JTG_TRST PE_03 PE_02 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PB_01 PB_03 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PA_09 PD_09 PB_06 MLB0_CLKN PB_03 MLB0_CLKP PB_04 MLB0_DATN MLB0_DATP PB_05 MLB0_SIGN MLB0_SIGP PC_12 PF_04 PF_07 PE_12 PE_13 PE_14 PE_15 PF_00 PF_01 PF_02 PF_03 PC_13 PC_11 PD_10 PD_11 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions (Continued) Signal Name PPI0_D02 PPI0_D03 PPI0_D04 PPI0_D05 PPI0_D06 PPI0_D07 PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_D12 PPI0_D13 PPI0_D14 PPI0_D15 PPI0_FS1 PPI0_FS2 PPI0_FS3 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_SEL7 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_RDY SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SEL4 SPI1_SEL5 SPI1_SEL6 SPI1_SEL7 SPI1_SS SPI2_CLK SPI2_D2 SPI2_D3 SPI2_MISO SPI2_MOSI SPI2_RDY SPI2_SEL1 Description EPPI0 Data 2 EPPI0 Data 3 EPPI0 Data 4 EPPI0 Data 5 EPPI0 Data 6 EPPI0 Data 7 EPPI0 Data 8 EPPI0 Data 9 EPPI0 Data 10 EPPI0 Data 11 EPPI0 Data 12 EPPI0 Data 13 EPPI0 Data 14 EPPI0 Data 15 EPPI0 Frame Sync 1 (HSYNC) EPPI0 Frame Sync 2 (VSYNC) EPPI0 Frame Sync 3 (FIELD) SPI0 Clock SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Output 4 SPI0 Slave Select Output 5 SPI0 Slave Select Output 6 SPI0 Slave Select Output 7 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Ready SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Output 4 SPI1 Slave Select Output 5 SPI1 Slave Select Output 6 SPI1 Slave Select Output 7 SPI1 Slave Select Input SPI2 Clock SPI2 Data 2 SPI2 Data 3 SPI2 Master In, Slave Out SPI2 Master Out, Slave In SPI2 Ready SPI2 Slave Select Output 1 Rev. B | Port D D D D C D C C C C E C C E C C C C C C C C C C A F F D C C C C C C C F A B D D C B B B B B C B Page 32 of 142 | June 2018 Pin Name PD_12 PD_13 PD_14 PD_15 PC_05 PD_09 PC_01 PC_02 PC_03 PC_04 PE_00 PC_07 PC_08 PE_01 PC_14 PC_15 PC_06 PC_01 PC_02 PC_03 PC_05 PC_04 PC_05 PC_06 PA_09 PF_05 PF_04 PD_05 PC_04 PC_07 PC_08 PC_09 PC_11 PC_10 PC_11 PF_11 PA_14 PB_02 PD_07 PD_06 PC_10 PB_14 PB_12 PB_13 PB_10 PB_11 PC_00 PB_15 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SPI2_SEL2 SPI2_SEL3 SPI2_SEL4 SPI2_SEL5 SPI2_SEL6 SPI2_SEL7 SPI2_SS SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TM0_ACI0 TM0_ACI1 TM0_ACI2 TM0_ACI3 TM0_ACI4 TM0_ACI5 TM0_ACI6 TM0_ACI7 TM0_ACLK0 TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_ACLK5 TM0_ACLK6 TM0_ACLK7 TM0_CLK TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR7 TRACE0_CLK TRACE0_D00 TRACE0_D01 TRACE0_D02 Description SPI2 Slave Select Output 2 SPI2 Slave Select Output 3 SPI2 Slave Select Output 4 SPI2 Slave Select Output 5 SPI2 Slave Select Output n SPI2 Slave Select Output n SPI2 Slave Select Input Boot Mode Control n Boot Mode Control n Boot Mode Control n Clock/Crystal Input Clock/Crystal Input Processor Clock Output Active-High Fault Output Active-Low Fault Output Processor Hardware Reset Control Reset Output Crystal Output Crystal Output TIMER0 Alternate Capture Input 0 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Capture Input 6 TIMER0 Alternate Capture Input 7 TIMER0 Alternate Clock 0 TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Alternate Clock 5 TIMER0 Alternate Clock 6 TIMER0 Alternate Clock 7 TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 6 TIMER0 Timer 7 TRACE0 Trace Clock TRACE0 Trace Data 0 TRACE0 Trace Data 1 TRACE0 Trace Data 2 Rev. B | Page 33 of 142 Port F C D A A B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed F F C C C Not Applicable Not Applicable Not Applicable Not Applicable F C D E Not Applicable Not Applicable Not Applicable C E F F B B C E D F F F F | June 2018 Pin Name PF_10 PC_00 PD_08 PA_15 PA_10 PB_07 PB_15 SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 PF_09 PF_11 PC_12 PC_14 PC_13 DAI0_PIN041 DAI0_PIN191 CNT0_TO SYS_CLKIN1 PF_06 PC_01 PD_09 PE_02 DAI0_PIN031 DAI0_PIN201 SYS_CLKIN0 PC_03 PE_12 PF_05 PF_07 PB_01 PB_03 PC_15 PE_14 PD_07 PF_06 PF_00 PF_01 PF_02 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions (Continued) Signal Name TRACE0_D03 TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_TX UART2_CTS UART2_RTS UART2_RX UART2_TX USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL VDD_EXT VDD_INT VDD_DMC VDD_HADC VDD_USB 1 Description TRACE0 Trace Data 3 TRACE0 Trace Data 4 TRACE0 Trace Data 5 TRACE0 Trace Data 6 TRACE0 Trace Data 7 TWI0 Serial Clock TWI0 Serial Data TWI1 Serial Clock TWI1 Serial Data TWI2 Serial Clock TWI2 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Transmit UART2 Clear to Send UART2 Request to Send UART2 Receive UART2 Transmit USB0 Clock/Crystal Input USB0 Data - USB0 Data + USB0 OTG ID USB0 VBUS Control USB0 Bus Voltage USB0 Crystal External Voltage Domain Internal Voltage Domain DMC VDD HADC/TMU VDD USB VDD Port F D D D D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed D D F F E E F F A A C C Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Signal is routed to the DAI0_PINnn pin through the DAI0_PBnn pin buffers using the SRU. Rev. B | Page 34 of 142 | June 2018 Pin Name PF_03 PD_10 PD_11 PD_12 PD_13 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA PD_06 PD_05 PF_09 PF_08 PE_14 PE_00 PF_11 PF_10 PA_11 PA_10 PC_13 PC_12 USB_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB_XTAL VDD_EXT VDD_INT VDD_DMC VDD_HADC VDD_USB ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 GPIO MULTIPLEXING FOR 400-BALL CSP_BGA PACKAGE Table 13 through Table 18 identify the pin functions that are multiplexed on the GPIO pins of the 400-ball CSP_BGA package. Table 13. Signal Multiplexing for Port A Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap ETH0_PTPPPS0 ETH0_MDIO ETH0_MDC ETH0_RXD1 ETH0_RXD0 ETH0_RXD2 ETH0_RXD3 LP1_D6 UART2_RTS UART2_CTS SPI0_SEL4 SPI2_SEL6 ACM0_A3 ACM0_T0 SPI1_SEL4 SPI2_SEL5 Multiplexed Function 1 C2_FLG0 ACM0_A4 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap LP1_ACK SPI1_SEL5 LP1_CLK TM0_TMR3 Table 14. Signal Multiplexing for Port B Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 Multiplexed Function 0 ETH0_RXCLK_REFCLK ETH0_CRS ETH0_RXCTL_RXDV ETH0_RXERR ETH0_TXCLK ETH0_TXD3 ETH0_TXD2 ETH0_TXD0 ETH0_TXD1 ETH0_TXCTL_TXEN SPI2_MISO SPI2_MOSI SPI2_D2 SPI2_D3 SPI2_CLK SPI2_SEL1 MLB0_CLKOUT MLB0_DAT MLB0_SIG MLB0_CLK TM0_TMR4 SPI2_SEL7 SPI2_SS Rev. B | Page 35 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 15. Signal Multiplexing for Port C Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 Multiplexed Function 0 SPI2_SEL3 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL1 SPI1_SEL2 CAN0_RX CAN0_TX CAN1_RX CAN1_TX Multiplexed Function 1 SPI2_RDY PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_D06 ETH0_COL PPI0_D13 PPI0_D14 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap TM0_ACLK2 TM0_CLK SPI0_SS SPI0_RDY PPI0_FS3 PPI0_CLK MSI0_CD MSI0_INT PPI0_FS1 PPI0_FS2 SPI1_RDY UART2_TX UART2_RX ACM0_A1 ACM0_A2 C2_FLG1 TM0_TMR5 Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 SPI0_SEL7 SPI1_SEL7 SPI1_SEL6 ETH0_PTPPPS1 LP1_D7 LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 C1_FLG3 CNT0_ZM CNT0_DG PPI0_D07 PPI0_D00 PPI0_D01 PPI0_D02 PPI0_D03 PPI0_D04 PPI0_D05 UART0_RTS UART0_CTS TM0_TMR7 SPI2_SEL4 HADC0_EOC_DOUT TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 ETH0_PTPAUXIN0 ETH0_PTPAUXIN1 Multiplexed Function 1 PPI0_D12 PPI0_D15 Multiplexed Function 2 UART1_RTS C1_FLG1 SPI1_SS TM0_ACLK4 TM0_ACI2 TM0_ACI4 TM0_ACI3 Table 16. Signal Multiplexing for Port D Signal Name PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 Multiplexed Function Input Tap TM0_ACLK3 Table 17. Signal Multiplexing for Port E Signal Name PE_00 PE_01 PE_02 Multiplexed Function 0 ETH0_PTPPPS2 ETH0_PTPPPS3 LP0_CLK Rev. B | Page 36 of 142 | June 2018 Multiplexed Function 3 Multiplexed Function Input Tap ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 17. Signal Multiplexing for Port E (Continued) Signal Name PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 Multiplexed Function 0 LP0_ACK LP0_D0 LP0_D1 LP0_D2 LP0_D3 LP0_D4 LP0_D5 LP0_D6 LP0_D7 MSI0_D0 MSI0_D1 MSI0_D2 MSI0_D3 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap Multiplexed Function 3 Multiplexed Function Input Tap TM0_TMR0 CNT0_UD TM0_TMR6 C1_FLG0 UART1_CTS C2_FLG3 Table 18. Signal Multiplexing for Port F Signal Name PF_00 PF_01 PF_02 PF_03 PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 PF_11 Multiplexed Function 0 MSI0_D4 MSI0_D5 MSI0_D6 MSI0_D7 MSI0_CLK ETH0_PTPCLKIN0 ETH0_PTPAUXIN2 ETH0_PTPAUXIN3 UART0_TX UART0_RX UART1_TX UART1_RX Multiplexed Function 1 TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 C1_FLG2 TM0_TMR1 TRACE0_CLK TM0_TMR2 Multiplexed Function 2 SPI0_SEL6 SPI0_SEL5 TM0_ACLK1 MSI0_CMD TM0_ACI0 SPI2_SEL2 ACM0_A0 SPI1_SEL3 C2_FLG2 TM0_ACI1 Table 19 shows the internal timer signal routing. This table applies to both the 400-ball CSP_BGA and 176-lead LQFP packages. Table 19. Internal Timer Signal Routing Timer Input Signal TM0_ACLK01 TM0_ACI5 TM0_ACLK5 TM0_ACI6 TM0_ACLK6 TM0_ACI7 TM0_ACLK7 1 Internal Source SYS_CLKIN1 DAI0_PB04_O DAI0_PB03_O DAI0_PB20_O DAI0_PB19_O CNT0_TO SYS_CLKIN0 Not applicable for LQFP package. Rev. B | Page 37 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 176-LEAD LQFP SIGNAL DESCRIPTIONS * The pin name column identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a GPIO pin). The processor pin definitions are shown Table 20 for the 176-lead LQFP package. The columns in this table provide the following information: * The DAI pins and their associated signal routing units (SRUs) connect inputs and outputs of the DAI peripherals (SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio Interface (DAI) chapter of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for complete information on the use of the DAIs and SRUs. * The signal name column includes the signal name for every pin and the GPIO multiplexed pin function, where applicable. * The description column provides a descriptive name for each signal. * The port column shows whether or not a signal is multiplexed with other signals on a GPIO port pin. Table 20. ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions Signal Name ACM0_A0 ACM0_A1 ACM0_A2 ACM0_A3 ACM0_A4 ACM0_T0 C1_FLG0 C1_FLG1 C1_FLG2 C1_FLG3 C2_FLG0 C2_FLG1 C2_FLG2 C2_FLG3 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_UD CNT0_ZM DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 Description ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 External Trigger n SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Count Up and Direction CNT0 Count Zero Marker DAI0 Pin 1 DAI0 Pin 2 DAI0 Pin 3 DAI0 Pin 4 DAI0 Pin 5 DAI0 Pin 6 DAI0 Pin 7 DAI0 Pin 8 DAI0 Pin 9 DAI0 Pin 10 DAI0 Pin 11 DAI0 Pin 12 DAI0 Pin 13 DAI0 Pin 14 Rev. B | Port A C C A B A D D C D B C C D C C C C D D D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Page 38 of 142 | June 2018 Pin Name PA_08 PC_14 PC_15 PA_14 PB_01 PA_15 PD_00 PD_01 PC_09 PD_06 PB_00 PC_14 PC_15 PD_05 PC_12 PC_13 PC_14 PC_15 PD_08 PD_00 PD_07 DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 20. ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions (Continued) Signal Name DAI0_PIN15 DAI0_PIN16 DAI0_PIN17 DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 ETH0_COL ETH0_CRS ETH0_MDC ETH0_MDIO ETH0_PTPAUXIN0 ETH0_PTPAUXIN1 ETH0_PTPPPS0 ETH0_PTPPPS1 ETH0_RXCLK_REFCLK ETH0_RXCTL_RXDV ETH0_RXD0 ETH0_RXD1 ETH0_RXD2 ETH0_RXD3 ETH0_RXERR ETH0_TXCLK ETH0_TXCTL_TXEN ETH0_TXD0 ETH0_TXD1 ETH0_TXD2 ETH0_TXD3 HADC0_EOC_DOUT HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST LP1_ACK LP1_CLK LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 LP1_D6 Description DAI0 Pin 15 DAI0 Pin 16 DAI0 Pin 17 DAI0 Pin 18 DAI0 Pin 19 DAI0 Pin 20 EMAC0 MII Collision detect EMAC0 Carrier Sense/RMII Receive Data Valid EMAC0 Management Channel Clock EMAC0 Management Channel Serial Data EMAC0 PTP Auxiliary Trigger Input 0 EMAC0 PTP Auxiliary Trigger Input 1 EMAC0 PTP Pulse Per Second Output 0 EMAC0 PTP Pulse Per Second Output 1 EMAC0 RXCLK (10/100/1000) or REFCLK (10/100) EMAC0 RXCTL (10/100/1000) or CRS (10/100) EMAC0 Receive Data 0 EMAC0 Receive Data 1 EMAC0 Receive Data 2 EMAC0 Receive Data 3 EMAC0 Receive Error EMAC0 Transmit Clock EMAC0 TXCTL (10/100/1000) or TXEN (10/100) EMAC0 Transmit Data 0 EMAC0 Transmit Data 1 EMAC0 Transmit Data 2 EMAC0 Transmit Data 3 HADC0 End of Conversion/Serial Data Out HADC0 Analog Input at channel 0 HADC0 Analog Input at channel 1 HADC0 Analog Input at channel 2 HADC0 Analog Input at channel 3 HADC0 Ground Reference for ADC HADC0 External Reference for ADC JTAG Clock JTAG Serial Data In JTAG Serial Data Out JTAG Mode Select JTAG Reset LP1 Acknowledge LP1 Clock LP1 Data 0 LP1 Data 1 LP1 Data 2 LP1 Data 3 LP1 Data 4 LP1 Data 5 LP1 Data 6 Rev. B | Page 39 of 142 | June 2018 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed C B A A D D A D B B A A A A B B B B B B B D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B B D D D D D D A Pin Name DAI0_PIN15 DAI0_PIN16 DAI0_PIN17 DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 PC_06 PB_01 PA_11 PA_10 PD_14 PD_15 PA_09 PD_08 PB_00 PB_01 PA_13 PA_12 PA_14 PA_15 PB_03 PB_04 PB_09 PB_07 PB_08 PB_06 PB_05 PD_09 HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST PB_01 PB_03 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PA_09 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 20. ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions (Continued) Signal Name LP1_D7 MLB0_CLK MLB0_CLKOUT MLB0_DAT MLB0_SIG PPI0_CLK PPI0_D00 PPI0_D01 PPI0_D02 PPI0_D03 PPI0_D04 PPI0_D05 PPI0_D06 PPI0_D07 PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_FS1 PPI0_FS2 PPI0_FS3 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_SEL7 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_RDY SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SEL4 SPI1_SEL5 SPI1_SEL6 SPI1_SEL7 SPI1_SS SPI2_CLK SPI2_D2 SPI2_D3 Description LP1 Data 7 MLB0 Single-Ended Clock MLB0 Single-Ended Clock Out MLB0 Single-Ended Data MLB0 Single-Ended Signal EPPI0 Clock EPPI0 Data 0 EPPI0 Data 1 EPPI0 Data 2 EPPI0 Data 3 EPPI0 Data 4 EPPI0 Data 5 EPPI0 Data 6 EPPI0 Data 7 EPPI0 Data 8 EPPI0 Data 9 EPPI0 Data 10 EPPI0 Data 11 EPPI0 Frame Sync 1 (HSYNC) EPPI0 Frame Sync 2 (VSYNC) EPPI0 Frame Sync 3 (FIELD) SPI0 Clock SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Output 4 SPI0 Slave Select Output 5 SPI0 Slave Select Output 6 SPI0 Slave Select Output 7 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Ready SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Output 4 SPI1 Slave Select Output 5 SPI1 Slave Select Output 6 SPI1 Slave Select Output 7 SPI1 Slave Select Input SPI2 Clock SPI2 Data 2 SPI2 Data 3 Rev. B | Port D B B B B C D D D D D D C D C C C C C C C C C C C C C C A D D D C C C C C C C A A B D D C B B B Page 40 of 142 | June 2018 Pin Name PD_09 PB_06 PB_03 PB_04 PB_05 PC_11 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PC_05 PD_09 PC_01 PC_02 PC_03 PC_04 PC_14 PC_15 PC_06 PC_01 PC_02 PC_03 PC_05 PC_04 PC_05 PC_06 PA_09 PD_03 PD_04 PD_05 PC_04 PC_07 PC_08 PC_09 PC_11 PC_10 PC_11 PA_08 PA_14 PB_02 PD_07 PD_06 PC_10 PB_14 PB_12 PB_13 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 20. ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions (Continued) Signal Name SPI2_MISO SPI2_MOSI SPI2_RDY SPI2_SEL1 SPI2_SEL2 SPI2_SEL3 SPI2_SEL4 SPI2_SEL5 SPI2_SEL6 SPI2_SEL7 SPI2_SS SYS_BMODE0 SYS_BMODE1 SYS_CLKIN0 SYS_CLKOUT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 TM0_ACI0 TM0_ACI1 TM0_ACI2 TM0_ACI3 TM0_ACI4 TM0_ACI5 TM0_ACI6 TM0_ACI7 TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_ACLK5 TM0_ACLK6 TM0_ACLK7 TM0_CLK TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR7 TRACE0_CLK TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 TRACE0_D04 Description SPI2 Master In, Slave Out SPI2 Master Out, Slave In SPI2 Ready SPI2 Slave Select Output 1 SPI2 Slave Select Output 2 SPI2 Slave Select Output 3 SPI2 Slave Select Output 4 SPI2 Slave Select Output 5 SPI2 Slave Select Output n SPI2 Slave Select Output n SPI2 Slave Select Input Boot Mode Control n Boot Mode Control n Clock/Crystal Input Processor Clock Output Active-High Fault Output Processor Hardware Reset Control Reset Output Crystal Output TIMER0 Alternate Capture Input 0 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Capture Input 6 TIMER0 Alternate Capture Input 7 TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Alternate Clock 5 TIMER0 Alternate Clock 6 TIMER0 Alternate Clock 7 TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 7 TRACE0 Trace Clock TRACE0 Trace Data TRACE0 Trace Data TRACE0 Trace Data TRACE0 Trace Data TRACE0 Trace Data Rev. B | Page 41 of 142 Port B B C B A C D A A B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A A C C C Not Applicable Not Applicable Not Applicable A C D C Not Applicable Not Applicable Not Applicable C D D D B B C D A A A A A D | June 2018 Pin Name PB_10 PB_11 PC_00 PB_15 PA_07 PC_00 PD_08 PA_15 PA_10 PB_07 PB_15 SYS_BMODE0 SYS_BMODE1 SYS_CLKIN0 SYS_CLKOUT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 PA_06 PA_08 PC_12 PC_14 PC_13 DAI_PB04_O DAI_PB19_O CNT0_TO PA_00 PC_01 PD_09 PC_11 DAI_PB03_O DAI_PB20_O SYS_CLKIN0 PC_03 PD_02 PD_03 PD_04 PB_01 PB_03 PC_15 PD_07 PA_00 PA_01 PA_02 PA_03 PA_04 PD_10 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 20. ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions (Continued) Signal Name TRACE0_D05 TRACE0_D06 TRACE0_D07 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_TX UART2_CTS UART2_RTS UART2_RX UART2_TX Description TRACE0 Trace Data TRACE0 Trace Data TRACE0 Trace Data 7 TWI0 Serial Clock TWI0 Serial Data TWI1 Serial Clock TWI1 Serial Data TWI2 Serial Clock TWI2 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Transmit UART2 Clear to Send UART2 Request to Send UART2 Receive UART2 Transmit Rev. B Port D D D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed D D A A D D A A A A C C | Page 42 of 142 | June 2018 Pin Name PD_11 PD_12 PD_13 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA PD_06 PD_05 PA_06 PA_05 PD_01 PD_00 PA_08 PA_07 PA_11 PA_10 PC_13 PC_12 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 GPIO MULTIPLEXING FOR 176-LEAD LQFP PACKAGE Table 21 through Table 24 identify the pin functions that are multiplexed on the GPIO pins of the 176-lead LQFP package. Table 21. Signal Multiplexing for Port A Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 TRACE0_CLK TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 UART0_TX UART0_RX UART1_TX UART1_RX ETH0_PTPPPS0 ETH0_MDIO ETH0_MDC ETH0_RXD1 ETH0_RXD0 ETH0_RXD2 ETH0_RXD3 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap TM0_ACLK1 TM0_ACI0 SPI2_SEL2 ACM0_A0 LP1_D6 UART2_RTS UART2_CTS SPI1_SEL3 SPI0_SEL4 SPI2_SEL6 ACM0_A3 ACM0_T0 SPI1_SEL4 SPI2_SEL5 Multiplexed Function 1 C2_FLG0 ACM0_A4 Multiplexed Function 2 Multiplexed Function 3 LP1_ACK SPI1_SEL5 LP1_CLK TM0_TMR3 TM0_ACI1 Table 22. Signal Multiplexing for Port B Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 Multiplexed Function 0 ETH0_RXCLK_REFCLK ETH0_CRS ETH0_RXCTL_RXDV ETH0_RXERR ETH0_TXCLK ETH0_TXD3 ETH0_TXD2 ETH0_TXD0 ETH0_TXD1 ETH0_TXCTL_TXEN SPI2_MISO SPI2_MOSI SPI2_D2 SPI2_D3 SPI2_CLK SPI2_SEL1 MLB0_CLKOUT MLB0_DAT MLB0_SIG MLB0_CLK Multiplexed Function Input Tap TM0_TMR4 SPI2_SEL7 SPI2_SS Rev. B | Page 43 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 23. Signal Multiplexing for Port C Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 Multiplexed Function 0 SPI2_SEL3 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL1 SPI1_SEL2 CAN0_RX CAN0_TX CAN1_RX CAN1_TX Multiplexed Function 1 SPI2_RDY PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_D06 ETH0_COL C1_FLG2 C2_FLG2 PPI0_CLK Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap TM0_ACLK2 TM0_CLK SPI0_SS SPI0_RDY PPI0_FS3 PPI0_FS1 PPI0_FS2 SPI1_RDY UART2_TX UART2_RX ACM0_A1 ACM0_A2 Multiplexed Function 1 UART1_RTS UART1_CTS Multiplexed Function 2 CNT0_UD TM0_TMR6 C2_FLG1 TM0_TMR5 SPI1_SS TM0_ACLK4 TM0_ACI2 TM0_ACI4 TM0_ACI3 Table 24. Signal Multiplexing for Port D Signal Name PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 Multiplexed Function 0 C1_FLG0 C1_FLG1 TM0_TMR0 TM0_TMR1 TM0_TMR2 SPI0_SEL7 SPI1_SEL7 SPI1_SEL6 ETH0_PTPPPS1 LP1_D7 LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 Multiplexed Function 3 Multiplexed Function Input Tap SPI0_SEL5 SPI0_SEL6 UART0_RTS UART0_CTS TM0_TMR7 SPI2_SEL4 HADC0_EOC_DOUT TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 ETH0_PTPAUXIN0 ETH0_PTPAUXIN1 C2_FLG3 C1_FLG3 CNT0_ZM CNT0_DG PPI0_D07 PPI0_D00 PPI0_D01 PPI0_D02 PPI0_D03 PPI0_D04 PPI0_D05 Rev. B | Page 44 of 142 | June 2018 TM0_ACLK3 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x DESIGNER QUICK REFERENCE * The reset drive column specifies the active drive on the signal when the processor is in the reset state. Table 25 provides a quick reference summary of pin related information for circuit board design. The columns in this table provide the following information: * The power domain column specifies the power supply domain in which the signal resides. * The signal name column includes the signal name for every pin and the GPIO multiplexed pin function, where applicable. * The description and notes column identifies any special requirements or characteristics for a signal. These recommendations apply whether or not the hardware block associated with the signal is featured on the product. If no special requirements are listed, the signal can be left unconnected if it is not used. For multiplexed GPIO pins, this column identifies the functions available on the pin. * The type column identifies the I/O type or supply type of the pin. The abbreviations used in this column are analog (a), supply (s), ground (g) and Input, Output, and InOut. * The driver type column identifies the driver type used by the corresponding pin. The driver types are defined in the Output Drive Currents section of this data sheet. * The internal termination column specifies the termination present after the processor is powered up (both during reset and after reset). Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference Signal Name DAI0_PIN01 Type InOut DAI0_PIN02 InOut DAI0_PIN03 InOut DAI0_PIN04 InOut DAI0_PIN05 InOut DAI0_PIN06 InOut DAI0_PIN07 InOut DAI0_PIN08 InOut DAI0_PIN09 InOut DAI0_PIN10 InOut DAI0_PIN11 InOut DAI0_PIN12 InOut DAI0_PIN13 InOut DAI0_PIN14 InOut DAI0_PIN15 InOut Driver Type Internal Termination Reset Drive Power Domain Description and Notes VDD_EXT Desc: DAI0 Pin 1 A Programmable PullUp1 none Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 2 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 3 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 4 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: DAI0 Pin 5 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: DAI0 Pin 6 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 7 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 8 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 9 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 10 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: DAI0 Pin 11 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 12 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 13 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 14 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 15 Notes: See note2 Rev. B | Page 45 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name DAI0_PIN16 Type InOut DAI0_PIN17 InOut DAI0_PIN18 InOut DAI0_PIN19 InOut DAI0_PIN20 InOut DMC0_A00 Output DMC0_A01 Output DMC0_A02 Output DMC0_A03 Output DMC0_A04 Output DMC0_A05 Output DMC0_A06 Output DMC0_A07 Output DMC0_A08 Output DMC0_A09 Output DMC0_A10 Output DMC0_A11 Output DMC0_A12 Output DMC0_A13 Output DMC0_A14 Output DMC0_A15 Output DMC0_BA0 Output DMC0_BA1 Output DMC0_BA2 Output Driver Type Internal Termination Reset Drive Power Domain Description and Notes A Programmable PullUp1 none VDD_EXT Desc: DAI0 Pin 16 Notes: See note2 3 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 17 Notes: See note2 3 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 18 Notes: See note2 3 A Programmable PullUp none VDD_EXT Desc: DAI0 Pin 19 Notes: See note2 A Programmable PullUp3 none VDD_EXT Desc: DAI0 Pin 20 Notes: See note2 B none L VDD_DMC Desc: DMC0 Address 0 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 1 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 2 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 3 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 4 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 5 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 6 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 7 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 8 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 9 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 10 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 11 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 12 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 13 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 14 Notes: No notes B none L VDD_DMC Desc: DMC0 Address 15 Notes: No notes B none L VDD_DMC Desc: DMC0 Bank Address Input 0 Notes: No notes B none L VDD_DMC Desc: DMC0 Bank Address Input 1 Notes: No notes B none L VDD_DMC Desc: DMC0 Bank Address Input 2 Notes: No notes Rev. B | Page 46 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name DMC0_CAS Type Driver Type Internal Termination Output B none DMC0_CK Output C none DMC0_CKE Output B none DMC0_CK Output C none DMC0_CS0 Output B none DMC0_DQ00 InOut B none DMC0_DQ01 InOut B none DMC0_DQ02 InOut B none DMC0_DQ03 InOut B none DMC0_DQ04 InOut B none DMC0_DQ05 InOut B none DMC0_DQ06 InOut B none DMC0_DQ07 InOut B none DMC0_DQ08 InOut B none DMC0_DQ09 InOut B none DMC0_DQ10 InOut B none DMC0_DQ11 InOut B none DMC0_DQ12 InOut B none DMC0_DQ13 InOut B none DMC0_DQ14 InOut B none DMC0_DQ15 InOut B none DMC0_LDM Output B none DMC0_LDQS InOut none C Rev. B | Reset Drive Power Domain Description and Notes L VDD_DMC Desc: DMC0 Column Address Strobe Notes: No notes L VDD_DMC Desc: DMC0 Clock Notes: No notes L VDD_DMC Desc: DMC0 Clock enable Notes: No notes L VDD_DMC Desc: DMC0 Clock (complement) Notes: No notes L VDD_DMC Desc: DMC0 Chip Select 0 Notes: No notes none VDD_DMC Desc: DMC0 Data 0 Notes: No notes none VDD_DMC Desc: DMC0 Data 1 Notes: No notes none VDD_DMC Desc: DMC0 Data 2 Notes: No notes none VDD_DMC Desc: DMC0 Data 3 Notes: No notes none VDD_DMC Desc: DMC0 Data 4 Notes: No notes none VDD_DMC Desc: DMC0 Data 5 Notes: No notes none VDD_DMC Desc: DMC0 Data 6 Notes: No notes none VDD_DMC Desc: DMC0 Data 7 Notes: No notes none VDD_DMC Desc: DMC0 Data 8 Notes: No notes none VDD_DMC Desc: DMC0 Data 9 Notes: No notes none VDD_DMC Desc: DMC0 Data 10 Notes: No notes none VDD_DMC Desc: DMC0 Data 11 Notes: No notes none VDD_DMC Desc: DMC0 Data 12 Notes: No notes none VDD_DMC Desc: DMC0 Data 13 Notes: No notes none VDD_DMC Desc: DMC0 Data 14 Notes: No notes none VDD_DMC Desc: DMC0 Data 15 Notes: No notes L VDD_DMC Desc: DMC0 Data Mask for Lower Byte Notes: No notes none VDD_DMC Desc: DMC0 Data Strobe for Lower Byte Notes: External weak pull-down required in LPDDR mode Page 47 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name DMC0_LDQS Type InOut Driver Type Internal Termination C none DMC0_ODT Output B none DMC0_RAS Output B none DMC0_RESET Output B none DMC0_RZQ a B none DMC0_UDM Output B none DMC0_UDQS InOut C none DMC0_UDQS InOut C none DMC0_VREF a none DMC0_WE Output B none GND g none HADC0_VIN0 a NA none HADC0_VIN1 a NA none HADC0_VIN2 a NA none HADC0_VIN3 a NA none HADC0_VIN4 a NA none HADC0_VIN5 a NA none HADC0_VIN6 a NA none Rev. B | Reset Drive Power Domain Description and Notes none VDD_DMC Desc: DMC0 Data Strobe for Lower Byte (complement) Notes: No notes L VDD_DMC Desc: DMC0 On-die termination Notes: No notes L VDD_DMC Desc: DMC0 Row Address Strobe Notes: No notes L VDD_DMC Desc: DMC0 Reset (DDR3 only) Notes: No notes none VDD_DMC Desc: DMC0 External calibration resistor connection Notes: Applicable for DDR2 and DDR3 only. Pull down using a 34 Ohm resistor. L VDD_DMC Desc: DMC0 Data Mask for Upper Byte Notes: No notes none VDD_DMC Desc: DMC0 Data Strobe for Upper Byte Notes: External weak pull-down required in LPDDR mode none VDD_DMC Desc: DMC0 Data Strobe for Upper Byte (complement) Notes: No notes none VDD_DMC Desc: DMC0 Voltage Reference Notes: No notes L VDD_DMC Desc: DMC0 Write Enable Notes: No notes none Desc: Ground Notes: No notes none VDD_HADC Desc: HADC0 Analog Input at channel 0 Notes: Connect to GND through a resistor if not used4 none VDD_HADC Desc: HADC0 Analog Input at channel 1 Notes: Connect to GND through a resistor if not used4 none VDD_HADC Desc: HADC0 Analog Input at channel 2 Notes: Connect to GND through a resistor if not used4 none VDD_HADC Desc: HADC0 Analog Input at channel 3 Notes: Connect to GND through a resistor if not used4 none VDD_HADC Desc: HADC0 Analog Input at channel 4 Notes: Connect to GND through a resistor if not used4 none VDD_HADC Desc: HADC0 Analog Input at channel 5 Notes: Connect to GND through a resistor if not used4 none VDD_HADC Desc: HADC0 Analog Input at channel 6 Notes: Connect to GND through a resistor if not used4 Page 48 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name HADC0_VIN7 Type a Driver Type Internal Termination NA none HADC0_VREFN s NA none HADC0_VREFP s NA none JTG_TCK Input PullUp JTG_TDI Input PullUp JTG_TDO Output A none JTG_TMS InOut PullUp JTG_TRST Input MLB0_CLKN Input NA MLB0_CLKP Input NA MLB0_DATN InOut I MLB0_DATP InOut I MLB0_SIGN InOut I MLB0_SIGP InOut I PA_00 InOut A Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Programmable PullUp1 PA_01 InOut PA_02 A PullDown Reset Drive Power Domain Description and Notes none VDD_HADC Desc: HADC0 Analog Input at channel 7 Notes: Connect to GND through a resistor if not used4 none VDD_HADC Desc: HADC0 Ground Reference for ADC Notes: Connect to GND if HADC and TMU are not used none VDD_HADC Desc: HADC0 External Reference for ADC Notes: No notes none VDD_EXT Desc: JTAG Clock Notes: No notes none VDD_EXT Desc: JTAG Serial Data In Notes: No notes High-Z when VDD_EXT Desc: JTAG Serial Data Out JTG_TRST is Notes: No notes low, not affected by SYS_HWRST none VDD_EXT Desc: JTAG Mode Select Notes: No notes none VDD_EXT Desc: JTAG Reset Notes: No notes none VDD_EXT Desc: MLB0 Differential Clock (-) Notes: No notes none VDD_EXT Desc: MLB0 Differential Clock (+) Notes: No notes none VDD_EXT Desc: MLB0 Differential Data (-) Notes: No notes none VDD_EXT Desc: MLB0 Differential Data (+) Notes: No notes none VDD_EXT Desc: MLB0 Differential Signal (-) Notes: No notes none VDD_EXT Desc: MLB0 Differential Signal (+) Notes: No notes none VDD_EXT A Programmable PullUp1 none VDD_EXT InOut A Programmable PullUp1 none VDD_EXT PA_03 InOut A Programmable PullUp1 none VDD_EXT PA_04 InOut A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 0 Notes: See note2 Desc: PORTA Position 1 Notes: See note2 Desc: PORTA Position 2 Notes: See note2 Desc: PORTA Position 3 Notes: See note2 Desc: PORTA Position 4 Notes: See note2 Rev. B | Page 49 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name PA_05 Type InOut PA_06 InOut PA_07 InOut PA_08 InOut PA_09 InOut PA_10 InOut PA_11 InOut PA_12 InOut PA_13 InOut PA_14 InOut PA_15 InOut PB_00 InOut PB_01 InOut PB_02 InOut PB_03 InOut PB_04 InOut PB_05 InOut PB_06 InOut PB_07 InOut PB_08 InOut PB_09 InOut Driver Type Internal Termination Reset Drive Power Domain Description and Notes A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 5 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 6 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 7 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 8 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 9 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 10 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 11 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 12 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 13 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 14 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTA Position 15 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTB Position 0 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTB Position 1 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTB Position 2 Notes: See note2 H none none VDD_EXT Desc: PORTB Position 3 Notes: Connect to VDD_EXT or GND if not used H none none VDD_EXT Desc: PORTB Position 4 Notes: Connect to VDD_EXT or GND if not used H none none VDD_EXT Desc: PORTB Position 5 Notes: Connect to VDD_EXT or GND if not used H none none VDD_EXT Desc: PORTB Position 6 Notes: Connect to VDD_EXT or GND if not used H none none VDD_EXT Desc: PORTB Position 7 Notes: Connect to VDD_EXT or GND if not used H none none VDD_EXT Desc: PORTB Position 8 Notes: Connect to VDD_EXT or GND if not used H none none VDD_EXT Desc: PORTB Position 9 Notes: Connect to VDD_EXT or GND if not used Rev. B | Page 50 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name PB_10 Type InOut Driver Type Internal Termination H none PB_11 InOut H none PB_12 InOut H none PB_13 InOut H none PB_14 InOut H none PB_15 InOut A Programmable PullUp1 PC_00 InOut A Programmable PullUp1 PC_01 InOut A Programmable PullUp1 PC_02 InOut A Programmable PullUp1 PC_03 InOut A Programmable PullUp1 PC_04 InOut A Programmable PullUp1 PC_05 InOut A Programmable PullUp1 PC_06 InOut A Programmable PullUp1 PC_07 InOut A Programmable PullUp1 PC_08 InOut A Programmable PullUp1 PC_09 InOut A Programmable PullUp1 PC_10 InOut A Programmable PullUp1 PC_11 InOut A Programmable PullUp1 PC_12 InOut A Programmable PullUp1 PC_13 InOut A Programmable PullUp1 PC_14 InOut A Programmable PullUp1 PC_15 InOut A Programmable PullUp1 Rev. B | Reset Drive Power Domain Description and Notes none VDD_EXT Desc: PORTB Position 10 Notes: Connect to VDD_EXT or GND if not used none VDD_EXT Desc: PORTB Position 11 Notes: Connect to VDD_EXT or GND if not used none VDD_EXT Desc: PORTB Position 12 Notes: Connect to VDD_EXT or GND if not used none VDD_EXT Desc: PORTB Position 13 Notes: Connect to VDD_EXT or GND if not used none VDD_EXT Desc: PORTB Position 14 Notes: Connect to VDD_EXT or GND if not used none VDD_EXT Desc: PORTB Position 15 Notes: See note2 none VDD_EXT Desc: PORTC Position 0 Notes: See note2 none VDD_EXT Desc: PORTC Position 1 Notes: See note2 none VDD_EXT Desc: PORTC Position 2 Notes: See note2 none VDD_EXT Desc: PORTC Position 3 Notes: See note2 none VDD_EXT Desc: PORTC Position 4 Notes: See note2 none VDD_EXT Desc: PORTC Position 5 Notes: See note2 none VDD_EXT Desc: PORTC Position 6 Notes: See note2 none VDD_EXT Desc: PORTC Position 7 Notes: See note2 none VDD_EXT Desc: PORTC Position 8 Notes: See note2 none VDD_EXT Desc: PORTC Position 9 Notes: See note2 none VDD_EXT Desc: PORTC Position 10 Notes: See note2 none VDD_EXT Desc: PORTC Position 11 Notes: See note2 none VDD_EXT Desc: PORTC Position 12 Notes: See note2 none VDD_EXT Desc: PORTC Position 13 Notes: See note2 none VDD_EXT Desc: PORTC Position 14 Notes: See note2 none VDD_EXT Desc: PORTC Position 15 Notes: See note2 Page 51 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name PD_00 Type InOut PD_01 InOut PD_02 InOut PD_03 InOut PD_04 InOut PD_05 InOut PD_06 InOut PD_07 InOut PD_08 InOut PD_09 InOut PD_10 InOut PD_11 InOut PD_12 InOut PD_13 InOut PD_14 InOut PD_15 InOut PE_00 InOut PE_01 InOut PE_02 InOut PE_03 InOut PE_04 InOut PE_05 InOut PE_06 InOut PE_07 InOut Driver Type Internal Termination Reset Drive Power Domain Description and Notes A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 0 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 1 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 2 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 3 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 4 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 5 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 6 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 7 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 8 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 9 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 10 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTD Position 11 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTD Position 12 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTD Position 13 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTD Position 14 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTD Position 15 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTE Position 0 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 1 Notes: See note2 H none none VDD_EXT Desc: PORTE Position 2 Notes: Connect to VDD_EXT or GND if not used A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 3 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 4 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 5 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 6 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 7 Notes: See note2 Rev. B | Page 52 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name PE_08 Type InOut PE_09 InOut PE_10 InOut PE_11 InOut PE_12 InOut PE_13 InOut PE_14 InOut PE_15 InOut PF_00 InOut PF_01 InOut PF_02 InOut PF_03 InOut PF_04 InOut PF_05 InOut PF_06 InOut PF_07 InOut PF_08 InOut PF_09 InOut PF_10 InOut PF_11 InOut SYS_BMODE0 Input SYS_BMODE1 Input SYS_BMODE2 Input SYS_CLKIN0 a Driver Type Internal Termination Reset Drive Power Domain Description and Notes A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 8 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 9 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 10 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTE Position 11 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 12 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTE Position 13 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTE Position 14 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTE Position 15 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 0 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 1 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTF Position 2 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 3 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 4 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 5 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 6 Notes: See note2 A Programmable PullUp1 none VDD_EXT Desc: PORTF Position 7 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 8 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 9 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 10 Notes: See note2 1 A Programmable PullUp none VDD_EXT Desc: PORTF Position 11 Notes: See note2 NA none none VDD_EXT Desc: Boot Mode Control n Notes: No connection not allowed NA none none VDD_EXT Desc: Boot Mode Control n Notes: No connection not allowed NA none none VDD_EXT Desc: Boot Mode Control n Notes: No connection not allowed NA none none VDD_EXT Desc: Clock/Crystal Input Notes: No connection not allowed Rev. B | Page 53 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name SYS_CLKIN1 Type a Driver Type Internal Termination NA none SYS_CLKOUT a H none SYS_FAULT InOut A none SYS_FAULT InOut A none SYS_HWRST Input NA none SYS_RESOUT Output A none SYS_XTAL0 a NA none SYS_XTAL1 a NA none TWI0_SCL InOut D none TWI0_SDA InOut D none TWI1_SCL InOut D none TWI1_SDA InOut D none TWI2_SCL InOut D none TWI2_SDA InOut D none USB0_DM InOut F none USB0_DP InOut F none USB0_ID InOut none Rev. B | Reset Drive Power Domain Description and Notes none VDD_EXT Desc: Clock/Crystal Input Notes: Connect to GND if not used High-Z when VDD_EXT Desc: Processor Clock Output SYS_HWRST Notes: No notes and JTG_TRST are both active5 none VDD_EXT Desc: Active-High Fault Output Notes: Pull down if not used none VDD_EXT Desc: Active-Low Fault Output Notes: Pull up if not used none VDD_EXT Desc: Processor Hardware Reset Control Notes: No connection not allowed High-Z when VDD_EXT Desc: Reset Output SYS_HWRST Notes: No notes and JTG_TRST are both active5 none VDD_EXT Desc: Crystal Output Notes: No notes none VDD_EXT Desc: Crystal Output Notes: No notes none VDD_EXT Desc: TWI0 Serial Clock Notes: Add external pull-up if used. Connect to GND if not used. none VDD_EXT Desc: TWI0 Serial Data Notes: Add external pull-up if used. Connect to GND if not used. none VDD_EXT Desc: TWI1 Serial Clock Notes: Add external pull-up if used. Connect to GND if not used. none VDD_EXT Desc: TWI1 Serial Data Notes: Add external pull-up if used. Connect to GND if not used. none VDD_EXT Desc: TWI2 Serial Clock Notes: Add external pull-up if used. Connect to GND if not used. none VDD_EXT Desc: TWI2 Serial Data Notes: Add external pull-up if used. Connect to GND if not used. none VDD_USB Desc: USB0 Data- Notes: Add external pull-down if not used6 none VDD_USB Desc: USB0 Data + Notes: Add external pull-down if not used6 none VDD_USB Desc: USB0 OTG ID Notes: Connect to GND when USB is not used6 Page 54 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued) Signal Name USB0_VBC Type InOut Driver Type Internal Termination E none USB0_VBUS InOut G USB0_CLKIN a none USB0_XTAL a none VDD_DMC s none VDD_EXT s none VDD_HADC s none VDD_INT s none VDD_USB s none none Reset Drive Power Domain Description and Notes none VDD_USB Desc: USB0 VBUS Control Notes: Add external pull-down if not used6 none VDD_USB Desc: USB0 Bus Voltage Notes: Connect to GND when USB is not used6 none VDD_USB Desc: USB0/USB1 Clock/Crystal Input Notes: Connect to GND when USB is not used6 none VDD_USB Desc: USB0/USB1 Crystal Notes: No notes none Desc: DMC VDD Notes: No notes none Desc: External Voltage Domain Notes: No notes none Desc: HADC/TMU VDD Notes: Can be left floating if HADC and TMU are not used none Desc: Internal Voltage Domain Notes: No notes none Desc: USB VDD Notes: Connect to VDD_EXT when USB is not used 1 Disabled by default. Input by default. When unused, terminate externally in hardware or enable the internal pull-up resistor (when applicable) in software. When present, the internal pull-up design holds the internal path from the pins at the expected logic levels. To pull up the external pads to the expected logic levels, use external resistors.. 3 Enabled by default. 4 All HADC0_VINx pins can be connected directly to GND if HADC and TMU are not used. 5 Actively driven by processor otherwise. 6 Guidance also applies to models that do not feature the associated hardware block. See Table 2 or Table 3 for further information. 2 Rev. B | Page 55 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPECIFICATIONS For information about product specifications, contact your Analog Devices representative. OPERATING CONDITIONS Parameter Conditions Min Nominal Max Unit CCLK 450 MHz CCLK 500 MHz 1.05 1.10 3.13 3.13 1.7 1.425 3.13 0.49 x VDD_DMC 1.10 1.15 3.3 3.3 1.8 1.5 3.3 0.50 x VDD_DMC 1.15 1.20 3.47 3.47 1.9 1.575 3.47 0.51 x VDD_DMC V V V V V V V V 2.5 0 2.0 0.7 x VVBUSTWI 3.30 VDD_HADC V VHADC_REF + 0.2 V V VVBUSTWI V VDD_INT Internal (Core) Supply Voltage VDD_EXT VDD_HADC VDD_DMC1 VHADC_REF3 VHADC0_VINx VIH4 VIHTWI5, 6 External (I/O) Supply Voltage Analog Power Supply Voltage DDR2/LPDDR Controller Supply Voltage DDR3 Controller Supply Voltage USB Supply Voltage DDR2 Reference Voltage Applies to the DMC0_VREF pin HADC Reference Voltage HADC Input Voltage High Level Input Voltage High Level Input Voltage VDD_EXT = 3.47 V VDD_EXT = 3.47 V VIL4 VILTWI5, 6 Low Level Input Voltage Low Level Input Voltage VDD_EXT = 3.13 V VDD_EXT = 3.13 V 0.8 0.3 x VVBUSTWI V V VIL_DDR27 VIL_DDR37 VIH_DDR27 VIH_DDR37 VIL_LPDDR8 VIH_LPDDR8 TJ Low Level Input Voltage Low Level Input Voltage High Level Input Voltage High Level Input Voltage Low Level Input Voltage High Level Input Voltage Junction Temperature 400-Ball CSP_BGA VREF - 0.25 VREF - 0.175 TJ Junction Temperature 400-Ball CSP_BGA TJ Junction Temperature 176-Lead LQFP-EP TJ Junction Temperature 176-Lead LQFP-EP TJ Junction Temperature 400-Ball CSP_BGA TJ Junction Temperature 400-Ball CSP_BGA TJ Junction Temperature 176-Lead LQFP-EP TJ Junction Temperature 176-Lead LQFP-EP VDD_DMC = 1.7 V VDD_DMC = 1.425 V VDD_DMC = 1.9 V VDD_DMC = 1.575 V VDD_DMC = 1.7 V VDD_DMC = 1.9 V TAMBIENT = 0C to +70C CCLK 450 MHz TAMBIENT = -40C to +100C CCLK 450 MHz TAMBIENT = 0C to +70C CCLK 450 MHz TAMBIENT = -40C to +105C CCLK 450 MHz TAMBIENT = 0C to +70C CCLK 500 MHz TAMBIENT = -40C to +95C CCLK 500 MHz TAMBIENT = 0C to +70C CCLK 500 MHz TAMBIENT = -40C to +100C CCLK 500 MHz VDD_USB2 VDDR_VREF Rev. B | Page 56 of 142 | June 2018 0.8 x VDD_DMC 0 95 V V V V V V C -40 +125 C 0 90 C -40 +125 C 0 100 C -40 +125 C 0 95 C -40 +125 C VREF + 0.25 VREF + 0.175 0.2 x VDD_DMC ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Parameter Conditions Min AUTOMOTIVE USE ONLY Junction Temperature 400-Ball CSP_BGA TJ (Automotive Grade) TJ Junction Temperature 176-Lead LQFP-EP (Automotive Grade) TJ Junction Temperature 400-Ball CSP_BGA (Automotive Grade) TJ Junction Temperature 176-Lead LQFP-EP (Automotive Grade) TAMBIENT = -40C to +105C CCLK 450 MHz TAMBIENT = -40C to +105C CCLK 450 MHz TAMBIENT = -40C to +105C CCLK 500 MHz TAMBIENT = -40C to +105C CCLK 500 MHz Nominal Max Unit -40 +1309 C -40 +1259 C -40 +1339 C -40 +1309 C 1 Applies to DDR2/DDR3/LPDDR signals. If not used, VDD_USB must be connected to 3.3 V. 3 VHADC_VREF must always be less than VDD_HADC. 4 Parameter value applies to all input and bidirectional pins except the TWI, DMC, USB, and MLB pins. 5 Parameter applies to TWI signals. 6 TWI signals are pulled up to VBUSTWI. See Table 26. 7 This parameter applies to all DMC0 signals in DDR2/DDR3 mode. VREF is the voltage applied to the VREF_DMC pin, nominally VDD_DMC/2. 8 This parameter applies to DMC0 signals in LPDDR mode. 9 Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information. 2 Table 26. TWI_VSEL Selections and VDD_EXT/VBUSTWI VBUSTWI TWI_VSEL Selections TWI000 TWI100 1 1 VDD_EXT Nominal Min Nominal Max Unit 3.30 3.13 3.30 3.47 V 3.30 4.75 5.00 5.25 V Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset. Rev. B | Page 57 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Clock Related Operating Conditions Table 27 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the table applies to all speed grades except where expressly noted. Table 27. Clock Operating Conditions Parameter fCCLK Core Clock Frequency Restriction Min fCCLK fSYSCLK 100 30 Typ 1 fSYSCLK SYSCLK Frequency fSCLK0 SCLK0 Frequency2 fSYSCLK fSCLK0 fSCLK1 SCLK1 Frequency fSYSCLK fSCLK1 Max Unit 500 MHz 250 MHz 125 MHz 125 MHz fDCLK LPDDR Clock Frequency 200 MHz fDCLK DDR2 Clock Frequency 400 MHz fDCLK DDR3 Clock Frequency 450 MHz fOCLK Output Clock Frequency3 250 MHz fSYS_CLKOUTJ SYS_CLKOUT Period Jitter 4, 5 1 % fPCLKPROG Programmed PPI Clock When Transmitting Data and Frame Sync 62.5 MHz fPCLKPROG Programmed PPI Clock When Receiving Data or Frame Sync 50 MHz fPCLKEXT External PPI Clock When Receiving Data and Frame Sync6, 7 62.5 MHz fPCLKEXT fSCLK0 6, 7 fPCLKEXT External PPI Clock Transmitting Data or Frame Sync fLCLKTPROG Programmed Link Port Transmit Clock fPCLKEXT fSCLK0 fLCLKREXT External Link Port Receive Clock6, 7 fSPTCLKPROG Programmed SPT Clock When Transmitting Data and Frame Sync fSPTCLKPROG Programmed SPT Clock When Receiving Data or Frame Sync 50 MHz 125 MHz 125 MHz 62.5 MHz 31.25 MHz fSPTCLKEXT fSCLK0 62.5 MHz fSPTCLKEXT fSCLK0 31.25 MHz fLCLKEXT fSCLK0 6, 7 fSPTCLKEXT External SPT Clock When Receiving Data and Frame Sync fSPTCLKEXT External SPT Clock Transmitting Data or Frame Sync6, 7 fSPICLKPROG Programmed SPI2 Clock When Transmitting Data 75 MHz Programmed SPI0, SPI1 Clock When Transmitting Data 62.5 MHz Programmed SPI2 Clock When Receiving Data 75 MHz fSPICLKPROG Programmed SPI0, SPI1 Clock When Receiving Data fSPICLKEXT fSPICLKEXT fACLKPROG 62.5 MHz External SPI2 Clock When Receiving Data6, 7 fSPICLKEXT fSCLK1 75 MHz External SPI0, SPI1 Clock When Receiving Data6, 7 fSPICLKEXT fSCLK0 62.5 MHz External SPI2 Clock When Transmitting Data6, 7 fSPICLKEXT fSCLK1 45 MHz External SPI0, SPI1 Clock When Transmitting Data6,7 fSPICLKEXT fSCLK0 62.5 MHz 56.25 MHz Programmed ACM Clock 1 When using MLB, there is a requirement that the fSYSCLK value must be a minimum of 100 MHz for both 3-pin and 6-pin modes and for all supported speeds. The minimum frequency for SCLK0 applies only when using the USB. fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT. 4 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due to the dependency on these factors, the measured jitter can be higher or lower than this typical specification for each end application. 5 The value in the Typ field is the percentage of the SYS_CLKOUT period. 6 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications section for that peripheral. 7 The peripheral external clock frequency must also be less than or equal to the fSCLK (fSCLK0 or fSCLK1) that clocks the peripheral. 2 3 Rev. B | Page 58 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 28. PLL Operating Conditions Parameter fPLLCLK Min 200 PLL Clock Frequency CSEL (1-31) SYSSEL (1-31) SYS_CLKIN PLL Max 1000 CCLK S0SEL (1-7) SCLK0 S1SEL (1-7) SCLK1 SYSCLK PLLCLK DSEL (1-31) DCLK OSEL (1-127) OUTCLK Figure 7. Clock Relationships and Divider Values Rev. B | Page 59 of 142 | June 2018 Unit MHz ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ELECTRICAL CHARACTERISTICS Parameter Conditions Min 1 2 VOH High Level Output Voltage At VDD_EXT = minimum, IOH = -1.0 mA VOL1 Low Level Output Voltage At VDD_EXT = minimum, IOL = 1.0 mA2 3 Typ Max 2.4 Unit V 0.4 V VOH_DDR2 High Level Output Voltage At VDD_DDR = minimum, IOH = -5.8 mA for DDR2 DS = 40 VOL_DDR23 Low Level Output Voltage At VDD_DDR = minimum, IOL = 5.8 mA for DDR2 DS = 40 VOH_DDR23 High Level Output Voltage At VDD_DDR = minimum, IOH = -3.4 mA for DDR2 DS = 60 VOL_DDR23 Low Level Output Voltage At VDD_DDR = minimum, IOL = 3.4 mA for DDR2 DS = 60 VOH_DDR34 High Level Output Voltage At VDD_DDR = minimum, IOH = -5.8 mA for DDR3 DS = 40 VOL_DDR34 Low Level Output Voltage At VDD_DDR = minimum, IOL = 5.8 mA for DDR3 DS = 40 VOH_DDR34 High Level Output Voltage At VDD_DDR = minimum, IOH = -3.4 mA for DDR3 DS = 60 VOL_DDR34 Low Level Output Voltage At VDD_DDR = minimum, IOL = 3.4 mA for DDR3 DS = 60 VOH_LPDDR5 High Level Output Voltage At VDD_DDR = minimum, IOH = -6.0 mA for LPDDR VOL_LPDDR5 Low Level Output Voltage At VDD_DDR = minimum, IOL = 6.0 mA for LPDDR 0.32 V IIH6, 7 High Level Input Current At VDD_EXT = maximum, VIN = VDD_EXT maximum 10 A Low Level Input Current At VDD_EXT = maximum, VIN = 0 V 10 A IIL_PU Low Level Input Current Pull-Up At VDD_EXT = maximum, VIN = 0 V 200 A IIH_PD8 High Level Input Current Pull-Down At VDD_EXT = maximum, VIN = VDD_EXT maximum 200 A IOZH9 Three-State Leakage Current At VDD_EXT/VDD_DDR = maximum, VIN = VDD_EXT/VDD_DDR maximum 10 A IOZL9 Three-State Leakage Current At VDD_EXT/VDD_DDR = maximum, VIN = 0 V 10 A CIN10 Input Capacitance TCASE = 25C 5 pF IDD_IDLE VDD_INT Current in Idle fCCLK = 450 MHz ASFSHARC1 = 0.32 ASFSHARC2 = 0.32 ASFA5 = 0.25 fSYSCLK = 225 MHz fSCLK0/1 = 112.5 MHz (Other clocks are disabled) No Peripheral or DMA activity TJ = 25C VDD_INT = 1.1 V IIL6 7 Rev. B | Page 60 of 142 | 1.38 V 0.32 1.38 V 0.32 1.105 V V 0.32 1.105 V V 0.32 1.38 V V 410 June 2018 V mA ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Parameter Conditions Min Typ Max Unit IDD_IDLE VDD_INT Current in Idle fCCLK = 500 MHz ASFSHARC1 = 0.32 ASFSHARC2 = 0.32 ASFA5 = 0.25 fSYSCLK = 250 MHz fSCLK0/1 = 125 MHz (Other clocks are disabled) No Peripheral or DMA activity TJ = 25C VDD_INT = 1.15 V 477 mA IDD_TYP VDD_INT Current fCCLK = 450 MHz ASFSHARC1 = 1.0 ASFSHARC2 = 1.0 ASFA5 = 0.67 fSYSCLK = 225 MHz fSCLK0/1 = 112.5 MHz (Other clocks are disabled) DMA data rate = 600 MB/s TJ = 25C VDD_INT = 1.1 V 890 mA IDD_TYP VDD_INT Current fCCLK = 500 MHz ASFSHARC1 = 1.0 ASFSHARC2 = 1.0 ASFA5 = 0.67 fSYSCLK = 250 MHz fSCLK0/1 = 125 MHz (Other clocks are disabled) DMA data rate = 600 MB/s TJ = 25C VDD_INT = 1.15 V 1031 mA IDD_INT11 VDD_INT Current fCCLK 0 MHz fSCLK0/1 0 MHz See IDD_INT_TOT mA equation in the Total Internal Power Dissipation section. 1 Applies to all output and bidirectional pins except TWI, DMC, USB, and MLB. See the Output Drive Currents section for typical drive current capabilities. 3 Applies to all DMC output and bidirectional signals in DDR2 mode. 4 Applies to all DMC output and bidirectional signals in DDR3 mode. 5 Applies to all DMC output and bidirectional signals in LPDDR mode. 6 Applies to input pins: SYS_BMODE0-2, SYS_CLKIN0, SYS_CLKIN1, SYS_HWRST, JTG_TDI, JTG_TMS, and USB0_CLKIN. 7 Applies to input pins with internal pull-ups: JTG_TDI, JTG_TMS, and JTG_TCK. 8 Applies to signals: JTAG_TRST, USB0_VBUS. 9 Applies to signals: PA0-15, PB0-15, PC0-15, PD0-15, PE0-15, PF0-11, DAI0_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS, DMC0_UDQS, SYS_FAULT, SYS_FAULT, JTG_TDO, USB0_ID, USB0_DM, USB0_DP, and USB0_VBC. 10 Applies to all signal pins. 11 See "Estimating Power for ADSP-SC57x/2157x SHARC+ Processors" (EE-397) for further information. 2 Rev. B | Page 61 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Total Internal Power Dissipation Application Dependent Current Total power dissipation has two components: The application dependent currents include the dynamic current in the core clock domain of the two SHARC+ cores and the ARM Cortex-A5 core, as well as the dynamic current in the accelerator block. 1. Static, including leakage current 2. Dynamic, due to transistor switching characteristics for each clock domain Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. The following equation describes the internal current consumption. IDD_INT_TOT = IDD_INT_STATIC + IDD_INT_CCLK_SHARC1_DYN + IDD_INT_CCLK_SHARC2_DYN + IDD_INT_CCLK_A5_DYN + IDD_INT_DCLK_DYN + IDD_INT_SYSCLK_DYN + IDD_INT_SCLK0_DYN + IDD_INT_SCLK1_DYN + IDD_INT_OCLK_DYN + IDD_INT_ACCL_DYN + IDD_INT_USB_DYN + IDD_INT_MLB_DYN + IDD_INT_EMAC_DYN + IDD_INT_DMA_DR_DYN IDD_INT_STATIC is the sole contributor to the static power dissipation component and is specified as a function of voltage (VDD_INT) and junction temperature (TJ) in Table 29. Table 29. Static Current--IDD_INT_STATIC (mA) Voltage (VDD_INT) Dynamic current consumed by the core is subject to an activity scaling factor (ASF) that represents application code running on the processor cores (see Table 30 and Table 31). The ASF is combined with the CCLK frequency and VDD_INT dependent dynamic current data in Table 32 and Table 33, respectively, to calculate this portion of the total dynamic power dissipation component. IDD_INT_CCLK_SHARC1_DYN = Table 32 x ASFSHARC1 IDD_INT_CCLK_SHARC2_DYN = Table 32 x ASFSHARC2 IDD_INT_CCLK_A5_DYN = Table 33 x ASFA5 Table 30. Activity Scaling Factors for the SHARC+(R) Core 1 and Core 2 (ASFSHARC1 and ASFSHARC2) IDD_INT Power Vector ASF IDD-IDLE 0.32 IDD-NOP 0.55 IDD-TYP_3070 0.75 TJ (C) 1.05 1.10 1.15 1.20 IDD-TYP_5050 0.88 -40 4 5 6 7 IDD-TYP_7030 1.00 -20 6 8 9 11 IDD-PEAK_100 1.13 -10 8 10 12 14 0 11 13 16 18 +10 15 17 20 24 +25 22 26 30 35 IDD_INT Power Vector ASF +40 34 39 45 52 IDD-IDLE 0.25 +55 50 57 66 76 IDD-DHRYSTONE 0.67 0.53 Table 31. Activity Scaling Factors for the ARM(R) Cortex(R)-A5 Core (ASFA5) +70 74 84 95 109 IDD-TYP_2575 +85 107 121 137 155 IDD-TYP_5050 0.75 +100 153 172 194 218 IDD-TYP_7525 1.00 +105 173 195 219 246 IDD-PEAK_100 1.27 +115 217 243 273 305 +125 271 302 338 377 +133 323 359 400 446 The other 13 addends in the IDD_INT_TOT equation comprise the dynamic power dissipation component and fall into four broad categories: application-dependent currents, clock currents, currents from high speed peripheral operation, and data transmission currents. Rev. B | Page 62 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 32. Dynamic Current for Each SHARC+(R)Core (mA, with ASF = 1.00)1 Clock Current The dynamic clock currents provide the total power dissipated by all transistors switching in the clock paths. The power dissipated by each clock domain is dependent on voltage (VDD_INT), operating frequency, and a unique scaling factor. Voltage (VDD_INT) 1 fCCLK (MHz) 1.05 1.10 1.15 1.20 500 N/A 347 362 378 450 298 312 326 340 400 265 277 290 302 IDD_INT_SCLK0_DYN (mA) = 0.28 x fSCLK0 (MHz) x VDD_INT (V) IDD_INT_SYSCLK_DYN (mA) = 0.52 x fSYSCLK (MHz) x VDD_INT (V) 350 232 243 254 265 IDD_INT_SCLK1_DYN (mA) = 0.013 x fSCLK1 (MHz) x VDD_INT (V) 300 198 208 217 227 IDD_INT_DCLK_DYN (mA) = 0.08 x fDCLK (MHz) x VDD_INT (V) 250 165 173 181 189 IDD_INT_OCLK_DYN (mA) = 0.015 x fOCLK (MHz) x VDD_INT (V) 200 132 139 145 151 Current from High Speed Peripheral Operation 150 99 104 109 113 100 66 69 72 76 The following modules contribute significantly to power dissipation, and a single term is added when they are used. IDD_INT_USB_DYN = 9.6 mA (if USB is enabled in HS mode) N/A means not applicable. IDD_INT_MLB_DYN = 10 mA (if MLB 6-pin interface is enabled) Table 33. Dynamic Current for the ARM(R) Cortex(R)-A5 Core (mA, with ASF = 1.00)1 Voltage (VDD_INT) 1 fCCLK (MHz) 1.05 1.10 1.15 1.20 500 N/A 88 92 96 450 76 79 83 86 400 67 70 74 77 350 59 62 64 67 300 50 53 55 58 250 42 44 46 48 200 34 35 37 39 150 25 26 28 29 100 17 18 18 19 IDD_INT_EMAC_DYN = 10 mA (if EMAC is enabled) Data Transmission Current The data transmission current represents the power dissipated when moving data throughout the system via DMA. This current is proportional to the data rate. Refer to the power calculator available with "Estimating Power for ADSPSC57x/2157x SHARC+ Processors" (EE-397) to estimate IDD_INT_DMA_DR_DYN based on the bandwidth of the data transfer. N/A means not applicable. Rev. B | Page 63 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 HADC HADC Timing Specifications HADC Electrical Characteristics Table 37. HADC Timing Specifications Parameter Conversion Time1 Throughput Range TWAKEUP Table 34. HADC Electrical Characteristics Parameter IDD_HADC_IDLE IDD_HADC_ACTIVE Conditions Current consumption on VDD_HADC HADC is powered on, but not converting Current consumption on VDD_HADC during a conversion Typ Unit 2.0 mA 1 2.5 mA IDD_HADC_POWERDOWN Current consumption on 60 VDD_HADC Analog circuitry of the HADC is powered down A Typ 20 x TSAMPLE Max 1 100 Unit s MSPS s Refer to the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for additional information about TSAMPLE. TMU TMU Characteristics Table 38. TMU Characteristics Parameter Resolution Accuracy HADC DC Accuracy Typ 1 8 Unit C C Table 35. HADC DC Accuracy for CSP_BGA1 Parameter Resolution No Missing Codes (NMC) - Unrestricted No Missing Codes (NMC) - Pin Restrictions3 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Matching Gain Error Gain Error Matching 1 2 3 Unit2 Bits Bits Bits LSB LSB LSB LSB LSB LSB Typ 9 9 10 2 2 5 6 4 4 Table 39. TMU Gain and Offset Junction Temperature Range -40C to +40C 40C to 85C 85C to 133C See the Operating Conditions section for the HADC0_VINx specification. LSB = HADC0_VREFP / 512. Pin restrictions required: pins DAI18, DAI19, and DAI20 must be programmed to inputs and a static (non-switching) signal applied to the pins. Table 36. HADC DC Accuracy for LQFP_EP1 Parameter Resolution No Missing Codes (NMC) - Unrestricted No Missing Codes (NMC) - Pin Restrictions3 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Matching Gain Error Gain Error Matching Unit2 Bits Bits Bits LSB LSB LSB LSB LSB LSB Typ 7 7 9 2 2 5 6 4 4 1 See the Operating Conditions section for the HADC0_VINx specification. LSB = HADC0_VREFP / 128. 3 Pin restrictions required: pins DAI18, DAI19, and DAI20 must be programmed to inputs and a static (non-switching) signal applied to the pins. 2 Rev. B | Page 64 of 142 | June 2018 TMU_GAIN TMU_OFFSET Contact Analog Devices, Inc. Contact Analog Devices, Inc. Contact Analog Devices, Inc. ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Stresses at or above those listed in Table 40 may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Table 40. Absolute Maximum Ratings Parameter Internal (Core) Supply Voltage (VDD_INT) External (I/O) Supply Voltage (VDD_EXT) DDR2/LPDDR Controller Supply Voltage (VDD_DMC) DDR3 Controller Supply Voltage (VDD_DMC) DDR2 Reference Voltage (VDDR_VREF) USB PHY Supply Voltage (VDD_USB) HADC Supply Voltage (VDD_HADC) HADC Reference Voltage (VHADC_REF) DDR2/LPDDR Input Voltage1 DDR3 Input Voltage1 Digital Input Voltage1, 2 TWI Input Voltage1, 3 USB0_Dx Input Voltage1, 4 USB0_VBUS Input Voltage1, 4 Output Voltage Swing Analog Input Voltage5 IOH/IOL Current per Signal2 Storage Temperature Range Junction Temperature While Biased Rating -0.33 V to +1.26 V -0.33 V to +3.60 V -0.33 V to +1.90 V -0.33 V to +1.60 V -0.33 V to +1.90 V -0.33 V to +3.60 V -0.33 V to +3.60 V -0.33 V to +3.60 V -0.33 V to +1.90 V -0.33 V to +1.60 V -0.33 V to +3.60 V -0.33 V to +5.50 V -0.33 V to +5.25 V -0.33 V to +6 V -0.33 V to VDD_EXT +0.5 V -0.2 V to VDD_HADC +0.2 V 6 mA (maximum) -65C to +150C 133C 1 Applies only when the related power supply (VDD_DMC, VDD_EXT, or VDD_USB) is within specification. When the power supply is below specification, the range is the voltage being applied to that power domain 0.2 V. 2 Applies to 100% transient duty cycle. 3 Applies to TWI_SCL and TWI_SDA. 4 If the USB is not used, connect these pins according to Table 25. 5 Applies only when VDD_HADC is within specifications and 3.4 V. When VDD_HADC is within specifications and > 3.4 V, the maximum rating is 3.6 V. When VDD_HADC is below specifications, the range is VDD_HADC 0.2 V. Rev. B | Page 65 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 TIMING SPECIFICATIONS Specifications are subject to change without notice. Power-Up Reset Timing Table 41 and Figure 8 show the relationship between power supply startup and processor reset timing, related to the clock generation unit (CGU) and reset control unit (RCU). In Figure 8, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, and VDD_HADC. Table 41. Power-Up Reset Timing Parameter Min Max Unit Timing Requirement tRST_IN_PWR SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, VDD_HADC) and SYS_CLKINx are Stable and within Specification SYS_HWRST tRST_IN_PWR SYS_CLKIN0/1 V DD_SUPPLIES NOTE: V REFERS TO V ,V ,V , AND V . DD_SUPPLIES DD_INT DD_EXT DD_DMC DD_HADC Figure 8. Power-Up Reset Timing Rev. B | Page 66 of 142 | June 2018 11 x tCKIN ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Clock and Reset Timing Table 42 and Figure 9 describe clock and reset operations related to the CGU and RCU. Per the CCLK, SYSCLK, SCLK, DCLK, and OCLK timing specifications in Table 27, combinations of SYS_CLKIN and clock multipliers must not select clock rates in excess of the maximum instruction rate of the processor. Table 42. Clock and Reset Timing Parameter Min Max Unit 20 50 MHz 20 50 Timing Requirements fCKIN SYS_CLKINx Frequency (Crystal)1, 2, 3 SYS_CLKINx Frequency (External CLKIN) 1, 2, 3 MHz tCKINL CLKIN Low Pulse1 10 ns tCKINH CLKIN High Pulse1 10 ns tWRST RESET Asserted Pulse Width Low4 11 x tCKIN ns 1 Applies to PLL bypass mode and PLL nonbypass mode. The tCKIN period (see Figure 9) equals 1/fCKIN. 3 If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz. 4 Applies after power-up sequence is complete. See Table 41 and Figure 8 for power-up reset timing. 2 fCKIN SYS_CLKIN0/1 tCKINL tCKINH tWRST SYS_HWRST Figure 9. Clock and Reset Timing Rev. B | Page 67 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DDR2 SDRAM Clock and Control Cycle Timing Table 43 and Figure 10 show DDR2 SDRAM clock and control cycle timing, related to the DMC. Table 43. DDR2 SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.8 V 400 MHz1 Parameter Min Max Unit Switching Characteristics tCK Clock Cycle Time (CL = 2 Not Supported) 2.5 ns 2 Minimum Clock Pulse Width 0.48 0.52 tCK tCL(abs)2 Maximum Clock Pulse Width 0.48 0.52 tCK tIS Control/Address Setup Relative to DMC0_CK Rise 175 ps tIH Control/Address Hold Relative to DMC0_CK Rise 250 ps tCH(abs) 1 To ensure proper operation of DDR2, all the DDR2 requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). 2 As per JESD79-2E definition. tCK tCH tCL DMC0_CK DMC0_CK tIS tIH DMC0_Ax DMC0 CONTROL NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A0-A15 AND DMC0_BA0-BA2. Figure 10. DDR2 SDRAM Clock and Control Cycle Timing Rev. B | Page 68 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DDR2 SDRAM Read Cycle Timing Table 44 and Figure 11 show DDR2 SDRAM read cycle timing, related to the DMC. Table 44. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V 400 MHz1 Parameter Min Max Unit 0.2 ns Timing Requirements 1 tDQSQ DMC0_DQS to DMC0_DQ Skew for DMC0_DQS and Associated DMC0_DQxx Signals tQH DMC0_DQxx, DMC0_DQS Output Hold Time From DMC0_DQS tRPRE Read Preamble 0.9 tCK tRPST Read Postamble 0.4 tCK 0.8 ns To ensure proper operation of DDR2, all the DDR2 requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). tCK tCH tCL DMC0_CKx DMC0_CKx DMC0_Ax DMC0 CONTROL tRPRE DMC0_LDQS/DMC0_UDQS DMC0_LDQS/DMC0_UDQS tDQSQ tDQSQ tRPST tQH tQH DMC0_DQxx NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13 AND DMC0_BA0-1. Figure 11. DDR2 SDRAM Controller Input AC Timing Rev. B | Page 69 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DDR2 SDRAM Write Cycle Timing Table 45 and Figure 12 show DDR2 SDRAM write cycle timing, related to the DMC. Table 45. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V 400 MHz1 Parameter Min Max Unit -0.15 +0.15 tCK Switching Characteristics tDQSS DMC0_DQS Latching Rising Transitions to Associated Clock Edges2 tDS Last Data Valid to DMC0_DQS Delay 0.1 ns tDH DMC0_DQS to First Data Invalid Delay 0.15 ns tDSS DMC0_DQS Falling Edge to Clock Setup Time 0.2 tCK tDSH DMC0_DQS Falling Edge Hold Time From DMC0_CK 0.2 tCK tDQSH DMC0_DQS Input High Pulse Width 0.35 tCK tDQSL DMC0_DQS Input Low Pulse Width 0.35 tCK tWPRE Write Preamble 0.35 tCK tWPST Write Postamble 0.4 tCK tIPW Address and Control Output Pulse Width 0.6 tCK tDIPW DMC0_DQ and DMC0_DM Output Pulse Width 0.35 tCK 1 To ensure proper operation of the DDR2, all the DDR2 requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). 2 Write command to first DMC0_DQS delay = WL x tCK + tDQSS. DMC0_CK DMC0_CK tIPW DMC0_Ax DMC0 CONTROL tDSH tDSS tDQSS DMC0_LDQS/DMC0_UDQS DMC0_LDQS/DMC0_UDQS DMC0_DQSn DMC0_DQSn tWPRE tDQSL tDS tDH tDQSH tDIPW DMC0_LDM DMC0_UDM DMC0_DQx NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13 AND DMC0_BA0-1. Figure 12. DDR2 SDRAM Controller Output AC Timing Rev. B | Page 70 of 142 | June 2018 tWPST ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Table 46 and Figure 13 show mobile DDR SDRAM clock and control cycle timing, related to the DMC. Table 46. Mobile DDR SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.8 V 200 MHz1 Parameter Min Max Unit Switching Characteristics 1 tCK Clock Cycle Time (CL = 2 Not Supported) tCH Minimum Clock Pulse Width 0.45 0.55 tCK tCL Maximum Clock Pulse Width 0.45 0.55 tCK tIS Control/Address Setup Relative to DMC0_CK Rise 1 ns tIH Control/Address Hold Relative to DMC0_CK Rise 1 ns 5 ns To ensure proper operation of LPDDR, all the LPDDR requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). tCK tCH tCL DMC0_CK DMC0_CK tIS tIH DMC0_Ax DMC0 CONTROL NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A0-A15 AND DMC0_BA0-BA2. Figure 13. Mobile DDR SDRAM Clock and Control Cycle Timing Rev. B | Page 71 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Mobile DDR SDRAM Read Cycle Timing Table 47 and Figure 14 show mobile DDR SDRAM read cycle timing, related to the DMC. Table 47. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V 200 MHz1 Parameter Min Max Unit Timing Requirements 1 tQH DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS tDQSQ DMC0_DQS to DMC0_DQ Skew for DMC0_DQS and Associated DMC0_DQ Signals tRPRE Read Preamble tRPST Read Postamble 1.75 ns 0.4 ns 0.9 1.1 tCK 0.4 0.6 tCK To ensure proper operation of LPDDR, all the LPDDR requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). DMC0_CK tRPRE tRPST DMC0_LDQS/DMC0_HDQS tQH DMC0_DQx (DATA) Dn Dn+1 Dn+2 tDQSQ Figure 14. Mobile DDR SDRAM Controller Input AC Timing Rev. B | Page 72 of 142 | June 2018 Dn+3 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Mobile DDR SDRAM Write Cycle Timing Table 48 and Figure 15 show mobile DDR SDRAM write cycle timing, related to the DMC. Table 48. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V 200 MHz1 Parameter Min Max Unit 1.25 tCK Switching Characteristics tDQSS2 DMC0_DQS Latching Rising Transitions to Associated Clock Edges 0.75 tDS Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns) 0.48 ns tDH DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns) 0.48 ns tDSS DMC0_DQS Falling Edge to Clock Setup Time 0.2 tCK tDSH DMC0_DQS Falling Edge Hold Time From DMC0_CK 0.2 tCK tDQSH DMC0_DQS Input High Pulse Width 0.4 tCK tDQSL DMC0_DQS Input Low Pulse Width 0.4 tCK tWPRE Write Preamble 0.25 tCK tWPST Write Postamble 0.4 tCK tIPW Address and Control Output Pulse Width 2.3 ns tDIPW DMC0_DQ and DMC0_DM Output Pulse Width 1.8 ns 1 To ensure proper operation of LPDDR, all the LPDDR requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). 2 Write command to first DMC0_DQS delay = WL x tCK + tDQSS. DMC0_CK tDSS tDSH tDQSS DMC0_LDQS/DMC0_HDQS tWPRE tDS tDQSL tDH tDQSH tWPST tDIPW DMC0_DQ0-15/ DMC0_LDQM/DMC0_HDQM Dn Dn+1 Dn+2 Dn+3 tDIPW DMC0 CONTROL Write CMD NOTE: CONTROL = DMC0_CSx, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13 AND DMC0_BA0-1. tIPW Figure 15. Mobile DDR SDRAM Controller Output AC Timing Rev. B | Page 73 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DDR3 SDRAM Clock and Control Cycle Timing Table 49 and Figure 16 show mobile DDR3 SDRAM clock and control cycle timing, related to the DMC. Table 49. DDR3 SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.5 V 450 MHz1 Parameter Min Max Unit Switching Characteristics tCK Clock Cycle Time (CL = 2 Not Supported) 2.22 ns 2 Minimum Clock Pulse Width 0.47 0.53 tCK tCL(abs)2 Maximum Clock Pulse Width 0.47 0.53 tCK tIS Control/Address Setup Relative to DMC0_CK Rise 0.2 ns tIH Control/Address Hold Relative to DMC0_CK Rise 0.275 ns tCH(abs) 1 To ensure proper operation of the DDR3, all the DDR3 requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). 2 As per JESD79-3F definition. tCK tCH tCL DMC0_CK DMC0_CK tIS tIH DMC0_Ax DMC0 CONTROL NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A0-A15 AND DMC0_BA0-BA2. Figure 16. DDR3 SDRAM Clock and Control Cycle Timing Rev. B | Page 74 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DDR3 SDRAM Read Cycle Timing Table 50 and Figure 17 show mobile DDR3 SDRAM read cycle timing, related to the DMC. Table 50. DDR3 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.5 V 450 MHz1 Parameter Min Max Unit 0.15 ns Timing Requirements 1 tDQSQ DMC0_DQS to DMC0_DQ Skew for DMC0_DQS and Associated DMC0_DQ Signals tQH DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS 0.38 tCK tRPRE Read Preamble 0.9 tCK tRPST Read Postamble 0.3 tCK To ensure proper operation of the DDR3, all the DDR3 requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). tCK tCH tCL DMC0_CKx DMC0_CKx DMC0_Ax DMC0 CONTROL tRPRE DMC0_LDQS/DMC0_UDQS DMC0_LDQS/DMC0_UDQS tDQSQ tDQSQ tRPST tQH tQH DMC0_DQxx NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13 AND DMC0_BA0-1. Figure 17. DDR3 SDRAM Controller Input AC Timing Rev. B | Page 75 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DDR3 SDRAM Write Cycle Timing Table 51 and Figure 18 show mobile DDR3 SDRAM output ac timing, related to the DMC. Table 51. DDR3 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.5 V 450 MHz1 Parameter Min Max Unit +0.25 tCK Switching Characteristics tDQSS DMC0_DQS Latching Rising Transitions to Associated Clock Edges2 -0.25 tDS Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns) 0.125 ns tDH DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns) 0.150 ns tDSS DMC0_DQS Falling Edge to Clock Setup Time 0.2 tCK tDSH DMC0_DQS Falling Edge Hold Time From DMC0_CK 0.2 tCK tDQSH DMC0_DQS Input High Pulse Width 0.45 0.55 tCK tDQSL DMC0_DQS Input Low Pulse Width 0.45 0.55 tCK tWPRE Write Preamble 0.9 tCK tWPST Write Postamble 0.3 tCK tIPW Address and Control Output Pulse Width 0.840 ns tDIPW DMC0_DQ and DMC0_DM Output Pulse Width 0.550 ns 1 To ensure proper operation of the DDR3, all the DDR3 requirements must be strictly followed. See "Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors" (EE-387). 2 Write command to first DMC0_DQS delay = WL x tCK + tDQSS. DMC0_CK DMC0_CK tIPW DMC0_Ax DMC0 CONTROL tDSH tDSS tDQSS DMC0_LDQS/DMC0_UDQS DMC0_LDQS/DMC0_UDQS DMC0_DQSn DMC0_DQSn tDQSL tWPRE tDS tDH DMC0_LDM DMC0_UDM DMC0_DQx NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13 AND DMC0_BA0-1. Figure 18. DDR3 SDRAM Controller Output AC Timing Rev. B | Page 76 of 142 | June 2018 tDQSH tDIPW tWPST ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Enhanced Parallel Peripheral Interface (EPPI) Timing Table 52 and Table 53 and Figure 19 through Figure 27 describe enhanced parallel peripheral interface (EPPI) timing operations. In Figure 19 through Figure 27, POLC[1:0] represents the setting of the EPPI_CTL register, which sets the sampling/driving edges of the EPPI clock. When internally generated, the programmed PPI clock (fPCLKPROG) frequency in megahertz is set by the following equation where VALUE is a field in the EPPI_CLKDIV register that can be set from 0 to 65535: f SCLK0 f PCLKPROG = -------------------- VALUE + 1 1 t PCLKPROG = ---------------f PCLKPROG When externally generated, the EPPI_CLK is called fPCLKEXT: 1 t PCLKEXT = -------------f PCLKEXT Table 52. Enhanced Parallel Peripheral Interface (EPPI)--Internal Clock Parameter Min Max Unit Timing Requirements tSFSPI External FS Setup Before EPPI_CLK 6.5 ns tHFSPI External FS Hold After EPPI_CLK 0 ns tSDRPI Receive Data Setup Before EPPI_CLK 6.5 ns tHDRPI Receive Data Hold After EPPI_CLK 0 ns tSFS3GI External FS3 Input Setup Before EPPI_CLK Fall Edge in Clock Gating Mode 14 ns tHFS3GI External FS3 Input Hold Before EPPI_CLK Fall Edge in Clock Gating Mode 0 ns Switching Characteristics 1 tPCLKW EPPI_CLK Width1 0.5 x tPCLKPROG - 1.5 ns tPCLK EPPI_CLK Period1 tPCLKPROG - 1.5 ns tDFSPI Internal FS Delay After EPPI_CLK tHOFSPI Internal FS Hold After EPPI_CLK tDDTPI Transmit Data Delay After EPPI_CLK tHDTPI Transmit Data Hold After EPPI_CLK 3.6 -0.72 3.5 -0.5 See Table 27 for details on the minimum period that can be programmed for tPCLKPROG. Rev. B | Page 77 of 142 | June 2018 ns ns ns ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 FRAME SYNC DRIVEN DATA SAMPLED POLC[1:0] = 10 EPPI_CLK POLC[1:0] = 01 tDFSPI tPCLKW tHOFSPI tPCLK EPPI_FS1/2 tSDRPI tHDRPI EPPI_D00-23 Figure 19. EPPI Internal Clock GP Receive Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN DATA DRIVEN tPCLK POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tDFSPI tPCLKW tHOFSPI EPPI_FS1/2 tHDTPI tDDTPI EPPI_D00-23 Figure 20. EPPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPI tPCLKW tHFSPI tPCLK PPI_FS1/2 tSDRPI tHDRPI PPI_D00-23 Figure 21. EPPI Internal Clock GP Receive Mode with External Frame Sync Timing Rev. B | Page 78 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DATA DRIVEN / FRAME SYNC SAMPLED POLC[1:0] = 11 PPI_CLK POLC[1:0] = 00 tSFSPI tHFSPI tPCLKW tPCLK PPI_FS1/2 tDDTPI tHDTPI PPI_D00-23 Figure 22. EPPI Internal Clock GP Transmit Mode with External Frame Sync Timing EPPI_CLK tHFS3GI tSFS3GI EPPI_FS3 Figure 23. Clock Gating Mode with Internal Clock and External Frame Sync Timing Rev. B | Page 79 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 53. Enhanced Parallel Peripheral Interface (EPPI)--External Clock Parameter Min Max Unit Timing Requirements tPCLKW EPPI_CLK Width1 0.5 x tPCLKEXT - 0.5 ns tPCLK EPPI_CLK Period1 tPCLKEXT - 1 ns tSFSPE External FS Setup Before EPPI_CLK 2 ns tHFSPE External FS Hold After EPPI_CLK 3.7 ns tSDRPE Receive Data Setup Before EPPI_CLK 2 ns tHDRPE Receive Data Hold After EPPI_CLK 3.7 ns Switching Characteristics 1 tDFSPE Internal FS Delay After EPPI_CLK tHOFSPE Internal FS Hold After EPPI_CLK tDDTPE Transmit Data Delay After EPPI_CLK tHDTPE Transmit Data Hold After EPPI_CLK 15.3 2.4 ns ns 15.3 2.4 ns ns This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external EPPI_CLK ideal maximum frequency, see the fPCLKEXT specification in Table 27. FRAME SYNC DRIVEN DATA SAMPLED POLC[1:0] = 10 EPPI_CLK POLC[1:0] = 01 tDFSPE tPCLKW tHOFSPE tPCLK EPPI_FS1/2 tSDRPE tHDRPE EPPI_D00-23 Figure 24. EPPI External Clock GP Receive Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN DATA DRIVEN tPCLK POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tDFSPE tPCLKW tHOFSPE EPPI_FS1/2 tDDTPE tHDTPE EPPI_D00-23 Figure 25. EPPI External Clock GP Transmit Mode with Internal Frame Sync Timing Rev. B | Page 80 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPE tPCLKW tHFSPE tPCLK EPPI_FS1/2 tSDRPE tHDRPE EPPI_D00-23 Figure 26. EPPI External Clock GP Receive Mode with External Frame Sync Timing DATA DRIVEN / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPE tHFSPE tPCLKW tPCLK EPPI_FS1/2 tDDTPE tHDTPE EPPI_D00-23 Figure 27. EPPI External Clock GP Transmit Mode with External Frame Sync Timing Rev. B | Page 81 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Link Ports (LPs) In LP receive mode, the LP clock is supplied externally and is called fLCLKREXT, therefore the period can be represented by 1 t LCLKREXT = --------------f LCLKREXT In LP transmit mode, the programmed LP clock (fLCLKTPROG) frequency in megahertz is set by the following equation where VALUE is a field in the LP_DIV register that can be set from 1 to 255: f SCLK0 f LCLKTPROG = -------------------- VALUE 2 In the case where VALUE = 0, fLCLKTPROG = fSCLK0. For all settings of VALUE, the following equation is true: 1 t LCLKTPROG = -----------------f LCLKTPROG Calculation of the link receiver data setup and hold relative to the link clock is required to determine the maximum allowable skew that can be introduced in the transmission path length difference between LPx_Dx and LPx_CLK. Setup skew is the maximum delay that can be introduced in LPx_Dx relative to LPx_CLK (setup skew = tLCLKTWH minimum - tDLDCH - tSLDCL). Hold skew is the maximum delay that can be introduced in LPx_CLK relative to LPx_Dx (hold skew = tLCLKTWL minimum - tHLDCH - tHLDCL). Table 54. LPs--Receive1 Parameter Min Max Unit 112.5 MHz Timing Requirements fLCLKREXT LPx_CLK Frequency tSLDCL Data Setup Before LPx_CLK Low 0.9 ns tHLDCL Data Hold After LPx_CLK Low 1.4 ns tLCLKEW LPx_CLK Period2 tLCLKREXT - 0.8 ns tLCLKRWL LPx_CLK Width Low2 0.5 x tLCLKREXT ns tLCLKRWH LPx_CLK Width High2 0.5 x tLCLKREXT ns Switching Characteristic tDLALC LPx_ACK Low Delay After LPx_CLK Low3 1.5 x tSCLK0 + 4 1 2.5 x tSCLK0 + 12 ns Specifications apply to LP0 and LP1. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external LPx_CLK ideal maximum frequency, see the fLCLKTEXT specification in Table 27. 3 LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill. Rev. B | Page 82 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 tLCLKEW tLCLKRWH tLCLKRWL LPx_CLK tHLDCL tSLDCL LPx_D7-0 IN tDLALC LPx_ACK (OUT) Figure 28. LPs--Receive Rev. B | Page 83 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 55. LPs--Transmit1 Parameter Min Max Unit Timing Requirements tSLACH LPx_ACK Setup Before LPx_CLK Low 2 x tSCLK0 + 13.5 ns tHLACH LPx_ACK Hold After LPx_CLK Low -5.5 ns Switching Characteristics tDLDCH Data Delay After LPx_CLK High tHLDCH Data Hold After LPx_CLK High -2.3 tLCLKTWL2 LPx_CLK Width Low tLCLKTWH2 tLCLKTW2 tDLACLK 2.23 ns 0.4 x tLCLKTPROG 0.6 x tLCLKTPROG ns LPx_CLK Width High 0.4 x tLCLKTPROG 0.6 x tLCLKTPROG ns LPx_CLK Period N x tLCLKTPROG - 0.6 LPx_CLK Low Delay After LPx_ACK High tSCLK0 + 4 ns ns 2 x tSCLK0 + 1 x tLPCLK + 10 1 Specifications apply to LP0 and LP1. 2 See Table 27 for details on the minimum period that can be programmed for tLCLKTPROG. tLCLKTWH LAST BYTE TRANSMITTED tLCLKTWL FIRST BYTE TRANSMITTED1 LPx_CLK tDLDCH tHLDCH LPx_Dx (DATA) OUT tSLACH tHLACH tDLACLK LPx_ACK (IN) NOTES The tSLACH and tHLACH specifications apply only to the LPx_CLK falling edge. If these specifications are met, LPx_CLK extends and the dotted LPx_CLK falling edge does not occur as shown. The position of the dotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min must be used for tSLACH and tLCLKTWH Max for tHLACH. Figure 29. LPs--Transmit Rev. B | Page 84 of 142 | June 2018 ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Serial Ports (SPORTs) To determine whether a device is compatible with the SPORT at clock speed n, the following specifications must be confirmed: frame sync delay and frame sync setup and hold; data delay and data setup and hold; and serial clock (SPTx_CLK) width. In Figure 30, either the rising edge or the falling edge of SPTx_CLK (external or internal) can be used as the active sampling edge. When externally generated, the SPORT clock is called fSPTCLKEXT: 1 t SPTCLKEXT = ----------------------f SPTCLKEXT When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in megahertz is set by the following equation where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65535: f SCLK0 f SPTCLKPROG = ----------------------- CLKDIV + 1 1 t SPTCLKPROG = -------------------------f SPTCLKPROG Table 56. SPORTs--External Clock1 Parameter Min Max Unit Timing Requirements tSFSE Frame Sync Setup Before SPTx_CLK 2 (Externally Generated Frame Sync in either Transmit or Receive Mode)2 ns tHFSE Frame Sync Hold After SPTx_CLK 2.7 (Externally Generated Frame Sync in either Transmit or Receive Mode)2 ns tSDRE Receive Data Setup Before Receive SPTx_CLK2 ns 2 2 tHDRE Receive Data Hold After SPTx_CLK 2.7 ns tSPTCLKW SPTx_CLK Width3 0.5 x tSPTCLKEXT - 1.5 ns tSPTCLK SPTx_CLK Period3 tSPTCLKEXT - 1.5 ns Switching Characteristics tDFSE Frame Sync Delay After SPTx_CLK (Internally Generated Frame Sync in either Transmit or Receive Mode)4 tHOFSE Frame Sync Hold After SPTx_CLK 2 (Internally Generated Frame Sync in either Transmit or Receive Mode)4 tDDTE Transmit Data Delay After Transmit SPTx_CLK4 tHDTE Transmit Data Hold After Transmit SPTx_CLK4 14.5 ns 14 2 1 ns ns ns Specifications apply to all four SPORTs. Referenced to sample edge. 3 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPTx_CLK. For the external SPTx_CLK ideal maximum frequency see the fSPTCLKEXT specification in Table 27. 4 Referenced to drive edge. 2 Rev. B | Page 85 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 57. SPORTs--Internal Clock1 Parameter Min Max Unit Timing Requirements tSFSI tHFSI tSDRI tHDRI Frame Sync Setup Before SPTx_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)2 12 Frame Sync Hold After SPTx_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)2 -0.5 Receive Data Setup Before SPTx_CLK2 3.4 ns 1.5 ns Receive Data Hold After SPTx_CLK 2 ns ns Switching Characteristics tDFSI Frame Sync Delay After SPTx_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)3 tHOFSI Frame Sync Hold After SPTx_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)3 tDDTI Transmit Data Delay After SPTx_CLK3 3.5 -2.5 ns 3.5 3 ns ns tHDTI Transmit Data Hold After SPTx_CLK -2.5 ns tSPTCLKIW SPTx_CLK Width4 0.5 x tSPTCLKPROG - 2 ns tSPTCLK SPTx_CLK Period4 tSPTCLKPROG - 1.5 ns 1 Specifications apply to all four SPORTs. 2 Referenced to the sample edge. 3 Referenced to drive edge. 4 See Table 27 for details on the minimum period that can be programmed for tSPTCLKPROG. Rev. B | Page 86 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 DATA RECEIVE--INTERNAL CLOCK DRIVE EDGE DATA RECEIVE--EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW SPTx_A/BCLK (SPORT CLOCK) SPTx_A/BCLK (SPORT CLOCK) tDFSI tDFSE tSFSI tHOFSI tHFSI tSFSE tHFSE tSDRE tHDRE tHOFSE SPTx_A/BFS (FRAME SYNC) SPTx_A/BFS (FRAME SYNC) tSDRI tHDRI SPTx_A/BDx (DATA CHANNEL A/B) SPTx_A/BDx (DATA CHANNEL A/B) DATA TRANSMIT--INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT--EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW SPTx_A/BCLK (SPORT CLOCK) SPTx_A/BCLK (SPORT CLOCK) tDFSI tDFSE tHOFSI tSFSI tHFSI tSFSE tHOFSE SPTx_A/BFS (FRAME SYNC) SPTx_A/BFS (FRAME SYNC) tDDTI tDDTE tHDTI tHDTE SPTx_A/BDx (DATA CHANNEL A/B) SPTx_A/BDx (DATA CHANNEL A/B) Figure 30. SPORTs Rev. B | Page 87 of 142 | June 2018 tHFSE ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 58. SPORTs--Enable and Three-State1 Parameter Min Max Unit Switching Characteristics 1 2 tDDTEN Data Enable from External Transmit SPTx_CLK2 tDDTTE Data Disable from External Transmit SPTx_CLK2 1 2 tDDTIN Data Enable from Internal Transmit SPTx_CLK tDDTTI Data Disable from Internal Transmit SPTx_CLK2 ns 14 -2.5 ns 2.8 Specifications apply to all four SPORTs. Referenced to drive edge. DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT CLOCK EXTERNAL) tDDTEN tDDTTE SPTx_A/BDx (DATA CHANNEL A/B) DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT CLOCK INTERNAL) tDDTIN tDDTTI SPTx_A/BDx (DATA CHANNEL A/B) Figure 31. SPORTs--Enable and Three-State Rev. B | Page 88 of 142 | June 2018 ns ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 The SPTx_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPTx_TDV is asserted for communication with external devices. Table 59. SPORTs--Transmit Data Valid (TDV)1 Parameter Min Max Unit Switching Characteristics 1 2 tDRDVEN Data Valid Enable Delay from Drive Edge of External Clock2 tDFDVEN Data Valid Disable Delay from Drive Edge of External Clock2 2 2 tDRDVIN Data Valid Enable Delay from Drive Edge of Internal Clock tDFDVIN Data Valid Disable Delay from Drive Edge of Internal Clock2 -2.5 DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT EXTERNAL CLOCK) tDRDVEN tDFDVEN SPTx_A/BTDV DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT INTERNAL CLOCK) tDRDVIN tDFDVIN SPTx_A/BTDV Figure 32. SPORTs--Transmit Data Valid Internal and External Clock | Page 89 of 142 | June 2018 ns ns 3.5 Specifications apply to all four SPORTs. Referenced to drive edge. Rev. B ns 14 ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 60. SPORTs--External Late Frame Sync1 Parameter Min Max Unit 14 ns Switching Characteristics tDDTLFSE Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 02 tDDTENFS Data Enable for MCE = 1, MFD = 02 0.5 ns 1 Specifications apply to all four SPORTs. 2 The tDDTLFSE and tDDTENFS parameters apply to left justified as well as standard serial mode and MCE = 1, MFD = 0. DRIVE SAMPLE DRIVE SPTx_A/BCLK (SPORT CLOCK) tHFSE/I tSFSE/I SPTx_A/BFS (FRAME SYNC) tDDTE/I tDDTENFS tHDTE/I SPTx_A/BDx (DATA CHANNEL A/B) 1ST BIT 2ND BIT tDDTLFSE Figure 33. External Late Frame Sync Rev. B | Page 90 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Asynchronous Sample Rate Converter (ASRC)--Serial Input Port The ASRC input signals are routed from the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided in Table 61 are valid at the DAI0_PINx pins. Table 61. ASRC, Serial Input Port Parameter Min Max Unit Timing Requirements tSRCSFS1 1 1 Frame Sync Setup Before Serial Clock Rising Edge 4 ns tSRCHFS Frame Sync Hold After Serial Clock Rising Edge 5.5 ns tSRCSD1 Data Setup Before Serial Clock Rising Edge 4 ns tSRCHD1 Data Hold After Serial Clock Rising Edge 5.5 ns tSRCCLKW Clock Width tSCLK0 - 1 ns tSRCCLK Clock Period 2 x tSCLK0 ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the PCG can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAI0_PIN20-1 (SCLK) tSRCSFS tSRCHFS DAI0_PIN20-1 (FS) tSRCSD tSRCHD DAI0_PIN20-1 (SDATA) Figure 34. ASRC Serial Input Port Timing Rev. B | Page 91 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Asynchronous Sample Rate Converter (ASRC)--Serial Output Port For the serial output port, the frame sync is an input and it must meet setup and hold times with regard to SCLK on the output port. The serial data output has a hold time and delay specification with regard to serial clock. The serial clock rising edge is the sampling edge, and the falling edge is the drive edge. Table 62. ASRC, Serial Output Port Parameter Min Max Unit Timing Requirements tSRCSFS1 Frame Sync Setup Before Serial Clock Rising Edge 4 tSRCHFS Frame Sync Hold After Serial Clock Rising Edge 5.5 ns tSRCCLKW Clock Width tSCLK0 - 1 ns tSRCCLK Clock Period 2 x tSCLK0 ns 1 ns Switching Characteristics 1 tSRCTDD1 Transmit Data Delay After Serial Clock Falling Edge tSRCTDH1 Transmit Data Hold After Serial Clock Falling Edge 13 1 ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the PCG can be either CLKIN, SCLK0, or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAI0_PIN20-1 (SCLK) tSRCSFS tSRCHFS DAI0_PIN20-1 (FS) tSRCTDD tSRCTDH DAI0_PIN20-1 (SDATA) Figure 35. ASRC Serial Output Port Timing Rev. B | Page 92 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPI Port--Master Timing SPI0, SPI1, and SPI2 Table 63, Table 64, and Figure 36 describe the SPI port master operations. When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation where BAUD is a field in the SPIx_CLK register that can be set from 0 to 65535. For SPI0, SPI1, f SCLK0 f SPICLKPROG = --------------------- BAUD + 1 For SPI2, f SCLK1 f SPICLKPROG = --------------------- BAUD + 1 1 t SPICLKPROG = -------------------------f SPICLKPROG Note that * In dual-mode data transmit, the SPIx_MISO signal is also an output. * In quad-mode data transmit, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also outputs. * In dual-mode data receive, the SPIx_MOSI signal is also an input. * In quad-mode data receive, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also inputs. * Quad-mode is supported by SPI2 only. * CPHA is a configuration bit in the SPI_CTL register. Table 63. SPI0, SPI1 Port--Master Timing1 Parameter Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SPIx_CLK Edge (Data Input Setup) 3 ns tHSPIDM SPIx_CLK Sampling Edge to Data Input Invalid 1.2 ns tSPICLKPROG - 5 ns 1.5 x tSPICLKPROG - 5 ns 0.5 x tSPICLKPROG - 1.5 ns Switching Characteristics tSDSCIM SPIx_SEL low to First SPI_CLK Edge for CPHA = 12 SPIx_SEL low to First SPI_CLK Edge for CPHA = 0 tSPICHM 2 SPIx_CLK High Period3 3 tSPICLM SPIx_CLK Low Period 0.5 x tSPICLKPROG - 1.8 ns tSPICLK SPIx_CLK Period3 tSPICLKPROG - 1.5 ns tHDSM Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 12 1.5 x tSPICLKPROG - 5 ns Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 02 tSPICLKPROG - 5 ns tSPITDM Sequential Transfer Delay2, 4 tSPICLKPROG - 1.5 tDDSPIDM SPIx_CLK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SPIx_CLK Edge to Data Out Invalid (Data Out Hold) -3.75 1 All specifications apply to SPI0 and SPI1 only. 2 Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1. 3 See Table 27 for details on the minimum period that can be programmed for tSPICLKPROG. 4 Applies to sequential mode with STOP 1. Rev. B | Page 93 of 142 ns 2.7 | June 2018 ns ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 64. SPI2 Port--Master Timing1 Parameter Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SPIx_CLK Edge (Data Input Setup) 2.7 ns tHSPIDM SPIx_CLK Sampling Edge to Data Input Invalid 0.75 ns tSPICLKPROG - 5 ns Switching Characteristics SPIx_SEL low to First SPI_CLK Edge for CPHA = 12 tSDSCIM SPIx_SEL low to First SPI_CLK Edge for CPHA = 0 2 1.5 x tSPICLKPROG - 5 ns tSPICHM SPIx_CLK High Period3 0.5 x tSPICLKPROG - 1.5 ns tSPICLM SPIx_CLK Low Period3 0.5 x tSPICLKPROG - 1.5 ns tSPICLK SPIx_CLK Period3 tSPICLKPROG - 1.5 ns Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 1 1.5 x tSPICLKPROG - 5 ns Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 02 tSPICLKPROG - 5 ns 2 tHDSM 2, 4 tSPITDM Sequential Transfer Delay tDDSPIDM SPIx_CLK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SPIx_CLK Edge to Data Out Invalid (Data Out Hold) tSPICLKPROG - 1.5 ns 3.17 ns -2.4 ns 1 All specifications apply to SPI2 only. 2 Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1. 3 See Table 27 for details on the minimum period that may be programmed for tSPICLKPROG. 4 Applies to sequential mode with STOP 1. SPIx_SEL (OUTPUT) tSDSCIM tSPICLM tSPICHM tSPICLK tHDSM SPIx_CLK (OUTPUT) tDDSPIDM tHDSPIDM DATA OUTPUTS (SPIx_MOSI) tSSPIDM CPHA = 1 tHSPIDM DATA INPUTS (SPIx_MISO) tDDSPIDM tHDSPIDM DATA OUTPUTS (SPIx_MOSI) CPHA = 0 tSSPIDM tHSPIDM DATA INPUTS (SPIx_MISO) Figure 36. SPI Port--Master Timing Rev. B | Page 94 of 142 | June 2018 tSPITDM ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPI Port--Slave Timing SPI0, SPI1, and SPI2 Table 65, Table 66, and Figure 37 describe SPI port slave operations. Note that * In dual-mode data transmit, the SPIx_MOSI signal is also an output. * In quad-mode data transmit, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also outputs. * In dual-mode data receive, the SPIx_MISO signal is also an input. * In quad-mode data receive, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also inputs. * In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT: 1 t SPICLKEXT = ----------------------f SPICLKEXT * Quad mode is supported by SPI2 only. * CPHA is a configuration bit in the SPI_CTL register. Table 65. SPI0, SPI1 Port--Slave Timing1 Parameter Min Max Unit Timing Requirements tSPICHS SPIx_CLK High Period2 0.5 x tSPICLKEXT - 1.5 ns tSPICLS SPIx_CLK Low Period2 0.5 x tSPICLKEXT - 1.5 ns tSPICLKEXT - 1.5 ns 5 ns 2 tSPICLK SPIx_CLK Period tHDS Last SPIx_CLK Edge to SPIx_SS Not Asserted tSPITDS Sequential Transfer Delay tSPICLKEXT - 1.5 ns tSDSCI SPIx_SS Assertion to First SPIx_CLK Edge 11.7 ns tSSPID Data Input Valid to SPIx_CLK Edge (Data Input Setup) 2 ns tHSPID SPIx_CLK Sampling Edge to Data Input Invalid 1.6 ns Switching Characteristics tDSOE SPIx_SS Assertion to Data Out Active 0 tDSDHI SPIx_SS Deassertion to Data High Impedance 0 tDDSPID SPIx_CLK Edge to Data Out Valid (Data Out Delay) tHDSPID SPIx_CLK Edge to Data Out Invalid (Data Out Hold) 1.5 1 14.12 ns 12.6 ns 14.16 ns ns All specifications apply to SPI0 and SPI1. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 27. Rev. B | Page 95 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 66. SPI2 Port--Slave Timing1 Parameter Min Max Unit Timing Requirements tSPICHS SPIx_CLK High Period2 0.5 x tSPICLKEXT - 1.5 ns tSPICLS SPIx_CLK Low Period2 0.5 x tSPICLKEXT - 1.5 ns tSPICLKEXT - 1.5 ns 5 ns 2 tSPICLK SPIx_CLK Period tHDS Last SPIx_CLK Edge to SPIx_SS Not Asserted tSPITDS Sequential Transfer Delay tSPICLKEXT - 1.5 ns tSDSCI SPIx_SS Assertion to First SPIx_CLK Edge 10.5 ns tSSPID Data Input Valid to SPIx_CLK Edge (Data Input Setup) 2 ns tHSPID SPIx_CLK Sampling Edge to Data Input Invalid 1.6 ns Switching Characteristics tDSOE SPIx_SS Assertion to Data Out Active 0 tDSDHI SPIx_SS Deassertion to Data High Impedance 0 tDDSPID SPIx_CLK Edge to Data Out Valid (Data Out Delay) tHDSPID SPIx_CLK Edge to Data Out Invalid (Data Out Hold) 14 ns 11.5 ns 14 ns 1.5 ns 1 All specifications apply to SPI2 only. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 27. SPIx_SS (INPUT) tSDSCI tSPICLS tSPICHS tHDS tSPICLK SPIx_CLK (INPUT) tDSOE tDDSPID tDDSPID tHDSPID tDSDHI DATA OUTPUTS (SPIx_MISO) CPHA = 1 tSSPID tHSPID DATA INPUTS (SPIx_MOSI) tDSOE tHDSPID tDDSPID tDSDHI DATA OUTPUTS (SPIx_MISO) tHSPID CPHA = 0 tSSPID DATA INPUTS (SPIx_MOSI) Figure 37. SPI Port--Slave Timing Rev. B | Page 96 of 142 | June 2018 tSPITDS ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPI Port--SPIx_RDY Slave Timing SPIx_RDY provides flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register. Table 67. SPI Port--SPIx_RDY Slave Timing1 Parameter Conditions Min Max Unit FCCH = 0 3 x tSCLK1 4 x tSCLK1 + 10 ns FCCH = 1 4 x tSCLK1 5 x tSCLK1 + 10 ns Switching Characteristic tDSPISCKRDYS SPIx_RDY Deassertion from Last Valid Input SPIx_CLK Edge 1 All specifications apply to all three SPIs. tDSPISCKRDYS SPIx_CLK (CPOL = 0) CPHA = 0 SPIx_CLK (CPOL = 1) SPIx_CLK (CPOL = 0) CPHA = 1 SPIx_CLK (CPOL = 1) SPIx_RDY (O) Figure 38. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode Rev. B | Page 97 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPI Port--Open Drain Mode (ODM) Timing In Figure 39 and Figure 40, the outputs can be SPIx_MOSI, SPIx_MISO, SPIx_D2, and/or SPIx_D3, depending on the mode of operation. CPOL and CPHA are configuration bits in the SPI_CTL register. Table 68. SPI Port--ODM Master Mode Timing1 Parameter Min Max Unit Switching Characteristics 1 tHDSPIODMM SPIx_CLK Edge to High Impedance from Data Out Valid -1.1 tDDSPIODMM SPIx_CLK Edge to Data Out Valid from High Impedance -1 ns 6 ns Max Unit All specifications apply to all three SPIs. tHDSPIODMM tHDSPIODMM SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMM tDDSPIODMM Figure 39. ODM Master Mode Table 69. SPI Port--ODM Slave Mode1 Parameter Min Timing Requirements 1 tHDSPIODMS SPIx_CLK Edge to High Impedance from Data Out Valid tDDSPIODMS SPIx_CLK Edge to Data Out Valid from High Impedance 0 ns 11 All specifications apply to all three SPIs. tHDSPIODMS tHDSPIODMS SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMS tDDSPIODMS Figure 40. ODM Slave Mode Rev. B | Page 98 of 142 | June 2018 ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPI Port--SPIx_RDY Master Timing SPIx_RDY is used to provide flow control. CPOL and CPHA are configuration bits in the SPIx_CTL register, while LEADX, LAGX, and STOP are configuration bits in the SPIx_DLY register. Table 70. SPI Port--SPIx_RDY Master Timing1 Parameter Conditions Min Max Unit Timing Requirement tSRDYSCKM (2 + 2 x BAUD2) x tSCLK1 + 10 Setup Time for SPIx_RDY Deassertion Before Last Valid Data SPIx_CLK Edge ns Switching Characteristic tDRDYSCKM3 Assertion of SPIx_RDY to First SPIx_CLK BAUD = 0, CPHA = 0 4.5 x tSCLK1 Edge of Next Transfer BAUD = 0, CPHA = 1 4 x tSCLK1 2 5.5 x tSCLK1 + 10 ns 5 x tSCLK1 + 10 ns 2 BAUD > 0, CPHA = 0 (1 + 1.5 x BAUD ) x tSCLK1 (2 + 2.5 x BAUD ) x tSCLK1 + 10 ns BAUD > 0, CPHA = 1 (1 + 1 x BAUD2) x tSCLK1 (2 + 2 x BAUD2) x tSCLK1 + 10 ns 1 All specifications apply to all three SPIs. BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1. 3 Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero. 2 tSRDYSCKM SPIx_RDY SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) Figure 41. SPIx_RDY Setup Before SPIx_CLK Rev. B | Page 99 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 tDRDYSCKM SPIx_RDY SPIx_CLK (CPOL = 0) CPHA = 0 SPIx_CLK (CPOL = 1) SPIx_CLK (CPOL = 0) CPHA = 1 SPIx_CLK (CPOL = 1) Figure 42. SPIx_CLK Switching Diagram after SPIx_RDY Assertion Rev. B | Page 100 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Precision Clock Generator (PCG) (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes inputs directly from the DAI pins (via pin buffers) and sends outputs directly to the DAI pins. For the other cases, where the PCG inputs and outputs are not directly routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI0_PINx). Table 71. PCG (Direct Pin Routing) Parameter Min Max Unit Timing Requirements tPCGIP Input Clock Period tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input 4.5 Clock ns tHTRIG PCG Trigger Hold After Falling Edge of PCG Input Clock ns tSCLK x 2 ns 3 Switching Characteristics tDPCGIO tDTRIGCLK tDTRIGFS 1 tPCGOW2 1 2 PCG Output Clock and Frame Sync Active Edge Delay 2.5 After PCG Input Clock 13.5 ns PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 x tPCGIP) 13.5 + (2.5 x tPCGIP) ns PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D - PH) x tPCGIP) 13.5 + ((2.5 + D - PH) x tPCGIP) ns Output Clock Period 2 x tPCGIP - 1 ns D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference. Normal mode of operation. tSTRIG tHTRIG DAI0_PIN20-1 PCG_TRIGx_I DAI0_PIN20-1 PCG_EXTx_I (CLKIN) tPCGIP tDPCGIO DAI0_PIN20-1 PCG_CLKx_O tDTRIGCLK tDPCGIO DAI0_PIN20-1 PCG_FSx_O tDTRIGFS Figure 43. PCG (Direct Pin Routing) Rev. B | Page 101 of 142 | June 2018 tPCGOW ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 General-Purpose IO Port Timing Table 72 and Figure 44 describe I/O timing, related to the general-purpose ports (PORT). Table 72. General-Purpose Port Timing Parameter Min Max Unit Timing Requirement tWFI General-Purpose Port Pin Input Pulse Width 2 x tSCLK0 - 1.5 ns tWFI GPIO INPUT Figure 44. General-Purpose Port Timing General-Purpose I/O Timer Cycle Timing Table 73, Table 74, and Figure 45 describe timer expired operations related to the general-purpose timer (TIMER). The input signal is asynchronous in Width Capture Mode and External Clock Mode and has an absolute maximum input frequency of fSCLK/4 MHz. The Width Value value is the timer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 - 1. When externally generated, the TMx_CLK clock is called fTMRCLKEXT: 1 t TMRCLKEXT = ------------------------f TMRCLKEXT Table 73. Timer Cycle Timing--Internal Mode Parameter Timing Requirements Timer Pulse Width Input Low (Measured In SCLK Cycles)1 tWL Timer Pulse Width Input High (Measured In SCLK Cycles)1 tWH Switching Characteristic Timer Pulse Width Output (Measured In SCLK Cycles)2 tHTO Min Max 2 x tSCLK 2 x tSCLK tSCLK x WIDTH - 1.5 Unit ns ns tSCLK x WIDTH + 1.5 ns 1 The minimum pulse width applies for timer signals in width capture and external clock modes. 2 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 2 to 232 - 1). Table 74. Timer Cycle Timing--External Mode Parameter Timing Requirements Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1 tWL Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1 tWH Timer External Clock Period2 tEXT_CLK Switching Characteristic Timer Pulse Width Output (Measured In EXT_CLK Cycles)3 tHTO Min Max 2 x tEXT_CLK 2 x tEXT_CLK tTMRCLKEXT tEXT_CLK x WIDTH - 1.5 1 Unit ns ns ns tEXT_CLK x WIDTH + 1.5 ns The minimum pulse width applies for timer signals in width capture and external clock modes. This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external TMR_CLK maximum frequency, see the fTMRCLKEXT specification in Table 27. 3 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 - 1). 2 Rev. B | Page 102 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 TMR OUTPUT tHTO TMR INPUT tWH, tWL Figure 45. Timer Cycle Timing DAI0 Pin to DAI0 Pin Direct Routing Table 75 and Figure 46 describe I/O timing related to the DAI for direct pin connections only (for example, DAI0_PB01_I to DAI0_PB02_O). Table 75. DAI Pin to DAI Pin Routing Parameter Switching Characteristic Delay DAI Pin Input Valid to DAI Output Valid tDPIO Min Max Unit 1.5 12 ns DAI0_Pn tDPIO DAI0_Pm Figure 46. DAI Pin to DAI Pin Direct Routing Up/Down Counter/Rotary Encoder Timing Table 76 and Figure 47 describe timing, related to the general-purpose counter (CNT). Table 76. Up/Down Counter/Rotary Encoder Timing Parameter Min Max Unit Timing Requirement tWCOUNT Up/Down Counter/Rotary Encoder Input Pulse Width CNT0_UD CNT0_DG CNT0_ZM tWCOUNT Figure 47. Up/Down Counter/Rotary Encoder Timing Rev. B | Page 103 of 142 | June 2018 2 x tSCLK0 ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADC Controller Module (ACM) Timing Table 77 and Figure 48 describe ACM operations. When internally generated, the programmed ACM clock (fACLKPROG) frequency in megahertz is set by the following equation where CKDIV is a field in the ACM_TC0 register and ranges from 1 to 255: f SCLK1 f ACLKPROG = -----------------CKDIV + 1 1 t ACLKPROG = ----------------f ACLKPROG Setup cycles (SC) in Table 77 is also a field in the ACM_TC0 register and ranges from 0 to 4095. Hold Cycles (HC) is a field in the ACM_TC1 register that ranges from 0 to 15. Table 77. ACM Timing Parameter Min Max Unit Timing Requirements tSDR SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK 3.4 ns tHDR SPORT DRxPRI/DRxSEC Hold After ACMx_CLK 1.5 ns Switching Characteristics 1 tSCTLCS ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS (SC + 1) x tSCLK1 - 4.88 ns tHCTLCS ACM Control (ACMx_A[4:0]) Hold After Deassertion of CS HC x tACLKPROG - 1 ns tACLKW ACM Clock Pulse Width tACLK ACM Clock Period1 tHCSACLK tSCSACLK 1 (0.5 x tACLKPROG) - 1.6 ns tACLKPROG - 1.5 ns CS Hold to ACMx_CLK Edge -2.5 ns CS Setup to ACMx_CLK Edge tACLKPROG - 3.5 ns See Table 27 for details on the minimum period that can be programmed for tACLKPROG. DAIx_PIN20-1 (ACM0_FS/CS) CSPOL = 1/0 tSCSACLK DAIx_PIN20-1 (ACM_CLK) CLKPOL = 1/0 tACLK tACLKW tHCSACLK DAIx_PIN20-1 (ACM_A0-4) tSDR t SCTLCS DAIx_PIN20-1 (ACM0_T0) Figure 48. ACM Timing Rev. B | Page 104 of 142 | June 2018 tHDR t HCTLCS ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Universal Asynchronous Receiver-Transmitter (UART) Ports--Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference. Controller Area Network (CAN) Interface The CAN interface timing is described in the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference. Universal Serial Bus (USB) Table 78 describes the universal serial bus (USB) clock timing. Refer to the USB 2.0 Specification for timing and dc specifications for USB pins (including output characteristics for driver types E, F, and G listed in the ADSP-SC57x/ADSP-2157x Designer Quick Reference). Table 78. USB Clock Timing1 Parameter Min Max Unit Timing Requirements 1 fUSBS USB_CLKIN Frequency 24 24 MHz fsUSB USB_CLKIN Clock Frequency Stability -50 +50 ppm This specification is supported by USB0. Rev. B | Page 105 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 10/100 EMAC Timing Table 79 through Table 83 and Figure 49 through Figure 53 describe the MII and RMII EMAC operations. Table 79. 10/100 EMAC Timing: MII Receive Signal VDDEXT 3.3V Nominal Parameter1 Min Max Unit None 25 + 1% MHz Timing Requirements tERXCLKF ETH0_RXCLK_REFCLK Frequency (fSCLK = SCLK Frequency) tERXCLKW ETH0_RXCLK_REFCLK Width (tERxCLK = ETH0_RXCLK_REFCLK Period) tERxCLK x 35% tERXCLKIS Rx Input Valid to ETH0_RXCLK_REFCLK Rising Edge (Data In Setup) 1.75 ns tERXCLKIH ETH0_RXCLK_REFCLK Rising Edge to Rx Input Invalid (Data In Hold) 1.5 ns 1 tERxCLK x 65% ns MII inputs synchronous to ETH0_RXCLK_REFCLK are ETH0_RXD3-0, ETH0_RXCTL_RXDV, and ETH0_RXERR. tERXCLK tERXCLKW ETH0_RXCLK_REFCLK ETH0_RXD3-0 ETH0_RXCTL_RXDV ETH0_RXERR tERXCLKIS tERXCLKIH Figure 49. 10/100 EMAC Timing: MII Receive Signal Table 80. 10/100 EMAC Timing: MII Transmit Signal VDDEXT 3.3V Nominal 1 Parameter Min Max Unit Timing Requirements tETXCLKF ETH0_TXCLK Frequency (fSCLK = SCLK Frequency) None 25 + 1% MHz tETXCLKW ETH0_TXCLK Width (tETxCLK = ETH0_TXCLK Period) tETxCLK x 35% tETxCLK x 65% ns 11.4 ns Switching Characteristics tETXCLKOV ETH0_TXCLK Rising Edge to Tx Output Valid (Data Out Valid) tETXCLKOH ETH0_TXCLK Rising Edge to Tx Output Invalid (Data Out Hold) 1 MII outputs synchronous to ETH0_TXCLK are ETH0_TXD3-0. tETXCLK tETXCLKW ETH0_TXCLK tETXCLKOH ETH0_TXD3-0 ETH0_TXCTL_TXEN tETXCLKOV Figure 50. 10/100 EMAC Timing: MII Transmit Signal Rev. B | Page 106 of 142 | June 2018 2 ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 81. 10/100 EMAC Timing--RMII Receive Signal Parameter1 Min Max Unit Timing Requirements 1 tREFCLKF ETH0_RXCLK_REFCLK Frequency (fSCLK0 = SCLK0 Frequency) None 50 + 1% MHz tREFCLKW ETH0_RXCLK_REFCLK Width (tREFCLKF = ETH0_RXCLK_REFCLK Period) tREFCLK x 35% tREFCLK x 65% ns tREFCLKIS Rx Input Valid to RMII ETH0_RXCLK_REFCLK Rising Edge (Data In Setup) 1.75 ns tREFCLKIH RMII ETH0_RXCLK_REFCLK Rising Edge to Rx Input Invalid (Data In Hold) 1.6 ns RMII inputs synchronous to RMII ETH0_RXCLK_REFCLK are ETH0_RXD1-0, RMII ETH0_RXCTL_RXDV, and ETH0_RXERR. tREFCLKF ETH0_RXCLK_REFCLK tREFCLKW tREFCLKW ETH0_RXD1-0 ETH0_RXCTL_RXDV tREFCLKIS tREFCLKIH Figure 51. 10/100 EMAC Controller Timing--RMII Receive Signal Table 82. 10/100 EMAC Timing--RMII Transmit Signal Parameter1 Min Max Unit 11.9 ns Switching Characteristics 1 tREFCLKOV RMII ETH0_RXCLK_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid) tREFCLKOH RMII ETH0_RXCLK_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold) 2 RMII outputs synchronous to RMII ETH0_RXCLK_REFCLK are ETH0_TXD1-0. tREFCLK ETH0_RXCLK_REFCLK tREFCLKOH ETH0_TXD1-0 ETH0_TXEN tREFCLKOV Figure 52. 10/100 EMAC Controller Timing--RMII Transmit Signal Rev. B | Page 107 of 142 | June 2018 ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 83. 10/100/1000 EMAC Timing--RMII and RGMII Station Management Parameter1 Min Max Unit Timing Requirements tMDIOS ETH0_MDIO Input Valid to ETH0_MDC Rising Edge (Setup) 12.6 ns tMDCIH ETH0_MDC Rising Edge to ETH0_MDIO Input Invalid (Hold) 0 ns Switching Characteristics 1 tMDCOV ETH0_MDC Falling Edge to ETH0_MDIO Output Valid tMDCOH ETH0_MDC Falling Edge to ETH0_MDIO Output Invalid (Hold) tSCLK0 + 2 tSCLK0 -2.9 ns ns ETH0_MDC/ETH0_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETH0_MDC is an output clock with a minimum period that is programmable as a multiple of the system clock SCLK0. ETH0_MDIO is a bidirectional data line. ETH0_MDC (OUTPUT) tMDCOH ETH0_MDIO (OUTPUT) tMDCOV ETH0_MDIO (INPUT) tMDIOS tMDCIH Figure 53. 10/100 /1000 Ethernet MAC Controller Timing--RMII and RGMII Station Management Rev. B | Page 108 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 10/100/1000 EMAC Timing Table 84 and Figure 54 describe the RGMII EMAC timing. Table 84. 10/100/1000 EMAC Timing--RGMII Receive and Transmit Signals Parameter Min Max Unit Timing Requirements tSETUPR Data to Clock Input Setup at Receiver 1 ns tHOLDR Data to Clock Input Hold at Receiver 1 ns tGREFCLKF RGMII Receive Clock Period 8 ns tGREFCLKW RGMII Receive Clock Pulse Width 4 ns Switching Characteristics tSKEWT Data to Clock Output Skew at Transmitter -0.5 +0.5 ns tCYC Clock Cycle Duration 7.2 8.8 ns tDUTY_G Duty Cycle for RGMII Minimum tGREFCLKF x 45% tGREFCLKF x 55% ns ETH0_TXCLK (AT TRANSMITTER) tSKEWT tDUTY_G tCYC tDUTY_G ETH0_TXD3-0 ETH0_TXCTL_TXEN ETH0_RXCLK_REFCLK (AT RECEIVER) tGREFCLKW tSETUPR tGREFCLKW tHOLDR ETH0_RXD3-0 ETH0_RXCTL_CRS Figure 54. EMAC Timing--RGMII Rev. B | Page 109 of 142 | June 2018 tGREFCLKF ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Sony/Philips Digital Interface (S/PDIF) Transmitter Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. S/PDIF Transmitter Serial Input Waveforms Figure 55 and Table 85 show the right justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right justified to the next frame sync transition. Table 85. S/PDIF Transmitter Right Justified Mode Parameter Timing Requirement Frame Sync to MSB Delay in Right Justified Mode tRJD Conditions Nominal Unit 16-bit word mode 18-bit word mode 20-bit word mode 24-bit word mode 16 14 12 8 SCLK SCLK SCLK SCLK LEFT/RIGHT CHANNEL DAI_P20-1 FS DAI_P20-1 SCLK tRJD DAI_P20-1 SDATA LSB MSB MSB-1 MSB-2 Figure 55. Right Justified Mode Rev. B | Page 110 of 142 | June 2018 LSB+2 LSB+1 LSB ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Figure 56 and Table 86 show the default I2S justified mode. The frame sync is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left justified to the frame sync transition but with a delay. Table 86. S/PDIF Transmitter I2S Mode Parameter Timing Requirement tI2SD Frame Sync to MSB Delay in I2S Mode Nominal Unit 1 SCLK LEFT/RIGHT CHANNEL DAI_P20-1 (FS) DAI_P20-1 (SCLK) tI2SD DAI_P20-1 (SDATA) MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB Figure 56. I2S Justified Mode Figure 57 and Table 87 show the left justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left justified to the frame sync transition with no delay. Table 87. S/PDIF Transmitter Left Justified Mode Parameter Timing Requirement tLJD Frame Sync to MSB Delay in Left Justified Mode DAI_P20-1 (FS) LEFT/RIGHT CHANNEL DAI_P20-1 ((SCLK) tLJD DAI_P20-1 (SDATA) MSB MSB-1 MSB-2 LSB+2 LSB+1 Figure 57. Left Justified Mode Rev. B | Page 111 of 142 | June 2018 LSB Nominal Unit 0 SCLK ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 88. Input signals are routed to the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI0_PINx pins. Table 88. S/PDIF Transmitter Input Data Timing Parameter Min Max Unit Timing Requirements tSISFS1 1 1 Frame Sync Setup Before Serial Clock Rising Edge 3 ns tSIHFS Frame Sync Hold After Serial Clock Rising Edge 3 ns tSISD1 Data Setup Before Serial Clock Rising Edge 3 ns tSIHD1 Data Hold After Serial Clock Rising Edge 3 ns tSITXCLKW Transmit Clock Width 9 ns tSITXCLK Transmit Clock Period 20 ns tSISCLKW Clock Width 36 ns tSISCLK Clock Period 80 ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the PCG can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSITXCLKW tSITXCLK DAI0_PIN20-1 (TxCLK) tSISCLK tSISCLKW DAI0_PIN20-1 (SCLK) tSISFS tSIHFS DAI0_PIN20-1 (FS) tSISD tSIHD DAI0_PIN20-1 (SDATA) Figure 58. S/PDIF Transmitter Input Timing Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the internal biphase clock. Table 89. Oversampling Clock (TxCLK) Switching Characteristics Parameter Switching Characteristics Frequency for TxCLK = 384 x Frame Sync fTXCLK_384 Frequency for TxCLK = 256 x Frame Sync fTXCLK_256 Frame Rate (FS) fFS Rev. B Max Unit Oversampling ratio x frame sync 1/tSITXCLK 49.2 192.0 MHz MHz kHz | Page 112 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital PLL mode, the internal digital PLL generates the 512 x FS clock. Table 90. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Min Max Unit 5 ns Switching Characteristics tDFSI Frame Sync Delay After Serial Clock tHOFSI Frame Sync Hold After Serial Clock tDDTI Transmit Data Delay After Serial Clock tHDTI Transmit Data Hold After Serial Clock DRIVE EDGE -2 5 -2 SAMPLE EDGE DAI0_PIN20-1 (SCLK) tDFSI tHOFSI DAI0_PIN20-1 (FS) tDDTI tHDTI DAI0_PIN20-1 (DATA CHANNEL A/B) Figure 59. S/PDIF Receiver Internal Digital PLL Mode Timing Rev. B | Page 113 of 142 ns | June 2018 ns ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 MediaLB (MLB) All the numbers shown in Table 91 are applicable for all MLB speed modes (1024 FS, 512 FS, and 256 FS) for the 3-pin protocol, unless otherwise specified. Refer to the Media Local Bus Specification version 4.2 for more details. Table 91. 3-Pin MLB Interface Specifications Parameter tMLBCLK tMCKL tMCKH tMCKR tMCKF tMPWV1 tDSMCF tDHMCF tMCFDZ tMCDRV tMDZH2 CMLB 1 2 Min MLB Clock Period 1024 FS 512 FS 256 FS MLBCLK Low Time 1024 FS 512 FS 256 FS MLBCLK High Time 1024 FS 512 FS 256 FS MLBCLK Rise Time (VIL to VIH) 1024 FS 512 FS/256 FS MLBCLK Fall Time (VIH to VIL) 1024 FS 512 FS/256 FS MLBCLK Pulse Width Variation 1024 FS 512 FS/256 DAT/SIG Input Setup Time DAT/SIG Input Hold Time DAT/SIG Output Time to Three-State DAT/SIG Output Data Delay From MLBCLK Rising Edge Bus Hold Time 1024 FS 512 FS/256 DAT/SIG Pin Load 1024 FS 512 FS/256 Typ Max 20.3 40 81 Unit ns ns ns 6.1 14 30 ns ns ns 9.3 14 30 ns ns ns 1 2 0 1 3 ns ns 1 3 ns ns 0.7 2.0 nspp nspp 15 8 ns ns ns ns 2 4 ns ns 40 60 pf pf Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak. Board designs must ensure the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Rev. B | Page 114 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 MLB_SIG/ MLB_DAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLB_CLK tMCKR tMCKL tMCKF tMLBCLK tMCFDZ tMCDRV tMDZH MLB_SIG/ MLB_DAT (Tx, Output) VALID Figure 60. MLB Timing (3-Pin Interface) The ac timing specifications of the 6-pin MLB interface is detailed in Table 92. Refer to the Media Local Bus Specification version 4.2 for more details. Table 92. 6-Pin MLB Interface Specifications Parameter Differential Transition Time at the Input Pin (See Figure 61) tMT 2 MLBCP/N External Clock Operating Frequency (See Figure 62)1 Min Typ Max 1 0.6 102.4 5 Disable Turnaround Time From Transition of MLBCP/N (Low to High) fMCKR = 2048 x FS (See Figure 64) 0.6 7 ns tPLZ Enable Turnaround Time From Transition of MLBCP/N (Low to High) (See Figure 64) fMCKR = 2048 x FS 0.6 11.2 ns tSU MLBSP/N (MLBDP/N) Valid to Transition of MLBCP/N (Low to High) (See Figure 63) fMCKR = 2048 x FS 1 ns tHD MLBSP/N (MLBDP/N) Hold From Transition of MLBCP/N (Low to High) (See Figure 63)2 0.6 ns fMCKR Recovered Clock Operating Frequency (Internal, Not Observable at Pins, Only for Timing References) (See Figure 62) tDELAY Transmitter MLBSP/N (MLBDP/N) Output Valid From Transition of MLBCP/N (Low to High) (See Figure 63) tPHZ 90.112 Unit ns MHz MHz MHz MHz ns fMCKE 1 Conditions 20% to 80% VIN+/VIN- 80% to 20% VIN+/VIN- 2048 x FS at 44.0 kHz 2048 x FS at 50.0 kHz 2048 x FS at 44.0 kHz 2048 x FS at 50.0 kHz fMCKR = 2048 x FS 102.4 90.112 fMCKE (maximum) and fMCKR (maximum) include maximum cycle to cycle system jitter (tJITTER) of 600 ps for a bit error rate of 10E-9. Receivers must latch MLBSP/N (MLBDP/N) data within tHD (minimum) of the rising edge of MLBCP/N. Rev. B | Page 115 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 MLBCP/N MLBDP/N MLBSP/N tMT tMT 80% 20% Figure 61. MLB 6-Pin Transition Time MLBCP/N 1/fMCKE RECOVERED CLOCK (1:1) RECOVERED CLOCK (2:1) T1:1 T2:1 T2:1 NOTE: T1:1 = 1/fMCKE T2:1 = 1/(2 x fMCKE) Figure 62. MLB 6-Pin Clock Definitions Rev. B | Page 116 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 1/fMCKE MLBCP/N RECOVERED CLOCK 1/fMCKR tDELAY tDELAY MLBSP/N MLBDP/N (TRANSMIT) tSU tSU MLBSP/N MLBDP/N (RECEIVE) VALID VALID tHD tHD 1/fMCKE MLBCP/N 1/fMCKR RECOVERED CLOCK tDELAY tDELAY MLBSP/N MLBDP/N (TRANSMIT) tSU MLBSP/N MLBDP/N (RECEIVE) VALID VALID tHD tHD Figure 63. MLB 6-Pin Delay, Setup, and Hold Times Rev. B | Page 117 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 MLBCP/N RECOVERED CLOCK (1:1) tPHZ MLBDP/N MLNSP/N tPLZ MLBCP/N RECOVERED CLOCK (2:1) tPHZ MLBDP/N MLNSP/N tPLZ Figure 64. MLB 6-Pin Disable and Enable Turnaround Times Rev. B | Page 118 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Mobile Storage Interface (MSI) Controller Timing Table 93 and Figure 65 show I/O timing related to the MSI. Table 93. MSI Controller Timing Parameter Min Max Unit Timing Requirements tISU Input Setup Time 4.8 ns tIH Input Hold Time -0.5 ns Switching Characteristics 1 fPP Clock Frequency Data Transfer Mode1 tWL Clock Low Time 8 ns tWH Clock High Time 8 ns 45 MHz tTLH Clock Rise Time 3 ns tTHL Clock Fall Time 3 ns tODLY Output Delay Time During Data Transfer Mode tOH Output Hold Time 2.1 ns -1.8 ns tPP = 1/fPP. VOH (MIN) tPP MSI_CLK tTHL tISU tTLH tWL tIH VOL (MAX) tWH INPUT tODLY tOH OUTPUT NOTES: 1 INPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS. 2 OUTPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS. Figure 65. MSI Controller Timing Rev. B | Page 119 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Program Trace Macrocell (PTM) Timing Table 94 and Figure 66 provide I/O timing related to the PTM. Table 94. Trace Timing Parameter Min Max Unit Switching Characteristics tDTRD TRACE Data Delay From Trace Clock Maximum tHTRD TRACE Data Hold From Trace Clock Minimum 0.5 x tSCLK0 - 2.2 ns tPTRCK TRACE Clock Period Minimum 2 x tSCLK0 - 1 ns 0.5 x tSCLK0 + 4 tPTRCK TRACE0_CLK tHTRD D0 TRACE0_DX tDTRD D1 tDTRD Figure 66. Trace Timing Rev. B | Page 120 of 142 tHTRD | June 2018 ns ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Debug Interface (JTAG Emulation Port) Timing Table 95 and Figure 67 provide I/O timing related to the debug interface (JTAG Emulator Port). Table 95. JTAG Emulation Port Timing Parameter Min Max Unit Timing Requirements tTCK JTG_TCK Period 20 ns tSTAP JTG_TDI, JTG_TMS Setup Before JTG_TCK High 4 ns tHTAP JTG_TDI, JTG_TMS Hold After JTG_TCK High 4 ns tSSYS System Inputs Setup Before JTG_TCK High1 12 ns 5 ns 4 TCK 1 tHSYS System Inputs Hold After JTG_TCK High tTRSTW JTG_TRST Pulse Width (measured in JTG_TCK cycles)2 Switching Characteristics tDTDO JTG_TDO Delay From JTG_TCK Low tDSYS System Outputs Delay After JTG_TCK Low 3 1 13.5 ns 17 ns System Inputs = MLB0_CLKP, MLB0_DATP, MLB0_SIGP, DAI0_PIN20-01, DMC0_A15-0, DMC0_DQ15-0, DMC0_RESET, PA_15-0, PB_15-0, PC_15-0, PD_15-0, PE_15-0, PF_11-0, SYS_BMODE2-0, SYS_FAULT, SYS_FAULT, SYS_RESOUT, TWI2-0_SCL, TWI2-0_SDA2. 2 50 MHz maximum. 3 System Outputs = DMC0_A15-0, DMC0_BA2-0, DMC0_CAS, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ15-0, DMC0_LDM, DMC0_LDQS, DMC0_ODT, DMC0_RAS, DMC0_RESET, DMC0_UDM, DMC0_UDQS, DMC0_WE, MLB0_DATP, MLB0_SIGP, PA_15-0, PB_15-0, PC_15-0, PD_15-0, PE_15-0, PF_11-0, SYS_BMODE2-0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT, SYS_RESOUT. tTCK JTG_TCK tSTAP tHTAP JTG_TMS JTG_TDI tDTDO JTG_TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 67. JTAG Port Timing Rev. B | Page 121 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 OUTPUT DRIVE CURRENTS 50 Output drive currents for MLB pins are compliant with MOST150 LVDS specifications. Output drive currents for USB pins are compliant with the USB 2.0 specifications. 50 40 VDD_EXT = 3.47V AT -40C VDD_EXT = 3.30V AT +25C VDD_EXT = 3.13V AT +133C VOH 40 VOH 30 SOURCE CURRENT (mA) Figure 68 through Figure 80 show typical current-voltage characteristics for the output drivers of the ADSP-SC57x and ADSP2157x processors. The curves represent the current drive capability of the output drivers as a function of output voltage. VDD_EXT = 3.47V AT -40C VDD_EXT = 3.30V AT +25C VDD_EXT = 3.13V AT +133C 20 10 0 VOL -10 -20 VDD_EXT = 3.13V @ +133C VDD_EXT = 3.30V @ +25C VDD_EXT = 3.47V @ -40C -30 -40 SOURCE CURRENT (mA) 30 -50 0 20 0.5 1.0 3.0 3.5 4.0 10 0 Figure 70. Driver Type H Current (3.3 V VDD_EXT) VOL VDD_EXT = 3.13V AT +133C VDD_EXT = 3.30V AT +25C VDD_EXT = 3.47V AT -40C -10 0 -20 -30 VDD_DMC = 1.425V AT +133C VDD_DMC = 1.500V AT +25C VDD_DMC = 1.575V AT -40C -5 SOURCE CURRENT (mA) -40 -50 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) 3.0 3.5 4.0 Figure 68. Driver Type A Current (3.3 V VDD_EXT) 0 VOL VOL -10 -15 -20 VDD_EXT = 3.13V AT +133C VDD_EXT = 3.30V AT +25C VDD_EXT = 3.47V AT -40C -5 -10 -25 0 0.2 -15 -20 0.4 0.6 0.8 SOURCE VOLTAGE (V) 1.0 1.2 Figure 71. Driver Type B and Driver Type C (DDR3 Drive Strength 40 ) -25 -30 0 -35 -2 -40 SOURCE CURRENT (mA) SOURCE CURRENT (mA) 1.5 2.0 2.5 SOURCE VOLTAGE (V) -45 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) Figure 69. Driver Type D Current (3.3 V VDD_EXT) VOL -4 VDD_DMC = 1.425V AT +133C VDD_DMC = 1.500V AT +25C VDD_DMC = 1.575V AT -40C -6 -8 -10 -12 -14 -16 0 0.2 0.4 0.6 0.8 SOURCE VOLTAGE (V) 1.0 1.2 Figure 72. Driver Type B and Driver Type C (DDR3 Drive Strength 60 ) Rev. B | Page 122 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 0 25 -2 VOH SOURCE CURRENT (mA) SOURCE CURRENT (mA) VOL -4 20 15 10 VDD_DMC = 1.575V AT -40C VDD_DMC = 1.500V AT +25C VDD_DMC = 1.425V AT +133C 5 VDD_DMC = 1.7V AT +133C VDD_DMC = 1.8V AT +25C VDD_DMC = 1.9V AT -40C -6 v8 -10 -12 -14 -16 -18 -20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0.2 SOURCE VOLTAGE (V) 0.4 0.6 0.8 1.0 1.2 1.4 SOURCE VOLTAGE (V) Figure 73. Driver Type B and Driver Type C (DDR3 Drive Strength 40 ) Figure 76. Driver Type B and Driver Type C (DDR2 Drive Strength 60 ) 16 30 VOH 14 SOURCE CURRENT (mA) SOURCE CURRENT (mA) 25 12 10 8 6 VDD_DMC = 1.575V AT -40C VDD_DMC = 1.500V AT +25C VDD_DMC = 1.425V AT +133C 4 2 0.2 0.4 0.6 0.8 1.0 15 10 VDD_DMC = 1.9V AT -40C VDD_DMC = 1.8V AT +25C VDD_DMC = 1.7V AT +133C 5 0 0 VOH 20 1.2 1.4 1.6 0 1.8 0 0.5 SOURCE VOLTAGE (V) Figure 74. Driver Type B and Driver Type C (DDR3 Drive Strength 60 ) 2.0 2.5 Figure 77. Driver Type B and Driver Type C (DDR2 Drive Strength 40 ) 0 30 -5 -10 25 VDD_DMC = 1.7V AT +133C VDD_DMC = 1.8V AT +25C VDD_DMC = 1.9V AT -40C SOURCE CURRENT (mA) VOL SOURCE CURRENT (mA) 1.0 1.5 SOURCE VOLTAGE (V) -15 -20 -25 VOH 20 15 10 VDD_DMC = 1.9V AT -40C VDD_DMC = 1.8V AT +25C VDD_DMC = 1.7V AT +133C 5 -30 0 0.2 0.4 0.6 0.8 1.0 SOURCE VOLTAGE (V) 1.2 1.4 0 1.6 0 Figure 75. Driver Type B and Driver Type C (DDR2 Drive Strength 40 ) Rev. B | Page 123 of 142 0.5 1.0 1.5 SOURCE VOLTAGE (V) 2.0 2.5 Figure 78. Driver Type B and Driver Type C (DDR2 Drive Strength 60 ) | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Output Enable Time Measurement 0 VDD_DMC = 1.7V AT +133C VDD_DMC = 1.8V AT +25C VDD_DMC = 1.9V AT -40C -5 Output pins are considered enabled when they make a transition from a high impedance state to the point when they start driving. SOURCE CURRENT (mA) -10 VOL -15 The output enable time, tENA, is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving, as shown on the right side of Figure 82. If multiple pins are enabled, the measurement value is that of the first pin to start driving. -20 -25 -30 -35 REFERENCE SIGNAL -40 -45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 SOURCE VOLTAGE (V) tDIS tENA Figure 79. Driver Type B and Device Driver C (LPDDR) 45 40 VOH SOURCE CURRENT (mA) 35 OUTPUT STOPS DRIVING 30 OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE 25 Figure 82. Output Enable/Disable 20 Output Disable Time Measurement 15 Output pins are considered disabled when they stop driving, enter a high impedance state, and start to decay from the output high or low voltage. The output disable time, tDIS, is the interval from when a reference signal reaches a high or low voltage level to the point when the output stops driving, as shown on the left side of Figure 82). 10 VDD_DMC = 1.9V AT -40C VDD_DMC = 1.8V AT +25C VDD_DMC = 1.7V AT +133C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SOURCE VOLTAGE (V) Figure 80. Driver Type B and Device Driver C (LPDDR) Capacitive Loading TEST CONDITIONS All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 81 shows the measurement point for ac measurements (except output enable/disable). The measurement point, VMEAS, is VDD_EXT/2 for VDD_EXT (nominal) = 3.3 V. INPUT OR OUTPUT VMEAS Output delays and holds are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 83). VLOAD is equal to VDD_EXT/2. Figure 84 through Figure 88 show how output rise time varies with capacitance. The delay and hold specifications given must be derated by a factor derived from these figures. The graphs in Figure 84 through Figure 88 cannot be linear outside the ranges shown. VMEAS Figure 81. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Rev. B | Page 124 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 TESTER PIN ELECTRONICS 3.0 50: T1 DUT OUTPUT 45: 70: ZO = 50:(impedance) TD = 4.04 r 1.18 ns 50: 0.5pF 4pF 2pF 400: 2.5 RISE AND FALL TIMES (ns) VLOAD 2.0 tRISE = 3.3V AT 25C 1.5 tFALL = 3.3V AT 25C 1.0 0.5 NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, THE SYSTEM CAN INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. 00 15 20 25 30 35 40 Figure 85. Driver Type H Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_EXT = 3.3 V) 0.9 RISE AND FALL TIMES (ns) 0.8 35 30 RISE AND FALL TIMES (ns) 10 LOAD CAPACITANCE (pF) Figure 83. Equivalent Device Loading for AC Measurements (Includes All Fixtures) 25 5 tRISE = 3.3V AT 25C 20 tFALL = 3.3V AT 25C 0.7 tRISE = 1.8V AT 25C 0.6 0.5 tFALL = 1.8V AT 25C 0.4 0.3 0.2 15 0.1 10 0 0 2 5 50 100 150 200 10 12 Figure 86. Driver Type B and Driver Type C Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_DMC = 1.8 V) for LPDDR 0 0 4 6 8 LOAD CAPACITANCE (pF) 250 LOAD CAPACITANCE (pF) Figure 84. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_EXT = 3.3 V) 0.9 RISE AND FALL TIMES (ns) 0.8 0.7 tRISE = 1.8V AT 25C 0.6 0.5 tFALL = 1.8V AT 25C 0.4 0.3 0.2 0.1 0 0 2 4 6 8 LOAD CAPACITANCE (pF) 10 12 Figure 87. Driver Type B and Driver Type C Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_DMC = 1.8 V) for DDR2 Rev. B | Page 125 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 96. Thermal Characteristics for 400 CSP_BGA 0.9 Parameter JA JA JA JC JT JT JT RISE AND FALL TIMES (ns) 0.8 0.7 tRISE = 1.5V AT 25C 0.6 0.5 tFALL = 1.5V AT 25C 0.4 0.3 0.2 Conditions 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 14.24 12.61 12.09 5.71 0.08 0.14 0.17 Unit C/W C/W C/W C/W C/W C/W C/W Table 97. Thermal Characteristics for 176 LQFP_EP 0.1 0 0 2 4 6 8 LOAD CAPACITANCE (pF) 10 12 Figure 88. Driver Type B and Driver Type C Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_DMC = 1.5 V) for DDR3 ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application PCB, use the following equation: Parameter JA JA JA JC JT JT JT T J = T CASE + JT P D where: TJ = junction temperature (C). TCASE = case temperature (C) measured at the top center of the package. JT = from Table 96 and Table 97. PD = power dissipation (see the Total Internal Power Dissipation section for the method to calculate PD). Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first order approximation of TJ by the following equation: T J = T A + JA P D where TA = ambient temperature (C). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. In Table 96 and Table 97, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6. The junction to case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 6 layer PCB with 101.6 mm x 152.4 mm dimensions. Rev. B | Page 126 of 142 | June 2018 Conditions 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 11.95 10.43 9.98 11.10 0.15 0.24 0.29 Unit C/W C/W C/W C/W C/W C/W C/W ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x 400-BALL BGA BALL ASSIGNMENTS The ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Numerical by Ball Number) table lists the 400-ball BGA package by ball number. The ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) table lists the 400-ball BGA package by pin name. ADSP-SC57x/ADSP-2157x 400-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 Pin Name GND PA_10 PA_09 PA_11 PE_07 MLB0_CLKN MLB0_CLKP MLB0_SIGN GND SYS_XTAL0 SYS_CLKIN0 GND SYS_XTAL1 SYS_CLKIN1 GND USB0_DP USB0_DM PF_03 PF_05 GND PC_12 GND PA_13 PA_15 PB_01 PB_04 MLB0_DATN MLB0_DATP MLB0_SIGP JTG_TRST USB0_VBUS USB0_XTAL PB_10 JTG_TDO JTG_TMS PF_00 PF_01 PF_06 GND PF_07 PC_11 Ball No. C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 Pin Name PC_13 GND PA_12 PA_14 PB_03 PB_02 PE_10 PB_06 PB_05 SYS_HWRST USB0_ID USB0_CLKIN PB_12 PB_13 JTG_TDI PE_14 GND PF_08 PF_11 PC_06 PC_08 PE_04 GND PE_08 PE_11 PE_09 PB_08 PB_07 PB_09 SYS_CLKOUT PB_11 USB0_VBC PB_14 PE_13 PE_12 GND PF_10 DAI0_PIN01 DAI0_PIN04 PC_05 PE_05 Rev. B Ball No. E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 G01 G02 G03 | Page 127 of 142 Pin Name PE_03 PE_02 GND PB_00 VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_USB JTG_TCK PE_15 GND VDD_EXT PF_04 DAI0_PIN07 DAI0_PIN03 PC_02 PC_03 PC_04 PE_06 VDD_INT GND VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT GND VDD_INT PF_02 PF_09 DAI0_PIN02 DAI0_PIN06 PC_00 PC_14 PC_01 | June 2018 Ball No. G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 J01 J02 J03 J04 Pin Name VDD_EXT VDD_INT GND GND GND GND GND GND GND GND GND GND VDD_INT PB_15 DAI0_PIN08 DAI0_PIN10 DAI0_PIN09 PE_01 PC_09 PC_15 VDD_EXT VDD_INT GND GND GND GND GND GND GND GND GND GND VDD_INT VDD_EXT DAI0_PIN05 DAI0_PIN14 DAI0_PIN11 PE_00 PC_07 PC_10 VDD_EXT ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Ball No. J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 Pin Name VDD_INT GND GND GND GND GND GND GND GND GND GND VDD_INT VDD_EXT DAI0_PIN12 DAI0_PIN13 DAI0_PIN16 PD_14 PD_13 PD_15 VDD_EXT VDD_INT GND GND GND GND GND GND GND GND GND GND VDD_INT VDD_EXT DAI0_PIN15 DAI0_PIN19 DAI0_PIN18 PD_11 PD_10 PD_12 VDD_EXT VDD_INT GND GND GND GND GND GND GND Ball No. L13 L14 L15 L16 L17 L18 L19 L20 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 Pin Name GND GND GND VDD_INT VDD_EXT DAI0_PIN17 GND DAI0_PIN20 DMC0_A14 DMC0_A15 PD_09 VDD_EXT VDD_INT GND GND GND GND GND GND GND GND GND GND VDD_INT VDD_EXT HADC0_VIN7 HADC0_VIN5 HADC0_VIN6 DMC0_A11 DMC0_A13 DMC0_A12 VDD_DMC VDD_INT GND GND GND GND GND GND GND GND GND GND VDD_INT VDD_EXT HADC0_VIN4 HADC0_VIN3 GND Rev. B Ball No. P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 T01 T02 T03 T04 T05 T06 T07 T08 | Page 128 of 142 Pin Name DMC0_VREF DMC0_RZQ DMC0_A09 DMC0_A10 VDD_INT VDD_INT GND VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT GND VDD_INT VDD_INT HADC0_VIN1 HADC0_VIN0 HADC0_VREFP HADC0_VREFN PD_06 PD_07 PD_08 VDD_INT VDD_INT GND VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT GND VDD_INT VDD_INT DMC0_BA0 HADC0_VIN2 VDD_HADC PD_05 TWI0_SDA TWI0_SCL VDD_EXT GND VDD_DMC VDD_DMC VDD_DMC | June 2018 Ball No. T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 Pin Name VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC GND VDD_DMC DMC0_A02 DMC0_A01 DMC0_RESET DMC0_DQ15 DMC0_DQ14 TWI1_SDA GND TWI1_SCL VDD_EXT VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC DMC0_BA2 DMC0_WE GND DMC0_A06 DMC0_A03 DMC0_A00 TWI2_SDA DMC0_DQ13 GND PD_03 PD_04 PD_01 PA_08 PA_05 PA_03 PA_02 PA_01 PA_00 SYS_RESOUT SYS_FAULT DMC0_CAS DMC0_RAS ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Ball No. V17 V18 V19 V20 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Pin Name DMC0_BA1 GND DMC0_A04 DMC0_A05 TWI2_SCL GND DMC0_DQ12 DMC0_DQ11 DMC0_DQ09 PD_02 PD_00 PA_07 PA_06 PA_04 DMC0_DQ05 DMC0_DQ04 DMC0_DQ03 DMC0_DQ02 SYS_FAULT DMC0_ODT DMC0_A08 SYS_BMODE1 GND DMC0_A07 GND DMC0_UDQS DMC0_UDQS DMC0_DQ10 DMC0_DQ08 DMC0_UDM DMC0_LDM DMC0_CK DMC0_CK DMC0_DQ07 DMC0_DQ06 DMC0_LDQS DMC0_LDQS DMC0_DQ01 DMC0_DQ00 DMC0_CKE DMC0_CS0 SYS_BMODE0 SYS_BMODE2 GND Rev. B | Page 129 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x 400-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME) Pin Name DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 DAI0_PIN15 DAI0_PIN16 DAI0_PIN17 DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 Ball No. D19 F19 E20 D20 H18 F20 E19 G18 G20 G19 H20 J18 J19 H19 K18 J20 L18 K20 K19 L20 U20 T19 T18 U19 V19 V20 U18 W20 W17 P03 P04 N01 N03 N02 M01 M02 R18 V17 U15 V15 Y08 Y16 Y09 Y17 Y15 Y14 Pin Name DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. W14 W13 W12 W11 Y11 Y10 Y05 W05 Y04 W04 W03 V02 U02 U01 Y07 Y12 Y13 W16 V16 T20 P02 Y06 Y03 Y02 P01 U16 A01 A09 A12 A15 A20 B02 B19 C03 C18 D04 D17 E05 E16 F06 F15 G06 G07 G08 G09 G10 Rev. B Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND | Page 130 of 142 | June 2018 Ball No. G11 G12 G13 G14 G15 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L19 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 HADC0_VREFN HADC0_VREFP JTG_TCK Ball No. M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N20 P07 P14 R06 R15 T05 T16 U04 U17 V03 V18 W02 W19 Y01 Y20 P18 P17 R19 N19 N18 M19 M20 M18 P20 P19 E14 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Pin Name JTG_TDI JTG_TDO JTG_TMS JTG_TRST MLB0_CLKN MLB0_CLKP MLB0_DATN MLB0_DATP MLB0_SIGN MLB0_SIGP PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 PC_00 PC_01 PC_02 PC_03 PC_04 Ball No. C16 B14 B15 B10 A06 A07 B07 B08 A08 B09 V12 V11 V10 V09 W10 V08 W09 W08 V07 A03 A02 A04 C04 B03 C05 B04 E06 B05 C07 C06 B06 C10 C09 D09 D08 D10 B13 D12 C14 C15 D14 G17 G01 G03 F01 F02 F03 Pin Name PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 PF_00 PF_01 PF_02 PF_03 Ball No. E01 D01 J02 D02 H02 J03 C01 B01 C02 G02 H03 W07 V06 W06 V04 V05 T01 R01 R02 R03 M03 L02 L01 L03 K02 K01 K03 J01 H01 E04 E03 D03 E02 F04 A05 D05 D07 C08 D06 D16 D15 C17 E15 B16 B17 F17 A18 Rev. B Pin Name PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 PF_11 SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_CLKIN USB0_XTAL VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC | Page 131 of 142 | June 2018 Ball No. E18 A19 B18 B20 C19 F18 D18 C20 Y18 W18 Y19 A11 A14 D11 V14 W15 C11 V13 A10 A13 T03 T02 U05 U03 W01 V01 A17 A16 C12 D13 B11 C13 B12 N04 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T17 U07 U08 Pin Name VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_HADC VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT Ball No. U09 U10 U11 U12 U13 U14 E07 E08 E09 E10 E11 E12 E17 G04 H04 H17 J04 J17 K04 K17 L04 L17 M04 M17 N17 T04 U06 R20 F05 F07 F08 F09 F10 F11 F12 F13 F14 F16 G05 G16 H05 H16 J05 J16 K05 K16 L05 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Pin Name VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_USB Ball No. L16 M05 M16 N05 N16 P05 P06 P08 P09 P10 P11 P12 P13 P15 P16 R04 R05 R07 R08 R09 R10 R11 R12 R13 R14 R16 R17 E13 Rev. B | Page 132 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 CONFIGURATION OF THE 400-BALL CSP_BGA Figure 89 shows an overview of signal placement on the 400-ball CSP_BGA. TOP VIEW A1 BALL CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E U F G H J K GND L I/O SIGNALS M VDD_EXT N VDD_INT P VDD_DMC H R U VDD_USB H VDD_HADC T U V W Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 BALL CORNER 1 A B C D E U F G H J K L M N P H R T U V W Y BOTTOM VIEW Figure 89. 400-Ball CSP_BGA Configuration Rev. B | Page 133 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x 176-LEAD LQFP LEAD ASSIGNMENTS The ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Numerical by Lead Number) table lists the 176-lead LQFP package by lead number. The ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) table lists the 176-lead LQFP package by pin name. ADSP-SC57x/ADSP-2157x 176-LEAD LQFP LEAD ASSIGNMENTS (NUMERICAL BY LEAD NUMBER) Lead No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name VDD_INT GND VDD_INT PA_15 PA_14 PA_13 VDD_INT PA_12 VDD_EXT PA_10 PA_11 PC_15 PA_09 VDD_INT GND VDD_INT PC_14 PC_13 PC_12 PC_11 VDD_EXT PC_10 PC_09 PC_08 PC_07 PC_06 PC_05 PC_04 PC_03 VDD_INT VDD_EXT PC_02 PC_01 PC_00 PD_15 PD_14 PD_13 VDD_EXT VDD_INT PD_12 Lead No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name PD_11 PD_10 PD_09 GND GND VDD_EXT VDD_INT PD_08 PD_07 PD_06 PD_05 VDD_INT TWI0_SDA TWI0_SCL TWI1_SDA TWI1_SCL TWI2_SDA TWI2_SCL VDD_INT VDD_EXT PD_04 PD_03 PD_02 PD_01 GND VDD_INT PD_00 PA_08 PA_07 PA_06 VDD_EXT VDD_INT VDD_INT PA_05 PA_04 PA_03 PA_02 VDD_EXT PA_01 PA_00 Rev. B Lead No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 | Page 134 of 142 Pin Name SYS_RESOUT VDD_INT GND VDD_EXT SYS_FAULT SYS_BMODE0 SYS_BMODE1 VDD_INT GND VDD_HADC HADC0_VIN0 HADC0_VIN1 HADC0_VREFN HADC0_VIN2 HADC0_VIN3 HADC0_VREFP GND VDD_INT GND DAI0_PIN20 DAI0_PIN19 DAI0_PIN18 VDD_INT VDD_EXT DAI0_PIN17 DAI0_PIN16 DAI0_PIN15 DAI0_PIN14 VDD_INT DAI0_PIN13 DAI0_PIN12 DAI0_PIN11 DAI0_PIN10 VDD_INT VDD_EXT DAI0_PIN09 DAI0_PIN08 DAI0_PIN06 DAI0_PIN07 DAI0_PIN05 | June 2018 Lead No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name DAI0_PIN03 DAI0_PIN04 DAI0_PIN01 VDD_INT GND VDD_EXT DAI0_PIN02 PB_15 VDD_INT VDD_INT GND VDD_INT GND VDD_INT JTG_TCK JTG_TDO JTG_TDI JTG_TMS VDD_INT VDD_EXT PB_14 PB_13 VDD_EXT PB_12 VDD_INT PB_11 VDD_EXT PB_10 VDD_EXT VDD_INT SYS_HWRST VDD_EXT JTG_TRST SYS_CLKIN0 SYS_XTAL0 VDD_INT SYS_CLKOUT VDD_EXT PB_09 VDD_EXT ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Lead No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 1771 1 Pin Name PB_08 PB_07 VDD_INT VDD_EXT PB_06 PB_05 VDD_EXT PB_04 PB_03 VDD_INT VDD_EXT PB_02 PB_01 PB_00 VDD_INT GND GND Pin177 is the GND supply (see Figure 91) for the processor; this pad must connect to GND. Rev. B | Page 135 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57X/ADSP-2157X 176-LEAD LQFP LEAD ASSIGNMENTS (ALPHABETICAL BY PIN NAME) Pin Name DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 DAI0_PIN15 DAI0_PIN16 DAI0_PIN17 DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 GND GND GND GND GND GND GND GND GND GND GND GND GND GND HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST PA_00 Lead No. 123 127 121 122 120 118 119 117 116 113 112 111 110 108 107 106 105 102 101 100 02 15 44 45 65 83 89 97 99 125 131 133 176 1771 91 92 94 95 93 96 135 137 136 138 153 80 Pin Name PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 Lead No. 79 77 76 75 74 70 69 68 13 10 11 08 06 05 04 174 173 172 169 168 166 165 162 161 159 148 146 144 142 141 128 34 33 32 29 28 27 26 25 24 23 22 20 19 18 17 Rev. B Pin Name PC_15 PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 SYS_BMODE0 SYS_BMODE1 SYS_CLKIN0 SYS_CLKOUT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT | Page 136 of 142 | June 2018 Lead No. 12 67 64 63 62 61 51 50 49 48 43 42 41 40 37 36 35 86 87 154 157 85 151 81 155 54 53 56 55 58 57 09 21 31 38 46 60 71 78 84 104 115 126 140 143 147 Pin Name VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_HADC VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT 1 Lead No. 149 152 158 160 164 167 171 90 01 03 07 14 16 30 39 47 52 59 66 72 73 82 88 98 103 109 114 124 129 130 132 134 139 145 150 156 163 170 175 Pin 177 is the GND supply (see Figure 91) for the processor; this pad must connect to GND. ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 CONFIGURATION OF THE 176-LEAD LQFP LEAD CONFIGURATION Figure 90 shows the top view of the 176-lead LQFP lead configuration and Figure 91 shows the bottom view of the 176-lead LQFP lead configuration. LEAD 176 LEAD 133 LEAD 132 LEAD 1 LEAD 1 INDICATOR 176-LEAD LQFP TOP VIEW LEAD 44 LEAD 89 LEAD 45 LEAD 88 Figure 90. 176-Lead LQFP Lead Configuration (Top View) LEAD 176 LEAD 133 LEAD 1 LEAD 132 176-LEAD LQFP BOTTOM VIEW GND PAD (LEAD 177) LEAD 44 LEAD 89 LEAD 88 LEAD 45 Figure 91. 176-Lead LQFP Lead Configuration (Bottom View) Rev. B | Page 137 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 OUTLINE DIMENSIONS Dimensions in Figure 92 (for the 400-ball BGA) and Figure 93 (for the 176-lead LQFP) are shown in millimeters. A1 BALL CORNER 17.20 17.00 SQ 16.80 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A C B D E G 15.20 BSC SQ J L N 0.80 BSC W 1.50 1.36 1.21 0.90 REF BOTTOM VIEW DETAIL A DETAIL A SEATING PLANE Figure 92. 400-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-400-2) Dimensions shown in millimeters | Page 138 of 142 1.11 1.01 0.91 0.39 0.35 0.30 0.50 COPLANARITY 0.12 0.45 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1 Rev. B H K M P R U TOP VIEW F | June 2018 T V Y ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 26.20 26.00 SQ 25.80 0.75 0.60 0.45 24.10 24.00 SQ 23.90 1.60 MAX 133 133 176 1 1.00 REF 8.20 BSC SQ 132 PIN 1 INDICATOR 176 132 1 PIN 1 INDICATOR EXPOSED PAD 12 1.45 1.40 1.35 0.20 0.15 0.09 TOP VIEW (PINS DOWN) 44 0.15 0.10 0.05 0~7 SEATING PLANE 0.08 MAX COPLANARITY 89 45 VIEW A 88 45 88 0.27 0.22 0.17 0.50 BSC LEAD PITCH VIEW A 44 89 ROTATED 90 CCW BOTTOM VIEW (PINS UP) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD Figure 93. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] (SW-176-5) Dimensions shown in millimeters SURFACE-MOUNT DESIGN Table 98 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 98. CSP_BGA Data for Use with Surface-Mount Design Package BC-400-2 Package Ball Attach Type Solder Mask Defined Rev. B Package Solder Mask Opening 0.4 mm Diameter | Page 139 of 142 | June 2018 Package Ball Pad Size 0.5 mm Diameter ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 this data sheet carefully. Only the automotive grade products shown in Table 99 are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. AUTOMOTIVE PRODUCTS The following models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of Table 99. Automotive Products Processor Instruction Model 1, 2, 3 Rate (Max) AD21571WCSWZ4xx 450 MHz AD21571WCSWZ5xx 500 MHz AD21573WCBCZ4xx 450 MHz AD21573WCBCZ5xx 500 MHz ADSC570WCSWZ42xx 450 MHz ADSC570WCSWZ4xx 450 MHz ADSC571WCSWZ3xx 300 MHz ADSC571WCSWZ4xx 450 MHz ADSC571WCSWZ5xx 500 MHz ADSC572WCBCZ42xx 450 MHz ADSC572WCBCZ4xx 450 MHz ADSC573WCBCZ3xx 300 MHz ADSC573WCBCZ4xx 450 MHz ADSC573WCBCZ5xx 500 MHz ARM Instruction Rate (Max)4 N/A N/A N/A N/A 225 MHz 450 MHz 300 MHz 450 MHz 500 MHz 225 MHz 450 MHz 300 MHz 450 MHz 500 MHz Temperature Range5 -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C ARM Cores4 N/A N/A N/A N/A 1 1 1 1 1 1 1 1 1 1 SHARC+ Cores 2 2 2 2 1 1 2 2 2 1 1 2 2 2 1 External Memory Ports 0 0 1 1 0 0 0 0 0 1 1 1 1 1 Package Description 176-Lead LQFP_EP 176-Lead LQFP_EP Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Package Option SW-176-5 SW-176-5 BC-400-2 BC-400-2 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 Z = RoHS Compliant Part. xx denotes the current die revision. 3 For evaluation of all models, order the ADZS-SC573-EZLITE evaluation board. 4 N/A means not applicable. 5 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see the Operating Conditions section for the junction temperature (TJ) specification which is the only temperature specification. 2 Rev. B | Page 140 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ORDERING GUIDE Model1, 2 ADSP-21571KSWZ-4 ADSP-21571BSWZ-4 ADSP-21571CSWZ-4 ADSP-21571KSWZ-5 ADSP-21571BSWZ-5 ADSP-21571CSWZ-5 ADSP-21573KBCZ-4 ADSP-21573BBCZ-4 ADSP-21573CBCZ-4 ADSP-21573KBCZ-5 ADSP-21573BBCZ-5 ADSP-21573CBCZ-5 ADSP-SC570KSWZ-42 ADSP-SC570BSWZ-42 ADSP-SC570CSWZ-42 ADSP-SC570KSWZ-4 ADSP-SC570BSWZ-4 ADSP-SC570CSWZ-4 ADSP-SC571KSWZ-3 ADSP-SC571BSWZ-3 ADSP-SC571CSWZ-3 ADSP-SC571KSWZ-4 ADSP-SC571BSWZ-4 ADSP-SC571CSWZ-4 ADSP-SC571KSWZ-5 ADSP-SC571BSWZ-5 ADSP-SC571CSWZ-5 ADSP-SC572KBCZ-42 ADSP-SC572BBCZ-42 ADSP-SC572CBCZ-42 ADSP-SC572KBCZ-4 ADSP-SC572BBCZ-4 ADSP-SC572CBCZ-4 ADSP-SC573KBCZ-3 ADSP-SC573BBCZ-3 ADSP-SC573CBCZ-3 ADSP-SC573KBCZ-4 ADSP-SC573BBCZ-4 ADSP-SC573CBCZ-4 ADSP-SC573KBCZ-5 ADSP-SC573BBCZ-5 ADSP-SC573CBCZ-5 Processor Instruction Rate (Max) 450 MHz 450 MHz 450 MHz 500 MHz 500 MHz 500 MHz 450 MHz 450 MHz 450 MHz 500 MHz 500 MHz 500 MHz 450 MHz 450 MHz 450 MHz 450 MHz 450 MHz 450 MHz 300 MHz 300 MHz 300 MHz 450 MHz 450 MHz 450 MHz 500 MHz 500 MHz 500 MHz 450 MHz 450 MHz 450 MHz 450 MHz 450 MHz 450 MHz 300 MHz 300 MHz 300 MHz 450 MHz 450 MHz 450 MHz 500 MHz 500 MHz 500 MHz ARM Instruction Rate (Max)3 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 225 MHz 225 MHz 225 MHz 450 MHz 450 MHz 450 MHz 300 MHz 300 MHz 300 MHz 450 MHz 450 MHz 450 MHz 500 MHz 500 MHz 500 MHz 225 MHz 225 MHz 225 MHz 450 MHz 450 MHz 450 MHz 300 MHz 300 MHz 300 MHz 450 MHz 450 MHz 450 MHz 500 MHz 500 MHz 500 MHz Temperature Range4 0C to +70C -40C to +85C -40C to +105C 0C to +70C -40C to +85C -40C to +100C 0C to +70C -40C to +85C -40C to +100C 0C to +70C -40C to +85C -40C to +95C 0C to +70C -40C to +85C -40C to +105C 0C to +70C -40C to +85C -40C to +105C 0C to +70C -40C to +85C -40C to +105C 0C to +70C -40C to +85C -40C to +105C 0C to +70C -40C to +85C -40C to +100C 0C to +70C -40C to +85C -40C to +100C 0C to +70C -40C to +85C -40C to +100C 0C to +70C -40C to +85C -40C to +100C 0C to +70C -40C to +85C -40C to +100C 0C to +70C -40C to +85C -40C to +95C ARM Cores3 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SHARC+ Cores 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 1 External Memory Ports 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Package Description 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Pad 400-Ball CSP_BGA Package Option SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 SW-176-5 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 BC-400-2 Z =RoHS Compliant Part. For evaluation of all models, order the ADZS-SC573-EZLITE evaluation board. 3 N/A means not applicable. 4 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see the Operating Conditions section for the junction temperature (TJ) specification which is the only temperature specification. 2 Rev. B | Page 141 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16121-0-6/18(B) Rev. B | Page 142 of 142 | June 2018