LTC2631
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BLOCK DIAGRAM
FEATURES
APPLICATIONS
DESCRIPTION
Single 12-/10-/8-Bit I2C
VOUT DACs with
10ppm/°C Reference
The LTC
®
2631 is a family of 12-, 10-, and 8-bit voltage-
output DACs with an integrated, high accuracy, low-drift
reference in an 8-lead TSOT-23 package. It has a rail-to-rail
output buffer that is guaranteed monotonic.
The LTC2631-L has a full-scale output of 2.5V, and oper-
ates from a single 2.7V to 5.5V supply. The LTC2631-H
has a full-scale output of 4.096V, and operates from a 4.5V
to 5.5V supply. A 10ppm/°C reference output is available
at the REF pin.
Each DAC can also operate in External Reference mode,
in which a voltage supplied to the REF pin sets the full-
scale output.
The LTC2631 DACs use a 2-wire, I2C-compatible serial
interface. The LTC2631 operates in both the standard
mode (clock rate of 100kHz) and the fast mode (clock
rate of 400kHz).
The LTC2631 incorporates a power-on reset circuit. Op-
tions are available for reset to zero-scale or reset to mid-
scale after power-up.
Integral Nonlinearity (LTC2631A-LM12)
n Integrated Precision Reference
2.5V Full-Scale 10ppm/°C (LTC2631-L)
4.096V Full-Scale 10ppm/°C (LTC2631-H)
n Maximum INL Error: 1LSB (LTC2631A-12)
n Bidirectional Reference: Input or 10ppm/°C Output
n 400kHz I2C Interface
n Nine Selectable Addresses (LTC2631-Z)
n Low Noise (0.7mVP-P, 0.1Hz to 200kHz)
n Guaranteed Monotonic Over Temperature
n 2.7V to 5.5V Supply Range (LTC2631-L)
n Low Power Operation: 180µA at 3V
n Power Down to 1.8µA Maximum (C and I Grades)
n Power-On Reset to Zero or Mid-Scale Options
n Double-Buffered Data Latches
n Guaranteed Operation From –40°C to 125°C (H-Grade)
n 8-Lead TSOT-23 (ThinSOT™) Package
n Mobile Communications
n Process Control and Industrial Automation
n Automatic Test Equipment
n Portable Equipment
n Automotive
n Optical Networking
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. I2C and
ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5396245, 5859606,
6891433, 6937178 and 7414561.
(LTC2631-M)
DAC
REGISTER
RESISTOR
DIVIDER
INTERNAL
REFERENCE
INPUT
REGISTER
I2C
INTERFACE
DAC VOUT
SWITCH
CONTROL
DECODE LOGIC
SDA
VCC REF
GND
DACREF
2631 TA01
SCL
CA0
REF_SEL
I2C
ADDRESS
DECODE
CODE
0
INL (LSB)
0
0.5
4095
2631 TA01b
–0.5
–1.0 1024 2048 3072
1.0 VCC = 3V
VFS = 2.5V
LTC2631
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ...................................0.3V to 6V
REF_SEL, SCL, SDA .....................................0.3V to 6V
VOUT, CA0, CA1, REF .........0.3V to Min(VCC + 0.3V, 6V)
Operating Temperature Range
LTC2631C ................................................ 0°C to 70°C
LTC2631I..............................................40°C to 85°C
LTC2631H (Note 3) ............................ 40°C to 125°C
(Notes 1, 2)
CA0 1
SCL 2
SDA 3
GND 4
8 CA1
7 VOUT
6 REF
5 VCC
TOP VIEW
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C (NOTE 6), θJA = 195°C/W
CA0 1
SCL 2
SDA 3
GND 4
8 REF_SEL
7 VOUT
6 REF
5 VCC
TOP VIEW
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C (NOTE 6), θJA = 195°C/W
PIN CONFIGURATION
Maximum Junction Temperature........................... 150°C
Storage Temperature Range ...................65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
LTC2631-Z LTC2631-M
LTC2631
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LTC2631 A C TS8 –L M 12 #TRM PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = 2,500-Piece Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
M = Reset to Mid-Scale
Z = Reset to Zero-Scale
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
TS8 = 8-Lead Plastic TSOT-23
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = ±1LSB Maximum INL (12-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ORDER INFORMATION
LTC2631
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PRODUCT SELECTION GUIDE
PART NUMBER PART MARKING*
VFS WITH INTERNAL
REFERENCE
POWER-ON RESET
TO CODE PIN 8 RESOLUTION VCC MAXIMUM INL
LTC2631A-LM12
LTC2631A-LZ12
LTC2631A-HM12
LTC2631A-HZ12
LTD H F
LTD H G
LTD H H
LTD H J
2.5V • (4095/4096)
2.5V • (4095/4096)
4.096V • (4095/4096)
4.096V • (4095/4096)
Mid-Scale
Zero
Mid-Scale
Zero
REF_SEL
CA1
REF_SEL
CA1
12-Bit
12-Bit
12-Bit
12-Bit
2.7V – 5.5V
2.7V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
±1LSB
±1LSB
±1LSB
±1LSB
LTC2631-LM12
LTC2631-LM10
LTC2631-LM8
LTD H F
LTD H K
LTD H Q
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
REF_SEL
REF_SEL
REF_SEL
12-Bit
10-Bit
8-Bit
2.7V – 5.5V
2.7V – 5.5V
2.7V – 5.5V
±2.5LSB
±1LSB
±0.5LSB
LTC2631-LZ12
LTC2631-LZ10
LTC2631-LZ8
LTD H G
LTD H M
LTD H R
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Zero
Zero
Zero
CA1
CA1
CA1
12-Bit
10-Bit
8-Bit
2.7V – 5.5V
2.7V – 5.5V
2.7V – 5.5V
±2.5LSB
±1LSB
±0.5LSB
LTC2631-HM12
LTC2631-HM10
LTC2631-HM8
LTD H H
LTD H N
LTD H S
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
REF_SEL
REF_SEL
REF_SEL
12-Bit
10-Bit
8-Bit
4.5V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
±2.5LSB
±1LSB
±0.5LSB
LTC2631-HZ12
LTC2631-HZ10
LTC2631-HZ8
LTD H J
LTD H P
LTD H T
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Zero
Zero
Zero
CA1
CA1
CA1
12-Bit
10-Bit
8-Bit
4.5V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
±2.5LSB
±1LSB
±0.5LSB
*The temperature grade is identifi ed by a label on the shipping container.
LTC2631
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ELECTRICAL CHARACTERISTICS
LTC2631-8 LTC2631-10 LTC2631-12 LTC2631A-12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution l8 10 12 12 Bits
Monotonicity VCC = 3V, Internal Ref. (Note 4) l8 10 12 12 Bits
DNL Differential
Nonlinearity
VCC = 3V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB
INL Integral
Nonlinearity
VCC = 3V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1 LSB
ZSE Zero-Scale Error VCC = 3V, Internal Ref.,
Code = 0
l0.5 5 0.5 5 0.5 5 0.5 5 mV
VOS Offset Error VCC = 3V, Internal Ref.
(Note 5)
l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV
VOSTC VOS Temperature
Coeffi cient
VCC = 3V, Internal Ref.
(Note 5)
±10 ±10 ±10 ±10 µV/°C
FSE Full-Scale Error VCC = 3V, Internal Ref.
(Note 15)
l±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 %FSR
VFSTC Full-Scale
Voltage
Temperature
Coeffi cient
VCC = 3V, Internal Ref. (Note 10)
C-Grade
I-Grade
H-Grade
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
ppm/°C
ppm/°C
ppm/°C
Load Regulation Internal Ref., Mid-Scale,
VCC = 3V ±10%,
–5mA ≤ IOUT ≤ 5mA,
VCC = 5V ±10%,
–10mA ≤ IOUT ≤ 10mA
l
l
0.009
0.009
0.016
0.016
0.035
0.035
0.064
0.064
0.14
0.14
0.256
0.256
0.14
0.14
0.256
0.256
LSB/mA
LSB/mA
ROUT DC Output
Impedance
Internal Ref., Mid-Scale,
VCC = 3V ±10%,
–5mA ≤ IOUT ≤ 5mA,
VCC = 5V ±10%,
–10mA ≤ IOUT ≤ 10mA
l
l
0.09
0.09
0.156
0.156
0.09
0.09
0.156
0.156
0.09
0.09
0.156
0.156
0.09
0.09
0.156
0.156
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT DAC Output Span External Reference
Internal Reference
0 to VREF
0 to 2.5
V
V
PSR Power Supply Rejection VCC = 3V ±10% or 5V ±10% –80 dB
ISC Short-Circuit Output Current (Note 6)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT shorted to VCC
Full-Scale; VOUT shorted to GND
l
l
27
–28
48
–48
mA
mA
Power Supply
VCC Positive Supply Voltage For Specifi ed Performance l2.7 5.5 V
ICC Supply Current (Note 7) VCC = 3V, VREF = 2.5V, External Reference
VCC = 3V, Internal Reference
VCC = 5V, VREF = 2.5V, External Reference
VCC = 5V, Internal Reference
l
l
l
l
150
180
160
190
200
240
210
260
µA
µA
µA
µA
ISD Supply Current in Power-Down Mode
(Note 7)
VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
l
l
0.6
0.6
1.8
4
µA
µA
LTC2631
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input
Input Voltage Range l0V
CC V
Resistance l160 190 220 k
Capacitance 7.5 pF
IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 0.1 µA
Reference Output
Output Voltage l1.240 1.250 1.260 V
Reference Temperature Coeffi cient ±10 ppm/°C
Output Impedance 0.5 k
Capacitive Load Driving 10 µF
Short-Circuit Current VCC = 5.5V; REF Shorted to GND 2.5 mA
Digital I/O
VIL Low Level Input Voltage (SDA and SCL) (Note 14) l–0.5 0.3VCC V
VIH High Level Input Voltage (SDA and SCL) (Note 11) l0.7VCC V
VIL(CA
n
)Low Level Input Voltage on CA
n
(n = 0, 1)
See Test Circuit 1 l0.15VCC V
VIH(CA
n
)High Level Input Voltage on CA
n
(n = 0, 1)
See Test Circuit 1 l0.85VCC V
RINH Resistance from CA
n
(n = 0, 1)
to VCC to Set CA
n
= VCC
See Test Circuit 2 l10 k
RINL Resistance from CA
n
(n = 0, 1)
to GND to Set CA
n
= GND
See Test Circuit 2 l10 k
RINF Resistance from CA
n
(n = 0, 1)
to VCC or GND to Set CA
n
= Float
See Test Circuit 2 l2M
VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V
tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 12)
l20 + 0.1CB250 ns
tSP Pulse Width of Spikes Suppressed by
Input Filter
l050ns
IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l±1 µA
CIN I/O Pin Capacitance (Note 8) l10 pF
CBCapacitive Load for Each Bus Line l400 pF
CCA
n
External Capacitive Load on Address
Pin CA
n
(n = 0, 1)
l10 pF
LTC2631
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Performance
tSSettling Time VCC = 3V (Note 9)
±0.39% (±1LSB at 8-Bits)
±0.098% (±1LSB at 10-Bits)
±0.024% (±1LSB at 12-Bits)
3.2
3.8
4.1
µs
µs
µs
Voltage-Output Slew Rate 1 V/µs
Capacitance Load Driving 500 pF
Glitch Impulse At Mid-Scale Transition 2.1 nV•s
Multiplying Bandwidth External Reference 300 kHz
enOutput Voltage Noise Density At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
160
150
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Output Voltage Noise 0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
CREF = 0.33µF
20
20
650
670
µVP-P
µVP-P
µVP-P
µVP-P
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13).
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL SCL Clock Frequency l0 400 kHz
tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs
tLOW Low Period of the SCL Clock Pin l1.3 µs
tHIGH High Period of the SCL Clock Pin l0.6 µs
tSU(STA) Set-Up Time for a Repeated Start Condition l0.6 µs
tHD(DAT) Data Hold Time l0 0.9 µs
tSU(DAT) Data Set-Up Time l100 ns
trRise Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns
tfFall Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns
tSU(STO) Set-Up Time for Stop Condition l0.6 µs
tBUF Bus Free Time Between a Stop and Start Condition l1.3 µs
LTC2631
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
LTC2631-8 LTC2631-10 LTC2631-12 LTC2631A-12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution l8 10 12 12 Bits
Monotonicity VCC = 5V, Internal Ref. (Note 4) l8 10 12 12 Bits
DNL Differential
Nonlinearity
VCC = 5V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB
INL Integral
Nonlinearity
VCC = 5V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1 LSB
ZSE Zero-Scale Error VCC = 5V, Internal Ref., Code = 0 l0.5 5 0.5 5 0.5 5 0.5 5 mV
VOS Offset Error VCC = 5V, Internal Ref. (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV
VOSTC VOS Temperature
Coeffi cient
VCC = 5V, Internal Ref. (Note 5) ±10 ±10 ±10 ±10 µV/°C
FSE Full-Scale Error VCC = 5V, Internal Ref. (Note 15) l±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 %FSR
VFSTC Full-Scale
Voltage
Temperature
Coeffi cient
VCC = 5V, Internal Ref. (Note 10)
C-Grade
I-Grade
H-Grade
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
ppm/°C
ppm/°C
ppm/°C
Load Regulation VCC = 5V ±10%, Internal Ref.
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
l0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 LSB/mA
ROUT DC Output
Impedance
VCC = 5V ±10%, Internal Ref.
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
l0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT DAC Output Span External Reference
Internal Reference
0 to VREF
0 to 4.096
V
V
PSR Power Supply Rejection VCC = 5V ±10% –80 dB
ISC Short-Circuit Output Current (Note 6)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT shorted to VCC
Full-Scale; VOUT shorted to GND
l
l
27
–28
48
–48
mA
mA
Power Supply
VCC Positive Supply Voltage For Specifi ed Performance l4.5 5.5 V
ICC Supply Current (Note 7) VCC = 5V, VREF = 4.096V, External Reference
VCC = 5V, Internal Reference
l
l
160
200
220
270
µA
µA
ISD Supply Current in Power-Down Mode
(Note 7)
VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
l
l
0.6
0.6
1.8
4
µA
µA
LTC2631
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input
Input Voltage Range l0V
CC V
Resistance l160 190 220 k
Capacitance 7.5 pF
IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 0.1 µA
Reference Output
Output Voltage l2.032 2.048 2.064 V
Reference Temperature Coeffi cient ±10 ppm/°C
Output Impedance 0.5 k
Capacitive Load Driving 10 µF
Short-Circuit Current VCC = 5.5V; REF Shorted to GND 4.3 mA
Digital I/O
VIL Low Level Input Voltage (SDA and SCL) (Note 14) l–0.5 0.3VCC V
VIH High Level Input Voltage (SDA and SCL) (Note 11) l0.7VCC V
VIL(CA
n
)Low Level Input Voltage on CA
n
(n = 0, 1)
See Test Circuit 1 l0.15VCC V
VIH(CA
n
)High Level Input Voltage on CA
n
(n = 0, 1)
See Test Circuit 1 l0.85VCC V
RINH Resistance from CA
n
(n = 0, 1)
to VCC to Set CA
n
= VCC
See Test Circuit 2 l10 k
RINL Resistance from CA
n
(n = 0, 1)
to GND to Set CA
n
= GND
See Test Circuit 2 l10 k
RINF Resistance from CA
n
(n = 0, 1)
to VCC or GND to Set CA
n
= Float
See Test Circuit 2 l2M
VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V
tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 12)
l20 + 0.1CB250 ns
tSP Pulse Width of Spikes Suppressed by
Input Filter
l050ns
IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l±1 µA
CIN I/O Pin Capacitance (Note 8) l10 pF
CBCapacitive Load for Each Bus Line l400 pF
CCA
n
External Capacitive Load on Address
Pin CA
n
(n = 0, 1)
l10 pF
LTC2631
10
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Performance
tSSettling Time VCC = 5V (Note 9)
±0.39% (±1LSB at 8-Bits)
±0.098% (±1LSB at 10-Bits)
±0.024% (±1LSB at 12-Bits)
3.7
4.2
4.6
µs
µs
µs
Voltage-Output Slew Rate 1 V/µs
Capacitance Load Driving 500 pF
Glitch Impulse At Mid-Scale Transition 3.0 nV•s
Multiplying Bandwidth External Reference 300 kHz
enOutput Voltage Noise Density At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
210
200
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Output Voltage Noise 0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
CREF = 0.33µF
20
20
650
670
µVP-P
µVP-P
µVP-P
µVP-P
LTC2631
11
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TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13).
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL SCL Clock Frequency l0 400 kHz
tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs
tLOW Low Period of the SCL Clock Pin l1.3 µs
tHIGH High Period of the SCL Clock Pin l0.6 µs
tSU(STA) Set-Up Time for a Repeated Start Condition l0.6 µs
tHD(DAT) Data Hold Time l0 0.9 µs
tSU(DAT) Data Set-Up Time l100 ns
trRise Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns
tfFall Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns
tSU(STO) Set-Up Time for Stop Condition l0.6 µs
tBUF Bus Free Time Between a Stop and Start Condition l1.3 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
Note 4: Linearity and monotonicity are defi ned from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS),
rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and
linearity is defi ned from code 26 to code 4,095. For VFS = 4.096V and
N = 12, kL = 16 and linearity is defi ned from code 16 to code 4,095.
Note 5: Inferred from measurement at code 16 (LTC2631-12), code 4
(LTC2631-10) or code 1 (LTC2631-8), and at full-scale.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specifi ed maximum operating junction temperature may impair
device reliability.
Note 7: Digital inputs at 0V or VCC.
Note 8: Guaranteed by design and not production tested.
Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND.
Note 10: Temperature coeffi cient is calculated by dividing the maximum
change in output voltage by the specifi ed temperature range.
Note 11: Maximum VIH = VCC(MAX) + 0.5V
Note 12: CB = capacitance of one bus line in pF
Note 13: All values refer to VIH = VIH(MIN) and VIL = VIL(MAX) levels.
Note 14: Minimum VIL exceeds the Absolute Maximum rating. This
condition won’t damage the IC, but could degrade performance.
Note 15: Full-scale error is determined using the reference voltage
measured at the REF pin.
LTC2631
12
2631fb
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
Reference Output Voltage
vs Temperature
DNL vs Temperature
Full-Scale Output Voltage
vs Temperature
Settling to ±1LSB
Settling to ±1LSB
LTC2631-L12 (Internal Reference, VFS = 2.5V)
INL vs Temperature
CODE
0
INL (LSB)
0
0.5
4095
2631 G01
–0.5
–1.0 1024 2048 3072
1.0 VCC = 3V
CODE
0
DNL (LSB)
0
0.5
4095
2631 G02
–0.5
–1.0 1024
VCC = 3V
2048 3072
1.0
TEMPERATURE (°C)
–50 –25 25 75 125
VREF (V)
1.250
1.255
150
2631 G03
1.245
1.240 050 100
1.260
VCC = 3V
TEMPERATURE (°C)
–50 –25 25 75 125
INL (LSB)
0
0.5
150
2631 G04
–0.5
–1.0 050 100
1.0
VCC = 3V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50 –25 25 75 125
DNL (LSB)
0
0.5
150
2631 G05
–0.5
–1.0 050 100
1.0
VCC = 3V
DNL (POS)
DNL (NEG)
TEMPERATURE (°C)
–50 –25 25 75 125
FS OUTPUT VOLTAGE (V)
2.50
2.51
150
2631 G06
2.49
2.48 050 100
2.52
VCC = 3V
2µs/DIV
2631 G07
VOUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
SCL
2V/DIV
3.6µs
9th CLOCK OF
3rd DATA BYTE
2µs/DIV
2631 G08
VOUT
1LSB/DIV
3/4 SCALE TO 1/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
SCL
2V/DIV
4.1µs
9th CLOCK OF
3rd DATA BYTE
TA = 25°C, unless otherwise noted.
LTC2631
13
2631fb
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
Reference Output Voltage
vs Temperature
DNL vs Temperature
Full-Scale Output Voltage
vs Temperature
Settling to ±1LSB
Settling to ±1LSB
LTC2631-H12 (Internal Reference, VFS = 4.096V)
INL vs Temperature
TEMPERATURE (°C)
–50 –25 25 75 125
INL (LSB)
0
0.5
150
2631 G12
–0.5
–1.0 050 100
1.0
VCC = 5V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50 –25 25 75 125
DNL (LSB)
0
0.5
150
2631 G13
–0.5
–1.0 050 100
1.0
VCC = 5V
DNL (POS)
DNL (NEG)
TEMPERATURE (°C)
–50 –25 25 75 125
FS OUTPUT VOLTAGE (V)
4.095
4.105
150
2631 G14
4.085
4.075 050 100
4.115
VCC = 5V
CODE
0
INL (LSB)
0
0.5
4095
2631 G09
–0.5
–1.0 1024 2048 3072
1.0 VCC = 5V
CODE
0
DNL (LSB)
0
0.5
4095
2631 G10
–0.5
–1.0 1024 2048 3072
1.0 VCC = 5V
TEMPERATURE (°C)
–50 –25 25 75 125
VREF (V)
2.048
2.058
150
2631 G11
2.038
2.028 050 100
2.068
VCC = 5V
2µs/DIV
2631 G15
VOUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
SCL
5V/DIV
3.9µs
9th CLOCK OF
3rd DATA BYTE
2µs/DIV
2631 G16
VOUT
1LSB/DIV
SCL
5V/DIV
4.6µs
3/4 SCALE TO 1/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
9th CLOCK OF
3rd DATA BYTE
TA = 25°C, unless otherwise noted.
LTC2631
14
2631fb
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631-10
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
Load Regulation Current Limiting
LTC2631-8
LTC2631
CODE
0
INL (LSB)
0
0.5
1023
2631 G17
–0.5
–1.0 256 512 768
1.0 VCC = 5V
VFS = 4.096V
INTERNAL REF.
CODE
0
DNL (LSB)
0
0.5
1023
2631 G18
–0.5
–1.0 256 512 768
1.0 VCC = 5V
VFS = 4.096V
INTERNAL REF.
CODE
0
INL (LSB)
0
0.5
255
2631 G19
–0.5
–1.0 64 128 192
1.0 VCC = 3V
VFS = 2.5V
INTERNAL REF.
CODE
0
DNL (LSB)
0
0.25
255
2631 G20
–0.25
–0.50 64 128 192
0.50 VCC = 3V
VFS = 2.5V
INTERNAL REF.
IOUT (mA)
–30 –20 –10 0 10 20 30
ΔVOUT (mV)
0
2
4
6
8
2631 G21
–6
–4
–2
–8
–10
10
INTERNAL REF.
CODE = MIDSCALE
VCC = 5V (LTC2631-H)
VCC = 5V (LTC2631-L)
VCC = 3V (LTC2631-L)
IOUT (mA)
–30 –20 –10 0 10 20 30
$VOUT (V)
–0.05
0
0.05
0.10
0.15
2631 G22
–0.20
–0.15
–0.10
0.20
INTERNAL REF.
CODE = MIDSCALE
VCC = 5V (LTC2631-H)
VCC = 5V (LTC2631-L)
VCC = 3V (LTC2631-L)
TA = 25°C, unless otherwise noted.
LTC2631
15
2631fb
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631
Offset Error vs Temperature
Large-Signal Response
Headroom at Rails
vs Output Current Exiting Power-Down to Mid-Scale
Mid-Scale-Glitch Impulse Power-On Reset Glitch
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125 150
OFFSET ERROR (mV)
0
1
2
2631 G23
–1
–2
–3
3
IOUT (mA)
012345678910
VOUT (V)
2.5
2.0
3.5
3.0
4.0
2631 G29
1.5
1.0
0.5
0
5.0
4.5
3V (LTC2631-L) SOURCING
3V (LTC2631-L) SINKING
5V SOURCING
5V SINKING
2µs/DIV
VOUT
0.5V/DIV
2631 G26
VFS = VCC = 5V
1/4 SCALE TO 3/4 SCALE
2µs/DIV
VOUT
5mV/DIV
2631 G27
SCL
5V/DIV
LTC2631-L12, VCC = 3V:
2.1nV-s TYP
LTC2631-H12, VCC = 5V:
3.0nV-s TYP
9th CLOCK OF
3rd DATA BYTE
200µs/DIV
VCC
2V/DIV
2631 G28
LTC2631-L
VOUT
2mV/DIV
ZERO-SCALE
4µs/DIV
2631 G30
LTC2631-H
CS/LD
2V/DIV
VOUT
0.5V/DIV
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
GAIN ERROR (%FSR)
0.1
0.2
0.3
2631 G24
0.0
–0.3
–0.2
–0.1
–0.4
0.4 EXTERNAL REF.
VREF = 2.5V
Gain Error vs VCC Gain Error vs Temperature
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125 150
GAIN ERROR (%FSR)
0.1
0.2
0.3
2631 G25
0.0
–0.3
–0.2
–0.1
–0.4
0.4 EXTERNAL REF.
VREF = 2.5V
TA = 25°C, unless otherwise noted.
LTC2631
16
2631fb
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631
Multiplying Bandwidth
Noise Voltage vs Frequency 0.1Hz to 10Hz Voltage Noise
Supply Current vs Logic Voltage
Supply Current
vs REF_SEL Voltage
FREQUENCY (Hz)
100
NOISE VOLTAGE (nV/√Hz)
200
300
1M
2631 G34
100
01k 10k 100k
500
400
INTERNAL REF.
CODE = MIDSCALE
LTC2631-H
(VCC = 5V)
LTC2631-L
(VCC = 4V)
1s/DIV
10µV/DIV
2631 G35
LTC2631-L, VCC = 4V
INTERNAL REF.
CODE = MIDSCALE
LOGIC VOLTAGE (V)
0
ICC (mA)
1.2
0.8
0.4
1.0
0.6
0.2
0.0 42
2631 G31
531
VCC = 5V
VCC = 3V
(LTC2631-L)
SWEEP SCL AND SDA
BETWEEN 0V AND VCC
REF_SEL VOLTAGE (V)
0
ICC (mA)
0.5
0.3
0.4
0.2
0.1 42
2631 G32
531
VCC = 5V
VCC = 3V
(LTC2631-L)
SWEEP REF_SEL
BETWEEN 0V AND VCC
FREQUENCY (Hz)
1k
dB
0
–2
–6
–8
–14
–4
–12
–10
–16
–18 100k
2631 G33
1000k10k
VCC = 5V
VREF(DC) = 2V
VREF(AC) = 0.2VP-P
CODE = FULL SCALE
TA = 25°C, unless otherwise noted.
LTC2631
17
2631fb
PIN FUNCTIONS
CA0 (Pin 1): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it fl oating to select an I2C slave address for the
part (see Tables 1 and 2).
SCL (Pin 2): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to VCC.
SDA (Pin 3): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open-drain
N-channel output during acknowledgment. SDA requires
a pull-up resistor or current source to VCC.
GND (Pin 4): Ground.
VCC (Pin 5): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V
(LTC2631-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2631-H). Bypass
to GND with a 0.1µF capacitor.
REF (Pin 6): Reference Voltage Input or Output. When
External Reference mode is selected, REF is an input (0V
≤ VREF ≤ VCC) where the voltage supplied sets the full-
scale voltage. When Internal Reference is selected, the
10ppm/°C 1.25V (LTC2631-L) or 2.048V (LTC2631-H)
internal reference is available at the pin. This output may
be bypassed to GND with up to 10µF (0.33µF is recom-
mended), and must be buffered when driving external DC
load current.
VOUT (Pin 7): DAC Analog Voltage Output.
CA1 (Pin 8, LTC2631-Z): Chip Address Bit 1. Tie this pin
to VCC, GND or leave it fl oating to select an I2C slave ad-
dress for the part (see Table 1).
REF_SEL (Pin 8, LTC2631-M): Selects default Reference
at power up. Tie to VCC to select the Internal Reference,
or GND to select an External Reference. After power-up,
the logic state at this pin is ignored and the reference may
be changed only by software command.
LTC2631
18
2631fb
BLOCK DIAGRAMS
DAC
REGISTER
RESISTOR
DIVIDER
INTERNAL
REFERENCE
INPUT
REGISTER
I2C
INTERFACE
DAC VOUT
SWITCH
CONTROL
DECODE LOGIC
SDA
VCC REF
GND
DACREF
2631 BD
SCL
CA0
REF_SEL
I2C
ADDRESS
DECODE
DAC
REGISTER
RESISTOR
DIVIDER
INTERNAL
REFERENCE
INPUT
REGISTER
I2C
INTERFACE
DAC VOUT
SWITCH
CONTROL
DECODE LOGIC
SDA
VCC REF
GND
DACREF
SCL
CA1
CA0
I2C
ADDRESS
DECODE
LTC2631-Z
LTC2631-M
LTC2631
19
2631fb
TEST CIRCUITS
100Ω RINH/RINL/RINF
VIH(CAn)/VIL(CAn)
CAn
GND
2631 TC
VCC
Test Circuit 2Test Circuit 1
CAn
Test Circuits for I2C Digital I/O (See Electrical Characteristics)
LTC2631
20
2631fb
TIMING DIAGRAMS
Figure 1. Serial Interface Timing
Figure 2. Typical LTC2631 Write Transaction
SDA
tf
S
tr
tLOW
tHD(STA)
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
tHD(DAT)
tSU(DAT)
tSU(STA)
tHD(STA)
tSU(STO)
tSP tBUF
tr
tf
tHIGH
SCL
S P S 2631 F01
ACK ACK
123456789123456789123456789123456789
2631 F02
ACK
START
SDA A6 A5 A4 A3
SLAVE ADDRESS
A2 A1 A0 W
SCL
C2C3 C1 C0 X X X X XXXX
ACK
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
LTC2631
21
2631fb
OPERATION
The LTC2631 is a family of single voltage-output DACs in
8-lead ThinSOT packages. Each DAC can operate rail-to-rail
using an external reference, or with its full-scale voltage
set by an integrated reference. Twelve combinations of
accuracy (12-, 10-, and 8-bit), power-on reset value (zero
or mid-scale), and full-scale voltage (2.5V or 4.096V) are
available. The LTC2631 is controlled using a 2-wire I2C
interface.
Power-On Reset
The LTC2631-HZ/LTC2631-LZ clear the output to zero-scale
when power is fi rst applied, making system initialization
consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2631
contains circuitry to reduce the power-on glitch: the analog
output typically rises less than 5mV above zero-scale
during power on if the power supply is ramped to 5V in
1ms or more. In general, the glitch amplitude decreases as
the power supply ramp time is increased. See “Power-On
Reset Glitch” in the Typical Performance Characteristics
section.
The LTC2631-HM/LTC2631-LM provide an alternative
reset, setting the output to mid-scale when power is fi rst
applied.
Default reference mode selection is described in the Ref-
erence Modes section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 5) is in transition.
Transfer Function
The digital-to-analog transfer function is
VOUT(IDEAL) =k
2N
VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and VREF is either 2.5V (LTC2631-
LM/LTC2631-LZ) or 4.096V (LTC2631-HM/LTC2631-HZ)
when in Internal Reference mode, and the voltage at REF
(Pin 6) when in External Reference mode.
I2C Serial Interface
The LTC2631 communicates with a host using the stan-
dard 2-wire I2C interface. The Timing Diagrams (Figures 1
and 2) show the timing relationship of the signals on the
bus. The two bus lines, SDA and SCL, must be high when
the bus is not in use. External pull-up resistors or current
sources are required on these lines. The value of these
pull-up resistors is dependent on the power supply and
can be obtained from the I2C specifi cations. For an I2C
bus operating in the fast mode, an active pull-up will be
necessary if the bus capacitance is greater than 200pF.
The LTC2631 is a receive-only (slave) device. The master
can write to the LTC2631. The LTC2631 does not respond
to a read from the master.
START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communi-
cation to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has fi nished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was properly received. The
Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during
the Acknowledge clock pulse. The slave-receiver must pull
down the SDA bus line during the Acknowledge clock pulse
so that it remains a stable LOW during the HIGH period
of this clock pulse. The LTC2631 responds to a write by a
LTC2631
22
2631fb
OPERATION
master in this manner but does not acknowledge a read
operation; in that case, SDA is retained HIGH during the
period of the Acknowledge clock pulse.
Chip Address
The state of pins CA0 and CA1 (LTC2631-HZ/LTC2631-
LZ) determines the slave address of the part. These pins
can each be set to any one of three states: VCC, GND or
oat. This results in nine (LTC2631-HZ/LTC2631-LZ) or
three (LTC2631-HM/LTC2631-LM) selectable addresses
for the part. The slave address assignments are shown
in Tables 1 and 2.
Table 1. Slave Address Map (LTC2631-Z)
CA1 CA0 A6 A5 A4 A3 A2 A1 A0
GND GND 0 0 1 0 0 0 0
GND FLOAT 0 0 1 0 0 0 1
GND VCC 0010010
FLOAT GND 0 0 1 0 0 1 1
FLOAT FLOAT 0 1 0 0 0 0 0
FLOAT VCC 0100001
VCC GND 0 1 0 0 0 1 0
VCC FLOAT 0 1 0 0 0 1 1
VCC VCC 0110000
GLOBAL ADDRESS 1 1 1 0 0 1 1
Table 2. Slave Address Map (LTC2631-M)
CA0 A6 A5 A4 A3 A2 A1 A0
GND 0 0 1 0 0 0 0
FLOAT 0 0 1 0 0 0 1
VCC 0010010
GLOBAL ADDRESS 1 1 1 0 0 1 1
In addition to the address selected by the address pins, the
part also responds to a global address. This address allows
a common write to all LTC2631 parts to be accomplished
using one 3-byte write transaction on the I2C bus. The
global address, listed at the end of Tables 1 and 2, is a 7-bit
hardwired address not selectable by CA0/CA1. If another
address is required, please consult the factory.
The maximum capacitive load allowed on the CA0/CA1
address pins is 10pF, as these pins are driven during ad-
dress detection to determine if they are fl oating.
Write Word Protocol
The master initiates communication with the LTC2631
with a START condition and a 7-bit slave address followed
by the Write bit (W) = 0. The LTC2631 acknowledges by
pulling the SDA pin low at the ninth clock if the 7-bit slave
address matches the address of the part (set by CA0/CA1)
or the global address. The master then transmits 3-bytes
of data. The LTC2631 acknowledges each byte of data by
pulling the SDA line low at the ninth clock of each data
byte transmission. After receiving three complete bytes
of data, the LTC2631 executes the command specifi ed in
the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2631 does not acknowledge the
extra bytes of data (SDA is high during the 9th clock).
The format of the three data bytes is shown in Figure 3. The
rst byte of the input word consists of the 4-bit command,
followed by four don’t-cares bits. The next two bytes
contain the 16-bit data word, which consists of the 12-,
10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8
don’t-cares bits (LTC2631-12, LTC2631-10 and LTC2631-8
respectively). A typical LTC2631 write transaction is
shown in Figure 4.
The command bit assignments (C3-C0) are shown in
Table 3. The fi rst four commands in the table consist of
write and update operations. A write operation loads a
16-bit data word from the 32-bit shift register into the
input register. In an update operation, the data word is
copied from the input register to the DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
LTC2631
23
2631fb
OPERATION
Table 3. Command Codes
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power Up) DAC Register
0 0 1 1 Write to and Update (Power Up) DAC Register
0 1 0 0 Power Down
0 1 1 0 Select Internal Reference
0 1 1 1 Select External Reference
*Command codes not shown are reserved and should not be used.
Reference Modes
For applications where an accurate external reference is
not available, the LTC2631 has a user-selectable, integrated
reference. The LTC2631-LM/LTC2631-LZ provide a full-
scale output of 2.5V. The LTC2631-HM/LTC2631-HZ provide
a full-scale output of 4.096V. The internal reference can be
useful in applications where the supply voltage is poorly
regulated. Internal Reference mode can be selected by using
command 0110, and is the power-on default for LTC2631-
HZ/LTC2631-LZ, as well as for LTC2631-HM/LTC2631-LM
when REF_SEL is tied high.
The 10ppm/°C, 1.25V (LTC2631-LM/LTC2631-LZ) or
2.048V (LTC2631-HM/LTC2631-HZ) internal reference
is available at the REF pin. Adding bypass capacitance
to the REF pin will improve noise performance; 0.33µF
is recommended, and up to 10µF can be driven without
oscillation. This output must be buffered when driving
external DC load current.
Alternatively, the DAC can operate in External Reference
mode using command 0111. In this mode, an input voltage
supplied externally to the REF pin provides the reference
(0V ≤ VREF ≤ VCC) and the supply current is reduced.
External Reference mode is the power-on default for
LTC2631-HM/LTC2631-LM when REF_SEL is tied low.
The reference mode of LTC2631-HZ/LTC2631-LZ can be
changed only by software command. The same is true for
LTC2631-HM/LTC2631-LM after power-on, after which the
logic state on REF_SEL is ignored.
Power-Down Mode
For power-constrained applications, the LTC2631’s power-
down mode can be used to reduce the supply current
whenever the DAC output is not needed. When in power
down, the buffer amplifi er, bias circuit, and reference
circuit are disabled and draw essentially zero current. The
DAC output is put into a high-impedance state, and the
output pin is passively pulled to ground through a 200k
resistor. Input and DAC register contents are not disturbed
during power down.
Figure 3. Command and Data Input Format
C3
1ST DATA BYTE
Input Word (LTC2631-12)
Write Word Protocol for LTC2631
C2 C1 C0 XXXXD9D10D11
SWA
SLAVE ADDRESS 1ST DATA BYTE
D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
A 2ND DATA BYTE A 3RD DATA BYTE A P
2631 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2631-10)
C2 C1 C0 XXXXD7D8D9 D6 D5 D4 D3 D2 D1 D0 XXXXX
X
2ND DATA BYTE 3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2631-8)
C2 C1 C0 XXXXD5D6D7 D4 D3 D2 D1 D0 XXXXXXX
X
2ND DATA BYTE 3RD DATA BYTE
LTC2631
24
2631fb
OPERATION
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.8µA
maximum (C and I grades) and the REF pin becomes high
impedance (typically > 1G).
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 3. The
DAC is powered up and its voltage output is updated.
Normal settling is delayed while the bias, reference, and
amplifi er circuits are re-enabled. When the REF pin output
is bypassed to GND with 1nF or less, the power-up delay
time is 20µs for settling to 12-bits. This delay increases
to 200µs for 0.33µF, and 10ms for 10µF.
Voltage Output
The LTC2631’s integrated rail-to-rail amplifi er has guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifi ers ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifi ers DC output
impedance is 0.1 when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50 typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50 • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Charac-
teristics section.
The amplifi er is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage-output device, the output is lim-
ited to voltages within the supply range.
Since the analog output of the DAC cannot go below ground,
it may limit the lowest codes, as shown in Figure 5b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at VCC, as shown in Figure 5c. No full-scale limiting can
occur if VREF is less than VCC – FSE.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2631 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1). Note that the LTC2631 is no more susceptible to this
effect than any other parts of this type; on the contrary, it
allows layout-based performance improvements to shine
rather than limiting attainable performance with excessive
internal resistance.
Another technique for minimizing errors is to use a sepa-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2631 is sinking large currents, this current fl ows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confi ne digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
LTC2631
25
2631fb
OPERATION
Figure 4. Typical LTC2631 Input Waveform—Programming 12-Bit DAC Output for Full-Scale
ACK ACK
91234567891234567812345678912345678 9
2631 F04
ACK
START
X = DON’T CARE
STOP
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
SDA A6 A5 A4 A3 A2 A1 A0
SCL
VOUT
C2C3
C3 C2 C1 C0 X X X X
C1 C0 X X X X ACK
COMMAND
D11 D10 D9 D8 D7 D6 D5 D4
MS DATA
D3 D2 D1 D0 X X X X
LS DATA
A6 A5 A4 A3 A2 A1 A0 W
SLAVE ADDRESS
LTC2631
26
2631fb
OPERATION
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits)
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
2631 F05
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
0V 2,0480 4,095
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
LTC2631
27
2631fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.22 – 0.36
8 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) TS8 TSOT-23 0802
2.90 BSC
(NOTE 4)
0.65 BSC
1.95 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.52
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
LTC2631
28
2631fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 1108 REV B • PRINTED IN USA
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Programmable ±5V Output
SDA
SCL
CA0
0.1µF
VOUT = ±5V
VCC REF
VOUT
I2C BUS LTC2631A
-LM12
2631 TA03
+
LTC2054
GND
REF_SEL
8
3
2
1
4
56
7
5V
CA0
5V
–10V
10V
5
4
6
7
8
9
10
1
2
3
5
4
3
1
2
LT1991
M9
M3
M1
P1
P3
P9
VEE
VCC
OUT
REF
0.1µF
0.1µF
0.1µF
1.7k 1.7k