74AUP2G14GM - NXP Semiconductors

1. General description

The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept

standard input signals. They are capable of transforming slowly changing input signals

into sharply defined, jitter-free output signals.

This device ensures a very low static and dynamic power consumption across the entire

VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF

circuitry disables the outpu t, preventing the damaging ba ckflow current through the device

when it is powered down.

The input s switch at differ ent points fo r positive and negative-going si gnals. The difference

between the po sit ive vo ltage VT+ and the negative voltage VT is defined as the input

hysteresis voltage VH.

2. Features and benefits

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

ESD protection:

HBM JESD22-A114F Class 3A exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

Low static power consumption; ICC = 0.9 A (maximum)

Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of VCC

IOFF circuitry provides partial Power-down mode operation

Multiple package options

Specified from 40 Cto+85C and 40 Cto+125C

3. Applications

Wave and pulse shaper

Astable multivibrator

Monostable multivibrator

74AUP2G14

Low-power dual Schmitt trigger inverter

Rev. 4 — 1 December 2011 Product data sheet

Product data sheet Rev. 4 — 1 December 2011 2 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

4. Ordering information

5. Marking

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

6. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AUP2G14GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363

74AUP2G14GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;

6 terminals; body 1 1.45 0.5 mm SOT886

74AUP2G14GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;

6 terminals; body 1 10.5 mm SOT891

74AUP2G14GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;

6 terminals; body 0.9 1.0 0.35 mm SOT1115

74AUP2G14GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;

6 terminals; body 1.0 1.0 0.35 mm SOT1202

Table 2. Marking

Type number Marking code[1]

74AUP2G14GW pK

74AUP2G14GM pK

74AUP2G14GF pK

74AUP2G14GN pK

74AUP2G14GS pK

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

mnb082

1A 1Y

2A 2Y

mnb083

mnb084

2A 2Y

1A 1Y

Product data sheet Rev. 4 — 1 December 2011 3 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

7. Pinning information

7.1 Pinning

7.2 Pin description

8. Functional description

[1] H = HIGH voltage level; L = LOW voltage level.

Fig 4. Pin configuration SOT363 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 ,

SOT1115 and SOT1202

74AUP2G14

1A 1Y

GND

2A 2Y

001aad704

VCC

74AUP2G14

GND

001aad705

VCC

Transparent top view

74AUP2G14

GND

001aad663

VCC

Transparent top view

Table 3. Pin description

Symbol Pin Description

1A 1 data input

GND 2 ground (0 V)

2A 3 data input

2Y 4 data output

VCC 5 supply voltage

1Y 6 data output

Table 4. Function table[1]

Input Output

nA nY

Product data sheet Rev. 4 — 1 December 2011 4 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

9. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.

For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.

10. Recommended operating conditions

11. Static characteristics

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +4.6 V

IIK input clamping current VI<0V 50 - mA

VIinput voltage [1] 0.5 +4.6 V

IOK output clamping current VO<0V 50 - mA

VOoutput voltage Active mode an d Pow e r-d ow n m ode [1] 0.5 +4.6 V

IOoutput cur r en t VO=0 VtoV

CC -20 mA

ICC supply current - 50 mA

IGND ground curre nt 50 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb =40 C to +125 C[2] -250mW

Table 6. Recommended operating con ditions

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.8 3.6 V

VIinput voltage 0 3.6 V

VOoutput voltage Active mode 0 VCC V

Power-down mode; VCC =0V 0 3.6 V

Tamb ambient temperature 40 +125 C

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Tamb = 25 C

VOH HIGH-level output voltage VI = VT+ or VT

IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V

IO = 1.1 mA; VCC = 1.1 V 0.75  VCC -- V

IO = 1.7 mA; VCC = 1.4 V 1.11 - - V

IO = 1.9 mA; VCC = 1.65 V 1.32 - - V

IO = 2.3 mA; VCC = 2.3 V 2.05 - - V

IO = 3.1 mA; VCC = 2.3 V 1.9 - - V

IO = 2.7 mA; VCC = 3.0 V 2.72 - - V

IO = 4.0 mA; VCC = 3.0 V 2.6 - - V

Product data sheet Rev. 4 — 1 December 2011 5 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

VOL LOW-level output voltage VI = VT+ or VT

IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V

IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V

IO = 1.7 mA; VCC = 1.4 V - - 0.31 V

IO = 1.9 mA; VCC = 1.65 V - - 0.31 V

IO = 2.3 mA; VCC = 2.3 V - - 0.31 V

IO = 3.1 mA; VCC = 2.3 V - - 0.44 V

IO = 2.7 mA; VCC = 3.0 V - - 0.31 V

IO = 4.0 mA; VCC = 3.0 V - - 0.44 V

IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A

IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A

IOFF additional power-off leakage

current VI or VO = 0 V to 3.6 V;

VCC =0Vto0.2V --0.2 A

ICC supply current VI = GND or VCC; IO = 0 A;

VCC = 0.8 V to 3.6 V --0.5A

ICC additional supply current VI = VCC  0.6 V; IO = 0 A;

VCC =3.3V --40A

CIinput capacitance VI = GND or VCC; VCC = 0 V to 3.6 V - 1.1 - pF

COoutput capacitance VO = GND; VCC = 0 V - 1.7 - pF

Tamb = 40 C to +85 C

VOH HIGH-level output voltage VI = VT+ or VT

IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V

IO = 1.1 mA; VCC = 1.1 V 0.7  VCC -- V

IO = 1.7 mA; VCC = 1.4 V 1.03 - - V

IO = 1.9 mA; VCC = 1.65 V 1.30 - - V

IO = 2.3 mA; VCC = 2.3 V 1.97 - - V

IO = 3.1 mA; VCC = 2.3 V 1.85 - - V

IO = 2.7 mA; VCC = 3.0 V 2.67 - - V

IO = 4.0 mA; VCC = 3.0 V 2.55 - - V

VOL LOW-level output voltage VI = VT+ or VT

IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V

IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V

IO = 1.7 mA; VCC = 1.4 V - - 0.37 V

IO = 1.9 mA; VCC = 1.65 V - - 0.35 V

IO = 2.3 mA; VCC = 2.3 V - - 0.33 V

IO = 3.1 mA; VCC = 2.3 V - - 0.45 V

IO = 2.7 mA; VCC = 3.0 V - - 0.33 V

IO = 4.0 mA; VCC = 3.0 V - - 0.45 V

IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A

IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A

Table 7. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 1 December 2011 6 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

IOFF additional power-off leakage

current VI or VO = 0 V to 3.6 V;

VCC =0Vto0.2V --0.6 A

ICC supply current VI = GND or VCC; IO = 0 A;

VCC = 0.8 V to 3.6 V --0.9A

ICC additional supply current VI = VCC  0.6 V; IO = 0 A;

VCC =3.3V --50A

Tamb = 40 C to +125 C

VOH HIGH-level output voltage VI = VT+ or VT

IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.11 - - V

IO = 1.1 mA; VCC = 1.1 V 0.6  VCC -- V

IO = 1.7 mA; VCC = 1.4 V 0.93 - - V

IO = 1.9 mA; VCC = 1.65 V 1.17 - - V

IO = 2.3 mA; VCC = 2.3 V 1.77 - - V

IO = 3.1 mA; VCC = 2.3 V 1.67 - - V

IO = 2.7 mA; VCC = 3.0 V 2.40 - - V

IO = 4.0 mA; VCC = 3.0 V 2.30 - - V

VOL LOW-level output voltage VI = VT+ or VT

IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V

IO = 1.1 mA; VCC = 1.1 V - - 0.33  VCC V

IO = 1.7 mA; VCC = 1.4 V - - 0.41 V

IO = 1.9 mA; VCC = 1.65 V - - 0.39 V

IO = 2.3 mA; VCC = 2.3 V - - 0.36 V

IO = 3.1 mA; VCC = 2.3 V - - 0.50 V

IO = 2.7 mA; VCC = 3.0 V - - 0.36 V

IO = 4.0 mA; VCC = 3.0 V - - 0.50 V

IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A

IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A

IOFF additional power-off leakage

current VI or VO = 0 V to 3.6 V;

VCC =0Vto0.2V --0.75 A

ICC supply current VI = GND or VCC; IO = 0 A;

VCC = 0.8 V to 3.6 V --1.4A

ICC additional supply current VI = VCC  0.6 V; IO = 0 A;

VCC =3.3V --75A

Table 7. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 1 December 2011 7 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

12. Dynamic characteristics

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.

Symbol Parameter Conditions 25 C40 C to +125 CUnit

Min Typ[1] Max Min Max

(85 C) Max

(125 C)

CL = 5 pF

tpd propagation delay nA to nY; see Figure 7 [2]

VCC = 0.8 V - 19.9 - - - - ns

VCC = 1.1 V to 1.3 V 2.7 5.9 11.0 2.4 11.1 11.2 ns

VCC = 1.4 V to 1.6 V 2.6 4.3 6.6 2.4 7.1 7.4 ns

VCC = 1.65 V to 1.95 V 2.1 3.7 5.4 2.0 6.0 6.2 ns

VCC = 2.3 V to 2.7 V 2.0 3.0 4.1 1.7 4.5 4.7 ns

VCC = 3.0 V to 3.6 V 1.9 2.8 3.6 1.5 3.9 4.0 ns

CL = 10 pF

tpd propagation delay nA to nY; see Figure 7 [2]

VCC = 0.8 V - 23.4 - - - - ns

VCC = 1.1 V to 1.3 V 2.9 6.8 12.7 2.8 12.8 12.9 ns

VCC = 1.4 V to 1.6 V 2.8 5.0 7.7 2.6 8.2 8.6 ns

VCC = 1.65 V to 1.95 V 2.7 4.2 6.2 2.5 6.7 7.1 ns

VCC = 2.3 V to 2.7 V 2.3 3.6 4.8 2.1 5.2 5.5 ns

VCC = 3.0 V to 3.6 V 2.1 3.3 4.3 2.0 4.5 4.7 ns

CL = 15 pF

tpd propagation delay nA to nY; see Figure 7 [2]

VCC = 0.8 V - 26.9 - - - - ns

VCC = 1.1 V to 1.3 V 3.3 7.6 14.3 3.0 14.5 14.7 ns

VCC = 1.4 V to 1.6 V 3.3 5.5 8.6 2.9 9.4 9.8 ns

VCC = 1.65 V to 1.95 V 2.8 4.7 7.0 2.8 7.7 8.1 ns

VCC = 2.3 V to 2.7 V 2.7 4.0 5.5 2.4 5.9 6.2 ns

VCC = 3.0 V to 3.6 V 2.6 3.8 4.8 2.2 5.2 5.4 ns

CL = 30 pF

tpd propagation delay nA to nY; see Figure 7 [2]

VCC = 0.8 V - 37.3 - - - - ns

VCC = 1.1 V to 1.3 V 4.0 9.8 18.7 3.9 19.6 20.0 ns

VCC = 1.4 V to 1.6 V 3.7 7.1 11.2 3.8 12.3 12.9 ns

VCC = 1.65 V to 1.95 V 3.6 6.0 9.1 3.6 10.0 10.6 ns

VCC = 2.3 V to 2.7 V 3.5 5.2 6.9 3.2 7.5 7.9 ns

VCC = 3.0 V to 3.6 V 3.3 4.8 6.1 3.1 7.1 7.4 ns

Product data sheet Rev. 4 — 1 December 2011 8 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

[1] All typical values are measured at nominal VCC.

[2] tpd is the same as tPLH and tPHL.

[3] All specified values are the average typical values over all stated loads.

[4] CPD is used to determine the dynamic power dissipation (PD in W).

PD=C

PD VCC2fiN+(CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of the outputs.

13. Waveforms

CL = 5 pF, 10 pF, 15 pF and 30 pF

CPD power dissipation

capacitance fi = 1 MHz; VI=GNDto V

CC [3][4]

VCC = 0.8 V - 2.6 - - - - pF

VCC = 1.1 V to 1.3 V - 2.7 - - - - pF

VCC = 1.4 V to 1.6 V - 2.9 - - - - pF

VCC = 1.65 V to 1.95 V - 3.1 - - - - pF

VCC = 2.3 V to 2.7 V - 3.7 - - - - pF

VCC = 3.0 V to 3.6 V - 4.3 - - - - pF

Table 8. Dynam ic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.

Symbol Parameter Conditions 25 C40 C to +125 CUnit

Min Typ[1] Max Min Max

(85 C) Max

(125 C)

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 7. T he d ata input (nA) to output (nY) propagation delays

mna344

PHL

PLH

nA input

nY output

GND

Table 9. Measurement points

Supply voltage Output Input

VCC VMVMVItr = tf

0.8 V to 3.6 V 0.5  VCC 0.5  VCC VCC  3.0 ns

Product data sheet Rev. 4 — 1 December 2011 9 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

[1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, set-up and hold times and pulse width

RL=1M.

14. Transfer characteristics

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be e qual to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 8. Test circuit for measuring switching times

001aac521

DUT

VIVO

EXT

5 kΩ

Table 10. Test data

Supply voltage Load VEXT

VCC CLRL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ

0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 Mopen GND 2  VCC

Table 11. Transfer characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.

Symbol Parameter Conditions 25 C40 C to +125 CUnit

Min Typ Max Min Max

(85 C) Max

(125 C)

VT+ positive-going

threshold voltage see Figure 9 and Figure 10

VCC = 0.8 V 0.30 - 0.60 0.30 0.60 0.62 V

VCC = 1.1 V 0.53 - 0.90 0.53 0.90 0.92 V

VCC = 1.4 V 0.74 - 1.11 0.74 1.11 1.13 V

VCC = 1.65 V 0.91 - 1.29 0.91 1.29 1.31 V

VCC = 2.3 V 1.37 - 1.77 1.37 1.77 1.80 V

VCC = 3.0 V 1.88 - 2.29 1.88 2.29 2.32 V

VTnegative-going

threshold voltage see Figure 9 and Figure 10

VCC = 0.8 V 0.10 - 0.60 0.10 0.60 0.60 V

VCC = 1.1 V 0.26 - 0.65 0.26 0.65 0.65 V

VCC = 1.4 V 0.39 - 0.75 0.39 0.75 0.75 V

VCC = 1.65 V 0.47 - 0.84 0.47 0.84 0.84 V

VCC = 2.3 V 0.69 - 1.04 0.69 1.04 1.04 V

VCC = 3.0 V 0.88 - 1.24 0.88 1.24 1.24 V

Product data sheet Rev. 4 — 1 December 2011 10 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

15. Waveforms transfer characteristics

VHhysteresis voltage (VT+ VT); see Figure 9,

Figure 10, Figure 11 and

Figure 12

VCC = 0.8 V 0.07 - 0.50 0.07 0.50 0.50 V

VCC = 1.1 V 0.08 - 0.46 0.08 0.46 0.46 V

VCC = 1.4 V 0.18 - 0.56 0.18 0.56 0.56 V

VCC = 1.65 V 0.27 - 0.66 0.27 0.66 0.66 V

VCC = 2.3 V 0.53 - 0.92 0.53 0.92 0.92 V

VCC = 3.0 V 0.79 - 1.31 0.79 1.31 1.31 V

Table 11. Transfer characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.

Symbol Parameter Conditions 25 C40 C to +125 CUnit

Min Typ Max Min Max

(85 C) Max

(125 C)

VT+ and VT limits at 70 % and 20 %.

Fig 9. Transfer characteristic Fig 10. Definition of VT+, VT and VH

mna207

VHVT+

VT−

mna208

T+

T−

Fig 11. Typical transfer characteristics; VCC = 1.8 V

VI (V)

0 2.01.60.8 1.20.4

001aad691

160

240

ICC

(μA)

Product data sheet Rev. 4 — 1 December 2011 11 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

16. Application information

The slow input rise and fall times cause additional power dissipation, this can be

calculated using the following formula:

Padd =f

i(trICC(AV) +t

fICC(AV))VCC where:

Padd = additional power dissipation (W);

fi= input frequency (MHz) ;

tr=rise time (ns); 10%to90%;

tf= fall time (ns); 90 % to 10 %;

ICC(AV) = average additional supply current (A).

Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 13.

An example of a relaxation circuit using the 74AUP2G14 is shown in Figure 14.

Fig 12. Typical transfer characteristics; VCC = 3.0 V

001aad692

VI (V)

0 3.02.01.0

400

800

1200

ICC

(μA)

Product data sheet Rev. 4 — 1 December 2011 12 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

(1) Positive-going edge.

(2) Negative-going edge.

Fig 13. Average ICC as a function of VCC

001aad027

VCC (V)

0.8 3.82.81.8

0.1

0.2

0.3

ΔICC(AV)

(mA)

(1)

(2)

Average values for variable a are given in Table 12.

Fig 14. Relaxation oscillator

mna035

---1

aRC

-----------------

=

Table 12. Variable values

Supply voltage Variable a

1.1 V 1.28

1.5 V 1.22

1.8 V 1.24

2.8 V 1.34

3.3 V 1.45

Product data sheet Rev. 4 — 1 December 2011 13 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

17. Package outline

Fig 15. Package outline SOT363 (SC-88)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT363 SC-88

wBM

pin 1

index A

detail X

vMA

0 1 2 mm

scale

132

456

Plastic surface-mounted package; 6 leads SOT363

UNIT A1

max bpcDEe1HELpQywv

mm 0.1 0.30

0.20 2.2

1.8

0.25

0.10 1.35

1.15 0.65

1.3 2.2

2.0 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15 0.25

0.15

1.1

0.8

04-11-08

06-03-16

Product data sheet Rev. 4 — 1 December 2011 14 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

Fig 16. Package outline SOT886 (XSON6)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT886 MO-252

SOT886

04-07-15

04-07-22

DIMENSIONS (mm are the original dimensions)

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 1.5

1.4 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

6×

(2)

4×

(2)

Product data sheet Rev. 4 — 1 December 2011 15 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

Fig 17. Package outline SOT891 (XSON6)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT891

05-04-06

07-05-15

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

mm 0.20

0.12 1.05

0.95 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.350.55

max

0.5 0.04

6×

(1)

4×

(1)

Note

1. Can be visible in some manufacturing processes.

Product data sheet Rev. 4 — 1 December 2011 16 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

Fig 18. Package outline SOT1115 (XSON6)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1115

sot1115_po

10-04-02

10-04-07

Unit

mm max

nom

min

0.35 0.04 0.95

0.90

0.85

1.05

1.00

0.95 0.55 0.3 0.40

0.35

0.32

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON6: extremely thin small outline package; no leads;

6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1

index area

(4×)(2)

e1e1

321

6 5 4

(6×)(2) A1A

Product data sheet Rev. 4 — 1 December 2011 17 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

Fig 19. Package outline SOT1202 (XSON6)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1202

sot1202_po

10-04-02

10-04-06

Unit

mm max

nom

min

0.35 0.04 1.05

1.00

0.95

1.05

1.00

0.95 0.55 0.35 0.40

0.35

0.32

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON6: extremely thin small outline package; no leads;

6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1

index area

(4×)(2)

e1e1

123

6 5 4

(6×)(2)

Product data sheet Rev. 4 — 1 December 2011 18 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

18. Abbreviations

19. Revision history

Table 13. Abbreviations

Acronym Description

CDM Charged Device Mo del

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

Table 14. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AUP2G14 v.4 20111201 Product data sheet - 74AUP2G14 v.3

Modifications: •Legal pages updated.

74AUP2G14 v.3 20100722 Product data sheet - 74AUP2G14 v.2

74AUP2G14 v.2 20090703 Product data sheet - 74AUP2G14 v.1

74AUP2G14 v.1 20061219 Product data sheet - -

Product data sheet Rev. 4 — 1 December 2011 19 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semico nductors’ aggregate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specificati on for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 1 December 2011 20 of 21

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipmen t or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or f ailed product claims result ing from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

20.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74AUP2G14

Low-power dual Schmitt trigger inverter

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 1 December 2011

Document identifier: 74AUP2G14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Functional description . . . . . . . . . . . . . . . . . . . 3

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

10 Recommended operating conditions. . . . . . . . 4

11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

12 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

14 Transfer characteristics . . . . . . . . . . . . . . . . . . 9

15 Waveforms transfer characteristic s. . . . . . . . 10

16 Application information. . . . . . . . . . . . . . . . . . 11

17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18

19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18

20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19

20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19

20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

20.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

21 Contact information. . . . . . . . . . . . . . . . . . . . . 20

22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21