1-Mbit (64K x 16) Static RAM
CY62126DV30 MoBL®
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05230 Rev. *H Revised July 18, 2006
Features
• Very high speed
—55 ns
• Temperature Ranges
—Industrial: –40°C to 85°C
—Automotive: –40°C to 125°C
• Wide voltage range
— 2.2V - 3.6V
• Pin compatible with CY62126BV
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— T ypical active current: 5 mA @ f = fMax (55 ns speed)
• Ultra-low standby power
• Easy memory expansion with CE and OE featur es
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 48-ball VFBGA and
44-pin TSOP Type II packages
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular te lephones. Th e device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when dese lected (CE
HIGH). The input/output pins (I/O0 through I/O15) a re placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified b y the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) i s
LOW , then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress appl ication note “System Design Guidelines” on ht tp://www.cypress.com.
64K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
WE
BLE
BHE
A0
A1
A9
A10
CE
Logic Block Diagram
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 2 of 12
Notes:
2. Typical values are included f or reference only and are not guaranteed or t ested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
3. NC pins are not connected to the die.
4. E3 (DNU) can be left as NC or VSS to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
Product Portfolio
Product Range
VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA) Standby, ISB2
(µA)f = 1 MHz f = fMax
Min. Typ. Max. Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.
CY62126DV30L Automotive 2.2 3.0 3.6 55 0.85 1.5 510 1.5 15
CY62126DV30LL Industrial 55 0.85 1.5 510 1.5 4
Pin Configurations[3, 4]
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
NC
DNU
VCC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24 NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
48-ball VFBGA
Top View
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground
Potential..............................................................−0.3 to 3.9V
DC Voltage Applied to Outputs
in High-Z S tate[6]....................................−0.3V to VCC + 0.3V
DC Input Voltage[6] ................................−0.3V to VCC + 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range Ambient Temperature (TA) VCC[7]
Industrial −40°C to +85°C 2.2V to 3.6V
Automotive −40°C to +125°C 2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
CY62126DV30-55
UnitMin. Typ.[5] Max.
VOH Output HIGH
Voltage 2.2V < VCC < 2.7V IOH = −0.1 mA 2.0 V
2.7V < VCC < 3.6V IOH = −1.0 mA 2.4
VOL Output LOW
Voltage 2.2V < VCC < 2.7V IOL = 0.1 mA 0.4 V
2.7V < VCC < 3.6V IOL = 2.1 mA 0.4
VIH Input HIGH
Voltage 2.2V < VCC < 2.7V 1.8 VCC + 0.3 V
2.7V < VCC < 3.6V 2.2 VCC + 0.3
VIL Input LOW V oltage 2.2V < VCC < 2.7V −0.3 0.6 V
2.7V < VCC < 3.6V −0.3 0.8
IIX Input Leakage
Current GND < VI < VCC Ind’l −1+1 µA
Auto −4+4
IOZ Output Leakage
Current GND < VO < VCC, Output Disabled Ind’l −1+1 µA
Auto −4+4
ICC VCC Operating
Supply Current f = fMax = 1/tRC VCC = 3.6V,
IOUT = 0 mA, CMOS
level
510 mA
f = 1 MHz 0.85 1.5
ISB1 Automatic CE
Power-down
Current—
CMOS Inputs
CE > VCC − 0.2V,
VIN > VCC − 0.2V,
VIN < 0.2V,
f = fMax (Address and Data Only),
f = 0 (OE, WE, BHE and BLE)
LInd’l 1.5 5µA
Auto 1.5 15
LL 1.5 4
ISB2 Automatic CE
Power-down
Current—
CMOS Inputs
CE > VCC − 0.2V,
VIN > VCC − 0.2V or
VIN < 0.2V, f = 0, VCC = 3.6V
LInd’l 1.5 5µA
Auto 1.5 15
LL 1.5 4
Notes:
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
6. VIL(min.) = −2.0V for puls e du r a ti o ns less than 20 ns. , VIH(max.) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device operation requires linear ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 µs.
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 4 of 12
AC Test Loads and Waveforms
Data Retention Waveform
Notes:
8. Tested initially and after any design or pr oces changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs.
Capacitance[8]
Parameter Description Test Cond itions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = VCC(typ) 8pF
COUT Output Capacitance 8pF
Thermal Resistance[8]
Parameter Description Test Conditions TSOP VFBGA Unit
ΘJA Thermal Resistance (Junction to Ambient) Still Air , soldered on a 3 x 4.5 inch,
2-layer printed circuit board 55 76 °C/W
ΘJC Thermal Resistance (Junction to Case) 12 11 °C/W
Data Retention Characteristics
Parameter Description Conditions Min. Typ[2] Max. Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current VCC=1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V LInd’l 4µA
LAuto 10
LL Ind’l 3
tCDR[8] Chip Deselect to Data
Retention Time 0ns
tR[9] Operation Recovery Time 100 µs
VCC Typ
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT VTH
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise TIme: 1 V/ns Fall Time: 1 V/ns
Parameters 2.5V 3.0V Unit
R1 16600 1103 Ohms
R2 15400 1554 Ohms
RTH 8000 645 Ohms
VTH 1.2 1.75 Volts
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
CE
VCC
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 5 of 12
Switching Characteristics (Over the Operating Range)[10]
Parameter Description
CY62126DV30-55
UnitMin. Max.
Read Cycle
tRC Read Cycle Time 55 ns
tAA Address to Data Valid 55 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 55 ns
tDOE OE LOW to Data Valid 25 ns
tLZOE OE LOW to Low Z[11] 5ns
tHZOE OE HIGH to High Z[11, 12] 20 ns
tLZCE CE LOW to Low Z[11] 10 ns
tHZCE CE HIGH to High Z[11, 12] 20 ns
tPU CE LOW to Power-up 0ns
tPD CE HIGH to Power-down 55 ns
tDBE BLE/BHE LOW to Data Valid 25 ns
tLZBE BLE/BHE LOW to Low Z[11] 5ns
tHZBE BLE/BHE HIGH to High-Z[11, 12] 20 ns
Write Cycle[13]
tWC Write Cycle Time 55 ns
tSCE CE LOW to Write End 40 ns
tAW Address Set-up to Write End 40 ns
tHA Address Hold from Write End 0ns
tSA Address Set-up to Write Start 0ns
tPWE WE Pulse Width 40 ns
tBW BLE/BHE LOW to Write End 40 ns
tSD Data Set-up to Write End 25 ns
tHD Data Hold from Write End 0ns
tHZWE WE LOW to High Z[11, 12] 20 ns
tLZWE WE HIGH to Low Z[11] 10 ns
Notes:
10.Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of
the specified IOL.
11.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE.
12.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
13.The internal Writ e time of t he memory is de fined by the o verlap of WE, CE = VIL, BHE and/or BLE = VIL. All sig nals must be ACTIVE to initiate a write and any
of these signals can termina te a write by going INACTIVE. The da ta input set-up an d hold timing should be refe renced to the edge of the signa l that terminate s
the write.
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 6 of 12
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
Read Cycle No. 2 (OE Controlled)[15, 16]
Notes:
14.Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
15.WE is HIGH for Read cycle.
16.Address valid prior to or coincident with CE, BHE, BLE transition LOW.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DOE
t
LZOE
tDBE
IMPEDANCE
I
CC
I
SB
HIGH
V
DATA OUT
OE
CE
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 7 of 12
Write Cycle No. 1 (WE Controlled[12, 13, 16, 17, 18]
Write Cycle No. 2 (CE Controlled)[12, 13, 16, 17, 18]
Notes:
17.Data I/O is high-impedance if OE = VIH.
18.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19.During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms(continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN VALID
NOTE19
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
NOTE 19
tBW
tSA
CE
ADDRESS
WE
DATAI/O
OE
BHE/BLE
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 8 of 12
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
Write Cycle No. 4 (BHE/BLE-controlled, OE LOW)[17, 18]
Switching Waveforms(continued)
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
NOTE 19
tBW
CE
ADDRESS
WE
DATAI/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
VALID
NOTE 19
t
BW
tSCE
t
PWE
DATA I/O
ADDRESS
CE
WE
BHE/BLE
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 9 of 12
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
L X X H H High Z Output Disabled Active (ICC)
L H L L L Data Out (I/O0–I/O15)Read Active (ICC)
L H L H L High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)Read Active (ICC)
L L X L L Data In (I/O0–I/O15)Write Active (ICC)
L L X H L High Z (I/O8–I/O15);
Data In (I/O0–I/O7)Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
High Z (I/O0–I/O7)Write Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
55 CY62126DV30LL-55BVI 51-85150 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) Industrial
CY62126DV30LL-55BVXI 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) (Pb-free)
CY62126DV30LL-55ZI 51-85087 44-pin TSOP II
CY62126DV30LL-55ZXI 44-pin TSOP II (Pb-free)
CY62126DV30L-55BVXE 51-85150 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) (Pb-free) Automotive
CY62126DV30L-55ZSXE 51-85087 44-pin TSOP II (Pb-free)
Please contact your local Cypress sales representative for availability of these parts
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 10 of 12
Package Diagrams
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
51-85150-*D
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 11 of 12
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change without notice. C ypr ess S em icon ductor Corporation assumes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered tra demark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams(continued)
44-pin TSOP II (51-85087)
51-85087-*A
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CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H Page 12 of 12
Document History Page
Document Title: CY62126DV30 MoBL® 1-Mbit (64K x 16) Static RAM
Document Number: 38-05230
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 117689 08/27/02 JUI New Data Sheet
*A 127313 06/13/03 MPR Changed From Advanced Status to Preliminary.
Changed ISB2 to 5 µA (L), 4 µA (LL)
Changed ICCDR to 4 µA (L), 3 µA (LL)
Changed CIN from 6 pF to 8 pF
*B 128340 07/22/03 JUI Changed from Preliminary to Final
Add 70-ns speed, updated ordering information
*C 129002 08/29/03 CDY Changed ICC 1 MHz typ from 0.5 mA to 0.85 mA
*D 238050 See ECN A JU Fixed typ o: Changed tDBE from 70 ns to 35 ns
*E 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #8 on page #4
Added Pb-free package ordering information on page # 9
Changed 44-pin TSOP-II package name from Z44 to ZS44
*F 335861 See ECN SYT Added Temperature Ranges in the Features Section on Page # 1
Added Automotive Product Information for CY62126DV30-L for 55 ns
Added ISB1 and ISB2 va lues for Automotive range of CY621 26DV30-L for 55 ns
Added Automotive Information for ICCDR in the Data Retention Characteristics table
Added Pb-free packages in the ordering information
Changed 44-pin TSOP-II package name from ZS44 to Z44
*G 357256 See ECN PCI Added Pin Configuration and Package Diagram for 56-Lead QFN Package
Updated Thermal Characteristics and Ordering Information Table
Added Automotive Specs for IIX and IOZ in the DC Electrical Characteristics table on
Page# 4
*H 486789 See ECN VKN Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901
North First Street” to “198 Champion Cour t”
Removed 45 ns and 70ns Speed bin from Product offering
Removed 56-pin QFN package
Updated Ordering Information Table
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