1-Mbit (64K x 16) Static RAM
CY62126DV30 MoBL®
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05230 Rev. *H Revised July 18, 2006
Features
• Very high speed
—55 ns
• Temperature Ranges
—Industrial: –40°C to 85°C
—Automotive: –40°C to 125°C
• Wide voltage range
— 2.2V - 3.6V
• Pin compatible with CY62126BV
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— T ypical active current: 5 mA @ f = fMax (55 ns speed)
• Ultra-low standby power
• Easy memory expansion with CE and OE featur es
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 48-ball VFBGA and
44-pin TSOP Type II packages
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular te lephones. Th e device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when dese lected (CE
HIGH). The input/output pins (I/O0 through I/O15) a re placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified b y the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) i s
LOW , then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress appl ication note “System Design Guidelines” on ht tp://www.cypress.com.
64K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
WE
BLE
BHE
A0
A1
A9
A10
CE
Logic Block Diagram
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