MAX 9000 Programmable Logic Device Family Features... High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture 5,0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface Built-inJTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149,1-1990 High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1) 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz Fully compliant with the peripheral component interconnect Special Interest Groups (PCI SIG) PCI Local Bus Specification, Revision 2.2 Dual-output macrocell for independent use of combinatorial and registered logic FastTrack Interconnect for fast, predictable interconnect delays Input/output registers with clear and clock enable on all 1/O pins Programmable output slew-rate control to reduce switching noise MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices Configurable expander product-term distribution allowing up to 32 product terms per macrocell Programmable power-saving mode for more than 50% power reduction in each macrecell Table 1. MAX 9000 Device Features Feature EPM93820 EPM9400 EPM9480 EPM9560 EPM9320A EPM9560A Usable gates 6,000 8,000 10,000 12,000 Flipflops 484 580 676 772 Macrocells 320 400 480 560 Logic array blocks (LABs) 20 25 30 35 Maximum user I/O pins 168 159 175 216 tpp, (ns) 10 15 10 10 tesy (ns) 3.0 5 3.0 3.0 teeo (ns) 45 7 48 4.8 font (MHz) 144 118 144 144 Altera Corporation A-DS-M5000-06 471MAX 9000 Programmable Logic Device Family Data Sheet ...and More Features 472 Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable security bit for protection of proprietary designs Software design support and automatic place-and-route provided by Alteras MAX+PLUS II development system on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System /6000 workstations Additional design entry and simulation support provided by EDIF 200 and 30 O netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Alteras Master Programming Unit (MPU), BitBlaster serial download cable, ByteBlaster parallel port download cable, and ByteBlasterMV parallel port download cable, as well as programming hardware from third-party manufacturers Offered in a variety of package options with 84 to 356 pins (see Table 2} Table 2. MAX 90008 Package Options & /O Counts Note (1) Device 84-Pin | 208-Pin | 240-Pin | 280-Pin | 304-Pin | 356-Pin PLCC ROFP ROFP PGA ROFP BGA EPM9320 60 (2) 132 - 168 - 168 EPM9320A | 60 (2) 132 - - - 168 EPM9400 59 (2) 139 159 - - - EPM9480 - 146 175 - - - EPM9560 - 153 191 216 216 216 EPMS560A - 153 191 - - 216 Notes: (y) (2) MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power quad flat pack (RQFP), ceramic pin-grid array (PGA), and ball-grid array (BGA) packages. Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Alfera Devices) in this data book. Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet General Description The MAX 9000 family of in-system-programmable, high-density, high- performance EPLDs is based on Alteras third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROM- based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed prade of the MAX 9000 family is compliant with the PCT Local Bus Specification, Revision 2,2. Table 3 shows the speed grades available for MAX 9000 devices. Table 3. MAX 9000 Speed Grade Availability Device Speed Grade -10 15 20 EPM9320 ae EPM9320A of EPM9400 ww EPM9480 ee ae EPM9560 rf a EPM9560A we Table 4 shows the performance of MAX 9000 devices for typical functions. Table 4. MAX 9000 Performance _Noie (1) Application Macrocells Used Speed Grade Units -10 15 -20 16-bit loadable counter 16 144 118 100 MHz 16-bit up/down counter 16 144 118 100 MHz 16-bit prescaled counter 16 144 118 100 MHz 16-bit address decode 1 5.6 (10) 7.9 (15) 10 (20) ns 16-to-1 multiplexer 1 7.7 (12.1) 10.9 (18) 16 (26) ns Note: (1) Internal logic array block (LAB) pertormance is shown. Numbers in parentheses show external delays trom row input pin to row I/O pin. Altera Corporation The MAX 9000 architecture supports high-density integration of system- level logic functions. It easily integrates multiple programmable logic devices ranging from PALs, GALs, and 22V10s to field-programmable gate array (FPGA) devices and EPLDs. 473MAX 9000 Programmable Logic Device Family Data Sheet All MAX 9000 device packages provide four dedicated inputs for global control signals with large fan-outs. Each I/O pin has an associated I/O cell register with a clock enable control on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. MAX 9000 EPLDs provide 5.0-V in-system programmability (ISP). This feature allows the devices to be programmed and reprogrammed on the printed circuit board (PCB) for quick and efficient iterations during design development and debug cycles. MAX 9000 devices are guaranteed for 100 program and erase cycles. MAX 9000 EPLDs contain 320 to 560 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/ fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. For increased flexibility, each macrocell offers a dual-output structure that allows the register and the product terms to be used independently. This feature allows register-rich and combinatorial- intensive designs to be implemented efficiently. The dual-output structure of the MAX 9000 macrocell also improves logic utilization, thus increasing the effective capacity of the devices. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high-speed parallel expander product terms to provide up to 32 product terms per macrocell. The MAX 9000 family provides programmable speed/ power optimization. Speed-critical portions of a design can run at high speed /full power, while the remaining portions run at reduced speed /low power. This speed /power optimization feature enables the user to configure one or more macrocells to operate at 50% or less power while adding only a nominal timing delay. MAX 9000 devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. MAX 9000 devices offer the MultiVolt feature, which allows output drivers to be set for either 3.3-V or 5.0-V operation in mixed- voltage systems. 474 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet a a BS Functional Description Altera Corporation The MAX 9000 family is supported by Alteras MAX+PLUS I development system, a single, integrated software package that offers schematic, textincluding VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 200 and 3 0 0, LPM, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX- workstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Softiware Data Sheet. MAX 9000 devices use a third-generation MAX architecture that yields both high performance and a high degree of utilization for most applications. The MAX 9000 architecture includes the following elements: Logic array blocks Macrocells Expander product terms (shareable and parallel) FastTrack Interconnect Dedicated inputs 1/O cells RBRRR RE Figure 1 shows a block diagram of the MAX 9000 architecture. 475MAX 9000 Programmable Logic Device Family Data Sheet Figure 1. MAX 9800 Device Block Diagram vO Cell + (100) Logie Array Block (LAB) Fastirack inferconnect Macrocell LAB Local Array 476 Logic Array Blocks The MAX 9000 architecture is based on linking high-performance, flexible logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays that are fed by the LAB local array, as shown in Figure 2 on page 477. Multiple LABs are linked together via the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. The 1/O pins are supported by I/O cells (OCs) located at the end of each row (herizontal) and column (vertical) path of the FastTrack Interconnect. Each LAB is fed by 33 inputs from the row interconnect and 16 feedback signals from the macrocells within the LAB. All of these signals are available within the LAB in their true and inverted form. In addition, 16 shared expander product terms (expanders) are available in their inverted form, for a total of 114 signals that feed each product term in the LAB. Each LAB is also fed by two low-skew global clocks and one global clear that can be used for register control signals in all 16 macrocells. Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet LABs drive the row and column interconnect directly. Each macrocell can drive out of the LAB onto one or both routing resources. Once on the row or column interconnect, signals can traverse to other LABs or to the IOCs. Figure 2. MAX 9000 Logic Array Plock Row FastTrack intarconnect _ Global Control Select DIN1 ("> : 1 DIN2 [> : j DIN3 (> al] bin4 [> ] \ To Peripheral Bus and por LABs in the Device fe- To Peripheral Bus LAB Local Array (114 Channels) -- Shared Expander Signals Altera Corporation YY Macrocell 1 Macrocell 2 Macracell 3 Macrocell 4 Macrocell 5 Macracell 6 Macrocell 7 Macracell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 ea 16 + Local Feedback ~ Column FastTrack iniarconnect 477MAX 9000 Programmable Logic Device Family Data Sheet Macrocells The MAX 9000 macrocell consists of three functional blocks: the product terms, the product-term select matrix, and the programmable register. The macrocell can be individually configured for both sequential and combinatorial logic operation. See Figure 3. Figure 3. MAX 9800 Macrocell & Local Array LAB Local Array Global Global 33 ow Clear Clocks Fastirack interconnect, inputs 4 Parallel | Expanders trom Oiher Macrocells} 2 Macrocett Alegister = Programmable Input Select Bypass Aeqisier f / To Row or Column FasiTrack Interconnect Clock/ Enable Select Product- Term Select Matrix Local Array Feedback 16 Local Feedbacks 16 Shareable Expander Product Combinatorial logic is implemented in the local array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocells register clear, preset, clock, and clock enable control functions. Two kinds of expander product terms (expanders) are available to supplement macrocell logic resources: Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The MAX+PLUS H software automatically optimizes product-term allocation according to the logic requirements of the design. 478 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet For registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation with programmable clock control. The flipflop can also be bypassed for combinatorial operation. During design entry, the user specifies the desired register type; the MAX+PLU5 I software then selects the most efficient register operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: # By either global clock signal. This mode achieves the fastest clock-to- output performance. # By a global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. # By an array clockimplemented witha product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins (DIN1 and DIN). Each register also supports asynchronous preset and clear functions. As shown in Figure 3, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear inputs to registers are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the dedicated global clear pin (DIN2). The global clear can be programmed for active-high or active-low operation. All MAX 9000 macrocells offer a dual-output structure that provides independent register and combinatorial logic output within the same macrocell. This function is implemented by a process called register packing. When register packing is used, the product-term select matrix allocates one product term to the D input of the register, while the remaining product terms can be used to implement unrelated combinatorial logic. Both the registered and the combinatorial output of the macrocell can feed either the FastTrack Interconnect or the LAB local array. Altera Corporation 479MAX 9000 Programmable Logic Device Family Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, some logic functions are more complex and require additional product terms. Although another macrocell can supply the required logic resources, the MAX 9000 architecture also offers both shareable and parallel expander product terms that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the LAB local array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (thacay + fsexp) is incurred when shareable expanders are used. Figure 4 shows how shareable expanders can feed multiple macrocells. Figure 4. MAX 9000 Shareable Expanders Shareable expanders can be shared by any or ail macrocells in fhe LAP. LAB Local Array 33 Row ii: FastTrack Interconnect Signals Weeeue rererererrreerrrerere: ner rnnennnnn nnn mere nny Macrocefl Product-Term Logic / Product-Term Select Matrix Macrocelt Product-Term Logic 16 Local 16 Shared Feedbacks Expanders 480 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. Figure 5 shows how parallel expanders can feed the neighboring macrocell. Figure 5. MAX 9000 Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. 33 Row Fast?rack interconnect LA} Local Signals Array From . Previous Macrocall Maerocell Product- Term Logic Macrocell Product Term Logic To Next 16Local 16 Shared Macrocell Feedbacks Expanders Altera Corporation 481MAX 9000 Programmable Logic Device Family Data Sheet 482 The MAX+PLUS I Compiler automatically allocates as many as three sets of up to five parallel expanders to macrocells that require additional product terms. Each set of expanders incurs a small, incremental timing delay (tpryp). For example, if a macrocell requires 14 product terms, the Compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 x tppyp. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower- numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7,6, and 5. Within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. FastTrack Interconnect Tn the MAX 9000 architecture, connections between macrocells and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal and vertical routing channels that traverse the entire device. This device-wide routing structure provides predictable performance even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. Figure 6 shows the interconnection of four adjacent LABs with row and column interconnects. Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Figure 6. MAX 9000 Device interconnect Resources Each LAP is named on the basis of ifs physical row (A, B, , efc.) and column (1, 2, 3, efe.) position within the device. , ~. See Figure . f for delaits. Column FastTrack interconnect ~~ Row FastTrack ~ inferconnect loca <7) See Figure ? |, for details. LAB AT ~|" The LABs within MAX 9000 devices are arranged into a matrix of columns and rows. Table 5 shows the number of columns and rews in each MAX 9000 device. Table 5. MAX 9000 Rows & Columns Altera Corporation Devices Rows Columns EPM9320, EPM9320A 5 EPM9400 5 5 EPM9480 6 5 EPMs560, EPM9560A 7 5 483MAX 9000 Programmable Logic Device Family Data Sheet Each row of LABs has a dedicated row interconnect that routes signals both into and out of the LABs in the row. The row interconnect can then drive 1/O pins or feed other LABs in the device. Each row interconnect has a total of 96 channels. Figure 7 shows how a macrocell drives the row and column interconnect. Figure 7. MAX 9000 LAB Connections to Row & Column interconnect 96 Row Channels Dual-oufput macrocell feeds both FastTrack inferconnect and LAB local array. 48 Column Channels Each macrocell drives A A one row channel. t Ah o> tet) + 1 Local Array Each macrocell drives one of three column channels. Additional multiplexer provides column-to-row path if macrocell drives row channel. 484 Each macrocell in the LAB can drive one of three separate column interconnect channels. The column channels run vertically across the entire device, and are shared by the macrocells in the same column. The MAX+PLUS I Compiler optimizes connections te a column channel automatically. Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet A row interconnect channel can be fed by the output of the macrocell through a 4-to-1 multiplexer that the macrocell shares with three column channels. If the multiplexer is used for a macrocell-to-row connection, the three column signals can access another row channel via an additional 3-to-1 multiplexer. Within any LAB, the multiplexers provide all 48 column channels with access to 32 row channels. Row-io-1/0 Cell Connections Figure 8 illustrates the connections between row interconnect channels and IOCs. An input signal from an IOC can drive two separate row channels. When an JOC is used as an output, the signal is driven by a 10-to-1 multiplexer that selects the row channels. Each end of the row channel feeds up to eight IOCs on the periphery of the device. Figure & MAX 90008 Rew-to-l0 Connections 10 | a | . Row FastTrack L Interconnect 4 e 96 r Each 100 is driven by / a 10-fo-1 multiplexer. Each i0 can drive up fo two row channels. Column-to-l/0 Cell Connections Each end of a column channel has up to 10 IOCs (see Figure 9). An input signal from an IOC can drive two separate column channels. When an IOC is used as an output, the signal is driven by a 17-to-1 multiplexer that selects the column channels. Altera Corporation 485MAX 9000 Programmable Logic Device Family Data Sheet 486 Figure 9. MAX 96680 Column-io-i0C Cannections loc 1019] Each IOC is driven by a T7-to-7 muftiplexer~~__ Each lOC can drive up WV WF to two cofumnA channels. Column FastTrack Interconnect Dedicated Inputs In addition to the general-purpose I/O pins, MAX 9000 devices have four dedicated input pins. These dedicated inputs provide low-skew, device- wide signal distribution to the LABs and IOCs in the device, and are typically used for global clock, clear, and output enable control signals. The global control signals can feed the macrocell or IOC clock and clear inputs, as well as the IOC output enable. The dedicated inputs can also be used as general-purpose data inputs because they can feed the row FastTrack Interconnect (see Figure 2 on page 477). 1/0 Cells Figure 10 shows the IOC block diagram. Signals enter the MAX 9000 device from either the 1/O pins that provide general-purpose input capability or from the four dedicated inputs. The IOCs are located at the ends of the row and column interconnect channels. Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Figure 10. MAX $000 I0 Peripheral Control Bus [12..0] *- cc ars To Row or ~@ - Column FastTrack Interconnect Ai Fram Row or tI Column FastTrack D Q Interconnect Slew-Rate Control I/O pins can be used as input, output, or bidirectional pins. Each IOC has an IOC register with a clock enable input. This register can be used either as an input register for external data that requires fast setup times, or as an output register for data that requires fast clock-to-output performance. The IOC register clock enable allows the global clock to be used for fast clock-to-output performance, while maintaining the flexibility required for selective clocking. The clock, clock enable, clear, and output enable controls for the IOCs are provided by a network of 1/0 control signals. These signals can be supplied by either the dedicated input pins or internal logic. The IOC control-signal paths are designed to minimize the skew across the device. All control-signal sources are buffered onto high-speed drivers that drive the signals around the periphery of the device. This peripheral bus can be configured to provide up to eight output enable signals, up to four clock signals, up to six clock enable signals, and up to two clear signals. Table 6 on page 488 shows the sources that drive the peripheral bus and how the IOC control signals share the peripheral bus. Altera Corporation 487MAX 9000 Programmable Logic Device Family Data Sheet Output Configuration 488 The output buffer in each IOC has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces board-level noise and adds a nominal timing delay to the output buffer delay (fap) parameter. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. The slew rate control affects both rising and falling edges of the output signals. Table 6. Peripheral Pus Sources Peripheral Control Source Signal EPmg9320 | Epmg4o0 | EPmo4so | EPMg560 EPM9320A EPMS560A OF0/ENAO Row GC Row E Row F Row G OE1L/ENAL Row B Row E Row F Row F OEZ /ENAZ Row A Row E Row E Row E OF3/ENA3 Row B Row B Row B Row B OE4/ENA4 Row A Row A Row A Row A OBS Row D Row D Row D Row D OE6 Row G Row C Row C Row G OE7/CLR1 Row B/GokR |Row B/cor |Row B/cor | Row B/cor CLRO/ENAS Row A/GCLR | Row A/GcLR | Row A/GcLR | Row A/GCLR CLKO GCLR1 GCLE1 GCLE1 GCLRL CLE1 GCLK2 GCLEZ GCLK2 GCLK2 CLKZ Row D Row D Row D Row D CLK3 Row C Row C Row C Row G The MAX 9000 device architecture supports the MultiVolt I/O interface feature, which allows MAX 9000 devices to interface with systems of differing supply voltages. The 5.0-V devices in all packages can be set for 3.3- or 5.0-V I/O pin operation. These devices have one set of Vcc pins for internal operation and input buffers (VCCINT), and another set for 1/O output drivers (VCCIO). The VCCINT pins must always be connected to a5.0-V power supply. With a5.0-V Vecynt level, input voltages are at TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet In-System Programma- bility (ISP) Programming with External Hardware 2 8 Altera Corporation The VCCI pins can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with Vccjo levels lower than 4.75 V incur a nominally greater timing delay of tgp instead of top;. MAX 9000 devices can be programmed in-system through a 4-pin JTAG interface. ISP offers quick and efficient iterations during design development and debug cycles. The MAX 9000 architecture internally generates the 12.0-V programming voltage required to program EEPROM cells, eliminating the need for an external 12.0-V power supply to program the devices on the board. During ISP, the 1/O pins are tri-stated to eliminate board conflicts. ISP simplifies the manufacturing flow by allowing the devices to be mounted on a printed circuit board with standard pick-and-place equipment before they are programmed. MAX 9000 devices can be programmed by downloading the information via in-circuit testers, embedded processors, or the Altera BitBlaster, ByteBlaster, or ByteBlasterM download cable. (The ByteBlaster cable is obsolete and has been replaced by the ByteBlasterMV cable, which can interface with 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high pin-count packages (e.g., QFP packages) due to device handling. MAX 9000 devices can also be reprogrammed in the field (i.e., product upgrades can be performed in the field via software or medem). In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers platforms have difficulties supporting an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm are marked with an FP suffix in the ordering code. MAX 9000 devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardivare Data Sheet. 489MAX 9000 Programmable Logic Device Family Data Sheet ) IEEE Std. 1149.1 (JTAG) The MAX+PLUS 1H software can use text- or waveform-format test vectors created with the MAX+PLUS I] Text Editor or Waveform Editor to test a programmed device. For added design verification, designers can perform functional testing to compare the functional behavior of a MAX 9000 device with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices. oe For more information, see Programming Hardware Manufacturers. MAX 9000 devices support JIAG BST circuitry as specified by IEEE Std. 1149.1-1990, Table 7 describes the JTAG instructions supported by the MAX 9000 family. The pin-out tables starting on page 505 show the Bo un da ry-Sca n location of the JTAG control pins for each device. If the JTAG interface is Support not required, the JTAG pins are available as user 1/O pins. Table 7. MAX 9000 JTAG instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS Places the 1-bit bypass register between the TDI and TDo pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. IDCODE Selects the IDCODE register and places it between TDI and TDo, allowing the IDCODE to be shifted out of TDo. Supported by the EPM9320A, EPM9400, EPM9480, and EPMS560A devices only. UESCODE Selects the user electronic signature (UESCODE) register and allows the UESCODE ta be shifted aut of TDo serially. This instruction is supported by MAX SO00A devices only. ISP Instructions These instructions are used when programming MAX 8000 devices via the JTAG ports with the BitBlaster or ByteBlasterMV download cable, or using a Jam File (jam), Jam Byte-Code File (.jJbe), or Serial Vector Format (.svf} File via an embedded processor or test equipment. 490 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet The instruction register length for MAX 9000 devices is 10 bits. EPM9320A and EPM9560A devices support a 16-bit UESCODE register. Tables 8 and 9 show the boundary-scan register length and device IDCODE information for MAX 9000 devices. Table 8. MAX 9000 Boundary-Scan Register Length Device Boundary-Scan Register Length EPMg320, EPM9320A 504 EPMs400 552 EPMs480 600 EPM8560, EPM9560A 648 Table 9. 32-Bit MAX 9008 Device IDCODE Note (1) Device IDCODE (32 Bits) Version Part Number Manufacturer's 1 (4 Bits) (16 Bits) (2) Identity (11 Bits) | (1 Bit) EPM9320A (3) | G000 |1001 9011 9910 OO00] 09901101110 1 EPM9400 0000 11001 0100 cO00 OoOD] Of001101110 1 EPM9480 0000 11001 0100 1000 oooD] of001101110 1 EPMS560A (3) | 0000 |1001 0101 0110 o000] 00001101110 1 Notes: (1) The IDCODEs least significant bit (LSB) is always 1. (2) The most significant bit (MSB) is on the left. (3) Although the EPM9320A and EPM9560A devices support the IDCODE instruction, the EPM9320 and EPM9560 devices do not. Figure 11 shows the timing requirements for the JTAG signals. Altera Corporation 491MAX 9000 Programmable Logic Device Family Data Sheet Figure 17. MAX 9800 JTAG Waveforms TDI x x x xX TCK TDG Signal toa Be Captured Signal to Be Driven Table 10 shows the JTAG timing parameters and values for MAX 9000 devices. Table 10. JTAG Timing Parameters & Values for MAX 9000 Devices Symbol Parameter Min | Max | Unit tucp TCK clock period 100 ns tcH TCK clock high time 50 ns Tct TCK clock low time 50 ns typsy | JTAG port setup time 20 ns typH JTAG port hald time 45 ns typco | JTAG port clock to output 25 |] ns typzx | JTAG port high impedance te valid output 25 ns typxz | JTAG port valid output to high impedance 25 ns tussu | Capture register setup time 20 ns Tsu Capture register hold time 45 ns tusco | Update register clack to output 25 | ns tiszx Update register high impedance to valid output 25 ns tysxz | Update register valid output to high impedance 25 ns * = ae For detailed information on JTAG operation in MAX 9000 devices, refer to Application Note 39 (IEEE 1149.1 (TAG) Boundary-Scan Testing in Altera Devices). 492 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Programmable Speed/Power Control Design Security Generic Testing Altera Corporation MAX 9000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. Because most logic applications require only a small fraction of all gates to operate at maximum frequency, this feature allows total power dissipation to be reduced by 50% or more. The designer can program each individual macrocell in a MAX 9000 device for either high-speed (i.e., with the Turbo Bit option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. Asa result, speed-critical paths in the design can run at high speed, while remnaining paths operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (,p,) for the LAB local array delay (f,0ca1)- All MAX 9000 EPLDs contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security, because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is erased. MAX 9000 EPLDs are fully functionally tested. Complete testing of each programmable EEPROM bit and all logic functionality ensures 100% programming yield. AC test measurements are taken under conditions equivalent to these shown in Figure 12. Test patterns can be used and then erased during the early stages of the production flow. Figure 12. MAX 9000 AC Test Conditions Power supply transients can affect AC vee measurements. Simultaneous transitions of multiple outputs should be avoided for 4642 <2 accurate measurement. Threshold fests (703.2) = must not be performed under AC Device To Test Output System condifions. Large-amplitude, fast ground- current transients normally occur as the device outputs discharge the load capacitances. When these transients flow 2502 Cc >_4 itic j (8.06 KQ) = C1 (includes through the parasitic inductance between < JIG capacitance) the device ground pin and the test sysfeM ying input ground, significant reductions in rise and fall observable noise immunity can resuit. limes < 3ns Numbers in parentheses are for 3.3-V outputs. Numbers without parentheses are for 5.0-V devices or outputs. 493MAX 9000 Programmable Logic Device Family Data Sheet Operating Tables 11 through 17 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and C on d iti ons capacitance for MAX 9000 devices. Table 11. MAX 9000 Device Absoiute Maximum Ratings Note (7) Symbol Parameter Conditions Min Max | Unit Voc Supply voltage With respect to ground (2) -2.0 7.0 Vv Vi DC input voltage -2.0 7.0 Vv Vecigp | Supply voltage during in-system -2.0 7.0 Vv programming lout DC output current, per pin -25 25 mA Tstc Storage temperature No bias -65 150 6 TamB Ambient temperature Under bias -65 135 C Ty Junction temperature Ceramic packages, under bias 150 es PQFP and RQFP packages, under bias 135 S Table 12. MAX 9000 Device Recommended Operating Conditions Symbol Parameter Conditions Min Max | Unit Vocint | Supply voltage for internal logic and (3), (4) 4.75 5.25 Vv input butters (4.50) (5.50) Voecio Supply voltage for output drivers, (3), (4) 4.75 5.25 Vv 5.0-V operation (4.50) (5.503 Supply voltage for output drivers, (3), (4) 3.00 3.60 Vv 3.3-V operation (3.00) (3.60) Vecigp | Supply voltage during in-system 4.75 5.25 Vv programming Vi Input voltage (2) -0.5 Vecont+ |] 0.5 Vo Output voltage Veco Vv Ta Ambient temperature For commercial use 70 For industrial use -40 85 6 Ty Junction temperature For commercial use 0 90 C For industrial use 40 105 et tp Input rise time 40 ns te Input fall time 40 ns 494 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Table 13. MAX 9000 Device DC Operating Conditions Notes (4), (6) Symbol Parameter Conditions Min Max | Unit Vin High-level input voltage 2.0 Veonrt | 0.5 Vit Low-level input voltage (2) -0.5 0.8 Vv Vou 5.0-V high-level TTL output voltage lon =4 MA DS, Vecio= 4.75 (7) 2.4 Vv 3.3-V high-level TTL output voltage lon =4 MA DS, Vecio= 3.00 (7) 2.4 Vv 3.3-V high-level CMOS output voltage = | lo = -0.1 MA DC, Vegig = 3.00 V (7) Vecio Vv 0.2 Voi 5.0-V low level TTL output voltage lo, = 12 MA DC, Vegi = 4.75 V (7) 0.45 Vv 3.3-V low-level TTL output voltage lo, = 12 MA DC, Vecig = 3.00 V (7) 0.45 Vv 3.3-V low-level CMOS output voltage lo, = 0.1 mA DC, Vocig = 3.00 V (7) 0.2 Vv I, \/O pin leakage current of dedicated input | V) = Voo or ground (8) -10 10 pA pins loz Tri-state output off-state current Vo=Vec or ground -40 40 pA Table 14. MAX 9000 Device Capacitance: EPM9320, EPM9400, EPM9480 & EPM9560 Devices _ Note (9) Symbol Parameter Conditions Min Max | Unit Com Dedicated input capacitance Vin =0 V.f=1.0 MHz 18 pF Cone Dedicated input capacitance Vin =0 V.f=1.0 MHz 18 pF Coins Dedicated input capacitance Vin =90 V, t= 1.0 MHz 17 pF Coin Dedicated input capacitance Vin =9 V, t= 1.0 MHz 20 pF Cio VO pin capacitance Vin =O, t= 1.0 MHz 12 pF Table 15. MAX 9000A Device Capacitance: EPM9320A & EPMS560A Devices _Noie (9) Symbol Parameter Conditions Min Max | Unit Com Dedicated input capacitance Vin =0 V.f=1.0 MHz 16 pF Cpine Dedicated input capacitance Vin =9 V, f= 1.0 MHz 10 pF Coins Dedicated input capacitance Vin =90 V, t= 1.0 MHz 10 pF Cpina Dedicated input capacitance Vin =90 V, t= 1.0 MHz 12 pF Cio VO pin capacitance Vin =O, t= 1.0 MHz & pF Table 16. MAX 9000 Device Typical Ipe Supply Current Values Symbal Parameter Conditions EPM9320 | EPM9400 | EPM9480 | EPM9560 | Unit lect lec supply current (low-power | = ground, 106 132 140 146 mA mede, standby, typical) no load (10) Altera Corporation 495MAX 9000 Programmable Logic Device Family Data Sheet Table 17. MAX 9000A Device Typical lee Supply Current Values Symbol Parameter Conditions EPM9320A EPM9560A Unit leet lec supply current (low-power mode, standby, typical) V, = ground, na load (70) 99 174 mA Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Minimum DC input on 1/0 pins is -0.5 V and on the tour dedicated input pins is -0.3 V. During transitions, the inputs may undershcot to -2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. (3) Vec must rise monotonically. (4) Numbers in parentheses are for industrial-temperature-range devices. (5) Typical values are for T, = 25 Cand Voc = 5.0 V. (6) These values are specitied under the MAX 9000 recommended operating conditions, shown in Table 12 on page 494. (7) This parameter is measured with 50% ot the outputs each sinking 12 mA. The Ipy parameter reters to high-level TTL or CMOS output current; the I5;, parameter refers to the low-level TTL or CMOS output current. (8) JIAG pin input leakage is typically 60 WA. (9) Capacitance is sampletested only and is measured at 25 C. (10) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. Iec is measured at 0 C. Figure 13 shows typical output drive characteristics for MAX 9000 devices with 5.0-V and 3.3-V Vecjo. Figure 13. Output Drive Characteristics of MAX 9000 Devices 5.0-V 3.3-V 150 150 lon. 120 120 Typical, = ag L Vocig = 5.0 Typical |, 90 Output Room Temperature Output Current (mA) Current (mA) 60 60 lon 30 30 1 1 1 1 1 2 3 4 5 Output Voltage (V) Note: (1) Gutput drive characteristics include the JTAG TDo pin. 496 Note (7) low Vecio = 3.3 V Room Temperature lou 1 1 1 1 1 1 2 335 4 5 Output Voltage (V} Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Timing Model oe SRS 5 Altera Corporation The continuous, high-performance FastTrack Interconnect ensures predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industry- standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point- to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. The MAX 9000 timing model in Figure 14 shows the delays that correspond to various paths and functions in the circuit. This model contains three distinct parts: the macrocell, IOC, and interconnect, including the row and column FastTrack Interconnect and LAB local array paths. Each parameter shown in Figure 14 is expressed as a worst- case value in the internal timing characteristics tables in this data sheet. Hand-calculations that use the MAX 9000 timing model and these timing parameters can be used to estimate MAX 9000 device performance. For more information on calculating MAX 9000 timing delays, see Application Note 77 (Understanding MAX 9000 Timing) in this data book. 497MAX 9000 Programmable Logic Device Family Data Sheet Figure 14. MAX 9000 Timing Modal yO Pin ri tow p tow cu fou eLA 4 low ios Ly rR Delays ws, toi io Global Input 498 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Tables 18 through 21 show timing for MAX 9000 devices. Table 18. MAX 9000 External Timing Characteristics Note (1) Symbol Parameter Conditions Speed Grade Unit 10 15 20 Min | Max | Min | Max | Min | Max tep1 Row I/O pin input te row I/O | C1 = 35 pF (2) 10.0 15.0 20.0 ns pin output top Column I/O pin input to Ci =35pF | EPM9320A 10.8 ns column |/O pin output (2) EPM9320 16.0 23.0 ns EPM9400 16.2 23.2 ns EPMs480 16.4 23.4 ns EPMS560A 11.4 ns EPM9560 16.6 23.6 ns tesu Global clock setup time for I/O 3.0 5.0 6.0 ns cell tey Global clock hold time for I/O 0.0 0.0 0.0 ns cell treo Global clock to I/O cell output | C1 = 35 pF 1.03)| 48 [1.03] 7.0 11.0] 85 ns delay tent Minimum internal global clock | (4) 69 8.5 10.0 ns period font Maximum internal glabal clock | (4) 1449 117.6 100.0 MHz frequency Altera Corporation 499MAX 9000 Programmable Logic Device Family Data Sheet Table 19. MAX 9000 internal Timing Characteristics Note (1) Symbol Parameter Conditions Speed Grade Unit -10 15 -20 Min | Max | Min | Max | Min | Max fap Logic array delay 3.5 40 45 ns trac Logic control array delay 3.5 4.0 4.5 ns fic Array clock delay 3.5 40 45 ns ten Register enable time 3.5 4.0 45 ns fsexp Shared expander delay 3.5 5.0 7.5 ns tpexp Parallel expander delay 0.5 1.0 2.0 ns tap Register delay 0.5 1.0 1.0 ns fcoma Combinatorial delay 0.4 1.0 1.0 ns toy Register setup time 24 3.0 40 ns fy Ragister hold time 2.0 3.5 45 ns fone Register preset time 3.5 4.0 45 ns ferr Register clear time 3.7 40 45 ns terp FastTrack drive delay 0.5 1.0 2.0 ns te pa Low-power adder (5) 10.0 15.0 20.0 ns 500 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Table 20. 10 Delays Symbol Parameter Conditions Speed Grade Unit -10 15 -20 Min | Max | Min | Max | Min | Max fropr VO row output data delay 0.2 0.2 1.5 ns trope VO column output data delay 0.4 0.2 1.5 ns fioc VO control delay (6) 0.5 1.0 2.0 ns fiorp VO register clock-to-output 0.6 1.0 1.5 ns delay trocomg | VO combinatorial delay 0.2 1.0 1.5 ns frosu register setup time betore 2.0 4.0 5.0 ns clock tion VO register hold time after 1.0 1.0 1.0 ns clock trocia lO register clear delay 1.5 3.0 3.0 ns fiorp VO register feedback delay 0.0 0.0 0.5 ns UinREG lO input pad and buffer to /O 3.5 45 5.5 ns register delay fincoma | VC input pad and buffer to row 1.5 2.0 2.5 ns and column delay fon; Output buffer and pad delay, | C1 = 35 pF 1.8 2.5 2.5 ns Slow slew rate = off, fone Output buffer and pad delay, | 1 = 35 pF 2.3 3.5 3.5 ns Slow slew rate = off, tons Output butfer and pad delay, | C1 = 35 pF 8.3 10.0 10.5 ns Slow slew rate = on, Veco =5.0Vor3.3aV hy Output buffer disable delay C1=5pF 2.5 2.5 2.5 ns tg Output buffer enable delay, C1 =35pF 2.5 2.5 2.5 ns Slow slew rate = off, lye Output buffer enable delay, C1 = 35 pF 3.0 3.5 3.5 ns Slow slew rate = off, toxg Output butfer enable delay, C1 = 36 pF 9.0 10.0 10.5 ns Slow slew rate = on, Veco =3.3Vor5.0V Altera Corporation 501MAX 9000 Programmable Logic Device Family Data Sheet Table 21. interconnect Delays Symbol Parameter Conditions Speed Grade Unit 10 15 20 Min | Max | Min | Max | Min | Max trocaL LAB local array delay 0.5 0.5 05 ns trow FastTrack row delay (6) 09 1.4 2.0 ns tcor FastTrack column delay (6) og 1.7 3.0 ns tow _p Dedicated input data delay 40 45 5.0 ns tow_ciw | Dedicated input clock delay 27 3.5 40 ns tow_cia | Dedicated input clear delay 45 5.0 55 ns tow toc | Dedicated input I/O register 2.5 3.5 45 ns clock delay tow_1o Dedicated input I/O register 5.5 6.0 6.5 ns control delay Notes to tables: (1) These values are specitied under the MAX 9000 device recommended operating conditions, shown in Table 12 on page 494, (2) See Applicafion Note 77 (Understanding MAX 9000 Timing) in this data book for more information on test conditions tor tpp, and tpps delays. (3) This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This parameter applies for both global and array clocking as well as both macrocell and 1/0 cell registers. (4) Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB. (5) The typ, parameter must be added to the troc4, parameter for macrocells running in low-power mode. (6) The frow, fcor, and foc delays are worst-case values for typical applications. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. Power Consumption 502 The supply power (P) versus frequency (fax) for MAX 9000 devices can be calculated with the following equation: P= Pint t Pio=leanr x Vcc + Plo The Pyg value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices) in this data book. The Iccnr Value depends on the switching frequency and the application logic. The Iccqyy value is calculated with the following equation: Tcanr = (AX MC ron) + [BX (MCpgy - MCyon)] + (C X MCusep x fMax X togic) Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Altera Corporation The parameters in this equation are shown below: MCyron = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS II Report File (.rpt) MCpry = Number of macrocells in the device MCysgp = Number of macrocells used in the design, as reported in the MAX+PLUS I Report File f Max = Highest clock frequency to the device togic = Average percentage of logic cells toggling at each clock (typically 12.5%) A,B,C Constants, shown in Table 22 Table 22. MAX 9008 ter Equation Constants Device Constant A Constant B Constant C EPMs320 0.84 0.33 0.056 EPM9320A 0.56 0.31 0.024 EPM9400 0.60 0.33 0.053 EPM9480 0.68 0.29 0.064 EPM9560 0.68 0.26 0.052 EPMS560A 0.56 0.34 0.024 This calculation provides an I-- estimate based on typical conditions with no output lead, using a typical pattern of a 16-bit, loadable, enabled up/down counter in each LAB. Actual I- values should be verified during operation, because the measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Figure 15 shows typical supply current versus frequency for MAX 9000 devices. 503MAX 9000 Programmable Logic Device Family Data Sheet Figure 15. fee vs. Frequency for MAX 8008 Devices (Part 1 of 2) 118 MHz Taorks 42 MHz Narr Tera T T T T T 25 so fo 100 125 Frequency (MHz) 118 MHz Frequency (MHz) EPM9320 1000 800 Typical L leg Active {mA} 400 200 o EPM9400 1000 B00 Typical ae log Active (mA) 400 200 o 504 EPM9320A 1000 4 goo 4 Typical legActive 0 {mA} J 400 4 | 144 MHz 200-4 Taras as 89 MHz es Mon-Turhe T T T T T 0 25 50 78 100 125 Frequency (MHz) EPM9480 1000 F B90 118 MHz Typical = I i i ec Active Turks (mA) 400 F 42 MHz 200F L Non-Torbe T T T T T 8 25 50 75 100 126 Frequency (MHz) Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Figure 15. fee vs. Frequency for MAX 8008 Devices (Part 2 of 2) EPM9560 1000 - 800 Typical Boo log Active (mA) 400 r 42 MHz 200 - . L Noa-Turhs 118 MHz 25 50 75 100 125 Frequency (MHz) EPM9560A 1000 F 300 / 00 + Typical 144 MHz log Active (mA) 400 200 r Non- Tart T T T T T 0 25 50 75 100 125 Frequency (MHz) D evi ce Tables 23 through 26 show the dedicated pin names and mumbers for each 2 EPM9320, EPM9320A, EPM9400, EPM9480, EPM9560, and EPM9560A Pin-Outs device package. Table 23. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 7 af2) Note (1) Pin Name | 84-Pin PLCC (2)| 208-Pin ROFP 280-Pin PGA (3) 356-Pin BGA DIN1 1 182 V10 AD13 (GCLE1) DIN2 84 183 U10 AF14 (GCLK2Z) DIN3 {GCLR) | 13 153 V17 AD1 DIN4 (GOR) |72 4 We AC24 TCK 43 78 AS Al8 TMS 55 49 D6 E23 TDI 42 79 C11 A13 TDO 30 108 A18 D3 Altera Corporation 505MAX 9000 Programmable Logic Device Family Data Sheet Table 23. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 2 of2) Noite (1) PinName | 84-Pin PLCC (2)} 208-Pin ROFP 280-Pin PGA (3) 356-Pin BGA GND 6, 18, 24, 25, 48, 114, 20, 24,31, 35, |D4, D5, Di6, E4,E5,E6, | AS, Az2, A25, A26, B25, 61, 67, 70 41, 42, 43, 44, 46, |} E15, E16, F5, F15, Gd, B26, D2, E1, E26, Fe, Gi, 47, 66, 85, 102, G15, H5, H15, J5, J15, K5, |G25, G26, H2, J1, J25, J26, 110,113, 114,115, |K15, L5,L15, M5, M15, N5, | Ke, Le6, M26, N1, N25, 116,118, 121, 122, |N15, P4, P5, P15, P16, R4, | P26, Re, 71, U2, U26, V1, 132, 133, 143, 152, |R5, R15, R16, 74, 75, T16 |V25, W25, Y26, AA2, ABI, 170, 189, 206 AB26, AC26, AE1, AF1, AF2, AF4, AF7, AF20 VCCINT 14, 21, 28, 57, 10, 19, 30, 45,112, |D15, E8, E10, E12, E14, D26, F1, H1, K26, N26, P1, (5.0Vonly) |64, 71 128, 139, 148 R7, R98, R11, R13, R14, U1, W26, AE26, AF25, T14 AF26 VCCIo 15, 37, 60, 79 5, 25, 36, 55, 72, D14, Ev, E98, E11, E13, R6, | Ai, A2, A21, B1, B10, B24, (3.3 of 5.0 V) 91,111, 127,138, |R8, R10, R12, 713, 715 D1, H26, K1, M25, R1, V26, 159, 176, 195 AA1, AC25, AF5, AF8, AF19 No Connect | 29 6, 7, 8, 9, 11, 12, B6, K19, L2, L4, L18, L19, |B4, BS, B6, B7, B8, BS, (N.C.} 13,15, 16,17, 18, |M1,M2,M3,M4,M16,M17, |B11, B12, B13, B14, B15, 109, 140, 141,142, |M18, M19, N1, N2, N3, N4, |B16, B18, B19, B20, B21, 144, 145, 146, 147, N16, N17, N18, N19, P1, B22, Bes, C4, C23, D4, 149, 150, 151 Pz, P3, P17, P18, P19, Ri, |D23, 64, E22, F4, F23, G4, R2, R3, R17, R18, R19, T1, |H4, H23, J23, K4, L4, L23, T2, 73, 717, 718, T19, U1, |N4, P4, P23, R3, R26, T2, U2, U3, U17, U18, U19, V1, | T3, T4, T5, T22, Te3, T24, V2, V19, W1 T25, T26, U3, U4, U5, U22, U23, U24, U25, V2, V3, V4, V5, V22, V23, V24, W1, We, W3, W4, W5, W22, Wes, We4, 1, Y2, Y3, 4, Y5, Y22, Y23, Ye4, Y25, AAS, AA4, AAS, AA22, AA23, AA24, AA25, AAZ6, AB2, AB3, AB4, AB5, AB23, AB24, AB25, AC1, AC2, AC23, AD4, AD23, AE4, AES, AE6, AE7, AES, AE11, AE12, AE14, AE15, AE16, AE18, AE19, AE20, AE21, AE22, AE23 VPP (4) 56 48 C4 E25 Total User 60 132 168 168 VO Pins (5) 506 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet Notes: (1) All pins not listed are user I/O pins. (2) Perform a complete thermal analysis betore committing a design to this device package. See Application Nate 74 (Evaluating Power for Allera Devices) in this data book. (3) EPM9320A devices are not offered in this package. (4) During in-system programming, each devices VPP pin must be connected to the 5.0-V power supply. During normal device operation, the VPP pin is pulled up internally and can be connected to the 5.0-V supply or left unconnected. (5) The user I/O pin count includes dedicated input pins and all 1/O pins. 66, 69, 73 43, 44, 46, 47, 66, 85, 102 110, 113, 114, 115, 116 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 Table 24. EPM9400 Dedicated Pin-Outs Note (1) Pin Name 84-Pin PLCC (2) 208-Pin ROFP 240-Pin ROFP DIN1 (GCLK1) 2 182 210 DIN2 (GCLKZ) 1 183 211 DIN3 (GCLR} 12 153 187 DIN4 (GOE) 74 4 234 TCR 43 78 91 TMS 54 49 68 TDI 42 79 92 TDO 31 108 114 GND 6, 13, 20, 26, 27,47, 60, 114, 20, 24, 31,35, 41,42, 15, 14, 25, 34, 45, 54, 65 66, 81, 96, 110, 115, 126 127, 146, 147, 166, 167 186, 200, 216, 229 VCCINT (5.0 V only) 16, 23, 30, 56, 63, 70 10, 19, 30, 45, 112, 128 139, 148 4, 24, 44 64, 117, 137 157, 177 VCCIO (3.3 or 5.0 V) 17, 37, 59, 80 5, 25, 36, 55, 72,91, 111, | 15, 35, 55, 73, 86, 101, 127, 138, 159, 176, 195 116, 136, 156, 176, 192, 205, 220, 235 No Connect (N.C.) - 6, 7, 8,9, 11, 12,13, 109, |1, 2,3, 6, 7, 8,9, 10, 11, 144, 145, 146,147,149, |12, 13, 168, 169, 170, 150, 151 171, 172, 173, 174, 175, 178, 179, 180, 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 VPP (3) 55 48 67 Total User I/O Pins (4) 59 139 159 Notes: (1) All pins not listed are user I/O pins. (2) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices) in this data book for more information. (3) During in-system programming, each devices VPP pin must be connected to the 5.0-V power supply. During normal device operation, the VPP pin is pulled up internally and can be connected to the 5.0-V supply or lett unconnected. (4) The user I/O pin count includes dedicated input pins and all I/O pins. Altera Corporation 507MAX 9000 Programmable Logic Device Family Data Sheet 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 Table 25. EPM9480 Dedicated Pin-Outs Note (1) Pin Name 208-Pin ROFP 240-Pin ROFP DIN1 (GCLK1) 182 210 DIN@ (GCLK2) 183 211 DIN3 {GCLR) 153 187 DIN4 (GOR) 4 234 TCK 78 91 TMS 49 68 TDI 79 92 TDO 108 114 GND 14, 20, 24, 31, 35,41, 42, |5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 VCCINT (5.0 V only) 10, 19, 30, 45, 112, 128, 139, 148 4, 24, 44, 64, 117, 137, 157,177 vecro (3.3 of 5.0 V) 5, 25, 36,55, 72, 91,111, 127, 138, 159, 176, 195 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 No Connect (N.C.) 6, 7, 8, 9, 109, 149, 150, 151 1, 2,3, 178, 179, 180, 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 VPP (2) 48 67 Total User I/O Pins (3) 146 175 Notes: (1) All pins not listed are user 1/O pins. (2) During in-system programming, each devices VPP pin must be connected to the 5.0-V power supply. During normal device operation, the VPP pin is pulled up internally and can be connected to the 5.0-V supply or left unconnected. (3) The user I/O pin count includes dedicated input pins and all 1/0 pins. 508 Altera Corporation