INTEGRATED CIRCUITS DATA SHEET 74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Product specification Supersedes data of 2003 Jun 20 2004 Mar 22 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A FEATURES DESCRIPTION * 5 V tolerant inputs and outputs, for interfacing with 5 V logic The 74LVC574A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. * Supply voltage range from 1.2 to 3.6 V * Inputs accept voltages up to 5.5 V Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. * CMOS low power consumption * Direct interface with TTL levels * High impedance when VCC = 0 V The 74LVC574A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an Output Enable (OE) input are common to all flip-flops. * 8-bit positive edge-triggered register * Independent register and 3-state buffer operation * Flow-through pin-out architecture * Complies with JEDEC standard no. 8-1A The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance off-state. Operation of the OE input does not affect the state of the flip-flops. * Specified from -40 to +85 C and -40 to +125 C. The 74LVC574A is functionally identical to the 74LVC374A, but has a different pin arrangement. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL PARAMETER tPHL/tPLH propagation delay CP to Qn CONDITIONS CL = 50 pF; VCC = 3.3 V TYPICAL UNIT 3.2 ns fmax maximum clock frequency 150 MHz CI input capacitance 5.0 pF CPD power dissipation capacitance per flip-flop notes 1 and 2 15 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2004 Mar 22 2 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A FUNCTION TABLE See note 1. INPUT OUTPUT OE CP Dn INTERNAL FLIP-FLOP Load and read register L l L L L h H H Load register and disable outputs H l L Z H h H Z OPERATING MODE Qn Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; = LOW-to-HIGH clock transition; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC574AD TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE -40 to +125 C 20 SO20 plastic SOT163-1 74LVC574ADB -40 to +125 C 20 SSOP20 plastic SOT339-1 74LVC574APW -40 to +125 C 20 TSSOP20 plastic SOT360-1 74LVC574ABQ -40 to +125 C 20 DHVQFN20 plastic SOT764-1 PINNING PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION 11 CP clock input (LOW-to-HIGH; edge triggered) 1 OE output enable input (active LOW) 2 D0 data input 12 Q7 data output 3 D1 data input 13 Q6 data output Q5 data output 4 D2 data input 14 5 D3 data input 15 Q4 data output 6 D4 data input 16 Q3 data output Q2 data output 7 D5 data input 17 8 D6 data input 18 Q1 data output 9 D7 data input 19 Q0 data output 10 GND ground (0 V) 20 VCC supply voltage 2004 Mar 22 3 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A handbook, halfpage handbook, halfpage OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 CP VCC 1 20 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 GND(1) 574 D4 6 OE D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 MNA797 Top view 10 11 GND CP MNA978 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO20 and (T)SSOP20. Fig.2 Pin configuration DHVQFN20. handbook, halfpage 11 11 handbook, halfpage 2 3 4 5 6 7 8 9 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 2 18 C1 EN 19 1D 17 3 18 16 4 17 15 5 16 6 15 7 14 8 13 9 12 14 13 12 OE 1 1 MNA798 MNA799 Fig.3 Logic symbol. 2004 Mar 22 Fig.4 Logic symbol (IEEE/IEC). 4 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A handbook, halfpage 2 D0 Q0 19 3 D1 Q1 18 4 D2 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 Q2 17 FF1 to FF8 Q3 16 3-STATE OUTPUTS Q4 15 11 CP 1 OE MNA800 Fig.5 Functional diagram. handbook, full pagewidth D0 D1 D Q D2 D CP Q D CP FF1 D3 Q D CP FF2 D4 Q D CP FF3 D5 Q D CP FF4 Q D CP FF5 D7 D6 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA801 Fig.6 Logic diagram. 2004 Mar 22 5 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage VO output voltage Tamb operating ambient temperature tr, tf input rise and fall times CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V 0 5.5 V output HIGH or LOW state 0 VCC V output 3-state 0 5.5 V in free air -40 +125 C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage -0.5 +6.5 V IIK input diode current VI < 0 - -50 mA VI input voltage note 1 -0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 - 50 mA VO output voltage output HIGH or LOW state; note 1 -0.5 VCC + 0.5 V output 3-state; note 1 -0.5 +6.5 V VO = 0 to VCC IO output source or sink current - 50 mA ICC, IGND VCC or GND current - 100 mA Tstg storage temperature -65 +150 C Ptot power dissipation - 500 mW Tamb = -40 to +125 C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 2004 Mar 22 6 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = -40 to +85 C; note 1 VIH HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage LOW-level output voltage VCC - - V 2.0 - - V 1.2 - - GND V 2.7 to 3.6 - - 0.8 V 2.7 VCC - 0.5 - - V VI = VIH or VIL IO = -12 mA VOL 1.2 2.7 to 3.6 IO = -100 A 3.0 VCC - 0.2 VCC - V IO = -18 mA 3.0 VCC - 0.6 - - V IO = -24 mA 3.0 VCC - 0.8 - - V IO = 12 mA 2.7 - - 0.40 V IO = 100 A 3.0 - GND 0.20 V IO = 24 mA 3.0 - - 0.55 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND; note 2 3.6 - 0.1 5 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 - 0.1 10 A Ioff power-off leakage supply VI or VO = 5.5 V 0.0 - 0.1 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - 0.1 10 A ICC additional quiescent supply VI = VCC - 0.6 V; current per input pin IO = 0 2.7 to 3.6 - 5 500 A 2004 Mar 22 7 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = -40 to +125 C VIH VIL VOH VOL HIGH-level input voltage LOW-level output voltage VCC - - V 2.7 to 3.6 2.0 - - V 1.2 - - GND V 2.7 to 3.6 - - 0.8 V IO = -12 mA 2.7 VCC - 0.65 - - V IO = -100 A 2.7 to 3.6 VCC - 0.3 - - V IO = -18 mA 3.0 VCC - 0.75 - - V IO = -24 mA 3.0 VCC - 1 - - V 2.7 - - 0.6 V LOW-level input voltage HIGH-level output voltage 1.2 VI = VIH or VIL VI = VIH or VIL IO = 12 mA IO = 100 A 2.7 to 3.6 - - 0.3 V IO = 24 mA 3.0 - - 0.8 V ILI input leakage current VI = 5.5 V or GND 3.6 - - 20 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 - - 20 A Ioff power-off leakage supply VI or VO = 5.5 V 0.0 - - 20 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - - 40 A ICC additional quiescent supply VI = VCC - 0.6 V; current per input pin IO = 0 2.7 to 3.6 - - 5000 A Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2004 Mar 22 8 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = -40 to +85 C; note 1 tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th fmax tsk(0) propagation delay CP to Qn see Figs 7 and 10 3-state output enable time OE to Qn see Figs 9 and 10 3-state output disable time OE to Qn see Figs 9 and 10 clock pulse width HIGH or LOW see Fig.7 set-up time Dn to CP see Fig.8 hold time Dn to CP see Fig.8 maximum clock frequency skew 2.7 1.5 3.6 8.0 ns 3.0 to 3.6 1.5 3.2(2) 7.0 ns 2.7 1.5 4.3 8.5 ns 3.0 to 3.6 1.5 3.5(2) 7.5 ns 2.7 1.5 2.8 6.5 ns 3.0 to 3.6 1.5 2.5(2) 6.0 ns 2.7 3.3 - - ns 3.0 to 3.6 3.4 1.7(2) - ns 2.7 2.0 - - ns 3.0 to 3.6 2.0 0.3(2) - ns 2.7 1.5 - - ns 3.0 to 3.6 1.5 -0.2(2) - ns 2.7 80 - - MHz 3.0 to 3.6 100 150(2) - MHz note 3 3.0 to 3.6 - - 1.0 ns 2.7 - - 10.0 ns 3.0 to 3.6 - - 9.0 ns 2.7 - - 11.0 ns 3.0 to 3.6 - - 9.5 ns Tamb = -40 to +125 C tPHL/tPLH propagation delay CP to Qn see Figs 7 and 10 tPZH/tPZL 3-state output enable time OE to Qn see Figs 9 and 10 3-state output disable time OE to Qn see Figs 9 and 10 tW clock pulse width HIGH or LOW see Fig.7 tsu set-up time Dn to CP see Fig.8 tPHZ/tPLZ th hold time Dn to CP fmax maximum clock frequency tsk(0) skew see Fig.8 note 3 2.7 - - 8.5 ns 3.0 to 3.6 - - 7.5 ns 2.7 - - - ns 3.0 to 3.6 - - - ns 2.7 - - - ns 3.0 to 3.6 - - - ns 2.7 - - - ns 3.0 to 3.6 - - - ns 2.7 - - - MHz 3.0 to 3.6 - - - MHz 3.0 to 3.6 - - - ns Notes 1. All typical values are measured at Tamb = 25 C. 2. These typical values are measured at VCC = 3.3 V. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2004 Mar 22 9 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A AC WAVEFORMS 1/fmax handbook, full pagewidth VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL MNA802 VM = 1.5 V at VCC 2.7 V. VM = 0.5 VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.7 Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. VI handbook, full pagewidth VM CP input GND t su t su th th VI VM Dn input GND VOH VM Qn output VOL MNA803 VM = 1.5 V at VCC 2.7 V. VM = 0.5 VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.8 Data setup and hold times for the Dn input to the CP input. 2004 Mar 22 10 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A VI handbook, full pagewidth OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled MNA804 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC 2.7 V; VX = VOL + 0.1VCC at VCC < 2.7 V. VY = VOH - 0.3 V at VCC 2.7 V; VY = VOH - 0.1VCC at VCC < 2.7 V. Fig.9 3-state enable and disable times. S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL = 500 VO 2 x VCC open GND D.U.T. CL = RT 50 pF RL = 500 MNA815 TEST S1 VCC VI tPLH/tPHL open <2.7 V VCC tPLZ/tPZL 2 x VCC 2.7 to 3.6 V 2.7 V tPHZ/tPZH GND Definitions for test circuit: RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to Zo of pulse generators. Fig.10 Load circuitry for switching times. 2004 Mar 22 11 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2004 Mar 22 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 12 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 2004 Mar 22 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 13 o Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2004 Mar 22 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 14 o Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- 2004 Mar 22 15 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC574A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Mar 22 16 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA76 (c) Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/03/pp17 Date of release: 2004 Mar 22 Document order number: 9397 750 13028