1
Microsemi Corporation
Copyright 2014, Microsemi Corporation. All Rights Reserved.
Features
Inputs/Outputs
• Accepts differential or single-ended input
• LVPECL, LVDS, CML, HCSL, LVCMOS
• On-chip input termination resistors and biasing for
AC coupled inputs
• Two precision LVDS outputs
• Operating frequency up to 750 MHz
Power
• Options for 2.5 V or 3.3 V power supply
• Current consumption of 44 mA
• On-chip Low Drop Out (LDO) Regulator for superior
power supply rejection
Performance
• Ultra low additive jitter of 78 fs RMS
Applications
• General purpose clock distribution
• Low jitter clock trees
• Logic translation
• Clock and data signal restoration
• Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
• PCI Express generation 1/2/3 clock distribution
• Wireless communications
• High performance microprocessor clock
distribution
April 2014
Figure 1 - Functional Block Diagram
clk_p
clk_n
ctrl
vt
Termination
and Bias
out1_p
out1_n
out0_p
out0_n
Buffer
ZL40213
Precision 1:2 LVDS Fanout Buffer
with On-Chip Input Termination
Data Sheet
Ordering Information
ZL40213LDG1 16 Pin QFN Trays
ZL40213LDF1 16 Pin QFN Tape and Reel
Matte Tin
Package size: 3 x 3 mm
-40oC to +85oC
ZL40213 Data Sheet
Table of Contents
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Microsemi Corporation
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.0 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ZL40213 Data Sheet
List of Figures
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Microsemi Corporation
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3 - Simplified Diagram of Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11 - Clock Input - DC-coupled 3.3V CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ZL40213 Data Sheet
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Microsemi Corporation
Change Summary
Page Item Change
1Applications Added PCI Express clock distribution.
5Pin Description Added exposed pad to Pin Description.
7Figure 4 and Figure 5 Removed 22 ohm series resistors from Figure 4 and 5.
These resistors are not required; however there is no impact
to performance if the resistors are included
17 Figure 19 Clarification of VID and VOD.
Below are the changes from the February 2013 issue to the April 2014 issue:
Page Item Change
7Figure 4 Changed text to indicate the circuit is not recommended for
VDD_driver=2.5V.
11 Figure 12 Changed gate values to +/+ on the left and -/- on the right.
Below are the changes from the November 2012 issue to the February 2013 issue:
ZL40213 Data Sheet
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Microsemi Corporation
1.0 Package Description
The device is packaged in a 16 pin QFN
14
16
6
4
2
NC
vdd
NC
vt
clk_p
vdd
gnd
NC
out1_n
out1_p
out0_n
8
12 10
out0_p
clk_n
ctrl
NC
gnd
Figure 2 - Pin Connections
2.0 Pin Description
Pin # Name Description
1, 4 clk_p, clk_n, Differential Input (Analog Input). Differential (or singled ended) input signals. For all
input signal configuration see“Clock Inputs” on page 6
12, 11,
10, 9,
out0_p, out0_n
out1_p, out1_n
Differential Output (Analog Output). Differential outputs.
8, 13 vdd Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal.
5, 16 gnd Ground. 0 V.
2vtOn-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm
termination resistors.
See “Clock Inputs” on page 6 for more information.
3ctrlDigital Control for On-Chip Input Termination (Input). Selects differential input mode;
0: DC coupled modes
1: AC coupled differential modes
These pins are internally pulled down to GND.
See “Clock Inputs” on page 6 for more information.
6, 7,
14, 15
NC No connection. Leave unconnected.
Exposed Pad Device GND.
ZL40213 Data Sheet
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Microsemi Corporation
3.0 Functional Description
he ZL40213 is an LVDS clock fanout buffer with two identical output clock drivers capable of operating at
frequencies up to 750MHz.
The ZL40213 provides an internal input termination network for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40213 can accept DC or AC coupled LVPECL and LVDS input
signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external
termination is also available.
The ZL40213 is designed to fan out low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
Receiver
clk_n
50
clk_p
Vt
50
Bias
ctrl
Figure 3 - Simplified Diagram of Input Stage
This following figures give the components values and configuration for the various circuits compatible with the
input stage and the use of the Vt and ctrl pins in each case.
In the following diagrams where the ctrl pin is "1" and the Vt pin is not connected, the Vt pin can be instead
connected to VDD with a capacitor.The same capacitor can also help in Figure 4 between Vt and VDD. This
capacitor will minimize the noise at the point between the two internal termination resistors and improve the overall
performance of the device.
ZL40213 Data Sheet
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Microsemi Corporation
Figure 4 - Clock Input - LVPECL - DC Coupled
Figure 5 - Clock Input - LVPECL - AC Coupled
LVPECL
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
For 3.3V R=50 ohms
Not recommended for VDD_driver=2.5V
R
LVPECL
Driver
VDD_driver VDD
Zo = 50 Ohms
Zo = 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
For 3.3V: R=150 ohms
For 2.5V: R=85 ohms
NC
RR
LVDS
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
NC
LVDS
Driver
VDD_driver VDD
Zo=50Ohms
Zo=50Ohms
clk_p
clk_n
Vt
Ctrl
“1”
NC
R
ForVDD_driver=3.3V:R=900Ohms
ForVDD_driver=2.5V:R=680Ohms
Note:RisonlyneededtoprovideaDCpathforthe
LVDSdriver.Seedriverdatasheetformoreinformation.
ZL40213 Data Sheet
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Microsemi Corporation
Figure 6 - Clock Input - LVDS - DC Coupled
Figure 7 - Clock Input - LVDS - AC Coupled
CML
Driver
VDD_driver VDD
Zo=50Ohms
Zo=50Ohms
clk_p
clk_n
Vt
Ctrl
“1”
R=50Ohms
NC
RR
HCSL
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
R= 50 Ohms
NC
RR
ZL40213 Data Sheet
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Microsemi Corporation
Figure 8 - Clock Input - CML- AC Coupled
Figure 9 - Clock Input - HCSL- AC Coupled
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms clk_p
clk_n
Vt
Ctrl
“1”
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms clk_p
clk_n
Vt
Ctrl
“1”
NC
ZL40213 Data Sheet
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Microsemi Corporation
Figure 10 - Clock Input - AC-coupled Single-Ended
Figure 11 - Clock Input - DC-coupled 3.3V CMOS
ZL40213 Data Sheet
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Microsemi Corporation
3.2 Clock Outputs
LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the
LVDS output stage is shown in Figure 12.
VDD
3mA
Output
+
+
‐
‐
Figure 12 - Simplified LVDS Output Driver
The methods to terminate the ZL40213 drivers are shown in the following figures.
LVDS
Receiver
VDD VDD_Rx
Zo=50Ohms
Zo=50Ohms
ZL40213
clk_p
clk_n
Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination)
LVDS
Receiver
VDD VDD_Rx
Zo=50Ohms
Zo=50Ohms
ZL40213
clk_p
clk_n
100Ohms
Figure 14 - LVDS DC Coupled Termination (External Receiver Termination)
LVDS
Receiver
VDD
VDD_Rx
Zo=50Ohms
Zo=50Ohms
ZL40213
clk_p
clk_n
100Ohms
R2
VDD_Rx
R1 R1
R2
Note:R1andR2valuesandneedforexternaltermination
dependonthespecificationoftheLVDSreceiver
Figure 15 - LVDS AC Coupled Termination
ZL40213 Data Sheet
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Microsemi Corporation
ZL40213 Data Sheet
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Microsemi Corporation
Figure 16 - LVDS AC Output Termination for CML Inputs
CML
Receiver
VDD
Zo=50Ohms
Zo=50Ohms
ZL40213
clk_p
clk_n
VDD_Rx
50Ohms
50Ohms
ZL40213 Data Sheet
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Microsemi Corporation
3.3 Device Additive Jitter
The ZL40213 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40213 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output of the ZL40213 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to
power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17.
+
Jin
2
Jadd
2Jps
2
Jin =Randominputclockjitter(RMS)
Jadd =Additivejitterduetothedevice(RMS)
Jps=Additivejitterduetopowersupplynoise(RMS)
Jout=Resultantrandomoutputclockjitter(RMS)
+Jout
2=Jin
2+Jadd
2+Jps
2
Figure 17 - Additive Jitter
ZL40213 Data Sheet
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Microsemi Corporation
3.4 Power Supply
This device operates with either a 2.5V supply or 3.3V supply.
3.4.1 Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40213 is equipped with a low drop out (LDO) power
regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The LDO regulator on
the ZL40213 allows this device to have superior performance even in the presence of external noise sources. The
on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the
additive jitter from power supply noise.
The performance of these clock buffers in the presence of power supply noise is detailed in ZLAN-403, “Power
Supply Rejection in Clock Buffers” which is available from Applications Engineering.
3.4.2 Power supply filtering
For optimal jitter performance, the device should be isolated from the power planes connected to its power supply
pins as shown in Figure 18.
• 10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating
• 0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating
• Capacitors should be placed next to the connected device power pins
• a 0.3 ohm resistor is recommended for the filter shown in Figure 18
Figure 18 - Decoupling Connections for Power Pins
VDD
0.3Ohms 0.1µF
10µF
ZL40213
8
13
3.4.3 PCB layout considerations
The power nets in Figure 18 can be implemented either as a plane island or routed power topology without
changing the overall jitter performance of the device.
Absolute Maximum Ratings*
Parameter Sym. Min. Max. Units
1Supply voltage VDD_R -0.5 4.6 V
2Voltage on any digital pin VPIN -0.5 VDD V
3Soldering temperature T260 °C
4Storage temperature TST -55 125 °C
5Junction temperature Tj125 °C
6Voltage on input pin Vinput VDD V
7Input capacitance each pin Cp500 fF
ZL40213 Data Sheet
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Microsemi Corporation
4.0 AC and DC Electrical Characteristics
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions*
Characteristics Sym. Min. Typ. Max. Units
1Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V
2Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V
3Operating temperature TA-40 25 85 °C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Characteristics - Current Consumption
Characteristics Sym. Min. Typ. Max. Units Notes
1Supply current LVDS drivers - loaded
(all outputs are active)
Idd_load 44 mA
DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V Supply
Characteristics Sym. Min. Typ. Max. Units Notes
1CMOS control logic high-level input VCIH 0.7*VDD V
2CMOS control logic low-level input VCIL 0.3*VDD V
3CMOS control logic Input leakage
current
IIL 1µA VI = VDD or 0 V
4Differential input common mode
voltage
VICM 1.1 1.6 VFor VDD = 2.5
5Differential input common mode
voltage
VICM 1.1 2.0 VFor VDD = 3.3
6LVDS Differential input voltage VID 0.25 1 V
7Differential input resistance VIR 80 100 120 ohm
ZL40213 Data Sheet
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Microsemi Corporation
* The VOD parameter was measured from 125 MHz to 750 MHz.
Figure 19 - Differential Voltage Parameter
* Supply voltage and operating temperature are as per Recommended Operating Conditions
Input
tP
tPWL
tpd
tPWH
Output
Figure 20 - Input To Output Timing
8LVDS output differential voltage* VOD 0.25 0.30 0.40 V
9LVDS output common mode voltage VCM 1.1 1.25 1.375 V
outx_p
outx_n
VOD
outx_p – outx_n
GND VICM
02*VOD
clk_p – clk_n
02*VID
clk_p
clk_n
VID
GND VCM
AC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V supply.
Characteristics Sym. Min. Typ. Max. Units Notes
1Maximum Operating Frequency 1/tp750 MHz
2Input to output clock propagation delay tpd 0 1 2 ns
3Output to output skew tout2out 50 100 ps
4Part to part output skew tpart2part 80 300 ps
5Output clock Duty Cycle degradation tPWH/ tPWL -5 0 5 %
6LVDS Output slew rate rsl 0.55 V/ns
DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V Supply
Characteristics Sym. Min. Typ. Max. Units Notes
Additive Jitter at 2.5 V*
Output Frequency (MHz) Jitter
Measurement
Filter
Typical
(fs)
Notes
1125 12 kHz - 20 MHz 120
2212.5 12 kHz - 20 MHz 102
3311.04 12 kHz - 20 MHz 88
4425 12 kHz - 20 MHz 91
5500 12 kHz - 20 MHz 77
6622.08 12 kHz - 20 MHz 78
7750 12 kHz - 20 MHz 78
ZL40213 Data Sheet
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Microsemi Corporation
5.0 Performance Characterization
*The values in this table were taken with a slew rate of approximately 0.8 V/ns.
Additive Jitter at 3.3 V*
Output Frequency (MHz) Jitter
Measurement
Filter
Typical
(fs)
Notes
1125 12 kHz - 20 MHz 123
2212.5 12 kHz - 20 MHz 104
3311.04 12 kHz - 20 MHz 92
4425 12 kHz - 20 MHz 94
5500 12 kHz - 20 MHz 78
6622.08 12 kHz - 20 MHz 79
7750 12 kHz - 20 MHz 80
*The values in this table were taken with a slew rate of approximately 0.8 V/ns.
* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test,
measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the
DUT.
Additive Jitter from a Power Supply Tone*
Carrier frequency Parameter Typical Units Notes
125MHz 25 mV at 100 kHz 38 fs RMS
750MHz 25 mV at 100 kHz 50 fs RMS
ZL40213 Data Sheet
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Microsemi Corporation
6.0 Typical Behavior
Typical Waveform at 155.52 MHz VOD versus Frequency
Power Supply Tone Frequency versus PSRR Power Supply Tone Magnitude versus PSRR
Propagation Delay versus Temperature
Note: This is for a single device. For more details see the
characterization section.
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 5 10 15 20
Voltage
Time (ns)
0.305
0.31
0.315
0.32
0.325
0.33
0 100 200 300 400 500 600 700 800
Voltage
Frequency (MHz)
-90
-85
-80
-75
-70
-65
-60
100 150 200 250 300 350 400 450 500
PSRR (dBc)
Power Supply Tone Frequency with 25 mV (kHz)
125 MHz
212.5 MHz
425 MHz
750 MHz
-90
-85
-80
-75
-70
-65
-60
-55
20 30 40 50 60 70 80 90 100
PSRR (dBc)
Power Supply Tone magnitude (mV) at 100 kHz
125 MHz
212.5 MHz
425 MHz
750 MHz
0.3
0.35
0.4
0.45
0.5
0.55
0.6
-40 -20 0 20 40 60 80 100
Propagation Delay (ns)
Temperature (°C)
ZL40213 Data Sheet
20
Microsemi Corporation
7.0 Package Thermal Characteristics
* Proper thermal management must be practiced to ensure that Tjmax is not exceeded.
Thermal Data
Parameter Symbol Test Condition Value Unit
Junction to Ambient Thermal Resistance ΘJA Still Air
1 m/s
2 m/s
67.9
61.6
58.1
oC/W
Junction to Case Thermal Resistance ΘJC Still Air 44.1 oC/W
Junction to Board Thermal Resistance ΘJB Still Air 23.2 oC/W
Maximum Junction Temperature* Tjmax 125 oC
Maximum Ambient Temperature TA85 oC
ZL40213 Data Sheet
21
Microsemi Corporation
8.0 Mechanical Drawing
© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
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ZL40213
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