2003 Semiconductor Components Industries, LLC.
November-2018, Rev. 7
Publication Order Number:
FDN360P /D
FDN360P
Single P-Channel, PowerTrench MOSFET
General Description
This P-Channel Logic Level MOSFET is
produced using ON Semiconductor advanced Power
Trench process that has been especially tailored to
minimize the on-state resistance and yet maintain
low gate charge for superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
–2 A, 30 V. RDS(ON) = 80 m @ VGS = 10 V
RDS(ON) = 125 m @ VGS = 4.5 V
High power version of industry Standard SOT-23
package. Identical pin-out to SOT-23 with 30%
higher power handling capability.
G
D
S
SuperSOT -3
TM
D
SG
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain-Source Voltage –30V
VGSS Gate-Source Voltage ±20 V
ID Drain Current Continuous (Note 1a) –2 A
Pulsed –10
Power Dissipation for Single Operation (Note 1a) 0.5
PD
(Note 1b) 0.46 W
TJ, TSTG Operating and Storage Junction Temperature Range 55 to +150 °C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
360 FDN360P 7’’ 8mm 3000 units
FDN360P
Low gate charge (6.2 nC typical)
High performance trench technology for extremely
low RDS(ON) .
These Devices are Pb-Free and are RoHS Compliant
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2
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol
Parameter Test Conditions Min Typ
Max
Units
Off Characteristics
BVDSS DrainSource Breakdown Voltage VGS = 0 V, ID = 250 µA –30 V
BVDSS
TJ Breakdown Voltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C –22 mV/°C
VDS = –24V, VGS = 0 V –1 µA
IDSS Zero Gate Voltage Drain Current VDS = 24V, VGS = 0 V, TJ=55°C –10
IGSSF GateBody Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
IGSSR GateBody Leakage, Reverse VGS = –20 V, VDS = 0 V –100 nA
On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA –1 –1.9 –3 V
VGS(th)
TJ Gate Threshold Voltage
Temperature Coefficient ID = 250 µA, Referenced to 25°C 4 mV/°C
RDS(on) Static DrainSource
OnResistance VGS = –10 V, ID = –2 A
VGS = 10 V, ID = 2 A, TJ=125°C
VGS= 4.5 V, ID = 1.5A
63
90
100
80
136
125
m
ID(on) OnState Drain Current VGS = –10 V, VDS = 5 V –10 A
gFS Forward Transconductance VDS = 5 V, ID = –2 A 5 S
Dynamic Characteristics
Ciss Input Capacitance 298 pF
Coss Output Capacitance 83 pF
Crss Reverse Transfer Capacitance
VDS = –15 V, V GS = 0 V,
f = 1.0 MHz 39 pF
Switching Characteristics (Note 2)
td(on) TurnOn Delay Time 6 12 ns
tr TurnOn Rise Time 13 23 ns
td(off) TurnOff Delay Time 11 20 ns
tf TurnOff Fall Time
VDD = –15 V, ID = –1 A,
VGS = –10 V, RGEN = 6
6 12 ns
Qg Total Gate Charge 6.2 9 nC
Qgs GateSource Charge 1 nC
Qgd GateDrain Charge
VDS = –15V, ID = 3.6 A,
VGS = –10 V
1.2 nC
DrainSource Diode Characteristics and Maximum Ratings
IS Maximum Continuous DrainSource Diode Forward Current 0.42A
VSD DrainSource Diode Forward
Voltage VGS = 0 V, IS = 0.42 A (Note 2) 0.8 1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 250°C/W when mounted on a
0.02 in2 pad of 2 oz. copper. b) 270°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%
FDN360P
Typical Characteristics
0
3
6
9
12
15
0 1 2 3 4 5
-VDS, DRAIN TO SOURCE VOLTAGE (V)
-ID, DRAIN CURRENT (A)
VGS = -10V
-3.5V
-3.0V
-4.5V
-4.0V
-5.0V
-6.0V
V
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 3 6 9 12 15
-ID, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
VGS = -3.5V
-6.0V
-5.0V
-4.0V
-10V
-4.5V
-7.0V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = -2A
VGS = -10V
0.05
0.1
0.15
0.2
0.25
0.3
2 4 6 8 10
-VGS, GATE TO SOURCE VOLTAGE (V)
RDS(ON), ON-RESISTANCE (OHM)
ID = -1A
TA = 125oC
TA = 25oC
Figure 3. On-Resistance Variation with
Temperature. Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
2
4
6
8
10
12345
-VGS, GATE TO SOURCE VOLTAGE (V)
-ID, DRAIN CURRENT (A)
TA = -55oC25oC
125oC
VDS = -5.0V
0.0001
0.001
0.01
0.1
1
10
00.2 0.4 0.6 0.8 11.2
-VSD, BODY DIODE FORWARD VOLTAGE (V)
-IS, REVERSE DRAIN CURRENT (A)
VGS = 0V
TA = 125oC
25oC
-55oC
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDN360P
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3
Typical Characteristics
0
2
4
6
8
10
01234567
Qg, GATE CHARGE (nC)
-VGS
, GATE-SOURCE VOLTAGE (V)
ID = -3.6A VDS = -5V -10V
-15V
0
100
200
300
400
0 6 12 18 24 30
-VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
CISS
COSS
CRSS
f = 1 MHz
VGS = 0 V
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.1 1 10 100
-VDS, DRAIN-SOURCE VOLTAGE (V)
-ID
, DRAIN CURRENT (A)
DC1s
100ms
µ
s
RDS(ON) LIMIT
VGS = -10V
SINGLE PULSE
RθJA =270oC/W
TA = 25oC
10ms1ms
10
µ
s
0
5
10
15
20
0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJA = 270°C/W
TA = 25°C
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
RθJA(t) = r(t) + RθJA
RθJA = 270 °C/W
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
P(pk)
t1t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDN360P
www.onsemi.com
4
SOT23, 3 Lead
CASE 527AG01
ISSUE O
DATE 19 DEC 2008
E1 E
A1
e
e1
b
D
3
12
c
A
TOP VIEW
SIDE VIEW END VIEW
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC TO-236.
SYMBOL MIN NOM MAX
q
θ
A
A1
b
c
D
E
E1
e
e1
L1
L
0.013
0.37
0.085
2.80
2.10
1.20
1.90 BSC
0.40 REF
1.12
0.10
0.50
0.18
3.04
2.64
1.40
0.54 REF
0.95 BSC
0.89
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34319E
ON SEMICONDUCTOR STANDARD
SOT23, 3 LEAD
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
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ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #SOT23300701 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
© Semiconductor Components Industries, LLC, 2008
December, 2008 Rev. 01O
Case Outline Number:
527AG
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