W25Q16JV
Publication Release Date: April 08, 2019
Revision H
3V 16M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI
For Industrial & Industrial Plus Grade
W25Q16JV
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Table of Contents
1. GENERAL DESCRIPTIONS ............................................................................................................. 4
2. FEATURES ....................................................................................................................................... 4
3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 5
3.1 Pin Configuration SOIC 150/208-mil .................................................................................... 5
3.2 Pad Configuration WSON 6x5-mm & USON 2x3-mm/4x3-mm, XSON 4x4-mm ................. 5
3.3 Pin Description SOIC 150/208-mil, WSON 6x5-mm, USON 2x3-mm/4x3-mm, XSON 4x4-
mm 5
3.4 Ball Configuration WLCSP ................................................................................................... 6
3.5 Ball Description WLCSP ....................................................................................................... 6
4. PIN DESCRIPTIONS ........................................................................................................................ 7
4.1 Chip Select (/CS) .................................................................................................................. 7
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 7
4.3 Write Protect (/WP) ............................................................................................................... 7
4.4 HOLD (/HOLD) ..................................................................................................................... 7
4.5 Serial Clock (CLK) ................................................................................................................ 7
4.1 Reset (/RESET)(1) ................................................................................................................. 7
5. BLOCK DIAGRAM ............................................................................................................................ 8
6. FUNCTIONAL DESCRIPTIONS ....................................................................................................... 9
6.1 Standard SPI Instructions ..................................................................................................... 9
6.2 Dual SPI Instructions ............................................................................................................ 9
6.1 Quad SPI Instructions........................................................................................................... 9
6.2 Software Reset & Hardware /RESET pin ............................................................................. 9
6.3 Write Protection .................................................................................................................. 10
6.4 Write Protect Features........................................................................................................ 10
7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 11
7.1 Status Registers ................................................................................................................. 11
Erase/Write In Progress (BUSY) Status Only ................................................................. 11
Write Enable Latch (WEL) Status Only ........................................................................... 11
Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable ................................. 11
Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable ........................................ 12
Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable ........................................ 12
Complement Protect (CMP) Volatile/Non-Volatile Writable ............................................ 12
Status Register Protect SRP, SRL) Volatile/Non-Volatile Writable ................................. 13
Erase/Program Suspend Status (SUS) Status Only ....................................................... 14
Security Register Lock Bits (LB3, LB2, LB1) Non-Volatile OTP Writable ......................... 14
8. QUAD ENABLE (QE) VOLATILE/NON-VOLATILE WRITABLE .............................................. 14
Write Protect Selection (WPS) Volatile/Non-Volatile Writable ........................................ 15
Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable ............................ 15
Reserved Bits Non Functional ........................................................................................ 15
W25Q16JV Status Register Memory Protection (WPS = 0, CMP = 0) ................................. 16
W25Q16JV Status Register Memory Protection (WPS = 0, CMP = 1) ................................. 17
W25Q16JV
Publication Release Date: April 08, 2019
- 2 - Revision H
W25Q16JV Individual Block Memory Protection (WPS=1) ................................................... 18
9. INSTRUCTIONS ............................................................................................................................. 19
9.1 Device ID and Instruction Set Tables ................................................................................. 19
Manufacturer and Device Identification ................................................................................. 19
Instruction Set Table 1 (Standard SPI Instructions) (1) .......................................................... 20
Instruction Set Table 2 (Dual/Quad SPI Instructions)(1) ......................................................... 21
Notes: ................................................................................................................................................ 21
9.2 Instruction Descriptions ...................................................................................................... 22
Write Enable (06h) ................................................................................................................ 22
Write Enable for Volatile Status Register (50h) ..................................................................... 22
Write Disable (04h) ............................................................................................................... 23
Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) ............... 23
Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) ............... 24
Read Data (03h) ................................................................................................................... 26
Fast Read (0Bh) ................................................................................................................... 27
Fast Read Dual Output (3Bh) ............................................................................................... 28
Fast Read Quad Output (6Bh) .............................................................................................. 29
Fast Read Dual I/O (BBh) ................................................................................................... 30
Fast Read Quad I/O (EBh) .................................................................................................. 31
Set Burst with Wrap (77h) ................................................................................................... 32
Page Program (02h) ........................................................................................................... 33
Quad Input Page Program (32h) ......................................................................................... 34
9.3 Sector Erase (20h) ............................................................................................................. 35
32KB Block Erase (52h) ........................................................................................................ 36
64KB Block Erase (D8h) ....................................................................................................... 37
Chip Erase (C7h / 60h) ......................................................................................................... 38
Erase / Program Suspend (75h) ........................................................................................... 39
Erase / Program Resume (7Ah) ............................................................................................ 40
Power-down (B9h) ................................................................................................................ 41
Release Power-down / Device ID (ABh) ............................................................................... 42
Read Manufacturer / Device ID (90h) ................................................................................... 43
Read Manufacturer / Device ID Dual I/O (92h) ..................................................................... 44
Read Manufacturer / Device ID Quad I/O (94h) .................................................................. 45
Read Unique ID Number (4Bh) ........................................................................................... 46
Read JEDEC ID (9Fh) ........................................................................................................ 47
Read SFDP Register (5Ah) ................................................................................................. 48
Erase Security Registers (44h) ........................................................................................... 49
Program Security Registers (42h) ....................................................................................... 50
Read Security Registers (48h) ............................................................................................ 51
Individual Block/Sector Lock (36h) ...................................................................................... 52
Individual Block/Sector Unlock (39h) .................................................................................. 53
Read Block/Sector Lock (3Dh) ............................................................................................ 54
Global Block/Sector Lock (7Eh) .......................................................................................... 55
Global Block/Sector Unlock (98h) ....................................................................................... 55
Enable Reset (66h) and Reset Device (99h) ...................................................................... 56
W25Q16JV
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10. ELECTRICAL CHARACTERISTICS............................................................................................... 57
10.1 Absolute Maximum Ratings (1) .......................................................................................... 57
10.2 Operating Ranges .............................................................................................................. 57
10.3 Power-Up Power-Down Timing and Requirements ........................................................... 58
10.4 DC Electrical Characteristics- ............................................................................................. 59
10.5 AC Measurement Conditions ............................................................................................. 60
10.6 AC Electrical Characteristics(6) ........................................................................................... 61
10.7 Serial Output Timing ........................................................................................................... 63
10.8 Serial Input Timing .............................................................................................................. 63
10.9 /WP Timing ......................................................................................................................... 63
11. PACKAGE SPECIFICATIONS ....................................................................................................... 64
11.1 8-Pin SOIC 150-mil (Package Code SN) 20131227 .......................................................... 64
11.3 8-Pin SOIC 208-mil (Package Code SS) ............................................................................ 65
11.4 8-Pad USON 2x3x0.6-mm^³ (Package Code UX) ............................................................. 66
11.5 8-Pad WSON 6x5-mm (Package Code ZP) ....................................................................... 67
11.6 8-Pad USON 4x3-mm (Package Code UU) ....................................................................... 68
11.7 8-Pad XSON 4x4x0.45-mm (Package Code XG) .............................................................. 69
11.8 8-Ball WLCSP (Package Code BY) .................................................................................... 70
12. ORDERING INFORMATION .......................................................................................................... 71
12.1 Valid Part Numbers and Top Side Marking ........................................................................ 72
13. REVISION HISTORY ...................................................................................................................... 74
W25Q16JV
Publication Release Date: April 08, 2019
- 4 - Revision H
1. GENERAL DESCRIPTIONS
The W25Q16JV (16M-bit) Serial Flash memory provides a storage solution for systems with limited space,
pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices.
They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing
voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption
as low as 1µA for power-down.
The W25Q16JV array is organized into 8,192 programmable pages of 256-bytes each. Up to 256 bytes can
be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB
block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q16JV has 512
erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in
applications that require data and parameter storage. (See figure 2.)
The W25Q16JV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad
output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2, and
I/O3. SPI clock frequencies of up to 133MHz are supported allowing equivalent clock rates of 266MHz
(133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad
I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash
memories.
Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64-
bit Unique Serial Number and three 256-bytes Security Registers.
2. FEATURES
New Family of SpiFlash Memories
W25Q16JV: 16M-bit / 2M-byte (2,097,152)
Standard SPI: CLK, /CS, DI, DO
Dual SPI: CLK, /CS, IO0, IO1
Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
Software & Hardware Reset(1)
Highest Performance Serial Flash
133MHz Single, Dual/Quad SPI clocks
266/532MHz equivalent Dual/Quad SPI
66MB/S continuous data transfer rate
Min. 100K Program-Erase cycles per sector
More than 20-year data retention
Efficient “Continuous Read”
Continuous Read with 8/16/32/64-Byte Wrap
As few as 8 clocks to address memory
Allows true XIP (execute in place) operation
Outperforms X16 Parallel Flash
Low Power, Wide Temperature Range
Single 2.7V to 3.6V supply
-40°C to +85°C operating range
-40°C to +105°C operating range
<1µA Power-down (typ.)
Flexible Architecture with 4KB sectors
Uniform Sector/Block Erase (4K/32K/64K-Byte)
Program 1 to 256 byte per programmable page
Erase/Program Suspend & Resume
Advanced Security Features
Software and Hardware Write-Protect
Power Supply Lock-Down and
Special OTP protection(2)
Top/Bottom, Complement array protection
Individual Block/Sector array protection
64-Bit Unique ID for each device
Discoverable Parameters (SFDP) Register
3X256-Bytes Security Registers with OTP locks
Volatile & Non-volatile Status Register Bits
Space Efficient Packaging
8-pin SOIC 150-mil / 208-mil
8-pad USON 2X3mm/4x3-mm
8-pad XSON 4x4-mm
8-pad WSON 6x5-mm
8-ball WLCSP
Contact Winbond for KGD and other options
Note: 1. Hardware /RESET pin is only available on SOIC-16 & TFBGA packages
2. Please contact Winbond for details.
W25Q16JV
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3. PACKAGE TYPES AND PIN CONFIGURATIONS
3.1 Pin Configuration SOIC 150/208-mil
Figure 1a. Pin Assignments, 8-pin SOIC150-mil/208-mil (Package Code SN, SS)
3.2 Pad Configuration WSON 6x5-mm & USON 2x3-mm/4x3-mm, XSON 4x4-mm
Figure 1b. Pad Assignments, 8-pad WSON 6x5-mm, USON 2X3-mm/4x3-mm, XSON 4x4-mm (Package Code ZP, UX, UU, XG)
3.3 Pin Description SOIC 150/208-mil, WSON 6x5-mm, USON 2x3-mm/4x3-mm,
XSON 4x4-mm
PIN NO.
PIN NAME
I/O
FUNCTION
1
/CS
I
Chip Select Input
2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
3
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)(2)
4
GND
Ground
5
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
6
CLK
I
Serial Clock Input
7
/HOLD or /RESET
(IO3)
I/O
Hold or Reset Input (Data Input Output 3)(2)
8
VCC
Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI.
1
2
3
4
/CS
DO (IO1)
/WP (IO2)
GND
VCC
/HOLD or /RESET
(IO3)
DI (IO0)
CLK
Top View
8
7
6
5
W25Q16JV
Publication Release Date: April 08, 2019
- 6 - Revision H
3.4 Ball Configuration WLCSP
GND
/CSVCC
Top View
GND
VCC
CLK
Bottom View
A1
B1
C1
D1
A2
B2
C2
D2
/HOLD (IO3)
CLK /WP (IO2)
DI(IO0)
DO(IO1)
DO(IO1)
B2 B1
A2 A1
C2 C1
D2
/CS
DI(IO0)
D1
/HOLD (IO3)
/WP (IO2)
Figure 1c. W25Q16JV Ball Assignments, 8-ball WLCSP (Package Code BY)
3.5 Ball Description WLCSP
BALL NO.
PIN NAME
I/O
FUNCTION
A1
VCC
Power Supply
A2
/CS
I
Chip Select Input
B1
/HOLD or
/RESET (IO3)
I/O
Hold or Reset Input (Data Input Output 3)(2)
B2
DO (IO1)
I/O
Data Output (Data Input Output 1)*1
C1
CLK
I
Serial Clock Input
C2
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)(2)
D1
DI (IO0)
I/O
Data Input (Data Input Output 0)*1
D2
GND
Ground
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
W25Q16JV
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4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58).
If needed a pull-up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q16JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data
or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data
to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When
QE=1, the /WP pin becomes IO2 and the /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware
protected. The /WP pin is active low.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful
when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of
Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3.
See Figure 1a-c for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
4.1 Reset (/RESET)(1)
A dedicated hardware /RESET pin is available on SOIC-16 and TFBGA packages. When it’s driven low for
a minimum period of ~1µS, this device will terminate any external or internal operations and return to its
power-on state.
Note:
1. Hardware /RESET pin is available on SOIC-16 or TFBGA; please contact Winbond for this package.
W25Q16JV
Publication Release Date: April 08, 2019
- 8 - Revision H
5. BLOCK DIAGRAM
Figure 2. W25Q16JV Serial Flash Memory Block Diagram
W25Q16JV
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6. FUNCTIONAL DESCRIPTIONS
6.1 Standard SPI Instructions
The W25Q16JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO
output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising
edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.2 Dual SPI Instructions
The W25Q16JV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: IO0 and IO1.
6.1 Quad SPI Instructions
The W25Q16JV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, and “Fast Read Quad I/O (EBh). These instructions allow data to be transferred to or from the device
four to six times the rate of ordinary Serial Flash. When using Quad SPI instructions, the DI and DO pins
become bidirectional IO0 and IO1, with the additional I/O pins: IO2, IO3.
6.2 Software Reset & Hardware /RESET pin
The W25Q16JV can be reset to the initial power-on state by a software Reset sequence. This sequence
must include two consecutive instructions: Enable Reset (66h) & Reset (99h). If the instruction sequence
is successfully accepted, the device will take approximately 30µS (tRST) to reset. No instruction will be
accepted during the reset period. For the SOIC-16 and TFBGA packages, W25Q16JV provides a dedicated
hardware /RESET pin. Drive the /RESET pin low for a minimum period of ~1µS (tRESET*) will interrupt any
on-going external/internal operations and reset the device to its initial power-on state. Hardware /RESET
pin has higher priority than other SPI input signals (/CS, CLK, IOs).
Note:
1. Hardware /RESET pin is available on SOIC-16 or TFBGA; please contact Winbond for his package.
2. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended
to ensure reliable operation.
3. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 package. If the reset function is not needed,
this pin can be left floating in the system.
W25Q16JV
Publication Release Date: April 08, 2019
- 10 - Revision H
6.3 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q16JV
provides several means to protect the data from inadvertent writes.
6.4 Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Registers
Additional Individual Block/Sector Locks for array protection
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q16JV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-
down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP[2:0]) bits. These settings allow a
portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect
(/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status
Register section for further information. Additionally, the Power-down instruction offers an extra level of
write protection as all instructions are ignored except for the Release Power-down instruction.
The W25Q16JV also provides another Write Protect method using the Individual Block Locks. Each 64KB
block (except the top and bottom blocks, total of 30 blocks) and each 4KB sector within the top/bottom
blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the
corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program
commands issued to the corresponding sector or block will be ignored. When the device is powered on, all
Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An
“Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When
WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of
the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
W25Q16JV
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7. STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25Q16JV. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the
device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock
status, Erase/Program Suspend status, and output driver strength. The Write Status Register instruction
can be used to configure the device write protection features, Quad SPI setting, Security Register OTP
locks, and output driver strength. Write access to the Status Register is controlled by the state of the non-
volatile Status Register Protect bits (SRL), the Write Enable instruction, and during Standard/Dual SPI
operations.
7.1 Status Registers
Figure 4a. Status Register-1
Erase/Write In Progress (BUSY) Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE
in AC Characteristics). When the program, erase or write status/security register instruction has completed,
the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
Write Enable Latch (WEL) Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable
state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and
Program Security Register.
Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The factory
default setting for the Block Protection Bits is 0, none of the array protected.
SRP
SEC
TB
BP
2
BP
1
BP
0
WEL
BUSY
TOP/BOTTOM PROTECT
WRITE ENABLE LATCH
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
STATUS REGISTER PROTECT
SECTOR PROTECT
BLOCK PROTECT BITS
WRITE IN PROGRESS
(volatile/non-volatile)
(volatile/non-volatile)
(volatile/non-volatile)
(volatile/non-volatile)
W25Q16JV
Publication Release Date: April 08, 2019
- 12 - Revision H
Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The
factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending
on the state of the SRL and WEL bits.
Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in the Status Register Memory Protection table. The default setting is SEC=0.
Complement Protect (CMP) Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance,
when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top
64KB block will become unprotected while the rest of the array become read-only. Please refer to the Status
Register Memory Protection table for details. The default setting is CMP=0.
W25Q16JV
- 13 -
Status Register Protect SRP, SRL) Volatile/Non-Volatile Writable
Three Status and Configuration Registers are provided for W25Q16JV. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device
is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,
Erase/Program Suspend status, and output driver strength, The Write Status Register instruction can be
used to configure the device write protection features, Quad SPI setting, Security Register OTP locks,
output driver. Write access to the Status Register is controlled by the state of the non-volatile Status Register
Protect bits (SRP, SRL), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP
pin.
SRL
SRP
/WP
Status
Register
Description
0
0
X
Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and cannot be
written to.
0
1
1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
1
X
X
Power Supply
Lock-Down
Status Register is protected and cannot be written to again
until the next power-down, power-up cycle.(1)
1
X
X
One Time
Program(2)
Status Register is permanently protected and cannot be written
to. (enabled by adding prefix command AAh, 55h)
1. When SRL =1 , a power-down, power-up cycle will change SRL =0 state.
2. Please contact Winbond for details regarding the special instruction sequence.
.
W25Q16JV
Publication Release Date: April 08, 2019
- 14 - Revision H
Figure 4b. Status Register-2
Erase/Program Suspend Status (SUS) Status Only
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
Security Register Lock Bits (LB3, LB2, LB1) Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
8. QUAD ENABLE (QE) Volatile/Non-Volatile Writable
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that enables Quad SPI
operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options “IM” &
“JM”), the /HOLD are enabled, the device operates in Standard/Dual SPI modes. When the QE bit is set to
a 1 (factory fixed default for part numbers with ordering options “IQ” &”JQ”), the Quad IO2 and IO3 pins are
enabled, and /HOLD function is disabled, the device operates in Standard/Dual/Quad SPI modes.
S
15
S
14
S
13
S
12
S
11
S
10
S
9
S
8
SUS
CMP
LB
3
LB
2
LB
1
(
R
)
QE
SR
L
S
tatus Register Lock
(
Volatile
/
Non
-
Volatile Writable
)
Complement Protect
(
Volatile
/
Non
-
Volatile Writable
)
Security Register Lock Bits
(Non-Volatile OTP Writable)
Reserved
Quad Enable
(
Volatile
/
Non
-
Volatile Writable
)
Suspend Status
(
Status
-
Only
)
W25Q16JV
- 15 -
(R) (R)
/HOLD or /Reset Functions
HOLD
/RST DRV1DRV0 (R)
Reserved
WPS(R)
Reserved
Reserved
Write Protect Selection
(Volatile/Non-Volatile Writable)
S16S17S19S20S21S22S23 S18
Figure 4c. Status Register-3
Write Protect Selection (WPS) Volatile/Non-Volatile Writable
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will
use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When
WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The
default value for all Individual Block Lock bits is 1 upon device power on or after reset.
Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
0, 0
100%
0, 1
75%
1, 0
50%
1, 1
25% (default)
Reserved Bits Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a Write Status Register” instruction, the Reserved Bits can be written
as “0”, but there will not be any effects.
W25Q16JV
Publication Release Date: April 08, 2019
- 16 - Revision H
W25Q16JV Status Register Memory Protection (WPS = 0, CMP = 0)
STATUS REGISTER(1)
W25Q16JV (16M-BIT) MEMORY PROTECTION(3)
SEC
TB
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
31
1F0000h 1FFFFFh
64KB
Upper 1/32
0
0
0
1
0
30 and 31
1E0000h 1FFFFFh
128KB
Upper 1/16
0
0
0
1
1
28 thru 31
1C0000h 1FFFFFh
256KB
Upper 1/8
0
0
1
0
0
24 thru 31
180000h 1FFFFFh
512KB
Upper 1/4
0
0
1
0
1
16 thru 31
100000h 1FFFFFh
1MB
Upper 1/2
0
1
0
0
1
0
000000h 00FFFFh
64KB
Lower 1/32
0
1
0
1
0
0 and 1
000000h 01FFFFh
128KB
Lower 1/16
0
1
0
1
1
0 thru 3
000000h 03FFFFh
256KB
Lower 1/8
0
1
1
0
0
0 thru 7
000000h 07FFFFh
512KB
Lower 1/4
0
1
1
0
1
0 thru 15
000000h 0FFFFFh
1MB
Lower 1/2
X
X
1
1
X
0 thru 31
000000h 1FFFFFh
2MB
ALL
1
0
0
0
1
31
1FF000h 1FFFFFh
4KB
U 1/512
1
0
0
1
0
31
1FE000h 1FFFFFh
8KB
U 1/256
1
0
0
1
1
31
1FC000h 1FFFFFh
16KB
U 1/128
1
0
1
0
X
31
1F8000h 1FFFFFh
32KB
U 1/64
1
1
0
0
1
0
000000h 000FFFh
4KB
L 1/512
1
1
0
1
0
0
000000h 001FFFh
8KB
L 1/256
1
1
0
1
1
0
000000h 003FFFh
16KB
L 1/128
1
1
1
0
X
0
000000h 007FFFh
32KB
L 1/64
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command
will be ignored.
W25Q16JV
- 17 -
W25Q16JV Status Register Memory Protection (WPS = 0, CMP = 1)
STATUS REGISTER(1)
W25Q16JV (16M-BIT) MEMORY PROTECTION(3)
SEC
TB
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X
X
0
0
0
0 thru 31
000000h 1FFFFFh
ALL
ALL
0
0
0
0
1
0 thru 30
000000h 1EFFFFh
1,984KB
Lower 31/32
0
0
0
1
0
0 thru 29
000000h 1DFFFFh
1,920KB
Lower 15/16
0
0
0
1
1
0 thru 27
000000h 1BFFFFh
1,792KB
Lower 7/8
0
0
1
0
0
0 thru 23
000000h 17FFFFh
1,536KB
Lower 3/4
0
0
1
0
1
0 thru 15
000000h 0FFFFFh
1MB
Lower 1/2
0
1
0
0
1
1 thru 31
010000h 1FFFFFh
1,984KB
Upper 31/32
0
1
0
1
0
2 and 31
020000h 1FFFFFh
1,920KB
Upper 15/16
0
1
0
1
1
4 thru 31
040000h 1FFFFFh
1,792KB
Upper 7/8
0
1
1
0
0
8 thru 31
080000h 1FFFFFh
1,536KB
Upper 3/4
0
1
1
0
1
16 thru 31
100000h 1FFFFFh
1MB
Upper 1/2
X
X
1
1
X
NONE
NONE
NONE
NONE
1
0
0
0
1
0 thru 31
000000h 1FEFFFh
2,044KB
L 511/512
1
0
0
1
0
0 thru 31
000000h 1FDFFFh
2,040KB
L 255/256
1
0
0
1
1
0 thru 31
000000h 1FBFFFh
2,032KB
L 127/128
1
0
1
0
X
0 thru 31
000000h 1F7FFFh
2,016KB
L 63/64
1
1
0
0
1
0 thru 31
001000h 1FFFFFh
2,044KB
U 511/512
1
1
0
1
0
0 thru 31
002000h 1FFFFFh
2,040KB
U 255/256
1
1
0
1
1
0 thru 31
004000h 1FFFFFh
2,032KB
U 127/128
1
1
1
0
X
0 thru 31
008000h 1FFFFFh
2,016KB
U 63/64
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command
will be ignored.
W25Q16JV
Publication Release Date: April 08, 2019
- 18 - Revision H
W25Q16JV Individual Block Memory Protection (WPS=1)
Figure 4d. Individual Block/Sector Locks
Notes:
1. Individual Block/Sector protection is only valid when WPS=1.
2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
Sector 0 (4KB)
Sector 1 (4KB)
Sector 14 (4KB)
Sector 15 (4KB)
Block 1 (64KB)
Block 30 (64KB)
Sector 0 (4KB)
Sector 1 (4KB)
Sector 14 (4KB)
Sector 15 (4KB)
Block 0
(64KB) Block 31
(64KB)
Individual Block Locks:
32 Sectors (Top/Bottom)
30 Blocks
Individual Block Lock:
36h + Address
Individual Block Unlock:
39h + Address
Read Block Lock:
3Dh + Address
Global Block Lock:
7Eh
Global Block Unlock:
98h
W25Q16JV
- 19 -
9. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25Q16JV consists of 48 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data
on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through
57. All read instructions can be completed after any clocked bit. However, all instructions that Write,
Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked)
otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes.
Additionally, while the memory is being programmed or erased, or when the Status Register is being written,
all instructions except for Read Status Register will be ignored until the program or erase cycle has
completed.
9.1 Device ID and Instruction Set Tables
Manufacturer and Device Identification
MANUFACTURER ID
(MF7 - MF0)
Winbond Serial Flash
EFh
Device ID
(ID7 - ID0)
(ID15 - ID0)
Instruction
ABh, 90h, 92h, 94h
9Fh
W25Q16JV-IQ/JQ
14h
4015h
W25Q16JV-IM*/JM*
14h
7015h
Note: For DTR, QPI supporting, please refer to W25Q16JV DTR datasheet.