HV257
Features
32 independent high voltage amplifiers
300V operating voltage
295V output voltage
2.2V/µs typical output slew rate
Adjustable output current source limit
Adjustable output current sink limit
Internal closed loop gain of 72V/V
12MΩ feedback impedance
Layout ideal for die applications
Applications
MEMS (microelectromechanical systems) driver
Piezoelectric transducer driver
Optical crosspoint switches (using MEMS
technology)
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General Description
The Supertex HV257 is a 32-channel, high voltage, sample and
hold amplifier array integrated circuit. It operates on a single high
voltage supply, up to 300V, and two low voltage supplies, VDD and
VNN.
All 32 sample and hold circuits share a common analog input,
VSIG. The individual sample and hold circuits are selected by a 5 to
32 logic decoder. The sampled voltage on the holding capacitor is
buffered by a low voltage amplifier and amplified by a high voltage
amplifier with a closed loop gain of 72V/V. The internal closed
loop gain is set for an input voltage range of 0 to 4.096V. The
input voltage can be up to 5.0V, but the output will saturate. The
maximum output voltage swing is 5.0V below the VPP high voltage
supply. The outputs can drive capacitive loads of up to 3000pF.
The maximum output source and sink current can be adjusted
by using two external resistors. An external RSOURCE resistor
controls the maximum sourcing current, and an external RSINK
resistor controls the maximum sinking current. The current limit
is approximately 12.5V divided by the external resistor value. The
setting is common for all 32 outputs. A low voltage silicon junction
diode is made available to help monitor the die temperature.
Typical Application Circuit
32-Channel High Voltage
Sample and Hold Amplifier Array
VSIG
A0
EN
A3
A2
A4
HVOUT0
HV257 High Voltage
Power Supply
Low Voltage
Power Supply
32
DGND AGND
HVOUT1
MEMS
Array
y
y
xx
HVOUT2
HVOUT3
HVOUT30
HVOUT31
A1
VNN
Low Voltage
Channel
Select
Sample
and Hold
High Voltage
OpAmp Array
RSOURCE
RSINK
Micro
Processor
DAC
2
HV257
Sym Parameter Min Typ Max Units Conditions
Operating Conditions
VPP High voltage positive supply 125 - 300 V ---
VDD Low voltage positive supply 6.0 - 7.5 V ---
VNN Low voltage negative supply -4.5 - -6.5 V ---
IPP VPP supply current - - 0.8 mA VPP = 300V, All HVOUT = 0V No load
IDD VDD supply current - - 5.0 mA VDD = 6.0 to 7.5V
INN VNN supply current -6.0 - - mA VNN = -4.5 to -6.5V
TJOperating temperature range -10 - 85 °C ---
Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect device
reliability. All voltages are referenced to device ground.
Parameter Value
VPP
, High voltage supply 310V
AVDD, Analog low voltage positive supply 8.0V
DVDD, Digital low voltage positive supply 8.0V
AVNN, Analog low voltage negative supply -7.0V
DVNN, Digital low voltage negative supply -7.0V
Logic input voltage -0.5V to DVDD
VSIG, Analog input signal 0V to 6.0V
Storage temperature range -65°C to 150°C
Maximum junction temperature 150°C
Product Marking
100-Lead MQFP (FG)
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Top Marking
HV257FG
LLLLLLLLLL
YYWW
CCCCCCCC AAA
Device
100-Lead MQFP
20.00x14.00mm body
3.15mm height (max)
0.65mm pitch
3.20mm footprint
HV257 HV257FG-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
100-Lead MQFP
(top view)
1
100
30
31
50
80 51
81
Ordering Information
100-Lead MQFP (FG)
(top view)
3
HV257
Sym Parameter Min Typ Max Units Conditions
HVOUT HVOUT voltage swing 0 - VPP-5.0 V ---
VINOS Input offset - - ±40 mV Input referred
SR HVOUT slew rate rise - 2.2 - V/µs No Load
HVOUT slew rate fall - 2.0 - V/µs No Load
BW HVOUT -3dB channel bandwidth - 4.0 - KHz VPP = 300V
AOOpen loop gain 70 100 - dB ---
AVClosed loop gain 68.4 72 75.6 V/V ---
RFB Feedback resistance from HVOUT to ground 9.6 12 - MΩ ---
CLOAD HVOUT capacitive load 0 - 3000 pF ---
ISOURCE HVOUT sourcing current limiting range 50 - 500 µA ISOURCE = 12.5V/RSOURCE
ISINK HVOUT sinking current limiting range 50 - 500 µA ISINK = 12.5V/RSINK
RSOURCE
External resistance range for setting
maximum current source 25 - 250 KΩ ---
RSINK
External resistance range for setting
maximum current sink 25 - 250 KΩ ---
CTDC DC channel to channel crosstalk -80 - - dB ---
PSRR Power supply rejection ratio for VPP
, VDD, VNN -40 - - dB ---
Sample and Hold
tAQ Acquisition time - 4.0 - µs ---
VPED Pedestal voltage - 1.0 - mV Input referred
RSW Sample and hold switch resistance - 5.0 - kΩ ---
CHSample and hold capacitor - 10 12 pF ---
VDROOP
Voltage droop rate during hold time relative
to input - 6.0 - V/s Output referred
VSIG Input signal voltage range 0 - 5.0 V ---
CSIG VSIG input capacitance - 33 - pF ---
Logic Decoder
tSU Set-up time-address to enable 75 - - ns ---
tHHold time-address to enable bar 75 - - ns ---
VIH Input logic high voltage 2.4 - VDD V ---
VIL Input logic low voltage 0 - 1.2 V ---
IIH Input logic high current - - 1.0 µA VIH = VDD
IIL Input logic low current -1.0 - - µA VIL = 0V
CIN Logic input capacitance - - 15 pF ---
Electrical Characteristics (over operating conditions, unless otherwise specified)
High Voltage Amplifier
4
HV257
Decoder Truth Table
Sym Parameter Min Typ Max Units Conditions
Temperature Diode
A4A3A2A1A0EN Selected S/H
L L L L L H 0
L L L L H H 1
L L L H L H 2
L L L H H H 3
↕ ↕ ↕ ↕ ↕ ↕ ↕
H H H H L H 30
H H H H H H 31
X X X X X L All Open
PIV Peak inverse voltage - - 5.0 V cathode to anode
VFForward diode drop - 0.6 - V IF = 100µA, anode to cathode at TA = 25°C
IFForward diode current - - 100 µA anode to cathode
TCVF temperature coefficient - -2.2 - mV/°C anode to cathode
Sample and Hold Timing
tSU tH
Hold Step
(Vpedestal )
Hold HoldSample
A0-A4
EN
HVOpamp
tR/F
Acquisition Window
5
HV257
Block Diagram
71R
R
AVNN
HVOUT0
VPP
AVNN
AVDD
S/H - 0
5 to 32
Decoder
VSIG
A0
A1
A2
A3
EN
A4
71R
R
S/H - 1
HVOUT1
VPP
71R
R
S/H - 31
HVOUT31
VPP
AVDD
AVNN
AVNN
CH
-
+
-
+
Q0
Q1
Q31
HVOUT
Current
Sink
Limiting
To all HVOUT
amplifiers
To all HVOUT
amplifiers
RSOURCE
RSINK
DVDD
AVNN
DGND
To internal digital VDD bus
To internal analog VNN bus
AGND
VPP
AVDD
To internal VPP bus
To internal analog VDD bus
DVDD
DVNN To internal digital VNN bus
AVDD
AVNN
AVNN
CH
CH
BYP-VPP
BYP-AVDD
BYP-AVNN
Anode Cathode
Bias Circuit
-
+
-
+
-
+
-
+
HVOUT
Current
Source
Limiting
6
HV257
Power Up/Down Issues
External Diode Protection
The device can be damaged due to improper power up / down
sequence. To prevent damage, please follow the acceptable
power up / down sequences, and add two external diodes as
shown in the diagram on the right. The first diode is a high
voltage diode across VPP and VDD, where the anode of the
diode is connected to VDD and the cathode of the diode
is connected to VPP. Any low current, high voltage diode,
such as a 1N4004, will be adequate. The second diode is a
Schottky diode across VNN and DGND, where the anode of
the Schottky diode is connected to VNN, and the cathode is
connected to DGND. Any low current Schottky diode such
as a 1N5817 will be adequate.
Acceptable Power Up Sequences
The HV257 can be powered up with any of the following
sequences listed below.
1) VPP 2) VNN 3) VDD 4) Inputs and Anode
1) VNN 2) VDD 3) VPP 4) Inputs and Anode
1) VDD & VNN 2) Inputs 3) VPP 4) Anode
Acceptable Power Down Sequences
The HV257 can be powered down with any of the following
sequences listed below.
1) Inputs and Anode 2) VDD 3) VNN 4) VPP
1) Inputs and Anode 2) VPP 3) VDD 4) VNN
1) Anode 2) VPP 3) Inputs 4) VNN & VDD
External Diode Protection Connection
Suggested Power Up/Down Sequence
The HV257 needs all power supplies to be fully up and all
channels refreshed with VSIG = 0V to force all high voltage
outputs to 0V. Before that time, the high voltage outputs
may have temporary voltage excursions above or below
GND level depending on selected power up sequence. To
minimize the excursions:
1. The VDD and VNN power supplies should be applied at
the same time (or within a few nanoseconds).
2. All channels should be continuously refreshed with
VSIG = 0V, just before, and while the VPP is ramping up.
Suggested VPP ramp up speed should be 10msec or longer
and ramp down to be 1msec or longer.
VDD VPP
1N4004 or similar
VNN DGND
1N5817 or similar
Recommended Power Up/Down Timing
0V
VNN
6.5V
-5.5V
0V
300V
0V
HVOUT
0V
VSIG
0 1 2 31 0 0 1 2
Gnd +/- V offset X 72
0V
EN
0V
6.5V
-5.5V
0V
VDD
VPP
300V
0V
0V
A0 - A4
Gnd +/- V offset X 72
0V
HVOUT Level at Power Up
Power Up Sequence
VNN Before VDD
0V
VNN
6.5V
-5.5V
-5.5V
0V
VDD
VPP0V
HVOUT 0V
0V
VNN
6.5V
6.5V
-5.5V
0V
VDD
VPP0V
HVOUT
0V
VDD Before VNN
7
HV257
RSINK / RSOURCE
Ground Isolation (AGND/DGND Isolation)
The VDD_BYP, VDD_BYP, and VNN_BYP pins are internal,
high impedance current, mirror gate nodes, brought out to
mantain stable opamp biasing currents in noisy power supply
environments. 0.1uF/25V bypass capacitors, added from
VPP_BYP pin to VPP, from VDD_BYP pin to VDD, and from
VNN_BYP to VNN, will force the high impedance gate nodes
to follow fluctuation of power lines. The expected voltages at
the VDD_BYP, and VNN_BYP pins are typically 1.5 volts
from their respectful power supply. The expected voltage at
VPP_BYP is typically 3V below VPP.
BYP_VPP
HVOpamp
VDD
VPP
BYP_VNN
VNN
Set by RSOURCE
Set by RSINK
HVOUT0
BYP _ VPP Cap
BYP _ VNN Cap
Current limit
Current limit
BYP_VDD
BYP_ VDD Cap
To internal biasing
0.1uF / 25V
0.1uF / 25V
0.1uF / 25V
HVOpamp
HVOUT31
It is important that the AGND pin is connected to a clean
ground. The hold capacitors are internally connected to the
AGND, and any ground noise will directly couple to the high
voltage outputs (with a gain of 72). The analog and digital
ground traces on the PCB should be physically separated to
reduce digital switching noise degrading the signal to noise
performance.
DGND
LVOpamp
AVDD VPP
AVNN
AGND1 (pins 89, 43)
VSIG HVOpamp HVOUT
1R
71R
AGND2 (pin 39)
EN, A0-A4
DVDD DVNN
DAC
External bypass caps:
C1 = 0.1µF / 500V
C2, C3, C4, C5 = 0.1µF / 25V
C_hold
10pFC_comp C_comp
C2
C1
C4
C3
C5 C6
Single star GND
Sample
switch
8
HV257
Typical Characteristics
ISINK vs RSINK
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
RSINK (KΩ)
ISINK (µA)
0
100
200
300
400
500
600
25k 150k 250k
min
max
0
20
40
60
80
100
120
1 2 4
Acquisition Window
(”one RC” response to one volt input step)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
VSIG Level (V)
One RC (nsec)
+85OC
+25OC
-10OC
HVOUT Charge Injection vs VSIG
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
VSIG Level (V)
HVOUT (mV)
-40
-20
0
20
40
0v 1v 2v 3v 4v
HVOUT (V/sec)
HVOUT Droop
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
HVOUT Level (V)
-2
0
2
3
0 150 280
1
-1
-10OC
85OC
25OC
9
HV257
Typical Characteristics (cont.)
Frequency (Hz)
0
-10
-20
-30
-40
-50
10 100 1k 10k 100k 1M
VPP PSRR (dB)
VPP PSRR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
Frequency (Hz)
0
-10
-20
-30
-40
-50
10 100 1k 10 100 1M
VDD PSRR (dB)
VDD PSRR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
Frequency
0
-10
-20
-30
-40
-50
10 100 1k 10k 100k 1M
VNN PSRR (dB)
VNN PSRR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
1.5
2.0
2.5
3.0
3.5
123
VIN (Volts)
Input Offset (mV)
Offset at -10OC
Offset at 25OC
Offset at 85OC
Input Offset vs VIN and Temperature
(VPP = 300V, VDD = 6.5V, VNN = 5.5V )
73.96
123
VIN (Volts)
Gain
Gain vs VIN
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC )
73.95
73.94
73.93
73.97
72.74
72.73
72.72
72.71
72.70
72.69
HVOUT Drift
HV257DFG-5037047 Q3 Dev # 3, Channel 16
(VPP = 300V, VDD = 6.5V, VNN = -5V, VSIG=1V, TA = 25OC)
73.014
73.016
73.018
73.02
73.022
73.024
73.026
73.028
73.03
Time (hours)
08
HVOUT (V)
10
HV257
Pad Configuration (not drawn to scale)
HVOUT0
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT5
HVOUT6
HVOUT7
HVOUT8
HVOUT9
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
VPP
Cathode
Anode
VPP
BYP-VPP
RSOURCE
RSINK
A4
A3
A2
A1
A0
EN
DVDD
DVNN
AGND
AGND
AVDD
AVNN
DVDD
DVNN
AGND
AVDD
AVNN
DGND
VSIG
Byp-AVNN
Byp-AVDD
Do Not Bond.
For testing only
Do Not Bond.
Leave Floating.
11
HV257
Pad Coordinates
Chip size: 17160μm x 5830μm
Center of die is (0,0)
Pad Name X (μm) Y (μm)
VPP -8338.5 2708.5
HVOUT0 -7895.0 2305.5
HVOUT1 7448.5 2305.5
HVOUT2 -7001.5 2305.5
HVOUT3 -6554.5 2305.5
HVOUT4 -6107.5 2305.5
HVOUT5 -5660.5 2305.5
HVOUT6 -5213.5 2305.5
HVOUT7 -4776.5 2305.5
HVOUT8 -4319.5 2305.5
HVOUT9 -3872.5 2305.5
HVOUT10 -3425.5 2305.5
HVOUT11 -2978.5 2305.5
HVOUT12 -2513.5 2305.5
HVOUT13 -2084.5 2305.5
HVOUT14 -1637.5 2305.5
HVOUT15 -1190.5 2305.5
HVOUT16 -743.5 2305.5
HVOUT17 -296.5 2305.5
HVOUT18 150.0 2305.5
HVOUT19 597.5 2305.5
HVOUT20 1044.5 2305.5
HVOUT21 1491.5 2305.5
HVOUT22 1938.5 2305.5
HVOUT23 2385.5 2305.5
HVOUT24 2832.5 2305.5
HVOUT25 3279.5 2305.5
HVOUT26 3726.5 2305.5
HVOUT27 4173.5 2305.5
HVOUT28 4620.5 2305.5
HVOUT29 5067.5 2305.5
Pad Name X (μm) Y (μm)
HVOUT30 5514.5 2305.5
HVOUT31 5961.5 2305.5
VPP 6659.0 2709.0
BYP-VPP 7045.0 2709.0
RSOURCE 7489.0 2709.0
RSINK 7969.0 2709.0
CATHODE 8366.0 2709.0
ANODE 8366.0 2199.0
AVNN 8047.0 425.0
BYP-AVDD 8047.0 125.5
BYP-AVNN 8047.0 -135.5
AVDD 8047.0 -704.5
VSIG 8047.0 -1072.5
AGND 8047.0 -1424.5
DVNN 8066.5 -1590.0
DVDD 8066.5 -1958.5
DGND 7867.0 -2192.0
A4 7723.0 -2684.0
A3 7319.0 -2684.0
A2 6913.0 -2684.0
A1 6508.5 -2684.0
A0 6103.5 -2684.0
EN 5698.0 -2684.0
N/C 5043.5 -2686.0
N/C 4638.5 -2686.0
N/C 4233.5 -2686.0
N/C 3828.5 -2686.0
N/C 3423.5 -2686.0
N/C 3018.5 -2686.0
N/C 2613.5 -2686.0
N/C 2208.5 -2686.0
Pad Name X (μm) Y (μm)
N/C 1803.5 -2686.0
N/C 1398.5 -2686.0
N/C 993.5 -2686.0
N/C 588.5 -2686.0
N/C 183.5 -2686.0
N/C -221.5 -2686.0
N/C -626.5 -2686.0
N/C -1031.5 -2686.0
N/C -1436.5 -2686.0
N/C -2412.0 -2686.0
N/C -2817.0 -2686.0
N/C -3222.0 -2686.0
N/C -3627.0 -2686.0
N/C -4032.0 -2686.0
N/C -4437.0 -2686.0
N/C -4842.0 -2686.0
N/C -5247.0 -2686.0
N/C -5652.0 -2686.0
N/C -6052.0 -2686.0
N/C -6462.0 -2686.0
N/C -6867.0 -2686.0
N/C -7272.0 -2686.0
N/C -7677.0 -2686.0
N/C -8082.0 -2686.0
DVDD -8373.0 -2250.5
DVNN -8373.0 -1949.0
AGND -8367.0 -1561.0
AVDD -8387.0 -1143.0
AVNN -8338.5 577.5
AGND -8341.0 916.5
12
HV257
Pin # Function Description
1 HVOUT31
Amplifier outputs.
2 HVOUT30
3 HVOUT29
4 HVOUT28
5 HVOUT27
6 HVOUT26
7 HVOUT25
8 HVOUT24
9 HVOUT23
10 HVOUT22
11 HVOUT21
12 HVOUT20
13 HVOUT19
14 HVOUT18
15 HVOUT17
16 HVOUT16
17 HVOUT15
18 HVOUT14
19 HVOUT13
20 HVOUT12
21 HVOUT11
22 HVOUT10
23 HVOUT9
24 HVOUT8
25 HVOUT7
26 HVOUT6
27 HVOUT5
28 HVOUT4
29 HVOUT3
30 HVOUT2
31 HVOUT1
32 HVOUT0
33 VPP High voltage positive supply. There are two pads.
Pin Description
13
HV257
Pin # Function Description
34-38 NC No connect
39 AGND Analog ground. There are three pads. They need to be externally connected.
40 AVNN Analog low voltage negative supply. This should be at the same potential as DVNN. There are
two pads.
41 NC No connect
42 AVDD Analog low voltage positive supply. This should be at the same potential as DVDD. There are
two pads.
43 AGND Analog ground. There are three pads. They need to be externally connected.
44 DVNN Digital low voltage negative supply. This should be at the same potential as AVNN. There are
two pads.
45 DVDD Digital low voltage positive supply. This should be at the same potential as AVDD. There are
two pads.
46-79 NC No Connect
80 EN Active logic high input. Logic low will keep sample and hold switches open.
81 A0
Decoder logic input. Addressed channel will close the sample and hold switch. Sample and hold
switches for unaddressed channels are kept open.
82 A1
83 A2
84 A3
85 A4
86 DGND Digital ground.
87 DVDD Digital low voltage positive supply. This should be at the same potential as AVDD. There are
two pads.
88 DVNN Digital low voltage negative supply. This should be at the same potential as AVNN. There are
two pads.
89 AGND Analog ground. There are three pads. They need to be externally connected.
90 VSIG Common input signal for all 32 sample and hold circuits.
91 AVDD Analog low voltage positive supply. This should be at the same potential as DVDD. There are
two pads.
92 BYP-AVNN Internally generated reference voltage. An external low voltage (1.0 - 10nF) capacitor needs to
be connected across AVNN and BYP-AVNN.
93 BYP-AVDD Internally generated reference voltage. An external low voltage (1.0 - 10nF) capacitor needs to
be connected across AVDD and BYP-AVDD.
94 AVNN Analog low voltage negative supply. This should be at the same potential as DVNN. There are
two pads.
95 Anode Anode side of a low voltage silicon diode that can be used to monitor die temperature.
96 Cathode Cathode side of a low voltage silicon diode that can be used to monitor die temperature.
Pin Description (cont.)
14
HV257
Pin # Function Description
97 RSINK External resistor from RSINK to VNN sets output current sinking limit. Current limit is
approximately 12.5V divided by RSINK resistor value.
98 RSOURCE External resistor from RSOURCE to VNN sets output current sourcing limit. Current limit is
approximately 12.5V divided by RSOURCE resistor value.
99 BYP-VPP Internally generated reference voltage. An external low voltage (1.0 - 10nF) capacitor needs to
be connected across VPP and BYP-VPP.
100 VPP High voltage positive supply. There are two pads.
Pin Description (cont.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
15
HV257
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV257
C102208
100-Lead MQFP Package Outline (FG)
20.00x14.00mm body, 3.15mm height (max), 0.65mm pitch, 3.20mm footprint
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ θ1
Dimension
(mm)
MIN 2.50* 0.00 2.50 0.22 22.95* 19.80* 16.95* 13.80* 0.65
BSC
0.73 1.60
REF
0.25
BSC
0O5O
NOM - - 2.70 - 23.20 20.00 17.20 14.00 0.88 - -
MAX 3.15 0.25 2.90 0.40 23.45* 20.20* 17.45* 14.20* 1.03 7O16O
JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-100MQFPFG, Version E101708.
1
100
Top View
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
θ1
b
e
Side View
A2
A
A1
E
E1
DD1
Seating
Plane
Note 1
(Index Area
E1/4 x D1/4)
Note:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
1.