19-5926; Rev 0; 6/11 IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Features The MAX5969D provides a complete interface for a powered device (PD) to comply with the IEEE(R) 802.3af/ at standard in a power-over-Ethernet (PoE) system. The MAX5969D provides the PD with a detection signature, classification signature, and an integrated isolation power switch with inrush current control. During the inrush period, the MAX5969D limits the current to less than 180mA before switching to the higher current limit (720mA to 880mA) when the isolation power MOSFET is fully enhanced. The device features an input UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off conditions. The MAX5969D can withstand up to 100V at the input. S IEEE 802.3af/at Compliant The MAX5969D supports a 2-event classification method as specified in the IEEE 802.3at standard and provide a signal to indicate when probed by a Type 2 power sourcing equipment (PSE). The device detects the presence of a wall adapter power source connection and allow a smooth switch over from the PoE power source to the wall power adaptor. S Thermally Enhanced, 5mm x 5mm, 16-Pin TQFN The MAX5969D also provides a power-good (PG) signal, two-step current limit and foldback, overtemperature protection, and di/dt limit. The MAX5969D is available in a 16-pin, 5mm x 5mm TQFN power package. This device is rated over the -40NC to +85NC extended temperature range. S 2-Event Classification or an External Wall Adapter Indicator Output S Simplified Wall Adapter Interface S PoE Classification 0-5 S 100V Input Absolute Maximum Rating S Inrush Current Limit of 180mA Maximum S Current Limit During Normal Operation Between 720mA and 880mA S Current Limit and Foldback S Legacy UVLO at 36V S Overtemperature Protection Applications IEEE 802.3af/at Powered Devices IP Phones, Wireless Access Nodes, IP Security Cameras WiMAXK Base Stations Ordering Information PART MAX5969DETE+ TEMP RANGE PIN-PACKAGE -40NC to +85NC 16 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. WiMAX is a trademark of WiMAX Forum. IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. ________________________________________________________________ Maxim Integrated Products1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX5969D General Description MAX5969D IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET ABSOLUTE MAXIMUM RATINGS VDD to VSS...........................................................-0.3V to +100V DET, RTN, WAD, PG, 2EC to VSS........................ -0.3V to +100V CLS to VSS...............................................................-0.3V to +6V Maximum Current on CLS (100ms maximum)..................100mA Continuous Power Dissipation (TA = +70NC) (Note 1) TQFN (derate 28.6mW/NC above +70NC) Multilayer Board......................................................2285.7mW Operating Temperature Range........................... -40NC to +85NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s)............................... +300NC Soldering Temperature.................................................. +260NC Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 2) TQFN Junction-to-Ambient Thermal Resistance (BJA)...............35NC/W Junction-to-Case Thermal Resistance (BJC)..................2.7NC/W Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VIN = (VDD - VSS) = 48V, RDET = 24.9k, RCLS = 615, and RSL = 60.4k. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 FA kI DETECTION MODE Input Offset Current Effective Differential Input Resistance IOFFSET dR VIN = 1.4V to 10.1V (Note 4) VIN = 1.4V up to 10.1V with 1V step, VDD = RTN = WAD = PG = 2EC (Note 5) 23.95 25.00 25.50 22.0 22.8 23.6 CLASSIFICATION MODE Classification Disable Threshold VTH,CLS VIN rising (Note 6) Classification Stability Time Classification Current 0.2 ICLASS VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG = 2EC V ms Class 0, RCLS = 619I 0 3.96 Class 1, RCLS = 117I 9.12 11.88 Class 2, RCLS = 66.5I 17.2 19.8 Class 3, RCLS = 43.7I 26.3 29.7 Class 4, RCLS = 30.9I 36.4 43.6 Class 5, RCLS = 21.3I 52.7 63.3 mA TYPE 2 (802.3at) CLASSIFICATION MODE Mark Event Threshold Hysteresis on Mark Event Threshold VTHM VIN falling 10.1 10.7 0.84 2_______________________________________________________________________________________ 11.6 V V IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET (VIN = (VDD - VSS) = 48V, RDET = 24.9k, RCLS = 615, and RSL = 60.4k. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN Mark Event Current IMARK VIN falling to enter mark event, 5.2V P VIN P 10.1V 0.25 Reset Event Threshold VTHR VIN falling 2.8 TYP MAX 0.85 UNITS mA 4 5.2 V 60 V 0.27 0.55 mA 36.6 V POWER MODE VIN Supply Voltage Range VIN Supply Current IQ VIN Turn-On Voltage VON VIN rising 34.3 VIN Turn-Off Voltage VOFF VIN falling 30 V (Note 7) 4.2 V VIN falling from 40V to 20V (Note 8) 30 tDELAY = minimum PG current pulse width after entering into power mode 87 VIN Turn-On/-Off Hysteresis VIN Deglitch Time VHYST_ UVLO tOFF_DLY Inrush to Operating Mode Delay tDELAY Isolation Power MOSFET On-Resistance RON_ISO RTN Leakage Current IRTN_LKG IRTN = 600mA 35.4 120 Fs 96 105 TJ = +25NC 0.5 0.7 TJ = +85NC 0.65 1 I TJ = +125NC 0.8 10 FA VRTN = 12.5V to 30V ms CURRENT LIMIT Inrush Current Limit Current Limit During Normal Operation IINRUSH ILIM Foldback Threshold During initial turn-on period, VRTN = 1.5V 90 135 180 mA After inrush completed, VRTN = 1V 720 800 880 mA VRTN (Note 9) 13 16.5 V VWAD rising, VIN = 14V to 48V (referenced to RTN) 8 10 V LOGIC WAD Detection Threshold VWAD-REF WAD Detection Threshold Hysteresis WAD Input Current VWAD falling, VRTN = 0V, VSS unconnected IWAD-LKG 9 0.725 VWAD = 10V (referenced to RTN) 2EC Sink Current V2EC = 3.5V (referenced to RTN), VSS unconnected 2EC Off-Leakage Current V2EC = 48V 1 1.5 V 3.5 FA 2.25 mA 1 FA _______________________________________________________________________________________3 MAX5969D ELECTRICAL CHARACTERISTICS (continued) MAX5969D IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET ELECTRICAL CHARACTERISTICS (continued) (VIN = (VDD - VSS) = 48V, RDET = 24.9k, RCLS = 615, and RSL = 60.4k. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS PG Sink Current VRTN = 1.5V, VPG = 0.8V, during inrush period PG Off-Leakage Current VPG = 60V MIN TYP MAX UNITS 125 230 375 FA 1 FA THERMAL SHUTDOWN Thermal-Shutdown Threshold TSD Thermal-Shutdown Hysteresis TJ rising +140 NC TJ falling 28 NC This device is 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design. The input offset current is illustrated in Figure 1. Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1. Classification current is turned off whenever the device is in power mode. UVLO hysteresis is guaranteed by design, not production tested. A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the MAX5969D to exit power-on mode. Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload condition across VDD and RTN. Note Note Note Note Note Note 3: 4: 5: 6: 7: 8: IIN dRi = 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) IOFFSET = IINi - VINi dRi IINi + 1 dRi IINi IOFFSET VINi 1V VINi + 1 VIN Figure 1. Effective Differential Input Resistance/Offset Current 4_______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET SIGNATURE RESISTANCE vs. INPUT VOLTAGE TA = -40NC 25.0 TA = +25NC 24.5 0.1 TA = +85NC 4 24.0 0 0 2 4 6 8 2 MAX5969D toc03 25.5 RSIGNATURE (kI) 0.2 TA = +85NC TA = -40NC 0 TA = +25NC -2 -4 0 10 2 4 6 8 10 0 2 4 VIN (V) VIN (V) 6 8 10 VIN (V) CLASSIFICATION CURRENT vs. INPUT VOLTAGE CLASSIFICATION SETTLING TIME MAX5969D toc05 MAX5969D toc04 70 CLASS 5 60 VIN 10V/div IIN (mA) 50 CLASS 4 40 30 CLASS 3 20 CLASS 2 IIN 200mA/div VCLS 1V/div CLASS 1 10 CLASS 0 RCLS = 30.9I 0 0 5 10 15 20 25 30 100Fs/div VIN (V) 2EC SINK CURRENT vs. 2EC VOLTAGE TA = +25NC 1.6 TA = -40NC TA = +85NC IPG (FA) 1.2 0.8 TA = +25NC 250 MAX5969D toc07 TA = -40NC PG SINK CURRENT vs. PG VOLTAGE 300 MAX5969D toc06 2.0 I2EC (mA) IIN (mA) 0.3 IIN = IVDD + IDET RDET = 24.9kI RTN = 2EC = PG = WAD = VDD INPUT OFFSET CURRENT (FA) IIN = IVDD + IDET RDET = 25.4kI RTN = 2EC = PG = WAD = VDD -40C P TA P +85NC 0.4 26.0 MAX5969D toc01 0.5 INPUT OFFSET CURRENT vs. INPUT VOLTAGE MAX5969D toc02 DETECTION CURRENT vs. INPUT VOLTAGE TA = +85NC 200 150 VSS UNCONNECTED V2EC REFERENCED TO RTN VWAD = 14V 0.4 100 0 0 10 20 30 V2EC (V) 40 50 60 50 0 10 20 30 40 50 60 VPG (V) _______________________________________________________________________________________5 MAX5969D Typical Operating Characteristics (VIN = (VDD - VSS) = 54V, RDET = 24.9k, RCLS = 615, and RSL = 60.4k. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.) Typical Operating Characteristics (continued) (VIN = (VDD - VSS) = 54V, RDET = 24.9k, RCLS = 615, and RSL = 60.4k. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.) INRUSH CURRENT LIMIT vs. RTN VOLTAGE NORMAL OPERATION CURRENT LIMIT vs. RTN VOLTAGE 800 CURRENT LIMIT (mA) 130 110 90 MAX5969D toc09 900 MAX5969D toc08 150 INRUSH CURRENT LIMIT (mA) MAX5969D IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET 700 600 500 400 300 70 200 50 0 10 20 30 40 50 100 60 0 10 20 30 40 50 VRTN (V) VRTN (V) INRUSH CONTROL WAVEFORM WITH TYPE 2 CLASSIFICATION INRUSH CONTROL WAVEFORM WITH TYPE 2 CLASSIFICATION MAX5969D toc11 MAX5969D toc10 VPG 0V 10V/div V2EC 0V 40V/div USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI 20ms/div 60 USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI V 0V RTN 50V/div VPG 0V 10V/div V2EC 0V 40V/div VRTN 0V 50V/div 0A IRTN 100mA/div IRTN 0A 200mA/div VDD 0V 50V/div VDD 0V 50V/div 20ms/div 6_______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET DET 3 I.C. 4 N.C. N.C. N.C. 13 + MAX5969D EP* 5 6 7 8 RTN 2 14 RTN VDD 15 VSS 1 16 VSS N.C. N.C. TOP VIEW 12 CLS 11 2EC 10 PG 9 WAD TQFN CONNECT TO VSS. Pin Description PIN NAME FUNCTION 1, 13-16 N.C. No Connection. Not internally connected. Leave N.C. unconnected. 2 VDD Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS. 3 DET Detection Resistor Input. Connect a signature resistor (RDET = 24.9kI) from DET to VDD. 4 I.C. Internally Connected. Leave unconnected, leave I.C. unconnected. 5, 6 VSS Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET. 7, 8 RTN Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical Application Circuit. _______________________________________________________________________________________7 MAX5969D Pin Configuration MAX5969D IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Pin Description (continued) PIN NAME FUNCTION WAD Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current sink turns on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used. PG Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC converter while turning on the hot-swap MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode. 11 2EC 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the 2EC current sink is enabled after the isolation MOSFET is fully on until VIN drops below the UVLO threshold. 2EC is latched when powered by a Type 2 PSE until VIN drops below the reset threshold. 2EC also asserts when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not latched if asserted by WAD. The 2EC current sink is turned off when the device is in sleep mode. 12 CLS Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the desired classification current. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification. -- EP 9 10 Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS through a resistive path and must be connected to VSS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane. 8_______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET VDD VDD EN CLS CLASSIFICATION VDD 2EC D SET Q CLR Q D SET Q CLR Q 5V REGULATOR 1.5mA VDD 5V PG 46A DET VON/VOFF VDD 230A VDD THERMAL SHUTDOWN tDELAY R S WAD Q 9V VSS ISWITCH RTN ISOLATION SWITCH K x ISWITCH MAX5969D S I0 1/K I1 MUX _______________________________________________________________________________________9 MAX5969D Simplified Block Diagram IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET MAX5969D Typical Operating Circuit 2-EVENT CLASSIFICATION DETECTION GND 2EC VDD RJ-45 AND BRIDGE RECTIFIER IN+ GND PG RDET 24.9kI 2EC/WAD DET MAX5969D WAD 68nF CLS ENABLE DC-DC CONVERTER 1.5mA SMAJ58A RCLS -54V 24V/48V BATTERY VSS IN- RTN 10 IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Operating Modes Depending on the input voltage (VIN = VDD - VSS), the MAX5969D operates in four different modes: PD detection, PD classification, mark event, and PD power. The device enters PD detection mode when the input voltage is between 1.4V and 10.1V. The device enters PD classification mode when the input voltage is between 12.6V and 20V. The device enters PD power mode once the input voltage exceeds VON. Detection Mode (1.4V VIN 10.1V) In detection mode, the power source equipment (PSE) applies two voltages on VIN in the 1.4V to 10.1V range (1V step minimum) and then records the current measurements at the two points. The PSE then computes DV/DI to ensure the presence of the 24.9k signature resistor. Connect the signature resistor (RDET) from VDD to DET for proper signature detection. The MAX5969D pulls DET low in detection mode. DET goes high impedance when the input voltage exceeds 12.5V. In detection mode, most of the MAX5969D internal circuitry is off and the offset current is less than 10A. If the voltage applied to the PD is reversed, install protection diodes at the input terminal to prevent internal damage to the MAX5969D (see the Typical Application Circuit). Since the PSE uses a slope technique (DV/DI) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process. Classification Mode (12.6V VIN 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. Class 0-5 is defined as shown in Table 1. (The IEEE 802.3af/at standard defines only Class 0-4 and Class 5 for any special requirement.) An external resistor (RCLS) connected from CLS to VSS sets the classification current. The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5969D exhibits a current characteristic with a value shown in Table 1. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by RCLS and the supply current of the MAX5969D so the total current drawn by the PD is within the IEEE 802.3af/at standard figures. The classification current is turned off whenever the device is in power mode. 2-Event Classification and Detection During 2-event classification, a Type 2 PSE probes PD for classification twice. In the first classification event, the PSE presents an input voltage between 12.6V and 20.5V and the MAX5969D presents the programmed load ICLASS. The PSE then drops the probing voltage below the mark event threshold of 10.1V and the MAX5969D presents the mark current (IMARK). This sequence is repeated one more time. When the MAX5969D is powered by a Type 2 PSE, the 2-event identification output 2EC asserts low after the internal isolation n-channel MOSFET is fully turned on. 2EC current sink is turned off when VDD goes below the UVLO threshold (VOFF) and turns on when VDD goes above the UVLO threshold (VON), unless VDD goes below VTHR to reset the latched output of the Type 2 PSE detection flag. Table 1. Setting Classification Current IEEE 802.3at PD CLASSIFICATION CURRENT SPECIFICATION (mA) CLASS MAXIMUM POWER USED BY PD (W) RCLS (I) VIN* (V) MIN MAX MIN 0 0.44 to 12.95 615 12.6 to 20 0 4 0 5 1 0.44 to 3.94 117 12.6 to 20 9 12 8 13 2 3.84 to 6.49 66.5 12.6 to 20 17 20 16 21 CLASS CURRENT SEEN AT VIN (mA) MAX 3 6.49 to 12.95 43.7 12.6 to 20 26 30 25 31 4 12.95 to 25.5 30.9 12.6 to 20 36 44 35 45 5 > 25.5 21.3 12.6 to 20 54 64 51 68 *VIN is measured across the MAX5969D input VDD to VSS. ______________________________________________________________________________________11 MAX5969D Detailed Description MAX5969D IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Alternatively, the 2EC output also serves as a wall adapter detection output when the MAX5969D is powered by an external wall power adapter. See the Wall Power Adapter Detection and Operation section for more information. to power mode. Inrush mode ensures the downstream DC-DC converter is turned off as the internal power MOSFET is turned on. Power Mode The MAX5969D enters power mode when VIN rises above the undervoltage lockout threshold (VON). When VIN rises above VON, the MAX5969D turns on the internal n-channel isolation MOSFET to connect VSS to RTN with inrush current limit internally set to 135mA (typ). The isolation MOSFET is fully turned on when the voltage at RTN is near VSS and the inrush current is reduced below the inrush limit. Once the isolation MOSFET is fully turned on, the MAX5969D changes the current limit to 800mA. The open-drain power-good output (PG) remains low for a minimum of tDELAY until the power MOSFET fully turns on to keep the downstream DC-DC converter disabled during inrush. For applications where an auxiliary power source such as a wall power adapter is used to power the PD, the MAX5969D features wall power adapter detection. The MAX5969D gives highest priority to the WAD and smoothly switch the power supply to WAD when it is detected. Once the input voltage (VDD - VSS) exceeds the mark event threshold, the MAX5969D enables wall adapter detection. The wall power adapter is connected from WAD to RTN. The MAX5969D detects the wall power adapter when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is detected, the internal n-channel isolation MOSFET turns off, 2EC current sink turns on, and classification current is disabled if VIN is in the classification range. Undervoltage Lockout Applications Information The MAX5969D operates up to a 60V supply voltage with a turn-on UVLO threshold (VON) at 35.4V and a turn-off UVLO threshold (VOFF) at 31V. When the input voltage is above VON, the MAX5969D enters power mode and the internal MOSFET is turned on. When the input voltage goes below VOFF for more than tOFF_DLY, the MOSFET turns off. Power-Good Output An open-drain output (PG) is used to allow disabling downstream DC-DC converter until the n-channel isolation MOSFET is fully turned on. PG is pulled low to VSS for a period of tDELAY and until the internal isolation MOSFET is fully turned on. The PG is also pulled low during sleep mode and coming out of thermal shutdown. Thermal-Shutdown Protection The MAX5969D includes thermal protection from excessive heating. If the junction temperature exceeds the thermal-shutdown threshold of +140NC, the MAX5969D turns off the internal power MOSFET, LED driver, and 2EC current sink. When the junction temperature falls below +112NC, the devices enter inrush mode and then return Wall Power Adapter Detection and Operation Operation with 12V Adapter Layout Procedure Careful PCB layout is critical to achieve high efficiency and low EMI. Follow these layout guidelines for optimum performance: 1) Place the input capacitor, classification resistor, and transient voltage suppressor as close as possible to the MAX5969D. 2) Use large SMT component pads for power dissipating devices such as the MAX5969D and the external diodes. 3) Use short and wide traces for high-power paths. 4) Use the MAX5969 evaluation kit layout as a reference. 5) Place enough vias in the pad for the EP of the MAX5969D so that heat generated inside can be effectively dissipated by the PCB copper. The recommended spacing for the vias is 1mm to 1.2mm pitch. The thermal vias should be plated (1oz copper) and have a small barrel diameter (0.3mm to 0.33mm). 12 IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET MAX5969D 2-EVENT CLASSIFICATION (ASSERTED ON) GND VDD RJ-45 AND BRIDGE RECTIFIER GND ENABLE 2EC/WAD DET MAX5969D I.5mA DC-DC CONVERTER WAD CLS SMAJ58A 12V BATTERY RCLS -54V IN+ PG RDET 24.9kI 68nF 2EC VSS IN- RTN THIS CIRCUIT ACHIEVES PROPER 2EC LOGIC WHEN BATTERY IS < 12.5V Figure 2. Typical Configuration When Using a 12V Wall Power Adapter ______________________________________________________________________________________13 MAX5969D IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Typical Application Circuit ISOLATED 2-EVENT CLASSIFICATION OUTPUT GND GND 2EC VDD PG PG 24.9kI 2EC/WAD VAC DET MAX5969D 68nF WAD VAC 1.4mA CLS 24/48V BATTERY SMAJ58A 43.7I VSS -54V GND 33kI 1.37MI RTN RTN 249I 4.7F 0.1F 51.5kI ISOLATED +5.3V/2A GND RTN PG ULVO/EN IN UFLG 0.1F 0.1F 22F VCC VCC ISOLATED RTN FB 10kI CS COMP MAX15000 22.1I NDRV GND CS CS RT 649I 619I 1kI 330pF 18.1kI 8.2nF 0.75I 8.06kI 0.1F 4.99kI VCC 4.99kI 1kI RTN 100pF 33nF 8.06kI 1kI 2.49kI 2.2nF RTN ISOLATED RTN 14 IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET PROCESS: BiCMOS For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 TQFN-EP T1655+4 21-0140 90-0121 ______________________________________________________________________________________15 MAX5969D Package Information Chip Information MAX5969D IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Revision History REVISION NUMBER REVISION DATE 0 6/11 DESCRIPTION Initial release PAGES CHANGED -- Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 16 (c) Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.