FEATURES
• Access time: 90ns
• Simple byte and page write
—Single 5V supply
• No external high voltages or V
PP
control
circuits
—Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
—Active: 50mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent
writes
• High speed page write capability
• Highly reliable
—Endurance: 100,000 write cycles
—Data retention: 100 years
• Early end of write detection
—D
ATA polling
—Toggle bit polling
• Two PLCC and LCC pinouts
—FT28C512
• FT28C010 EPROM pin compatible
—FT28C513
• Compatible with lower density EEPROMs
DESCRIPTION
The FT28C512/513 is a 64K x 8 EEPROM, fabricated
with Force’s proprietary, high performance, floating
gate CMOS technology. The FT28C512/513 is a 5V only
device.
The FT28C512/513 features the JEDEC
approved pin out for byte wide memories, compatible
with industry standard EPROMS.
The FT28C512/513 supports a 128-byte page write
operation, effectively providing a 39µs/byte write cycle
and enabling the entire memory to be written in less
than 2.5 seconds. The FT28C512/513 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the FT28C512/513 supports
the software data protection option.
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Y Buffers
Latches and
Decoder
Control
Logic and
Timing
512Kbit
EEPROM
Array
I/O0–I/O7
Data Inputs/Outputs
CE
OE
VCC
VSS
A7–A15
WE
A0–A6
FT28C512/513
5 Volt Byte Alterable EEPROM
Rev A
1/25
2011
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O5
I/O4
I/O3
I/O2
I/O1
Plastic DIP
CERDIP
FLAt Pack
SOIC (R)
Bottom
14
A0 16
I/O1 18
VSS
11A3
9 A5
7 A7
15
I/O0 17
I/O2 19
I/O3
5 A15 2
NC 36
VCC
20
I/O4
21
I/O5
34
NC
23
I/O7
25
A10
27
A11
29
A8
22
I/O6
32
NC
24
CE
26
OE
28
A9
30
A13
13
A1
12
A2
10
A4
8
A6
4 NC 3
NC 1
NC 35
WE 33
NC
31
A14
6
A12
PGA
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A13
A8
A9
A11
OE
A10
CE
I/O7
A14
I/O1
A12
A15
NC
NC
VCC
WE
NC
2 32
6 1
5 4 3
8
7
9
10
11
12
13 15 17 16 18 19 20
22
23
24
25
26
27
28
29
31
14 21
30
PLCC/LCC
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A9
A11
NC
OE
A10
CE
I/O6
A8
I/O1
A7
A12
VCC
WE
2 32
6 1
5 4 3
8
7
9
10
11
12
13 15 17 16 18 19 20
22
23
24
25
26
27
28
29
31
14 21
30
I/O2
VSS
NC
I/O3
I/O4
I/O5
A14
A15
A13
I/O7
TSOP
View
(Top View)
(Top View)
PIN DESCRIPTIONS
Addresses (A
0
–A
15
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input m ust be LO W to enab le all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read operations .
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the FT28C512/513
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the FT28C512/513.
PIN NAMES
Symbol Description
A
0
–A
15
Address Inputs
I/O
0
–I/O
7
Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
+5V
V
SS
Ground
NC No Connect
FT28C512
FT28C512
FT28C512 FT28C512
FT28C512
FT28C512/513
Rev A
2/25
2011
DEVICE OPERATION
Read
Read operations are initiated b y both OE and CE LO W.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The FT28C512/513 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 5ms.
Page Write Operation
The page write feature of the FT28C512/513 allows the
entire memor y to be wr itten in 2.5 seconds. Page write
allows tw o to one hundred twenty-eight b ytes of data to
be consecutively written to the FT28C512/513, prior to
the commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
source address), but the page address (A
7
through
A
15
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
The page write mode can be initiated dur ing any wr ite
operation. Follo wing the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by
the WE HIGH to LOW transition, must begin within
100µs of the f alling edge of the preceding WE. If a sub-
sequent WE HIGH to LOW transition is not detected
within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively, the page write window is infinitely
wide, so long as the host continues to access the
de vice within the byte load cycle time of 100µs .
Write Operation Status Bits
The FT28C512/513 provides the user two write opera-
tion status bits. These can be used to optimise a sys-
tem write cycle time. The status bits are mapped onto
the I/O bus as sho wn in Figure 1.
Figure 1. Status Bit Assignment
DATA Polling (I/O
7
)
The FT28C512/513 features DATA polling as a method
to indicate to the host system that the byte write or
page write cycle has completed. DATA Polling allows a
simple bit test operation to determine the status of the
FT28C512/513, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O
7
(i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true
data.
Toggle Bit (I/O
6
)
The FT28C512/513 also provides another method for
determining when the inter nal write cycle is complete.
During the inter nal programming cycle, I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete, the toggling will cease, and the device will
be accessible f or additional read or write operations .
5TBDP 43210I/O
Reserved
Toggle Bit
DATA Polling
FT28C512/513
Rev A
3/25
2011
DATA POLLING I/O
7
Figure 2a. DATA Polling Bus Sequence
CE
OE
WE
I/O7
FT28C512/513
Ready
Last
Write
HIGH Z VOL
VIH
A0–A15 AnAnAnAnAnAn
VOH
An
Figure 2b. DATA Polling Software Flow
DATA Polling can eff ectively halv e the time f or writing to
the FT28C512/513. The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The soft-
ware flow diagram in Figure 2b illustrates one method
of implementing the routine.
Write Data
Save Last Data
and Address
Read Last
Address
IO7
Compare?
Ready
No
Yes
Writes
Complete? No
Yes
FT28C512/513
Rev A
4/25
2011
THE TOGGLE BIT I/O
6
Figure 3a. Toggle Bit Bus Sequence
CE
OE
WE
FT28C512/513
Last
Write
I/O6HIGH Z
**
VOH VOL Ready
* Beginning and ending state of I/O6 will vary.
Figure 3b. Toggle Bit Software Flow
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to imple-
ment DATA Polling. This can be especially helpful in an
array comprised of multiple FT28C512/513 memories
that is frequently updated. Toggle Bit Polling can also
provide a method for status checking in multiprocessor
applications. The timing diag ram in Figure 3a illustr ates
the sequence of events on the bus. The software flow
diagram in Figure 3b illustr ates a method f or polling the
Toggle Bit.
HARDWARE DATA PROTECTION
The FT28C512/513 provides three hardware features
that protect nonv olatile data from inadv ertent writes.
– Noise Protection—A WE pulse typically less than
10ns will not initiate a write cycle.
– Def ault V
CC
Sense—All write functions are inhibited
when V
CC
is 3.6V.
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle dur-
ing power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
SOFTWARE DATA PROTECTION
The FT28C512/513 offers a software controlled data
protection feature. The FT28C512/513 is shipped from
Force with the software data protection NOT
ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected
during power-up/-down operations through the use of
external circuits. The host would then have open read
and write access of the device once VCC was stable .
Compare
FT28C512
No
Yes
Ok?
Compare
Accum with
Addr N
Load Accum
From Addr N
Last Write
Ready
FT28C512/513
Rev A
5/25
2011
The FT28C512/513 can be automatically protected dur-
ing power-up and power-down without the need for
external circuits by employing the software data pro-
tection feature. The internal software data protection
circuit is enabled after the first write operation utilising
the software algorithm. This circuit is nonvolatile and
will remain set for the life of the device unless the reset
command is issued.
Once the software protection is enab led, the FT28C512/
513 is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device. Note: The data in the three-byte
enable sequence is not written to the memory arra y.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 4a and 4b for the
sequence. The three byte sequence opens the page
write window, enabling the host to write from one to
one hundred twenty-eight b ytes of data. Once the page
load cycle has been completed, the device will auto-
matically be returned to the data protected state.
Software Data Protection
Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write
CE
WE
(VCC)
Write
Protected
VCC
0V
Data
Addr AAA
5555 55
2AAA A0
5555
≤ tBLC MAX
Writes
ok
Byte
or
Page
tWC
Note: All other timings and control pins are per page write timing requirements
FT28C512/513
Rev A
6/25
2011
Figure 4b. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protected
algorithm is used and data has been written, the
FT28C512/513 will automatically disable further writes,
unless another command is issued to cancel it. If no
further commands are issued the FT28C512/513 will be
write protected during power-down and after any sub-
sequent pow er-up. The state of A15 while ex ecuting the
algorithm is don’t care.
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Last
Write Data XX
to any
Write Data 80
to Address
5555
Write Data 55
to Address
2AAA
Write Data AA
to Address
5555
After tWC
Re-Enters Data
Protected State
Byte to
Last Address
Address Optional
Byte/Page
Load Operation
FT28C512/513
Rev A
7/25
2011
Resetting Software Data Protection
Figure 5a. Reset Software Data Protection Timing Sequence
CE
WE
Standard
Operating
Mode
VCC
Data
Addr AAA
5555 55
2AAA 80
5555 ≥ tWC
AA
5555 55
2AAA 20
5555
Note: All other timings and control pins are per page write timing requirements
Figure 5b. Software Sequence to Deactivate
Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algo-
rithm will reset the inter nal protection circuit. After tWC,
the FT28C512/513 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
SYSTEM CONSIDERATIONS
Because the FT28C512/513 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and wr ite operations. Proper
usage can provide the lowest possible power dissipa-
tion and eliminate the possibility of contention where
multiple I/O pins share the same b us.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the pri-
mary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
de vice(s) is/are outputting data on the bus .
Because the FT28C512/513 has two power modes,
(standby and active), proper decoupling of the memory
array is of prime concer n. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
be used between VCC and VSS at each device.
Depending on the size of the array, the value of the
capacitor ma y hav e to be larger.
Write Data 55
to Address
2AAA
Write Data 55
to Address
2AAA
Write Data A0
to Address
5555
Write Data AA
to Address
5555
Write Data 20
to Address
5555
Write Data AA
to Address
5555
FT28C512/513
Rev A
8/25
2011
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for
each 8 de vices employ ed in the arr ay. This b ulk capaci-
tor is employed to overcome the voltage droop caused
by the inductiv e eff ects of the PC board tr aces.
Active Supply Current vs. Ambient Temperature
Standby Supply Current vs. Ambient Temperature
ICC (RD) by Temperature Over Frequency
–55 –10 +125
10
11
12
13
14
Ambient Temperature (°C)
8+35 +80
VCC = 5V
9
ICC (mA)
–55 –10 +125
0.14
0.16
0.18
0.2
0.24
Ambient Temperature (°C)
0.1 +35 +80
0.22 VCC = 5V
0.12
ISB (mA)
0315
30
40
50
60
5.0 VCC
Frequency (MHz)
10 69
–55°C
+25°C
+125°C
12
20
70
ICC (mA)
FT28C512/513
Rev A
9/25
2011
ABSOLUTE MAXIMUM RATINGS
Temperature under bias
FT28C512/513................................... –10°C to +85°C
FT28C512I/513I............................... –65°C to +135°C
FT28C512M/513M........................... –65°C to +135°C
Storage temperature........................... –65°C to +150°C
Voltage on any pin with
respect to VSS.......................................... –1V to +7V
D.C. output current ................................................ 5mA
Lead temperature
(soldering, 10 seconds) ................................... 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
de vice (at these or an y other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions f or extended periods ma y affect de vice reliability.
RECOMMEND OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C
Supply Voltage Limits
FT28C512/513 5V ±10%
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Note: (1) VIL min. and VIH max. are f or ref erence only and are not tested.
POWER-UP TIMING
Symbol Parameter
Limits
Unit Test ConditionsMin. Max.
ICC VCC current (active) (TTL inputs) 50 mA CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = .4V/2.4V Levels @ f = 5MHz
ISB1 VCC current (standby) (TTL
inputs) 3mACE = VIH, OE = VIL, All I/O’s = open, other
inputs = VIH
ISB2 VCC current (standby) (CMOS
inputs) 500 µA CE = VCC – 0.3V, OE = VIL, All I/O’s = Open,
Other Inputs = VIH
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC, CE = VIH
VlL(1) Input LOW voltage –1 0.8 V
VIH(1) Input HIGH voltage 2 VCC + 1 V
VOL Output LOW voltage 0.4 V IOL = 2.1mA
VOH Output HIGH voltage 2.4 V IOH = –400µA
Symbol Parameter Max. Unit
tPUR(2) Power-up to read operation 100 µs
tPUW(2) Power-up to write operation 5 ms
FT28C512/513
Rev A
10/25
2011
CAPACITANCE TA = +25°C, F = 1MHZ, VCC = 5V
ENDURANCE AND DATA RETENTION
Symbol Parameter Max. Unit Test Conditions
CI/O(2) Input/output capacitance 10 pF VI/O = 0V
CIN(2) Input capacitance 10 pF VIN = 0V
Parameter Min. Max. Unit
Endurance 10,000 Cycles per byte
Endurance 100,000 Cycles per page
Data retention 100 Years
A.C. CONDITIONS OF TEST
MODE SELECTION
EQUIVALENT A.C. LOAD CIRCUIT
Note: (2) This parameter is periodically sampled and not 100%
tested.
SYMBOL TABLE
Input pulse levels 0V to 3V
Input rise and fall times 10ns
Input and output timing levels 1.5V
CE OE WE Mode I/O Power
L L H Read DOUT Active
L H L Write DIN Active
HXX
Standby and
write inhibit High Z Standby
X L X Write inhibit — —
X X H Write inhibit — —
5V
1.92KΩ
100pF
Output
1.37KΩ
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
FT28C512/513
Rev A
11/25
2011
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
Read Cycle
Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF
from the point when CE or OE return HIGH (whiche v er occurs first) to the time when the outputs are no longer driven.
Symbol Parameter
FT28C512-90 FT28C512-12 FT28C512-15 FT28C512-20 FT28C512-25
Unit
FT28C513-90 FT28C513-12 FT28C513-15 FT28C513-20 FT28C513-25
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tRC Read cycle time 90 120 150 200 250 ns
tCE Chip enable access time 90 120 150 200 250 ns
tAA Address access time 90 120 150 200 250 ns
tOE Output enable access time 40 50 50 50 50 ns
tLZ(3) CE LOW to active output 0 0 0 0 0 ns
tOLZ(3) OE LOW to active output 0 0 0 0 0 ns
tHZ(3) CE HIGH to high Z output 40 50 50 50 50 ns
tOHZ(3) OE HIGH to high Z output 40 50 50 50 50 ns
tOH Output hold from address
change 00000 ns
tCE
tRC
Address
CE
OE
WE
Data Valid
tOE
tLZ
tOLZ
tOH
tAA
tHZ
tOHZ
Data I/O
VIH
HIGH Z Data Valid
FT28C512/513
Rev A
12/25
2011
WRITE CYCLE LIMITS
WE Controlled Write Cycle
Note: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to complete the internal write operation.
Symbol Parameter Min. Max. Unit
tWC(4) Write cycle time 10 ms
tAS Address setup time 0 ns
tAH Address hold time 50 ns
tCS Write setup time 0 ns
tCH Write hold time 0 ns
tCW CE pulse width 100 ns
tOES OE HIGH setup time 10 ns
tOEH OE HIGH hold time 10 ns
tWP WE pulse width 100 ns
tWPH WE High recovery 100 ns
tDV Data valid 1 µs
tDS Data setup 50 ns
tDH Data hold 0 ns
tDW Delay to next write 10 µs
tBLC Byte load cycle 0.2 100 µs
Address
tAS
tWC
tAH
tOES
tDV
tDS tDH
tOEH
CE
WE
OE
Data In
Data Out HIGH Z
Data Valid
tCS tCH
tWP
FT28C512/513
Rev A
13/25
2011
CE Controlled Write Cycle
Page Write Cycle
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively per-
forming a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
Address
tAS
tOEH
tWC
tAH
tOES
tCS
tDV
tDS tDH
tCH
CE
WE
OE
Data In
Data Out HIGH Z
Data Valid
tCW
tWPH
WE
OE(5)
Last Byte
Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2
tWP
tWPH
tBLC
tWC
CE
Address*(6)
I/O
*For each successive write within the page write operation, A7–A15 should be the same or
writes to an unknown address could occur.
FT28C512/513
Rev A
14/25
2011
DATA Polling Timing Diagram(7)
Toggle Bit Timing Diagram
Note: (7) P olling oper ations are by definition read cycles and are theref ore subject to read cycle timings .
Address An
DIN = X
tWC
tOEH tOES
CE
WE
OE
I/O7
tDW
AnAn
DOUT = X DOUT = X
CE
OE
WE
I/O6
tOES
tDW
tWC
tOEH
HIGH Z *
*
*Starting and ending state will vary, depending upon actual tWC.
FT28C512/513
Rev A
15/25
2011
PACKAGING INFORMATION
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0.110 (2.79)
0.090 (2.29)
Typ. 0.100 (2.54)
1.690 (42.95)
Max.
0.023 (0.58)
0.014 (0.36)
Typ. 0.018 (0.46)
0.232 (5.90) Max.
0.060 (1.52)
0.015 (0.38)
Pin 1
0.200 (5.08)
0.125 (3.18) 0.065 (1.65)
0.033 (0.84)
Typ. 0.055 (1.40)
0.610 (15.49)
0.500 (12.70)
0.100 (2.54) Max.
0°
15°
32-Lead Hermetic Dual In-Line Package Type D
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.005 (0.13) Min.
0.150 (3.81) Min.
0.015 (0.38)
0.008 (0.20)
Seating
Plane
FT28C512/513
Rev A
16/25
2011
PACKAGING INFORMATION
0.150 (3.81) BSC
0.458 (11.63)
––
0.458 (11.63)
0.442 (11.22)
Pin 1
0.020 (0.51) x 45° Ref.
0.095 (2.41)
0.075 (1.91)
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.0.050 (1.27) BSC
0.028 (0.71)
0.022 (0.56)
(32) Plcs.
0.200 (5.08)
BSC
0.558 (14.17)
––
0.088 (2.24)
0.050 (1.27)
0.120 (3.05)
0.060 (1.52)
Pin 1 Index Corner
32-Pad Ceramic Leadless Chip Carrier Package Type E
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
0.300 (7.62)
BSC
0.015 (0.38)
Min.
0.400 (10.16)
BSC
0.560 (14.22)
0.540 (13.71)
DIA.
0.015 (0.38)
0.003 (0.08)
FT28C512/513
Rev A
17/25
2011
PACKAGING INFORMATION
32-Lead Ceramic Flat Pack Type F
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.019 (0.48)
0.015 (0.38)
0.045 (1.14) Max.
Pin 1 Index
132
0.120 (3.05)
0.090 (2.29)
0.045 (1.14)
0.026 (0.66)
0.007 (0.18)
0.004 (0.10)
0.370 (9.40)
0.270 (6.86)
0.830 (21.08) Max.
0.050 (1.27) BSC
0.488
0.430 (10.93)
0.347 (8.82)
0.330 (8.38)
0.005 (0.13) Min.
0.030 (0.76)
Min.
1.228 (31.19)
1.000 (25.40)
FT28C512/513
Rev A
18/25
2011
PACKAGING INFORMATION
0.021 (0.53)
0.013 (0.33)
0.420 (10.67)
0.050 (1.27) Typ.
Typ. 0.017 (0.43)0.045 (1.14) x 45°
0.300 (7.62)
Ref.
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
Pin 1
0.400
(10.16)Ref.
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
3° Typ.
0.048 (1.22)
0.042 (1.07)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.095 (2.41)
0.060 (1.52)
—
0.015 (0.38)
Seating Plane
±0.004 Lead
CO – Planarity
32-Lead Plastic Leaded Chip Carrier Package Type J
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
0.510"
Typical
0.050"
Typical
0.050"
Typical
0.300"
Ref.
FOO
TPRINT
0.400"
0.410"
0.030" Typical
32 Places
FT28C512/513
Rev A
19/25
2011
PACKAGING INFORMATION
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.022 (0.56)
0.014 (0.36)
0.160 (4.06)
0.125 (3.17)
0.625 (15.88)
0.590 (14.99)
0.110 (2.79)
0.090 (2.29)
1.665 (42.29)
1.644 (41.76)
1.500 (38.10)
Ref.
Pin 1 Index
0.160 (4.06)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
Pin 1
Seating
Plane
0.070 (17.78)
0.030 (7.62)
0.557 (14.15)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
0°
15°
32-Lead Plastic Dual In-Line Package Type P
Typ. 0.010 (0.25)
NOTES:
FT28C512/513
Rev A
20/25
2011
PACKAGING INFORMATION
32-Lead Ceramic Small Outline Gull Wing Package Type R
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
0.340
±0.007
See Detail “A”
For Lead
Information
0.440 Max.
0.560 Nom.
0.0192
0.0138
0.050
0.750
±0.005
0.840
Max.
0.060 Nom.
0.020 Min.
0.015 R Typ.
0.035 Min.
0.015 R
Typ.
0.035 Typ.
Detail “A”
0.560"
Typical
0.050"
Typical
0.050"
Typical
FOOTPRINT
0.030" Typical
32 Places
0.165 Typ.
NOTES:
FT28C512/513
Rev A
21/25
2011
PACKAGING INFORMATION
36-Lead Ceramic Pin Grid Array Package Type K
15 17 19 21 22
14 16 18 20 23
10 9 27 28
8 7 29 30
5 2 36 34 32
4 3 1 35 33
Typ. 0.100 (2.54)
All Leads
Pin 1 Index
NOTE: Leads 5, 14, 23, & 32
12 11 25 26
13
6 31
24
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
0.770 (19.56)
0.750 (19.05)
SQ
A
A
0.185 (4.70)
0.175 (4.45)
0.020 (0.51)
0.016 (0.41)
0.072 (1.83)
0.062 (1.57)
0.120 (3.05)
0.100 (2.54)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
0.050 (1.27)
0.008 (0.20)
A
A
FT28C512/513
Rev A
22/25
2011
REV 1.0 6/27/00
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
0.50 ± 0.04
(0.0197 ± 0.0016)
0.30 ± 0.05
(0.012 ± 0.002)
14.80 ± 0.05
(0.583 ± 0.002)
1.30 ± 0.05
(0.051 ± 0.002)
0.17 (0.007)
0.03 (0.001)
Typical
40 Places 15 Eq. Spc.@ 0.50 ± 0.04
0.0197 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) Overall
Tol. Non-Cumulative
Solder
FOOTPRINT
0.396 (10.058)
0.392 (9.957)
0.493 (12.522)
0.483 (12.268)
Pin #1 Ident
O 0.040 (1.016)
O 0.030 (0.762)
1
(0.038) 0.045 (1.143)
0.035 (0.889)
0.0025 (0.065)
0.557 (14.148)
0.547 (13.894)
Seating
Plane
A
0.007 (0.178)
0.040 (1.016)
15° Typ.
0.0197 (0.500)
0.048 (1.219)
0.010 (0.254)
0.006 (0.152)
0.017 (0.432)
0.032 (0.813) Typ.
0.017 (0.432)
0.020 (0.508) Typ.
0.006 (0.152)
Detail A
40-Lead Thin Small Outline Package (TSOP) Type T
0.965 X0.005 (0.127) Dp.
0.003 (0.076) Dp.
Plane
Seating
Typ.
4° Typ.
Pads
FT28C512/513
Rev A
23/25
2011
Ordering Information
Access Time
–90 = 90ns
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883 M5004
Package
D = 32-Lead CerDip
E = 32-Pad LCC
F = 32-Lead Flat Pack
J = 32-Lead PLCC
K = 36-Lead Pin Grid Array
P = 32-Lead Plastic Dip
R = 32-Lead Ceramic SOIC
T = 40-Lead TSOP
Device
Access Time
–90 = 90ns
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883 M5004
Package
E = 32-Pad LCC
J = 32-Lead PLCC
Device
FT28C512/513
FT28C512 XX XX
FT28C513XXXX
Rev A
24/25
2011
Ashley Crt, Henley,
Marlborough, Wilts, SN8 3RH UK
Tel: +44(0)1264 731200
Fax:+44(0)1264 731444
E-mail
sales@forcetechnologies.co.uk
www.forcetechnologies.co.uk
Life Support Applications
Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies
product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products
for use in such applications do so at their own risk and agree to fully indemnify Force Tecnologies for any damages resulting from such
improper use or sale.
All trademarks acknowledged Copyright Force Technologies Ltd 2011
Unless otherwise stated in this SCD/Data sheet , Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ
-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no
responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these
products, and makes no representation or warranties that these products are free f rom patent, copyright or mask work infringement, unless
otherwise specified.
Rev A
25/25
2011
