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GENERAL DESCRIPTION
The DS1100 series delay lines have five equally
spaced taps providing delays from 4ns to 500ns.
These devices are offered in surface-mount
packages to save PCB area. Low cost and
superior reliability over hybrid technology is
achieved by the combination of a 100% silicon
delay line and industry-standard µMAX and SO
packaging. The DS1100 5-tap silicon delay line
reproduces the input -lo gic st at e at the o ut put after
a fixed delay as specified by the extension of the
part number after the dash. The DS1100 is
designed to reproduce both leading and trailing
edges w it h equ al prec isio n. E ach t ap can drive up
to 10 74LS loads.
Maxim can customize standard products to meet
special needs.
FEATURES
All-S ilicon Timing Cir cuit
Five Taps E qu ally Spaced
5V Oper ation
De lays are S table and P r ecise
Bot h Leading- a nd Trailing-E dg e Accur acy
I mproved Replace ment for DS1000
Low-Po wer CMOS
TTL/CMOS-Compatible
Vapor-Phase, IR, and Wave Soldera ble
Custom Delays Available
Fast-Turn Prototype s
Delays Specified Over Both Commercial and
Indust rial T emperatu r e Ranges
PIN ASSIGNM ENT
PIN DESCRIPTION
TAP 1 to TAP 5 - T AP Output Number
VCC - +5V
GND - Ground
IN - Input
DS1100
5-Tap Economy Timing
Element (Delay Line)
19-5735; Rev 3/11
1
2
3
4
8
7
6
5
VCC
TAP 1
TAP 3
TAP 5
IN
TAP 2
TAP 4
GND
DS1100Z S O (150 mils)
DS1100U µMAX®
µ
MAX is a registered trademark of Maxim Integrated Products, Inc.
DS1100
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ABSOLUTE MAXIMUM RATINGS
Voltage Range o n A ny Pin Relative t o Ground ........................... -0.5V to +6.0V
Short-Cir cuit Output Curr ent ...................................................... 50mA for 1s
O per ating Te m perat ure Ra n ge .................................................... -40°C t o +85°C
Storage Temperature Ran ge ........................................................ -55°C to +125°C
Lead Temperat ur e (soldering, 10s) .............................................. +300°C
Soldering Temper ature (reflow)
Lead(Pb)-free........................................................................... +260°C
Contai ning lead( Pb) ................................................................. +240°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5. 0V ± 5%, TA = -40°C to +85°C, unl ess oth er w i se noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
4.75
5.00
5.25
V
5
High-Level
Input Volta ge
VIH 2.2
V
CC
+
0.3
V 5
Low-Level
Input Volta ge
VIL -0.3 0.8 V 5
Input-Leakage
Current II 0.0V ≤ VI ≤ VCC -1.0 1.0 μA
Active Current ICC
V
CC
= Max; Freq =
1MHz
30 50 mA 6, 8
High-Level
Output Current IOH VCC = Min; VOH = 4 -1 mA
Low-Level
Output Current IOL VCC = Min; VOL = 0.5 12 mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 5. 0V ± 5%, TA = -40°C to +85°C, unless oth er w i se noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Input
Pulse Width tWI
20% of
Tap 5
tPLH
ns 9
Input-to-Tap
Delay Tolerance
(Delays ≤ 40ns)
tPLH,
tPHL
+25°C 5V
-2
Table 1
+2
ns
1, 3, 4, 7
0°C to +70°C -3 Table 1 +3 ns
1, 2, 3, 4,
7
-40°C to +85°C -4 Table 1 +4 ns
1, 2, 3, 4,
7
Input-to-Tap
Delay Tolerance
(Delays > 40ns)
tPLH,
tPHL
+25°C 5V
-5
Table 1
+5
%
1, 3, 4, 7
0°C to +70°C -8 Table 1 +8 %
1, 2, 3, 4,
7
-40°C to +85°C -13 Table 1 +13 %
1, 2, 3, 4,
7
Power-Up Time
tPU
200
μs
In p ut Pe r iod
Period
2(tWI)
ns
9
CAPACITANCE
(TA = +25°C, unless other w i s e no te d.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
10
pF
DS1100
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NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and 5V for both leading and
t railing edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated
t emperat ur e r ange, and a supp ly-voltage range o f 4.75V to 5.25V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if
TAP1 s lows down, all other tap s also s low dow n; TAP3 can never be faster t han TAP2.
4) Intermediate delay values are available on a custom basis. For further information, email the factory
at custom.oscillators@maxim-ic.com.
5) All vo ltages ar e r eferenced to ground.
6) Measured with output s open.
7) See Test Conditions section at t he end of this dat a sheet.
8) Frequenc ies higher tha n 1M Hz result in higher ICC values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layout ).
Figure 1. LOGIC DIAGRAM
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
DS1100
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TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following p ulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): T he elapsed time between t he 20% and the 80% po int on t he leading edge o f the
input pulse.
tFALL (Input Fall Time): The elapsed time between t he 80% and t he 20% po int on t he trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on t he leading edge of any tap o ut put pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on t he trailing edge of a ny tap o utput pulse.
TEST SETUP DESC RIPTI ON
Figure 3 illust rat es t he hardware co nfiguratio n u sed for mea suring the t iming para met ers on the DS1100.
The input waveform is produced by a precision-pulse generator under software control. Time delays are
measured b y a time interva l co unt er ( 2 0p s resolutio n) co nnected b etween t he input and each t ap. E ach t ap
is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated , with each inst r u ment co nt ro lled by a centr al computer over an IE E E 488 bus.
TEST CONDITIONS INPUT
Ambient Temper atu r e: +25°C ±3°C
Supply V olt ag e ( VCC): 5.0V ±0.1V
Input Pulse: Hig h = 3.0V ±0.1V
Low = 0.0V ±0.1V
Source Impedance: 50Ω max
Rise and Fall Time : 3.0ns max (measured between 0.6V and 2.4V)
Pu lse Width: 500ns (1μs for -5 00 ve rsion)
Period: 1μs (2μs for -5 00 ve rs ion)
OUTPUT:
Each o utput is loaded w it h the equiva lent of one 74F04 input gat e. Delay is measured at the 1.5V leve l on
t he ris ing a nd falling edge.
Note: Above conditions are for test only and do not rest rict the operation of the device under oth er
dat a sheet con ditions.
DS1100
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Fig ur e 3. TEST CIRCUIT
Table 1. DS1100 PART NUMBER DELAY
PART
DS1100-xxx
NOM INAL DELAYS (ns)
TAP 1
TAP 2
TAP 3
TAP 4
TAP 5
-20
4
8
12
16
20
-25
5
10
15
20
25
-30
6
12
18
24
30
-35
7
14
21
28
35
-40
8
16
24
32
40
-45
9
18
27
36
45
-50
10
20
30
40
50
-60
12
24
36
48
60
-75
15
30
45
60
75
-100
20
40
60
80
100
-125
25
50
75
100
125
-150
30
60
90
120
150
-175
35
70
105
140
175
-200
40
80
120
160
200
-250
50
100
150
200
250
-300
60
120
180
240
300
-500
100
200
300
400
500
DS1100
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ORDERING INFORMA TION
PART
TEMP RANGE
PIN-PACKAGE
DS1100Z-xxx
-40
°
C to +85
°
C
8 SO
DS1100Z-xxx/T&R
-40°C to +85°C
8 SO
DS1100Z-xxx+
-40°C to +85°C
8 SO
DS1100Z-xxx+T
-40°C to +85°C
8 SO
DS1100U-xxx
-40
°
C to +85
°
C
8
µ
MAX
DS1100U-xxx/T&R
-40
°
C to +85
°
C
8
µ
MAX
DS1100U-xxx+
-40°C to +85°C
8 µMAX
DS1100U-xxx+T
-40°C to +85°C
8 µMAX
xxx D eno tes to tal time delay (ns) ( se e Ta ble 1).
+Denotes a lead( Pb)-free/RoHS-compliant package.
T&R and T = Tape and reel.
PACKAGE INFORMATION
For th e latest package outline in formation and land patterns (footprints), go to www.maxim-ic.com/packages. Not e that a “+” ,
“#” , or “-” in the package code indicates RoHS status only. Package drawings may sh ow a different suffix character, but the
drawing pertains to the package regardless of Ro HS st at u s.
PACKAGE TYPE PACK AG E CODE OU TLINE NO . LAND PATTERN NO.
8 SO (150 mils) S8+4 21-0041 90-0096
8 µMAX U8+1 21-0036 90-0092
DS1100
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Maxim cannot as sume responsibility for us e of any circuitry other than circuitr y entir ely embodied in a M ax im product . No circuit
patent licenses are imp lied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
201 1 M axim Integr at ed Pr od uc ts Maxim is a regi s t ered t r adem ar k of Ma xi m Integrated P r oduc t s .
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
3/11
Removed the DIP pack age from General Description, Pin Assignment,
and Ordering Information (no lo nger availab le ); change d µSOP
package type to µMAX; updated the Absolute Maximum Ratings
section; added the cust omer suppo rt ema il address to the electrical
characteristics Not e 4; added th e Ordering Information and Package
Information tables
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